A device clock lossless switching method and system

Abstract

The present invention relates to a method and system for lossless switching of device clocks, belonging to the field of navigation, timing and communication technology. It solves the problems existing in the prior art, such as the jump in clock frequency and phase of hard switching, which causes the deterioration of high-precision equipment performance; and the complex hardware structure, high cost and poor precision of soft switching. By obtaining a local sampling clock and multiple reference source clocks, and extracting and summarizing the time difference between the local sampling clock and each reference source clock in real time, a real-time compensation value is obtained; the local sampling clock is adjusted using the main control information; when clock switching is required, the backup control information is obtained based on the real-time compensation value, and the local sampling clock is adjusted to losslessly switch the main reference source clock to the backup reference source clock. This method can complete the lossless switching of the clock using a conventional voltage generating circuit. During and after the reference clock switching process, the clock frequency and phase output by the device are lossless, and the device performance is not damaged.

Description

Technical Field

[0001] The present invention relates to the technical fields of navigation, timing and communication, and in particular to a method and system for lossless switching of a device clock. Background Art

[0002] Clock switching technology is widely used in navigation, timing, communication and other fields.

[0003] Hard switching is the most common method for switching device clocks. This typically involves simultaneously inputting at least two clocks, monitoring the clock status via a monitoring circuit, and switching to the backup clock via a switch if the primary clock fails. Systems with more stringent clock requirements typically require not only monitoring the presence of both primary and backup clocks but also determining their operating status. Regardless of the method used, the final switchover is a hard switch. The output clock frequency and phase after a hard switch will differ from the original clock, resulting in jumps in clock frequency and phase before and after the switch. For high-precision equipment, hard switching can degrade performance and, in severe cases, even cause the equipment to malfunction. Several lossless switching methods exist in the prior art. Among these lossless switching methods, some use expensive rubidium clocks, which perform comprehensive calculations on the selected clock source and the local timing signal. This results in short-term uncertainty in the clock source during the clock selection and switching process. Some use multiple control cards, and different boards need to send clock data to each other, resulting in a lot of control logic interaction. Multiple phase-locked loops are also used for switching, and the clocks transmitted to the service cards will jitter during the switching process. When using a phase-locked loop solution, there is a problem of relocking the reference clock when switching. The locking time depends on the parameters of the phase-locked loop, so the clock will be briefly unlocked during this process. Some use a phase detector and a phase-locked loop. The phase detector mainly compares the phases of the two clocks. If the difference between the two clocks is relatively large, the phase detector may not truly reflect the phase difference.

[0004] In summary, existing clock switching technologies have problems such as hard switching causing jumps in clock frequency and phase, which deteriorates the performance of high-precision equipment; and soft switching causing complex hardware structure, high cost, and poor accuracy. Summary of the Invention

[0005] In view of the above analysis, the present invention aims to provide a method and system for lossless switching of device clocks, so as to solve the problems in existing clock switching technology, such as hard switching causing clock frequency and phase jumps, which deteriorates the performance of high-precision equipment; and soft switching causing complex hardware structure, high cost, and poor accuracy.

[0006] The purpose of the present invention is mainly achieved through the following technical solutions:

[0007] An embodiment of the present invention provides a method for lossless switching of a device clock, comprising the following steps:

[0008] Obtain local sampling clock and multiple reference source clocks;

[0009] Extracting and summarizing the time difference between the local sampling clock and each of the reference source clocks in real time, and using any of the reference source clocks as a main reference source clock to obtain a real-time compensation value between the main reference source clock and other reference source clocks;

[0010] Using the time difference between the master reference source clock and the local sampling clock to obtain master control information, and using the master control information to adjust the local sampling clock;

[0011] When clock switching is required, any one of the other reference source clocks is used as a backup reference source clock, and based on the real-time compensation value and using the time difference between the backup reference source clock and the local sampling clock, backup control information is obtained, and the local sampling clock is adjusted using the backup control information to switch the main reference source clock to the backup reference source clock.

[0012] Based on the further improvement of the above method, the local sampling clock is obtained, including:

[0013] Generate an initial local clock using a local adjustable clock source, and input the initial local clock into a clock generation module;

[0014] Generate a local sampling clock by adjusting the frequency of the clock generation module.

[0015] Based on a further improvement of the above method, the time difference between the local sampling clock and each reference source clock is extracted and summarized in real time, including:

[0016] Inputting the local sampling clock and multiple reference source clocks into the time difference extraction module simultaneously;

[0017] Using the time difference extraction module, the clock cycles of the local sampling clock and the clock cycles of each reference source clock are counted simultaneously in the same time period to obtain the local cycle number and the multi-channel reference cycle number;

[0018] Convert the difference between the reference cycle number and the local cycle number of each channel in the same time period into a time difference;

[0019] The time difference between the local sampling clock and each reference source clock is obtained by summarizing.

[0020] Based on a further improvement of the above method, a real-time compensation value between the main reference source clock and other reference source clocks is obtained, including:

[0021] Based on the time difference between the local sampling clock and each of the reference source clocks, obtain the time difference between the main reference source clock and the local sampling clock, and the time difference between any other reference source clock and the local sampling clock;

[0022] Based on the time difference between the main reference source clock and the local sampling clock, as well as the time difference between any other reference source clock and the local sampling clock, these two time differences are subtracted to obtain the time difference between the main reference source clock and the other reference source clocks, that is, the real-time compensation value.

[0023] Based on a further improvement of the above method, the local sampling clock is adjusted using the master control information, including:

[0024] Processing the main control information using a control voltage generating circuit to obtain a main control voltage;

[0025] The local sampling clock is adjusted using the master control voltage so that the local sampling clock is consistent with the master reference source clock.

[0026] Based on a further improvement of the above method, when clock switching is required, any one of the other reference source clocks is used as a backup reference source clock, and the main reference source clock is switched to the backup reference source clock, including:

[0027] When the time difference summary selection module receives a switching instruction, the time difference summary selection module switches to the backup reference source clock according to the switching instruction; or,

[0028] When the time difference extraction module detects that the reference source clock in use is abnormal, the time difference summary selection module automatically selects and switches to the backup reference source clock.

[0029] According to a further improvement of the above method, the backup control information is obtained based on the real-time compensation value and using the time difference between the backup reference source clock and the local sampling clock, including:

[0030] Use real-time compensation values to correct the time differences between reference source clocks;

[0031] After correction, the time difference between the backup reference source clock and the local sampling clock is used to obtain backup control information that is consistent with the main control information.

[0032] A further improvement based on the above method, using the backup control information to adjust the local sampling clock, includes:

[0033] Processing the standby control information using a control voltage generating circuit to obtain a standby control voltage;

[0034] The local sampling clock is adjusted by utilizing the backup control voltage so that the local sampling clock is consistent with the main reference source clock.

[0035] Based on a further improvement of the above method, a device clock lossless switching system that implements the device clock lossless switching method includes:

[0036] At least two reference source clocks, at least two time difference extraction modules corresponding to each reference source clock, a time difference aggregation selection module, a control voltage generation circuit, a local adjustable clock source and a clock generation module; wherein,

[0037] Any one of the at least two reference source clocks is used as a primary reference source clock, and any one of the remaining reference source clocks is used as a backup reference source clock;

[0038] adjusting a local sampling clock using the primary reference source clock, and

[0039] When clock switching is required, the primary reference source clock is switched to the backup reference source clock.

[0040] Based on the further improvement of the above method, the time difference extraction module is used to calculate the time difference between the corresponding reference source clock and the local sampling clock; it is also used to monitor whether the reference source clock is normal; it is also used to calculate the real-time compensation value between the main reference source clock and other reference source clocks;

[0041] The time difference aggregation and selection module is used to aggregate data from various time difference extraction modules and switch to the backup reference source clock if the current primary reference source clock is abnormal or when a switching instruction is received; it is also used to obtain and output primary control information based on the time difference between the primary reference source clock and the local sampling clock; and it is also used to obtain and output backup control information based on the real-time compensation value and the time difference between the backup reference source clock and the local sampling clock when switching to the backup reference source clock;

[0042] The control voltage generating circuit is configured to output a primary control voltage or a backup control voltage based on the primary control information or the backup control information; the primary control voltage is configured to adjust the local sampling clock when the primary reference source clock is used; and the backup control voltage is configured to adjust the local sampling clock when the backup reference source clock is switched to.

[0043] The local adjustable clock source is used to generate an initial local clock; and is also used to generate a local clock based on a control voltage;

[0044] The clock generation module is configured to generate a local sampling clock based on an initial local clock or a local clock.

[0045] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0046] 1. The device clock lossless switching method provided by the present invention has simple clock adjustment and low cost. It does not require hardware devices such as rubidium clocks, phase-locked loops, and phase detectors. The lossless clock switching can be completed using a conventional voltage generation circuit.

[0047] 2. The device clock lossless switching method provided by the present invention ensures that the clock frequency and phase output by the device are lossless during and after the reference clock switching process, thereby protecting the device without damaging the device performance.

[0048] 3. The device clock lossless switching method provided by the present invention has no restrictions on the external optional reference clock. It can use pulse per second (1pps) or reference clocks of 10MHz, 100MHz or other frequencies, and has a wide range of applications.

[0049] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following description, and some advantages will become apparent from the description or be learned through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.

[0051] Figure 1 This is a general flow chart of the device clock lossless switching method of the present invention;

[0052] Figure 2 This is a structural block diagram of a device clock lossless switching system according to an embodiment of the present invention;

[0053] Figure 3 This is the workflow of the device clock lossless switching method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0055] Example 1

[0056] A specific embodiment of the present invention discloses a method for lossless switching of device clocks, such as Figure 1 As shown, the following steps are included:

[0057] S1. Obtain local sampling clock and multiple reference source clocks;

[0058] The time difference between the local sampling clock and each reference source clock is extracted and summarized in real time, and any reference source clock is used as the main reference source clock to obtain a real-time compensation value between the main reference source clock and other reference source clocks.

[0059] S2. Using the time difference between the master reference source clock and the local sampling clock, obtain master control information and adjust the local sampling clock.

[0060] S3. When clock switching is required, any one of the other reference source clocks is used as a backup reference source clock. Based on the real-time compensation value and the time difference between the backup reference source clock and the local sampling clock, backup control information is obtained and the local sampling clock is adjusted to switch the primary reference source clock to the backup reference source clock.

[0061] Example 2

[0062] Based on the optimization of Example 1, the specific working process of the device clock lossless switching method is as follows: Figure 3 As shown, step S1 can be further refined into the following steps:

[0063] S11. Obtain a local sampling clock.

[0064] First, the system is powered on and a free-oscillating initial local clock is generated using a local adjustable clock source. This is then fed into the clock generation module. The clock generation module then adjusts the frequency to generate a local sampling clock based on the system's specifications. The higher the accuracy of the local sampling clock, the smaller the time difference step required.

[0065] The step of the time difference refers to the period of the local sampling clock;

[0066] For example, if the local sampling clock is selected as 10 MHz, the step of the time difference is 100 ns; if the sampling clock is selected as 100 MHz, the step of the time difference is 10 ns.

[0067] Therefore, the higher the accuracy requirement for the local sampling clock, the higher the requirement for the step index of the time difference.

[0068] S12. Obtain multiple reference source clocks.

[0069] Specifically, multiple reference source clocks are selected according to project requirements to serve as references for adjusting the local sampling clock. The purpose of selecting multiple reference source clocks is to ensure that when the currently used reference source clock fails, other working reference source clocks can be switched.

[0070] It is worth noting that, according to engineering practice experience, multiple reference source clocks in a system or device may have theoretically consistent frequencies or inconsistent frequencies.

[0071] S13. Extract and summarize the time difference between the local sampling clock and each reference source clock in real time.

[0072] Specifically, the local sampling clock and multiple reference source clocks are simultaneously input into the time difference extraction module.

[0073] By utilizing the time difference extraction module, the clock cycles of the local sampling clock and the clock cycles of the reference source clocks are counted simultaneously within the same time period.

[0074] The number of clock cycles of the local sampling clock is recorded as the number of local cycles;

[0075] The number of clock cycles of each reference source clock is recorded as the number of multi-channel reference cycles.

[0076] When the theoretical frequency of the reference source clock and the theoretical frequency of the local sampling clock are different, the number of clock cycles of the reference source clock and the number of clock cycles of the local sampling clock are counted simultaneously and the counting ends simultaneously to obtain the actual number of reference cycles and the actual number of local cycles. The local sampling clock is used as the standard, that is, based on the actual number of local cycles and the corresponding relationship between the theoretical frequency of the reference source clock and the theoretical frequency of the local sampling clock, the corresponding theoretical number of reference cycles within the same counting time period is obtained. The actual number of reference cycles and the theoretical number of reference cycles are then compared:

[0077] If the actual reference cycle number is greater than the theoretical reference cycle number, the actual frequency of the reference source clock is faster than the actual frequency of the local sampling clock. If this reference source clock is used as the primary reference source clock, the output frequency of the local sampling clock needs to be increased in the subsequent steps related to adjusting the local sampling clock.

[0078] If the actual reference cycle number is less than the theoretical reference cycle number, the actual frequency of the reference source clock is slower than the actual frequency of the local sampling clock. If this reference source clock is used as the primary reference source clock, the output frequency of the local sampling clock needs to be lowered in subsequent steps to adjust the local sampling clock.

[0079] For example, the theoretical frequency of the reference source clock is 10 MHz, and the theoretical frequency of the local sampling clock is 50 MHz. The number of clock cycles of the reference source clock and the number of clock cycles of the local sampling clock are counted simultaneously, and the counting ends simultaneously to obtain the actual number of reference cycles and the actual number of local cycles. When the actual number of local cycles is 50 MHz, the local sampling clock is used as the basis, and according to the correspondence between the theoretical frequency of the reference source clock and the theoretical frequency of the local sampling clock, the corresponding theoretical number of reference cycles in the same counting time period is 10 MHz. In this case, the actual number of reference cycles and the theoretical number of reference cycles need to be compared:

[0080] If the actual reference cycle number is greater than 10M, the actual frequency of the reference source clock is faster than the actual frequency of the local sampling clock. If this reference source clock is used as the primary reference source clock, the output frequency of the local sampling clock needs to be increased in the subsequent steps to adjust the local sampling clock.

[0081] If the actual reference cycle number is less than 10M, the actual frequency of the reference source clock is slower than the actual frequency of the local sampling clock. If this reference source clock is used as the primary reference source clock, you need to lower the output frequency of the local sampling clock in the subsequent steps to adjust the local sampling clock.

[0082] When the theoretical frequency of the reference source clock is the same as the theoretical frequency of the local sampling clock, you can directly compare the reference cycle counts and the local cycle counts:

[0083] If the local cycle number is less than the reference cycle number of a certain reference source clock, it means that the actual frequency of this reference source clock is faster than the actual frequency of the local sampling clock. If this reference source clock is used as the main reference source clock, you need to increase the output frequency of the local sampling clock in the subsequent steps related to adjusting the local sampling clock.

[0084] If the local cycle number is greater than the reference cycle number of a certain reference source clock, the actual frequency of this reference source clock is slower than the actual frequency of the local sampling clock. If this reference source clock is used as the primary reference source clock, you need to lower the output frequency of the local sampling clock in the subsequent steps to adjust the local sampling clock.

[0085] In the same time period, the difference between the reference cycle number and the local cycle number of each channel can be converted into a time deviation, and this deviation is the time difference in this embodiment.

[0086] The time difference between the local sampling clock and each reference source clock is obtained by summarizing.

[0087] The time difference extraction module also monitors the input of the reference source clock. If the current reference source clock is abnormal, it automatically switches to another reference source clock, namely the backup reference source clock. All reference source clocks of the device are input into the time difference aggregation selection module for the corresponding time difference calculation.

[0088] S14. Using any reference source clock as the main reference source clock, and combining the time difference between the local sampling clock and each reference source clock, obtain a real-time compensation value between the main reference source clock and other reference source clocks.

[0089] Preferably, when the device has high requirements for clock accuracy, it is necessary to first select any one of the multiple reference source clocks as the main reference source clock, and then use the clock generation module to generate a local sampling clock with a frequency higher than that of the main reference source clock to ensure the accuracy of the phase when the local sampling clock is subsequently adjusted, and then use step S13 to obtain the time difference between the local sampling clock and each reference source clock.

[0090] Specifically, all reference source clocks, including the primary reference source clock, are subjected to time difference calculations with the local sampling clock. Because the time difference aggregation and selection module processes the time differences between all reference source clocks and the local sampling clock in real time, subsequent switching between reference source clocks ensures that all channel data is up-to-date.

[0091] As mentioned in step S12, multiple reference clock sources within a system or device may have theoretically consistent frequencies or inconsistent frequencies. Regardless of the situation, in subsequent steps, when switching from the primary reference clock to another reference clock source, the local sampling clock will still be adjusted based on the primary reference clock source.

[0092] In the second case, each reference source clock has different characteristics, such as phase and frequency differences. These differences manifest as different time differences between the local sampling clock and each reference source clock. Therefore, the time difference aggregation selection module needs to correct the time differences of all channels using real-time compensation values.

[0093] For example, if the time difference between the primary reference source clock of channel 1 and the local sampling clock is 10ns, and the time difference between the backup reference source clock of channel 2 and the local sampling clock is 100ns, it can be determined that there is a 90ns deviation between the backup reference source clock of channel 2 and the primary reference source clock of channel 1, which is the real-time compensation value. Because the difference between different cycle numbers within the same time period can be converted into a time difference, the phase and frequency differences between the reference source clocks can be compensated by the time difference.

[0094] In subsequent steps, if the main reference source clock of channel 1 is switched to the backup reference source clock of channel 2, that is, the backup reference source clock of channel 2 is used, it is necessary to compensate the real-time compensation value of 90ns before using it, so that the local sampling clock is still based on the main reference source clock.

[0095] Since the effect of the reference source clock corrected by the real-time compensation value provided to the subsequent modules is consistent with the effect when the main reference source clock is used, switching the main reference source clock to the backup reference source clock or other reference source clock can achieve smooth switching between reference source clocks.

[0096] It is worth noting that, generally speaking, the characteristics of each reference source clock are relatively stable. Therefore, by switching the main reference source clock of channel 1 to the backup reference source clock of channel 2 and using the backup reference source clock of channel 2 and the real-time compensation value between it and the main reference source clock, the same effect as the main reference source clock can be achieved, which is very reliable.

[0097] Preferably, step S2 can be further refined into the following steps:

[0098] S21. Obtain master control information using the time difference between the master reference source clock and the local sampling clock; process the master control information to obtain a master control voltage.

[0099] The time difference summary selection module first uses any reference source clock as the main reference source clock, and then processes the time difference data between the main reference source clock and the local sampling clock output by the time difference extraction module and converts it into a data format that can be used by the control voltage generation circuit, namely the main control information.

[0100] For example, the time difference between the main reference source clock of channel 1 and the local sampling clock is positive 10ns, and the relationship between the output time difference of the subsequent VC-OCXO (Voltage Control-Oven Controlled Crystal Oscillator) and the voltage control end is 0.2ns / mv. Then, the time difference of positive 10ns is adjusted, and the main control information instructs the control voltage generating circuit to generate a 50mv voltage change.

[0101] The time difference aggregation selection module transmits the main control information to the control voltage generation circuit. The control voltage generation circuit can use a chip such as a digital-to-analog converter or an operational amplifier to generate a variable voltage.

[0102] If a DAC (Digital Analog Converter) is used as the control voltage generating circuit, the digital code and the output voltage have a one-to-one correspondence. When a specific voltage needs to be output, only the corresponding digital code needs to be input.

[0103] For example, a 12-bit unsigned DAC with an output range of 0 to 3.3V represents an output voltage step of 0.805mV. When the digital code is 2048, the voltage is approximately 1.65V. To increase the voltage by 50mV, add 62 to the original code. For a digital code of 2110, the output voltage is 1.7V.

[0104] If an operational amplifier is used to generate an adjustable voltage, PWM (Pulse Width Modulation) is generally input to the input of the operational amplifier, and a corresponding filtering circuit is added to the output of the operational amplifier to adjust the output voltage through the PWM wave.

[0105] S22. Use the master control voltage to adjust the local sampling clock so that the local sampling clock is consistent with the master reference source clock.

[0106] The voltage generated by the control voltage generation circuit is derived from the master control information, calculated based on the time difference between the local sampling clock and the master reference source clock. After adjusting the local sampling clock, when the time difference reaches 0, the local sampling clock and the master reference source clock are fully synchronized. The local sampling clock is generated from the local clock, ensuring a specific relationship between the controlled local clock and the input reference source clock.

[0107] Preferably, step S3 can be further refined into the following steps:

[0108] S31. When clock switching is required, any one of the other reference source clocks is used as a backup reference source clock, and the main reference source clock is switched to the backup reference source clock. Based on the real-time compensation value and the time difference between the backup reference source clock and the local sampling clock, the backup control information is obtained.

[0109] Specifically, when the time difference summary selection module receives a switching instruction, it switches to a normal reference source clock, i.e., the backup reference source clock, according to the switching instruction. Alternatively, when the time difference extraction module detects that the reference source clock in use is abnormal, the time difference summary selection module automatically switches to a normal reference source clock, i.e., the backup reference source clock. Because the time difference summary selection module continuously updates the time difference data of each reference source clock, and this data is corrected for the differences between the reference source clocks using real-time compensation values, any reference source clock other than the primary reference source clock is used as a backup reference source clock. The data provided to the next level, i.e., the backup control information, is theoretically the same as the primary control information. Therefore, the backup reference source clock does not change suddenly after switching, and therefore the control information input to the control voltage adjustment circuit does not change. In other words, the backup control information after switching is consistent with the primary control information before switching.

[0110] S32. Process the backup control information to obtain a backup control voltage; use the backup control voltage to adjust the local sampling clock so that the local sampling clock is consistent with the main reference source clock.

[0111] Specifically, since the backup control information after switching is consistent with the primary control information before switching, the control voltage output by the control voltage adjustment circuit is stable. At the same time, since the control voltage input to the local adjustable clock source does not change, the subsequent clock, that is, the local clock source, is unaware of the switching between the reference source clocks, ensuring that the local clock source frequency and phase do not change, thus ensuring seamless switching between the reference source clocks.

[0112] Example 3

[0113] A specific embodiment of the present invention discloses a device clock lossless switching system that implements any of the above-mentioned device clock lossless switching methods, such as Figure 2 As shown, it includes:

[0114] At least two reference source clocks, at least two time difference extraction modules corresponding to each reference source clock, a time difference aggregation selection module, a control voltage generation circuit, a local adjustable clock source and a clock generation module; wherein,

[0115] Any one of the at least two reference source clocks is used as a primary reference source clock, and any one of the remaining reference source clocks is used as a backup reference source clock;

[0116] adjusting a local sampling clock using the primary reference source clock, and

[0117] When clock switching is required, the primary reference source clock is switched to the backup reference source clock.

[0118] The time difference extraction module is used to calculate the time difference between the corresponding reference source clock and the local sampling clock, and is also used to monitor whether the reference source clock used is normal; and is also used to calculate the real-time compensation value between the main reference source clock and other reference source clocks;

[0119] The time difference aggregation and selection module is used to aggregate data from various time difference extraction modules and switch to the backup reference source clock if the current primary reference clock is abnormal or when a switching instruction is received; it is also used to obtain and output primary control information based on the time difference between the primary reference source clock and the local sampling clock; and it is also used to obtain and output backup control information based on the real-time compensation value and the time difference between the backup reference source clock and the local sampling clock when switching to the backup reference source clock;

[0120] The control voltage generating circuit is configured to output a primary control voltage or a backup control voltage based on the primary control information or the backup control information; the primary control voltage is configured to adjust the local sampling clock when the primary reference source clock is used; and the backup control voltage is configured to adjust the local sampling clock when the backup reference source clock is switched to.

[0121] The local adjustable clock source is used to generate an initial local clock; and is also used to generate a local clock based on a control voltage;

[0122] The clock generation module is configured to generate a local sampling clock based on an initial local clock or a local clock.

[0123] Those skilled in the art will appreciate that all or part of the process steps of the above-described embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a magnetic disk, an optical disk, a read-only memory, or a random access memory.

[0124] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for lossless switching of device clocks, characterized in that: The steps include: Obtain local sampling clock and multiple reference source clocks; Extracting and summarizing the time difference between the local sampling clock and each of the reference source clocks in real time, and using any of the reference source clocks as a master reference source clock to obtain a real-time compensation value between the master reference source clock and the other reference source clocks; wherein extracting and summarizing the time difference between the local sampling clock and each of the reference source clocks in real time comprises: simultaneously inputting the local sampling clock and multiple reference source clocks into a time difference extraction module; using the time difference extraction module, simultaneously counting the clock period of the local sampling clock and the clock period of each of the reference source clocks within the same time period to obtain a local cycle number and a multiple reference cycle number; converting the difference between the reference cycle number and the local cycle number within the same time period into a time difference; and summarizing the time difference between the local sampling clock and each of the reference source clocks; Obtaining a real-time compensation value between a master reference source clock and other reference source clocks, including: obtaining a time difference between the master reference source clock and the local sampling clock, and a time difference between any other reference source clock and the local sampling clock based on the time difference between the local sampling clock and each reference source clock; subtracting the time difference between the master reference source clock and the local sampling clock, and the time difference between any other reference source clock and the local sampling clock, to obtain a time difference between the master reference source clock and other reference source clocks, i.e., a real-time compensation value; Using the time difference between the master reference source clock and the local sampling clock to obtain master control information, and using the master control information to adjust the local sampling clock; When clock switching is required, any one of the other reference source clocks is used as a backup reference source clock, and based on the real-time compensation value and using the time difference between the backup reference source clock and the local sampling clock, backup control information is obtained, and the local sampling clock is adjusted using the backup control information to switch the main reference source clock to the backup reference source clock.

2. The device clock lossless switching method according to claim 1, characterized in that: Obtain the local sampling clock, including: Generate an initial local clock using a local adjustable clock source, and input the initial local clock into a clock generation module; Generate a local sampling clock by adjusting the frequency of the clock generation module.

3. The device clock lossless switching method according to claim 2, characterized in that: Use the master control information to adjust the local sampling clock, including: Processing the main control information using a control voltage generating circuit to obtain a main control voltage; The local sampling clock is adjusted using the master control voltage so that the local sampling clock is consistent with the master reference source clock.

4. The device clock lossless switching method according to claim 3, characterized in that: When clock switching is required, any of the other reference source clocks is used as a backup reference source clock, and the primary reference source clock is switched to the backup reference source clock. This includes: When the time difference summary selection module receives a switching instruction, the time difference summary selection module switches to the backup reference source clock according to the switching instruction; or, When the time difference extraction module detects that the reference source clock in use is abnormal, the time difference summary selection module automatically selects and switches to the backup reference source clock.

5. The device clock lossless switching method according to claim 4, characterized in that: Based on the real-time compensation value and using the time difference between the backup reference source clock and the local sampling clock, backup control information is obtained, including: Use real-time compensation values to correct the time difference between the reference source clocks; After correction, the time difference between the backup reference source clock and the local sampling clock is used to obtain backup control information that is consistent with the main control information.

6. The device clock lossless switching method according to claim 5, characterized in that: Use alternate control information to adjust the local sampling clock, including: Processing the standby control information using a control voltage generating circuit to obtain a standby control voltage; The local sampling clock is adjusted by utilizing the backup control voltage so that the local sampling clock is consistent with the main reference source clock.

7. A device clock lossless switching system for implementing the device clock lossless switching method according to any one of claims 1 to 6, characterized in that: include: At least two reference source clocks, at least two time difference extraction modules corresponding to each reference source clock, a time difference aggregation selection module, a control voltage generation circuit, a local adjustable clock source and a clock generation module; wherein, Any one of the at least two reference source clocks is used as a primary reference source clock, and any one of the remaining reference source clocks is used as a backup reference source clock; adjusting a local sampling clock using the primary reference source clock, and When clock switching is required, the primary reference source clock is switched to the backup reference source clock.

8. The device clock lossless switching system according to claim 7, characterized in that: The time difference extraction module is used to calculate the time difference between the corresponding reference source clock and the local sampling clock; it is also used to monitor whether the reference source clock is normal; it is also used to calculate the real-time compensation value between the main reference source clock and other reference source clocks; The time difference aggregation and selection module is used to aggregate the data of each time difference extraction module and switch to the backup reference source clock if the current main reference source clock is abnormal or when a switching instruction is received; it is also used to obtain and output the main control information based on the time difference between the main reference source clock and the local sampling clock; further configured to obtain and output backup control information based on the real-time compensation value and utilizing the time difference between the backup reference source clock and the local sampling clock when switching to the backup reference source clock; The control voltage generating circuit is configured to output a primary control voltage or a backup control voltage based on the primary control information or the backup control information; the primary control voltage is configured to adjust the local sampling clock when the primary reference source clock is used; and the backup control voltage is configured to adjust the local sampling clock when the backup reference source clock is switched to. The local adjustable clock source is used to generate an initial local clock; and is also used to generate a local clock based on a control voltage; The clock generation module is configured to generate a local sampling clock based on an initial local clock or a local clock.

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