Compression method of mapping table data, controller and memory
By splitting the physical addresses in the solid-state drive into multiple segments and assembling them into sets according to domain address types, and using targeted compression methods, the problem of large flash memory space occupied by the mapping table is solved, achieving efficient storage space utilization and improved read performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MAXIO TECHNOLOGY (HANGZHOU) CO LTD
- Filing Date
- 2022-08-31
- Publication Date
- 2026-05-12
AI Technical Summary
The current method of storing mapping tables in solid-state drives consumes a large amount of flash memory, resulting in low read performance.
The physical address is split into multiple segments, which are then grouped into sets according to the type of domain address. Each set is then compressed accordingly. Continuous flag bits and numerical bits are used to indicate the continuity of the domain address, and the compressed data is stored in a cache unit.
It significantly reduces the storage space occupied by the mapping table, reduces write amplification, extends the lifespan of the memory and related devices, and improves read performance.
Smart Images
Figure CN115391240B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data storage technology, and in particular to a method, controller, and memory for compressing mapping table data. Background Technology
[0002] Solid-state drives (SSDs) are hard drives made with solid-state electronic storage chips, mainly composed of a controller, storage media, and cache units. Currently, the most common SSDs use flash memory as the storage medium, such as NAND flash (non-volatile memory), and use SRAM or DRAM as cache units.
[0003] When using an SSD to store write data, an FTL (Flash Translation Layer) mapping table is needed to record the mapping relationship between the host logical space address and the flash memory physical address. Therefore, an SSD not only stores the user-written data but also the mapping table that maintains the write data mapping relationship. Currently, DRAM-less SSDs manage the mapping table by establishing a two-level mapping table. This involves grouping the logical addresses corresponding to write data into a first-level mapping table, which includes the logical addresses corresponding to multiple data blocks. Then, multiple second-level mapping tables are established in the flash memory, each storing the mapping relationship corresponding to one data block. In other words, each second-level mapping table stores the physical address corresponding to the logical address of a data block. This means that all the physical addresses corresponding to logical addresses are stored sequentially in the flash memory. This storage method consumes a large amount of flash memory space, and the number of second-level mapping tables becomes increasingly large as the amount of write data increases. Therefore, the current two-level mapping table storage method used in SSDs still consumes a large amount of flash memory space, resulting in relatively low read performance. Summary of the Invention
[0004] In view of the above problems, the object of the present invention is a method, controller and memory for compressing mapping table data, so as to solve the problems existing in the prior art.
[0005] According to a first aspect of the present invention, a method for compressing mapping table data is provided, the mapping table data including multiple physical addresses, wherein the compression method includes:
[0006] Each physical address is divided into multiple segments according to the types of domain addresses contained in the physical address, and each segment contains at least one type of domain address.
[0007] Each of the plurality of physical addresses contains segments of the same type of domain address, which are then grouped into sets corresponding to the domain address.
[0008] Compress consecutive field addresses among the multiple field addresses in each set; and
[0009] The compressed sets are stored in the cache unit in the order of the split segments.
[0010] Optionally, the different types of domain addresses include block addresses, page addresses, LUN codes, and page offsets.
[0011] Optionally, in the sets corresponding to the block address, the page address, and the LUN encoding, the consecutive field address is a plurality of field addresses with the same value that are sequentially adjacent; in the set corresponding to the page offset, the consecutive field address is a plurality of field addresses with consecutive values that are sequentially adjacent.
[0012] Optionally, each of the multiple segments into which the physical address is split corresponds to a domain address among the block address, the page address, the LUN encoding, and the page offset.
[0013] Optionally, one of the segments into which each physical address is split contains both the LUN encoding and the page offset domain address.
[0014] Optionally, the sets of different types of domain addresses may compress the consecutive domain addresses in different ways.
[0015] Optionally, in the compressed set, each domain address includes a continuity flag bit and a value bit. The continuity flag bit being 1 indicates that the domain addresses are consecutive, and the continuity flag bit being 0 indicates that the domain addresses are not consecutive. The value bit is used to store the value of the domain address.
[0016] Optionally, when the continuity flag is 1, the domain address value is followed by a continuity count value, which represents the number of consecutive domain addresses.
[0017] Optionally, compressing consecutive field addresses among the plurality of field addresses in each set includes:
[0018] Set the consecutive count value of the domain addresses contained in the first physical address to 1;
[0019] Determine whether the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address, where i is an integer greater than or equal to 1;
[0020] If the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address, then the consecutive count value is incremented by 1 until the domain address contained in the nth physical address is not consecutive to the domain address contained in the (n-1)th physical address. Then, the value of the domain address contained in the (n-1)th physical address is updated to the value bit of the cache unit, the consecutive flag position before the value bit is set to 1, and the consecutive count value is stored after the value bit, where n>i. Then, the consecutive count value is set to 1.
[0021] If the domain address contained in the (i+1)th physical address is not contiguous with the domain address contained in the ith physical address, and the domain address contained in the ith physical address is not contiguous with the domain address contained in the (i-1)th physical address, then the value of the domain address contained in the ith physical address is updated to the value bit in the cache unit, the contiguous flag position before the value bit is set to 0, and the contiguous count value is set to 1; and
[0022] The step of determining whether the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address is performed sequentially on multiple domain addresses in the set until all domain addresses have been determined.
[0023] Optionally, before the step of compressing consecutive field addresses among the plurality of field addresses in each set, the method further includes setting different encoding bits for different values of the field addresses in each set.
[0024] Optionally, setting different encoding bits for different values of the domain address in each set includes: setting different encoding bits for consecutively occurring and individually occurring identical values, wherein the consecutive flag bit of consecutively occurring values is 1, and the consecutive flag bit of individually occurring values is 0.
[0025] Optionally, compressing consecutive field addresses among the plurality of field addresses in each set includes:
[0026] The encoding bits of the domain address are stored in the numerical bits of the cache unit, and the consecutive count value is also stored after the encoding bits corresponding to the consecutive domain addresses.
[0027] Optionally, setting different encoding bits for different values of the domain address in each set includes: counting the frequency of occurrence of the domain address for each different value in the set, and setting different encoding bits using the Huffman algorithm.
[0028] Optionally, the cache unit storing multiple sets also stores header information, which includes the correspondence between the field address values and the encoding bits.
[0029] According to a second aspect of the present invention, a controller is provided, comprising:
[0030] A processor, connected to a host, is configured to receive write data from the host and execute the compression method described above.
[0031] A cache unit, connected to the processor, is used to store the write data. The cache unit is also used to store a first-level mapping table corresponding to the write data, and to store mapping table data corresponding to the first-level mapping table. The mapping table data is a second-level mapping table.
[0032] According to a third aspect of the present invention, a memory is provided, comprising:
[0033] The controller described above;
[0034] A storage medium, connected to the controller, is used to store write data according to the control of the controller.
[0035] The compression method for mapping table data provided in this application splits each physical address into multiple segments based on the types of domain addresses contained within the physical address. Segments containing the same type of domain addresses within each physical address then form sets corresponding to those domain addresses. Each set is then compressed individually, primarily focusing on compressing consecutive domain addresses. Finally, the compressed sets are stored sequentially in a cache unit according to the order of the split segments. This compression method segments and compresses each piece of data in the mapping table, resulting in a very high compression ratio. This significantly reduces the storage space occupied by the mapping table, minimizes write amplification, and extends the lifespan of the memory and related devices.
[0036] Furthermore, after splitting the physical addresses, targeted compression methods are selected according to the characteristics of each set. Different compression methods are used for sets corresponding to different types of domain addresses to further improve the compression ratio and reduce the storage space occupied by the mapping table.
[0037] In a further embodiment, different encoding bits are set for different values of the domain address in each set. The encoding bits are used to replace the values of the domain address and are stored in the cache space. For example, the frequency of different domain addresses is counted and encoded according to the Huffman algorithm. The encoding bits are used to replace the values, shortening the length of the stored data, thereby further reducing the space occupied by the mapping table data. When the secondary table is large, it will have a higher compression ratio. Attached Figure Description
[0038] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0039] Figure 1 This illustrates how a secondary mapping table is stored in a solid-state drive (SSD).
[0040] Figure 2 A data structure diagram of physical addresses in the mapping table data according to an embodiment of the present invention is shown;
[0041] Figure 3 A flowchart of a method for compressing mapping table data according to a first embodiment of the present invention is shown;
[0042] Figure 4 A flowchart of a method for compressing mapping table data according to a second embodiment of the present invention is shown;
[0043] Figure 5 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown. Detailed Implementation
[0044] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.
[0045] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0046] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0047] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0048] Figure 1 This illustrates how a secondary mapping table is stored in a solid-state drive.
[0049] likeFigure 1 As shown, DRAM-less solid-state drives use a two-level mapping table management method to store the mapping table. First, the logical addresses (LAAs) corresponding to the write data are grouped, and then stored according to data blocks. See also... Figure 1 On the left side, all logical addresses in the solid-state drive are divided into m+1 blocks (0 to m) and stored in the first-level mapping table. The first-level mapping table (first-level table) can be regarded as an array L1[m+1] with m+1 elements. The array L1[m+1] points to (m+1) cells, which are located on the storage unit of the DRAM-less solid-state drive (e.g., flash memory) and are used to store the second-level mapping table. Each second-level mapping table contains the mapping relationship between multiple logical addresses and multiple physical addresses. Assuming that each data block (each group) in the first-level mapping table has x logical addresses, then LAA0~LAA(x-1) is the 0th block, and LAA x~LAA(2x-1) is the first block. Taking L1[1] as an example, it points to a certain FAA (FlashAccess Agent) in the flash memory. The cells of the FAA store the mapping relationship between FAA0~FAA(x-1), that is, the FAA corresponding to LAA0~LAA(x-1) are stored in order. However, since the logical addresses LAA0 to LAA(x-1) are numerically consecutive, in some implementations, each cell can store the secondary mapping table as follows: first, store the logical starting address LAA0 (the first logical address), and then store the corresponding FAA0 to FAA(x-1) sequentially. Each cell has a fixed size, for example, 4KB. Assuming a secondary table requires one or two 4KB units, the secondary mapping table will occupy (m+1)*4KB or 2(m+1)*4KB of flash memory space. This method of storing all FAAs in flash memory consumes a large amount of flash memory space and has a large write amplification. In practical applications, the inventors found that many of the physical addresses stored in the aforementioned 4KB cells are numerically consecutive. Therefore, multiple consecutive physical addresses can be compressed, for example, by replacing the original multiple physical addresses with the first physical address and consecutive count values, thereby reducing the space occupied by the secondary mapping table. In numerous practical applications, the inventors also discovered that when compressing physical addresses based on data continuity, the compression rate is relatively low if the continuity is low.
[0050] Therefore, this invention proposes a method for compressing mapping table data. Based on the characteristics of writing mapping table data to flash memory, the physical address is split according to different domain address types. Each domain address of multiple physical addresses forms a set. By selecting a specific compression method for each set and compressing it individually, a higher compression ratio can be achieved, while also reducing flash memory space usage, decreasing write amplification of the solid-state drive, and improving read performance. This method is particularly suitable for compressing two-level mapping tables. The following specific embodiments illustrate the mapping table data compression method of this invention.
[0051] Figure 2 A data structure diagram of physical addresses in the mapping table data according to an embodiment of the present invention is shown.
[0052] according to Figure 1 In this storage method, two 4KB units can store 2048 FAAs. Each FAA occupies 4 bytes of space, so the physical address description is usually represented using 32 bits. Furthermore, flash memory typically includes multiple DIEs (LUNs), each DIE can include two Planes (Plane0 and Plane1), each Plane includes multiple Blocks, each Block includes multiple Pages, and each Page has multiple page offsets (Fragments). The physical address FAA is usually composed of the addresses of these different fields. These different field addresses can be used to locate the specific physical location of the data stored in the flash memory. For example... Figure 2 As shown, an FAA is typically composed of Blocks, Pages, LUNs (i.e., Dies), and Fragments. These can all be considered as different types of domain addresses contained in a physical address, with each type of domain address occupying a few bits in the FAA. A physical address can be divided into multiple segments based on the different types of domain addresses it contains, with each segment containing at least one type of domain address.
[0053] Figure 3 A flowchart of a method for compressing mapping table data according to a first embodiment of the present invention is shown, which specifically includes the following steps.
[0054] In step S101, each physical address is divided into multiple segments according to the types of domain addresses contained in the physical address, and each segment contains at least one type of domain address.
[0055] The compression method of this embodiment can be applied to solid-state drives (SSDs). An SSD includes a controller and a flash memory. The flash memory has multiple cells for storing mappings between multiple logical addresses and multiple physical addresses. The compression method of this embodiment is used to compress the mapping table data in each cell. Specifically, the mapping table data includes multiple physical addresses (FAAs), and each physical address (FAA) includes multiple types of domain addresses.
[0056] In this step, each physical address is split into multiple segments according to the different types of domain addresses. See [link to relevant documentation]. Figure 2 The physical address FAA contains different types of domain addresses, including block address, page address, LUN code, and page offset. Therefore, the physical address can be divided into four segments, each containing one type of domain address. Thus, each segment of a physical address corresponds to one of the following types of domain addresses: block address, page address, LUN code, or page offset. Alternatively, the physical address can be divided into three segments, with one segment containing both LUN code and page offset domain addresses, and the other two segments containing either block address or page address domain addresses. Of course, the physical address can also be divided into different segments, each containing at least one type of domain address, depending on the specific requirements.
[0057] In step S102, segments containing the same type of domain address in each of the multiple physical addresses are respectively grouped into sets corresponding to the domain address.
[0058] In the previous step, each physical address in the mapping table information was split in the same segmentation method. In this step, segments of multiple physical addresses with the same type of domain address are combined to form a set corresponding to the corresponding domain address. For example, all block addresses corresponding to all physical addresses are combined into a Block set, which contains all block addresses corresponding to all physical addresses, and all page addresses corresponding to all physical addresses are combined into a Page set, etc.
[0059] In step S103, consecutive field addresses in multiple field addresses within each set are compressed.
[0060] In this step, each set is compressed individually, mainly focusing on compressing consecutive field addresses. Since different types of field addresses have different contiguous patterns, different compression methods can be used for sets corresponding to different types of field addresses, or the same compression method can be used. Examples are provided below.
[0061] Assuming a 4TB (4096GB) solid-state drive, a secondary mapping table of 8KB size, with each FAA occupying 4 bytes, then a secondary mapping table contains 2048 FAAs. In the data structure corresponding to the physical address FAA, the block width is 11 bits, the page width is 12 bits, the LUN width is 3 bits, and the Frag width is 4 bits. To compress a certain secondary mapping table, first, a memory space is allocated in SRAM to store the compressed secondary mapping table data. The physical addresses are segmented according to Block, Page, LUN, and Frag and grouped into corresponding sets. Then, each set is compressed sequentially.
[0062] When compressing a domain address, a contiguous flag and a numeric bit need to be set for the domain address. A contiguous flag of 1 indicates that the domain address is contiguous, and a contiguous flag of 0 indicates that the domain address is not contiguous. The numeric bit is used to store the value of the domain address. When the contiguous flag is 1, a contiguous count value is also stored after the value of the domain address. The contiguous count value represents the number of consecutive domain addresses.
[0063] In this step, the compression methods for consecutive domain addresses differ depending on the type of domain address. A targeted compression method can be applied to the set based on the different characteristics of each type of domain address. For example, in the sets corresponding to block addresses, page addresses, and LUN codes, consecutive domain addresses are multiple consecutive domain addresses with the same value (Block1, Block1, Block1…); while in the set corresponding to page offsets, consecutive domain addresses are multiple consecutive domain addresses with consecutive values (Frag1, Frag2, Frag3…). For instance, the set of Blocks is compressed first, using 12 bits to store the Block compression information. The lower 11 bits are used as the value bits to store the Block's value, and the highest bit is used as a continuity flag to store the continuity count. If the highest bit is 1, it indicates that the 8 bits following the value bits store the continuity count; if the highest bit is 0, it indicates that the 11 bits following the highest bit store non-consecutive Block values. Alternatively, the continuity flag can be placed after the value bits, and the order is not limited, but to save storage space, the continuity count is only stored after the consecutive domain addresses.
[0064] In this embodiment, compressing consecutive field addresses in multiple field addresses in each set includes: setting the consecutive count value of the field addresses contained in the first physical address to 1; determining whether the field address contained in the (i+1)th physical address is consecutive to the field address contained in the ith physical address, where i is an integer greater than or equal to 1.
[0065] If the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address, the consecutive count value is incremented by 1 until the domain address contained in the nth physical address is not consecutive to the domain address contained in the (n-1)th physical address. Then, the value of the domain address contained in the (n-1)th physical address is updated to the value bit of the cache unit, the consecutive flag before the value bit is set to 1, and the consecutive count value is stored after the value bit, where n>i. Then, the consecutive count value is set to 1.
[0066] If the domain address contained in the (i+1)th physical address is not contiguous with the domain address contained in the ith physical address, and the domain address contained in the ith physical address is not contiguous with the domain address contained in the (i-1)th physical address, then update the value of the domain address contained in the ith physical address to the value bit of the cache unit, set the contiguous flag bit before the value bit to 0, and then set the contiguous count value to 1; sequentially perform the step of judging whether the domain address contained in the (i+1)th physical address is contiguous with the domain address contained in the ith physical address for multiple domain addresses in the set, until all domain addresses have been judged.
[0067] Specifically, the block value of the first FAA in the block set is retrieved, and the continuity count is set to 1. The block value of the second FAA is then retrieved, and it is checked whether it is continuous with the previous FAA's block value (i.e., whether it is the same as the previous FAA's block value). If they are the same, they are continuous. If continuous, the continuity count is incremented by 1, and the process continues to check the continuity of the next FAA's block value until a non-contiguous domain address appears. The block value of the previous FAA at that non-contiguous domain address and the continuity count are then updated in memory, with the highest bit set to 1, and the continuity count is set back to 1. If they are not continuous, the block value of the previous FAA is written into memory, with its highest bit set to 0, and the continuity count is reset to 1. The block value of the third FAA is then retrieved, and its continuity with the previous FAA's block value is checked. If the blocks are consecutive, increment the consecutive count by 1; if they are not consecutive and the consecutive count is 1, write the block value of the previous FAA into memory with its highest bit set to 0, and then set the consecutive count to 1; if they are not consecutive and the consecutive count is greater than 1, store the block value of the previous FAA and the consecutive count in memory.
[0068] In another embodiment, compressing consecutive field addresses in multiple field addresses in each set includes: setting the consecutive count value of the field addresses contained in the first physical address to 1; determining whether the field address contained in the (i+1)th physical address is consecutive to the field address contained in the ith physical address, where i is an integer greater than or equal to 1;
[0069] If the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address, and the consecutiveness count is 1 (i.e., the domain address contained in the ith physical address is not consecutive to the domain address contained in the (i-1)th physical address), then update the Block value to the numeric bits in memory (update the value of the domain address contained in the (i+1)th physical address to the numeric bits in the cache unit), set the consecutiveness flag before the numeric bits to 1, and then increment the consecutiveness count by 1.
[0070] If the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address, and the consecutive count value is greater than 1 (i.e., the domain address contained in the ith physical address is consecutive to the domain address contained in the (i-1)th physical address), then increment the consecutive count value by 1.
[0071] If the domain address contained in the (i+1)th physical address is not contiguous with the domain address contained in the ith physical address, and the contiguous count is 1 (i.e., the domain address contained in the ith physical address is not contiguous with the domain address contained in the (i-1)th physical address), then update the previous Block value to the value bits in memory (update the value of the domain address contained in the ith physical address to the value bits in the cache unit), set the contiguous flag before the value bits to 0, and then set the contiguous count to 1.
[0072] If the domain address contained in the (i+1)th physical address is not contiguous with the domain address contained in the ith physical address, and the contiguous count value is greater than 1 (i.e., the domain address contained in the ith physical address is contiguous with the domain address contained in the (i-1)th physical address), store the contiguous count value at this time, and then set the contiguous count value to 1.
[0073] Specifically, the block value of the first FAA in the block set is retrieved, and the continuity count is set to 1. The block value of the second FAA is then retrieved, and it is determined whether it is continuous with the previous FAA's block value (i.e., whether it is the same as the previous FAA's block value). If they are the same, they are continuous. If they are continuous and the continuity count is 1, the current block value (the second FAA's block value) is updated in memory with its highest bit set to 1, and the continuity count is incremented by 1. If they are not continuous and the continuity count is 1, the block value of the previous FAA (the first FAA's block value) is written into memory with its highest bit set to 0, and the continuity count is reset to 1. The block value of the third FAA is then retrieved, and its continuity with the previous FAA's block value is checked. If the consecutive count is 1, then update the current Block value (the Block value of the third FAA) in memory, setting its highest bit to 1, and increment the consecutive count by 1. If the consecutive count is greater than 1, then increment the consecutive count by 1. If the consecutive count is not 1, then write the previous FAA's Block value (the Block value of the second FAA) into memory, setting its highest bit to 0, and set the count to 1. If the consecutive count is not 1, then store the current consecutive count in the next 8-bit space adjacent to the count value in memory, and then reset the consecutive count to 1.
[0074] Furthermore, each domain address in the Block set is checked one by one, and the compressed set is updated to memory, cache unit or other storage unit. In this embodiment, it can be updated to SRAM first, and then transferred to flash memory after all sets are compressed.
[0075] In step S104, the compressed sets are stored in the cache unit in the order of the split segments.
[0076] In this step, the sets corresponding to each domain address are compressed sequentially according to the order of splitting the time domain addresses, and the compressed data is stored in the cache unit (SRAM). When the physical address is divided into 4 segments, the Page set and LUN set are compressed in the same way as the Block set, with the same value used as the domain address contiguous. The Frag set is compressed in a different way, with the domain address contiguous as the value contiguous (i.e., the current Frag value is equal to the Frag value of the previous FAA plus one, and 'a' and 'a+1' are considered contiguous). In the compressed Frag set, the Frag corresponding to the first contiguous domain address can be stored in the contiguous domain address, followed by the contiguous count value of the contiguous domain address, while the corresponding Frag is directly stored in the non-contiguous domain address. The Page set is compressed in the same way as the Block set, and its compressed data immediately follows the compressed data of the Block set. Then, the compressed data of the LUN set is stored after the Page set, and the compressed data of the Frag set is stored after the LUN set.
[0077] If the domain addresses of both LUN and Frag are in the same set, then the contiguousness of the domain addresses is determined by whether the Frags are contiguous. The compressed data of the set consisting of LUN and Frag is then stored in the Page set.
[0078] The above steps complete the mapping table data compression method of this embodiment. Using the example above, for instance, the data that previously required two 4KB blocks of space can be compressed to only one 4KB block or even less, achieving a compression rate of over 50%. This new storage method can save at least half of the storage space. Therefore, the mapping table data compression method provided in this embodiment of the invention splits each physical address into multiple segments based on the type of domain addresses contained within the physical address. Segments containing the same type of domain addresses in multiple physical addresses form sets corresponding to the domain addresses. Each set is then compressed individually. Finally, the compressed sets are stored in the cache unit according to the order of the split segments. This compression method segments each piece of data in the mapping table, resulting in an extremely high compression rate. This significantly reduces the storage space occupied by the mapping table, reduces write amplification, and extends the lifespan of the memory and related devices.
[0079] Furthermore, after splitting the physical addresses, a targeted compression method is selected according to the characteristics of each set. Different compression methods are used for sets corresponding to different types of domain addresses to further improve the compression ratio and reduce the storage space occupied by the mapping table. The compression method in this embodiment greatly saves the storage space occupied by the mapping table data, while reducing the number of reads from the flash memory, improving the read performance of the flash memory and the lifespan of the solid-state drive, and reducing write amplification.
[0080] The present invention also provides another embodiment, such as Figure 4 As shown, Figure 4 A flowchart of a method for compressing mapping table data according to a second embodiment of the present invention is shown, which specifically includes the following steps:
[0081] In step S201, each physical address is divided into multiple segments according to the types of domain addresses contained in the physical address, and each segment contains at least one type of domain address.
[0082] In step S202, segments containing the same type of domain address in each of the multiple physical addresses are respectively grouped into sets corresponding to the domain address.
[0083] Steps S201-S202 are the same as steps S101-S102 in the first embodiment, and will not be described again. In this embodiment, for example, the physical address is split into Block, Page, LUN+Frag, and each is composed of a different set for separate compression.
[0084] In step S203, different encoding bits are set for different values of the field address in each set.
[0085] This step is primarily applicable to the compression of Block and Page sets. In practical applications, for a two-level mapping table, the actual number of Block values involved in all FAAs is far less than the allocated bit width. For example, a Block with a bit width of 9 bits can represent 512 (2^9) Block values, but this two-level mapping table may only have 8 Block values. These 8 values may appear at different frequencies in the two-level mapping table. Simply re-encoding would lead to a waste of bits, so the Huffman compression algorithm can be used. The frequency of the domain address of each different value in the set is statistically analyzed, and different encoding bits are set using the Huffman algorithm. Huffman encoding compresses each value, given an encoding bit, and after using Huffman encoding, continuous data is also compressed simultaneously, resulting in a higher compression ratio in this embodiment. The following example illustrates this: There is a 4TB solid-state drive, a two-level mapping table of 8KB size, storing 2048 FAAs, where the Block bit width is 11, the Page bit width is 12, the LUN bit width is 3, and the Frag bit width is 4.
[0086] First, assume that all the Block values in this secondary mapping table are extracted to form a data set:
[0087] aaaaacccbaabcbbbbbbbaaabccaccccaaabacaaaaaccccccccaaaccca
[0088] The frequencies of different values in a Block are now statistically analyzed, and consecutive occurrences and isolated occurrences of the same value are also distinguished. For example, consecutive occurrences of 'a' are marked as 'a' (the number of consecutive occurrences is greater than or equal to 2). The frequency ranking of each value in the above dataset is shown in Table 1 below:
[0089] Block value Frequency of occurrence (times) a’ 6 c’ 5 b 4 a 3 c 2 b’ 1
[0090] Table 1
[0091] Furthermore, based on the frequencies obtained in Table 1 and the Huffman algorithm, a Huffman coding binary tree is constructed. From the constructed binary tree, the coded bits corresponding to each domain address can be obtained, as shown in Table 2 below:
[0092]
[0093]
[0094] Table 2
[0095] In this embodiment, setting different encoding bits for different values of the domain address in each set includes: setting different encoding bits for consecutively occurring and individually occurring identical values; the consecutive flag bit for consecutively occurring values is 1, and the consecutive flag bit for individually occurring values is 0. If the Block value found in the encoding bit table when reading data has a consecutive meaning, then the following 8 bits represent the consecutive count value. That is, each Block value has a flag indicating whether it is consecutive. For example, the consecutive flag bit (flag) of a' is 1. When a' is found in the encoding bit table, its consecutive flag bit is 1, and the following 8 bits store the consecutive count value.
[0096] In step S204, consecutive field addresses in multiple field addresses within each set are compressed.
[0097] This step specifically includes: storing the encoding bits of the domain address into the numerical bits of the cache unit, and storing consecutive count values after the encoding bits corresponding to consecutive domain addresses.
[0098] This step uses the encoded bits of the domain address to replace the numerical value of the domain address for storage. For example, the first 20 values in the above data set, aaaaacccbaabcbbbbbb, have the encoded value: 000000101111000000111010000000101011101110000000111. The following uses spaces to separate the encoded values to explain the meaning of each encoded value: 000000101 111 00000011 101 0 00000010 101 1101 1100 00000111 (51 bits) corresponds to: the encoding bit of a', where the number of consecutive a's is 5; the encoding bit of c', where the number of consecutive c's is 3; the encoding bit of b, the encoding bit of a', where the number of consecutive a's is 2; the encoding bit of b, the encoding bit of c, the encoding bit of b', where the number of consecutive b's is 7.
[0099] Following the example above, the Block collection can be compressed, and the compressed data can be stored in the cache unit.
[0100] In step S205, the compressed sets are stored in the cache unit in the order of the split segments.
[0101] In this step, each set is compressed sequentially. The Page set uses the same compression method as the Block set. In the LUN+Frag set, LUN and Frag are treated as a single unit, resulting in consecutive values. Therefore, a continuous counting method is used, compressing according to numerical continuity (Frag a and Frag a+1 are consecutive). 8 bits are used to store the data, with the highest bit storing a continuity flag to indicate whether the data is consecutive. The lower 7 bits store LUN and Frag information. If the highest bit is 1, it indicates consecutive data, and the following 8 bits store the continuity count; if the highest bit is 0, it indicates non-consecutive data, and the next 8 bits store the next valid data.
[0102] The cache unit storing multiple collections also stores header information, which contains the correspondence between the field address values (Block value / Page value) and the encoded bits. Therefore, the compressed data consists of four parts: header information, the compressed result of the Block collection, the compressed result of the Page collection, and the compressed results of the LUN and Frag collections.
[0103] and Figure 3 Compared to the previous embodiment, this embodiment adds encoding bits to replace the numerical values for storage. As can be seen from the above embodiments, the number of bits in the encoding bits is much smaller than the number of bits occupied by the domain address. Using encoding bits to replace the numerical values of the domain address for storage can further reduce the space occupied by the data and improve the compression ratio of the mapping table data. When the secondary table data is large, the compression method of this embodiment can achieve a higher compression ratio, thereby saving a lot of storage space for the solid-state drive and improving the response speed of the solid-state drive. It is understood that other encoding methods can also be used to set encoding bits for the domain address, replacing the numerical values of the domain address with encoding bits.
[0104] Figure 5 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown.
[0105] like Figure 5 As shown, the computer system 100 includes a host 110 and a solid-state drive (SSD). The SSD is a memory hard drive made of solid-state electronic storage chips. The SSD includes a controller 120 and a storage medium 130, such as a flash memory. The controller 120 is connected to the host 110 and is used to exchange write data with the host 110. The storage medium 130 is, for example, a NAND flash memory array. The controller 120 connects the host 110 and the flash memory 130, storing the write data from the host 110 into the flash memory 130. The controller 120 is used to perform the above-described... Figure 3-4 A method for compressing mapping table data.
[0106] The controller 120 includes a host interface 121, a processor 123, a cache unit 124, and a memory controller 128. The host interface 121 of the control system 120 is connected to the host 110 to transmit write data and read / write commands. The processor 123 is connected to the host interface 121, the cache unit 124, and the memory controller 128. The processor 123 is used, for example, to execute the aforementioned compression method. The cache unit 124 is, for example, SRAM, which stores a first-level mapping table corresponding to the write data, and stores mapping table data corresponding to the first-level mapping table. The mapping table data is a second-level mapping table. The memory controller 128 controls the transmission and storage of write data. The processor 123 is also used to implement the core software layer for memory control, namely the FTL (flash translation layer), enabling the operating system and file system to access the memory like a hard drive. This FTL also has features such as support for bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.
[0107] Storage medium 130 includes a flash memory chip array. To improve data read / write performance, the memory controller 128 of controller 120 can read and write to the flash memory chips of storage medium 130 via multiple channels (e.g., CH0 and CH2), with each channel connected to a group of flash memory chips. Controller 120 is also used to store the compressed secondary mapping table in cache unit 124 into physical blocks (131 or 132) of storage medium 130 to prevent data loss and facilitate the recovery of mapping table data.
[0108] In summary, the mapping table data compression method and solid-state drive provided in this application improve the compression ratio of mapping table data, reduce the occupation of flash memory space and the number of flash memory reads, reduce the write amplification of the solid-state drive, and extend the service life of the solid-state drive. Moreover, the compression algorithm is simple, computationally inefficient, and easy to implement. It can be implemented in software with minimal pressure on the solid-state drive, or it can be implemented in hardware with simple design and high compatibility.
[0109] It should be understood that the above method can be applied not only to solid-state drives (SSDs) but also to other types of storage devices such as eMMC and UFS. Like SSDs, eMMC and UFS storage devices have controllers and cache units, and the controller can implement the above method.
[0110] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for compressing mapping table data, wherein the mapping table data includes multiple physical addresses, The compression method includes: Each physical address is divided into multiple segments according to the types of domain addresses contained in the physical address. Each segment contains at least one type of domain address. The different types of domain addresses include block addresses, page addresses, LUN codes, and page offsets. Each of the plurality of physical addresses contains segments of the same type of domain address, which are then grouped into sets corresponding to the domain address. Compress consecutive field addresses among the multiple field addresses in each set; and The compressed sets are stored in the cache unit in the order of the split segments. In the sets corresponding to the block address, the page address, and the LUN encoding, the consecutive field address is a set of multiple field addresses with the same value that are sequentially adjacent; in the set corresponding to the page offset, the consecutive field address is a set of multiple field addresses with consecutive values that are sequentially adjacent.
2. The compression method according to claim 1, wherein, Each of the physical addresses is divided into multiple segments, each corresponding to one of the following domain addresses: the block address, the page address, the LUN code, and the page offset.
3. The compression method according to claim 1, wherein, One of the segments into which each physical address is split contains both the LUN encoding and the page offset domain address.
4. The compression method according to claim 1, wherein, The sets of domain addresses of different types do not compress the consecutive domain addresses in exactly the same way.
5. The compression method according to claim 1, wherein, In the compressed set, each domain address contains a continuity flag bit and a value bit. The continuity flag bit being 1 indicates that the domain address is continuous, and the continuity flag bit being 0 indicates that the domain address is not continuous. The value bit is used to store the value of the domain address.
6. The compression method according to claim 5, wherein, When the continuity flag is 1, the domain address value is followed by a continuity count value, which represents the number of consecutive domain addresses.
7. The compression method according to claim 6, wherein, Compressing consecutive field addresses among multiple field addresses in each set includes: Set the consecutive count value of the domain addresses contained in the first physical address to 1; Determine whether the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address, where i is an integer greater than or equal to 1; If the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address, then the consecutive count value is incremented by 1 until the domain address contained in the nth physical address is not consecutive to the domain address contained in the (n-1)th physical address. Then, the value of the domain address contained in the (n-1)th physical address is updated to the value bit of the cache unit, the consecutive flag position before the value bit is set to 1, and the consecutive count value is stored after the value bit, where n>i. Then, the consecutive count value is set to 1. If the domain address contained in the (i+1)th physical address is not contiguous with the domain address contained in the ith physical address, and the domain address contained in the ith physical address is not contiguous with the domain address contained in the (i-1)th physical address, then the value of the domain address contained in the ith physical address is updated to the value bit in the cache unit, the contiguous flag position before the value bit is set to 0, and the contiguous count value is set to 1; and The step of determining whether the domain address contained in the (i+1)th physical address is consecutive to the domain address contained in the ith physical address is performed sequentially on multiple domain addresses in the set until all domain addresses have been determined.
8. The compression method according to claim 6, further comprising, before the step of compressing consecutive field addresses among the plurality of field addresses in each set: Different encoding bits are set for different values of the domain address in each set.
9. The compression method according to claim 8, wherein, Setting different encoding bits for different values of the domain address in each set includes: setting different encoding bits for consecutively occurring and individually occurring identical values, wherein the consecutive flag bit of consecutively occurring values is 1, and the consecutive flag bit of individually occurring values is 0.
10. The compression method according to claim 9, wherein compressing consecutive field addresses among a plurality of field addresses in each set comprises: The encoding bits of the domain address are stored in the numerical bits of the cache unit, and the consecutive count value is also stored after the encoding bits corresponding to the consecutive domain addresses.
11. The compression method according to claim 8, wherein, Setting different encoding bits for different values of the domain address in each set includes: counting the frequency of occurrence of the domain address with each different value in the set, and setting different encoding bits using the Huffman algorithm.
12. The compression method according to claim 8, wherein, The cache unit storing multiple sets also stores header information, which includes the correspondence between the field address value and the encoding bit.
13. A controller, comprising: A processor, connected to a host, is configured to receive write data from the host and execute the compression method according to any one of claims 1-12; A cache unit, connected to the processor, is used to store the write data. The cache unit is also used to store a first-level mapping table corresponding to the write data, and to store mapping table data corresponding to the first-level mapping table. The mapping table data is a second-level mapping table.
14. A memory comprising: The controller according to claim 13; A storage medium, connected to the controller, is used to store write data according to the control of the controller.