Memory and method of operating the same

Abstract

A memory and an operating method thereof, the memory includes a memory device, a reading device, and a feedback device. The memory device stores a plurality of bits. The reading device includes a first reading circuit and a second reading circuit coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first reading circuit and the second reading circuit cooperate with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first reading circuit and the second reading circuit generate a second voltage signal corresponding to the plurality of bits after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device, the second voltage signal being different from the first voltage signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a memory and a method of operating a memory. BACKGROUND

[0002] Memories are commonly used to store data. To read the data stored in a memory, the memory generates a signal corresponding to the data stored in the memory. The voltage level of the signal corresponds to the bit value of the data. Different bit values of the data correspond to different voltage levels of the signal. By analyzing the voltage level of the signal, at least a portion of the data read can be known. SUMMARY

[0003] The present disclosure includes a memory including a memory device, a reading device, and a feedback device. The memory device is to store a plurality of bits. The reading device includes a first reading circuit and a second reading circuit. The first reading circuit is coupled to the memory device. The second reading circuit is coupled to the memory device and to the first reading circuit at a first node. The first reading circuit and the second reading circuit are to cooperate with each other to generate a first voltage signal at the first node based on at least a first bit of the plurality of bits. The feedback device is to adjust at least one of the first reading circuit and the second reading circuit based on the first voltage signal. The first reading circuit and the second reading circuit are to generate a second voltage signal corresponding to the plurality of bits after the at least one of the first reading circuit and the second reading circuit is adjusted by the feedback device, the second voltage signal being different from the first voltage signal.

[0004] The present disclosure includes a memory including a memory device, a reading device, a sensing device, and a feedback device. The reading device is coupled to the memory device and is to read data stored in the memory device to generate a first voltage signal, the first voltage signal corresponding to a first voltage distribution curve. The sensing device is to sense the first voltage signal and is to generate a plurality of digital signals, the digital signals corresponding to the sensed first voltage signal. The feedback device is to generate at least one control signal in response to the digital signals for controlling the reading device to generate a second voltage signal, the second voltage signal corresponding to a second voltage distribution curve different from the first voltage distribution curve.

[0005] The present disclosure includes a method of operating a memory, including: generating, by a complementary metal oxide semiconductor (CMOS) circuit, a first voltage signal associated with data stored in a memory device, wherein a voltage level of the first voltage signal corresponds to a first voltage distribution curve; reading out the first voltage signal to generate a digital signal associated with at least one first bit of the data; and controlling the CMOS circuit to generate a second voltage signal according to the digital signal, wherein the second voltage signal corresponds to the data, and a voltage level of the second voltage signal corresponds to a second voltage distribution curve, the second voltage distribution curve having a shift from the first voltage distribution curve or having a different profile from the first voltage distribution curve. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present disclosure can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] Figure 1 A schematic diagram of a memory according to some embodiments of the present disclosure;

[0008] Figure 2 A graph of a voltage distribution curve representing a relationship between voltage levels of a voltage signal and bit values of data shown in Figure 1

[0009] Figure 3A A circuit diagram of a memory cell corresponding to the memory cell shown in Figure 1

[0010] Figure 3B A circuit diagram of a logic unit corresponding to the logic unit shown in Figure 3A

[0011] Figure 4 A circuit diagram of a memory corresponding to the memory shown in Figure 1

[0012] Figure 5 A flowchart of a method of generating a voltage signal by a memory according to some embodiments of the present disclosure; Figure 1 Figure 3A Figure 4

[0013] Figure 6A Figure 6B ​​​​​​​​to represent a voltage profile of the relationship between the voltage level of a voltage signal according to some embodiments of the present disclosure and the bit value of data shown in Figure 4 a graph to represent a voltage profile of the relationship between the voltage level of a voltage signal according to some embodiments of the present disclosure and the bit value of data shown in

[0014] Figure 6C and Figure 6D to represent a voltage profile of the relationship between the voltage level of a voltage signal according to some embodiments of the present disclosure and the bit value of data shown in Figure 4 a graph to represent a voltage profile of the relationship between the voltage level of a voltage signal according to some embodiments of the present disclosure and the bit value of data shown in

[0015] SYMBOL DESCRIPTION

[0016] 100, 300, 400: memory

[0017] 110, 310, 410: memory device

[0018] 120, 320, 420: reading device

[0019] 122, 124, 322, 324, 422, 424: reading circuit

[0020] 130, 330, 430: readout device

[0021] 140, 340, 440: feedback device

[0022] 200, 600A, 600B, 600C, 600D: graph

[0023] 301, 342, 344, 442, 444, 446, 448: logic unit

[0024] 500: method DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of elements, materials, values, steps, configurations or the like are described below to simplify the present disclosure. Of course, those are merely examples and are not intended to be limiting. Other elements, materials, values, steps, configurations or the like are contemplated. For instance, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0026] In addition, for ease of description, spatially relative terms, such as "under", "below", "lower", "over", "upper", and the like, can be used herein for describing the orientation of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms mask, photomask, reticle, and pellicle are used to refer to the same item.

[0027] The terminology used throughout the following description and application claims is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present disclosure or any exemplary terms as set forth in the specification. One skilled in the art will be familiar with the fact that elements or processes can be referred to by different names. Many of the different embodiments detailed in this specification are merely illustrative and do not limit the scope and spirit of the present disclosure or the scope of any exemplary terms in any way.

[0028] Notably, terms such as "first" and "second" used herein to describe various components or processes are intended to distinguish one component or process from another component or process. However, the components, processes, and sequences thereof should not be limited by these terms. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and a second component can be similarly referred to as a first component.

[0029] In the following discussion and in the claims, the terms "including" "comprising" "having" "containing" "involving" and similar terms are to be interpreted as open-ended, i.e., not restricted to members in the listed groups only. As used herein, the term "and / or" means one or the other or both. As used herein, the term "or" means any one member of a set or none.

[0030] Figure 1 A schematic diagram of a memory 100 according to some embodiments of the present disclosure. As Figure 1 As illustratively shown in FIG. 1, the memory 100 includes a memory device 110, a read device 120, a sense device 130, and a feedback device 140. In some embodiments, the memory device 110 is implemented as a phase change random access memory (PCRAM). In some embodiments, the read device 120 is implemented as a complementary metal oxide semiconductor (CMOS) circuit. In some embodiments, the sense device 130 is implemented as a current sensing amplifier (SA).

[0031] In some embodiments, the memory device 110 is to store data DT including a plurality of bits, and to receive a voltage signal VSS. The data DT has various bit values in various embodiments. The read device 120 is to read the data DT to generate a voltage signal VS1 corresponding to the data DT. The readout device 130 is to generate a digital signal EN based on the voltage signal VS1. The feedback device 140 is to generate control signals S11 and S12 based on the digital signal EN to control the read device 120 to generate a voltage signal VS2. The voltage signal VS2 also corresponds to the data DT.

[0032] As illustratively shown in Figure 1 The read device 120 includes read circuits 122 and 124. The read circuit 122 is to receive a voltage signal VDD different from the voltage signal VSS at a node N13 and is coupled to a node N11. In some embodiments, the voltage signal VDD has a power supply voltage level, and the voltage signal VSS has a ground voltage level.

[0033] As illustratively shown in Figure 1 The read circuit 124 is coupled to the read circuit 122 at the node N11 and is coupled to the memory device 110 at a node N12. In some embodiments, the read circuits 122 and 124 correspond to two types of transistors, respectively. For example, the read circuit 122 includes P-type Metal-Oxide-Semiconductor (PMOS) transistors, and the read circuit 124 includes N-type Metal-Oxide-Semiconductor (NMOS) transistors.

[0034] In some embodiments, the read circuits 122 and 124 are to cooperate with each other to generate the voltage signals VS1 and VS2 at the node N11 based on the data DT. As illustratively shown in Figure 1 The read circuits 122 and 124 are coupled in series between the nodes N12 and N13. In some embodiments, the voltage signals VS1 and VS2 depend on the resistances of the read circuits 122 and 124. For example, when the resistance of the read circuit 122 increases and / or the resistance of the read circuit 124 decreases, the voltage levels of the voltage signals VS1 and VS2 decrease. In contrast, when the resistance of the read circuit 122 decreases and / or the resistance of the read circuit 124 increases, the voltage levels of the voltage signals VS1 and VS2 increase.

[0035] In some embodiments, read circuits 122 and 124 are used to generate a voltage signal VMSB, which is an embodiment of voltage signal VS1. The voltage signal VMSB corresponds to at least one bit of data DT, such as one or more most significant bits (MSBs).

[0036] In some embodiments, the readout device 130 is used to generate a digital signal EN based on a voltage signal VMSB. In some embodiments, the feedback device 140 is used to adjust the resistance of at least one of the readout circuits 122 and 124 based on the digital signal EN to generate a voltage signal VS2, the voltage signal VS2 having a voltage level that is at least partially different from the voltage level of the voltage signal VS1.

[0037] For example, in response to the voltage signal VMSB having a first bit value, the feedback device 140 adjusts the reading circuit 122 via the control signal S12, and in response to the voltage signal VMSB having a second bit value different from the first bit value, the feedback device 140 adjusts the reading circuit 124 via the control signal S11.

[0038] In some embodiments, after at least one of the readout circuits 122 and 124 is adjusted by the feedback device 140, the readout circuits 122 and 124 generate a voltage signal VS2. In other words, the voltage signal VS2 is an adjusted version of the voltage signal VS1.

[0039] Figure 2 To represent the voltage levels of voltage signals VS1, VS2 according to some embodiments of this disclosure, and Figure 1 Figure 200 shows the voltage distribution curves illustrating the relationship between the bit values ​​of the data DT. Figure 2 As illustrated herein, Figure 200 includes a horizontal axis and a vertical axis. See also Figure 1 and Figure 2 The horizontal axis corresponds to the bit value of data DT, and the vertical axis corresponds to the voltage level of node N11 or the voltage levels of voltage signals VS1 and VS2. In some embodiments, the bit value of data DT is referred to as the multiply-accumulated (MAC) value of data DT.

[0040] like Figure 2As illustrated, Figure 200 further includes voltage distribution curves C21 to C23. Voltage distribution curve C21 corresponds to the relationship between the voltage signal VS1 and the data DT. For example, in response to the data DT having a bit value PB, the voltage signal VS1 has a voltage level VPB1. Similarly, in response to the data DT having bit values ​​B11 to B14, the voltage signal VS1 has voltage levels V11 to V14 corresponding to the bit values ​​B11 to B14, respectively. Figure 2 In the illustrated embodiment, bit values ​​B11 and B12 are less than bit value PB, and bit values ​​B13 and B14 are greater than bit value PB. In some embodiments, bit value PB is a predetermined bit value. In some embodiments, bit values ​​B11 and B12 are two adjacent bit values, and bit values ​​B13 and B14 are two adjacent bit values. For example, bit value B11 is equal to bit value B12 minus one, and bit value B14 is equal to bit value B13 plus one.

[0041] As above Figure 1 As described in the illustrated embodiment, the feedback device 140 adjusts the voltage signal VS1 differently in response to different bit values ​​of the data DT to generate the voltage signal VS2. See also Figure 1 and Figure 2 In response to a bit value of data DT being less than bit value PB, voltage signal VS1 is adjusted along arrow A21 to generate voltage signal VS2 corresponding to voltage distribution curve C22. In other words, voltage distribution curve C22 has a shift from voltage distribution curve C21 along arrow A21, or has a different profile than voltage distribution curve C21.

[0042] See Figure 2 The voltage distribution curve C22 shown corresponds to data DT with bit values ​​B11 and B12, and voltage signal VS2 has voltage levels V21 and V22, respectively. For example... Figure 2 It is illustrated that voltage level V21 is less than voltage level V11, and voltage level V22 is less than voltage level V12. In some embodiments, the voltage level difference between voltage levels V21 and V22 is greater than the voltage level difference between voltage levels V11 and V12.

[0043] Similarly, in response to a bit value of data DT being greater than bit value PB, voltage signal VS1 is adjusted by arrow A22 to generate voltage signal VS2 corresponding to voltage distribution curve C23.

[0044] See Figure 2 The voltage distribution curve C23 shown corresponds to data DT with bit values ​​B13 and B14, and voltage signal VS2 has voltage levels V33 and V34 respectively. For example... Figure 2As illustratively shown, voltage level V33 is greater than voltage level V13, and voltage level V34 is greater than voltage level V14. In some embodiments, the voltage level difference between voltage levels V33 and V34 is greater than the voltage level difference between voltage levels V13 and V14.

[0045] In some embodiments, in response to data DT having a different bit value, reading device 120 is configured to generate a plurality of voltage signals VS1 and a plurality of voltage signals VS2. For example, one of voltage signals VS1 corresponds to bit value PB and has voltage level VPB1. For another example, one of voltage signals VS2 corresponds to bit value B11 and has voltage level V21.

[0046] Referring to Figure 1 and Figure 2 , arrows A21 and A22 correspond to control signals S11 and S12, respectively. In some embodiments, in response to data DT having a bit value greater than bit value PB, feedback device 140 is configured to adjust reading circuit 122 via control signal S12 such that adjusted reading circuit 122 and reading circuit 124 cooperate to generate voltage signals VS2 corresponding to voltage distribution curve C23. In some embodiments, in response to data DT having a bit value less than bit value PB, feedback device 140 is configured to adjust reading circuit 124 via control signal S11 such that reading circuit 122 and adjusted reading circuit 124 cooperate to generate voltage signals VS2 corresponding to voltage distribution curve C22.

[0047] In some approaches, a reading device generates voltage signals based on bit values of data stored in a memory device. However, voltage levels of the voltage signals are close to another voltage level corresponding to an adjacent bit value. Thus, it is difficult to distinguish the bit value from the adjacent bit value based on the voltage signals, and the data cannot be well read or recognized.

[0048] In contrast to the above approach, in some embodiments of the disclosure, voltage signals VS2 are generated based on bit values of data DT. Voltage distribution curves are optimized corresponding to bit values of data DT such that a voltage level difference between a voltage level (e.g., voltage level V21) corresponding to a bit value (e.g., bit value B11) and a voltage level (e.g., voltage level V22) corresponding to an adjacent bit value (e.g., bit value B12) is increased. Thus, when data DT has bit value B11, it is easy to distinguish bit value B11 from bit value B12 based on voltage signals VS2.

[0049] Figure 3A A circuit diagram of memory 300 corresponding to memory 100 shown in Figure 1 A circuit diagram of memory 300 corresponding to memory 100 shown in Figure 3AMemory 300 is illustratively shown to include memory device 310, read device 320, readout device 330, and feedback device 340. Referring to Figure 1 and Figure 3A Memory 300 is an embodiment of memory 100. Memory device 310, read device 320, readout device 330, and feedback device 340 correspond to memory device 110, read device 120, readout device 130, and feedback device 140, respectively. Accordingly, some descriptions are not repeated for the sake of brevity.

[0050] As illustratively shown in Figure 3A Memory device 110 is illustratively shown to include a plurality of memory cells MUI-MUN. It is noted that N is a positive integer. First ends of memory cells MUI-MUN are coupled to read device at node N32, and second ends of memory cells MUI-MUN are to receive voltage signal VSS at node N33. In other words, memory cells MUI-MUN are coupled in parallel between node N32 and N33. In some embodiments, each of memory cells MUI-MUN is to store one or more corresponding bits of data DT. For example, memory cell MUI stores at least one MSB of data DT.

[0051] In some embodiments, each of memory cells MUI-MUN includes phase change element PCE and switch MUS. As illustratively shown in Figure 3A Phase change element PCE and switch MUS are illustratively shown to be coupled in series between node N32 and N33.

[0052] In some embodiments, read device 320 includes read circuits 322 and 324. Referring to Figure 1 and Figure 3A Read circuits 322 and 324 are embodiments of read circuits 122 and 124. Accordingly, some descriptions are not repeated for the sake of brevity.

[0053] As illustratively shown in Figure 3A Read circuit 322 is to receive voltage signal VDD at node N34, and read circuit 324 is coupled to node N32. In some embodiments, read circuits 322 and 324 are to cooperate with each other to generate voltage signals VS1, VS2, and VMSB at node N31.

[0054] As illustratively shown in Figure 3A Read circuit 322 includes transistors P31-P33 and switch TM1. In some embodiments, transistors P31-P33 are implemented as PMOS transistors, and switch TM1 is implemented as a transmission gate.

[0055] As illustratively shown in Figure 3AThe diagram illustratively illustrates that one end of transistor P31 is coupled to node N34, and the other end of transistor P31 is coupled to node N31. One end of transistor P32 is coupled to node N34, and the other end of transistor P32 is coupled to node N31. The control terminal of transistor P32 is used to receive the enable voltage signal VP. One end of transistor P33 is used to receive the voltage signal VDD, and the other end of transistor P33 is coupled to the control terminal of transistor P31 at node N35. The control terminal of transistor P33 is used to receive the control signal S31B. One end of switch TM1 is coupled to node N35, and the other end of switch TM1 is used to receive the enable voltage signal VP. The control terminal of switch TM1 is used to receive the control signal S31B, and the other control terminal of switch TM1 is used to receive the control signal S31. In some embodiments, the control signal S31 and the control signal S31B are complementary.

[0056] In some embodiments, the control terminal of transistor P33 is of a different type from the control terminal of switch TM1 that receives the control signal S31B. Therefore, transistor P33 is turned off when switch TM1 is on, and turned on when switch TM1 is off.

[0057] In some embodiments, when control signal S31 has a first voltage level, switch TM1 is turned on to transmit the enable voltage signal VP to node N35, causing transistor P31 to turn on. In some embodiments, the first voltage level is the enable voltage level of a P-type transistor and the disable voltage level of an N-type transistor. When control signal S31B has the first voltage level, transistor P33 is turned on to transmit the voltage signal VDD with the disable voltage level to node N35, causing transistor P31 to turn off. In other words, transistor P31 is controlled by control signals S31 and S31B. Embodiments for controlling transistor P31 are not limited to... Figure 3A The configurations shown are not applicable to other configurations used to control transistor P31 based on control signals S31 and S31B, which are considered to be within the scope of this disclosure.

[0058] like Figure 3A The diagram illustrates that the readout circuit 324 includes transistors M31 to M33 and a switch TM2. In some embodiments, transistors M31 to M33 are implemented as NMOS transistors, and switch TM2 is implemented as a transmission gate.

[0059] like Figure 3AAs illustratively shown, one end of transistor M31 is coupled to node N32, and the other end of transistor M31 is coupled to node N31. One end of transistor M32 is coupled to node N32, and the other end of transistor M32 is coupled to node N31, and the control end of transistor M32 is configured to receive the enable voltage signal VN. One end of transistor M33 is configured to receive the voltage signal VSS, and the other end of transistor M33 is coupled to the control end of transistor M31 at node N36, and the control end of transistor M33 is configured to receive the control signal S32. One end of switch TM2 is coupled to node N36, and the other end of switch TM2 is configured to receive the enable voltage signal VN, and the control end of switch TM2 is configured to receive the control signal S32B, and the other control end of switch TM2 is configured to receive the control signal S32.

[0060] In some embodiments, the control end of transistor M33 and the control end of switch TM2 that receives the control signal S32 are of different types. Thus, transistor M33 is turned off when switch TM2 is turned on, and transistor M33 is turned on when switch TM2 is turned off.

[0061] In some embodiments, when the control signal S32B has a second voltage level, switch TM2 is turned on to transmit the enable voltage signal VN to node N36, so that transistor M31 is turned on. In some embodiments, the second voltage level is the enable voltage level for an N-type transistor, and is the disable voltage level for a P-type transistor. When the control signal S32 has the second voltage level, transistor M33 is turned on to transmit the voltage signal VSS having the disable voltage level to node N36, so that transistor M31 is turned off. In other words, transistor M31 is controlled by the control signals S32 and S32B. Embodiments for controlling transistor M31 are not limited to the configuration shown in Figure 3A Other configurations for controlling transistor M31 based on the control signals S32 and S32B are considered to be within the scope of the present disclosure.

[0062] In some embodiments, when transistors P31 and M31 are turned off, transistors P32 and M32 are configured to generate the voltage signal VS1 based on the data DT. The voltage level of the voltage signal VS1 depends on the resistance of transistors P32 and M32. When transistor P31 is turned on and transistor M31 is turned off, transistors P31, P32 and M32 are configured to generate the voltage signal VS2 based on the data DT. Transistors P31 and P32 are coupled in parallel between nodes N34 and N31, so that the resistance between nodes N34 and N31 is reduced compared to the case where transistor P31 is turned off. Thus, the voltage level of the voltage signal VS2 is higher than the voltage level of the voltage signal VS1. Referring to Figure 3A and Figure 2 , the voltage distribution curve C23 corresponds to the case where transistor P31 is turned on.

[0063] Similarly, when the transistor M31 is on and the transistor P31 is off, the transistors M31, P32 and M32 are used to generate the voltage signal VS2 based on the data DT. The transistors M31 and M32 are coupled in parallel between the nodes N32 and N31, such that the resistance between the nodes N32 and N31 is reduced compared to the case where the transistor M31 is off. Therefore, the voltage level of the voltage signal VS2 is lower than the voltage level of the voltage signal VS1. Referring to Figure 3A and Figure 2 , the voltage distribution curve C22 corresponds to the case where the transistor M31 is on.

[0064] As illustratively shown in Figure 3A , the readout device 330 is used to read out the voltage signal VMSB to generate the digital signals EN0 and EN1. In the embodiment shown in Figure 3A , the voltage signal VMSB carries the MSB of the data DT. The MSB has a bit value of 0 or 1. In response to the MSB having a bit value of 0, the digital signal EN0 has a bit value of 1 and the digital signal EN1 has a bit value of 0. In response to the MSB having a bit value of 1, the digital signal EN0 has a bit value of 0 and the digital signal EN1 has a bit value of 1.

[0065] Referring to Figure 3A and Figure 2 , when the MSB has a bit value of 1, the bit value of the data DT is greater than the bit value PB, while when the MSB has a bit value of 0, the bit value of the data DT is less than the bit value PB. Therefore, the feedback device 340 adjusts the voltage signal VS1 along the arrow A21 when the MSB has a bit value of 0, and adjusts the voltage signal VS1 along the arrow A22 when the MSB has a bit value of 1.

[0066] As illustratively shown in Figure 3A , the feedback device 340 includes the logic units 342 and 344. The logic unit 342 is used to generate the control signals S31 and S31B based on the digital signal EN1 and the voltage signal VSS. The logic unit 344 is used to generate the control signals S32 and S32B based on the digital signal EN0 and the voltage signal VSS. In some embodiments, the voltage signal VSS has a bit value of 0. Referring to Figure 3A and Figure 1 , the control signals S31 and S31B are embodiments of the control signal S12, and the control signals S32 and S32B are embodiments of the control signal S11.

[0067] As illustratively shown in Figure 3AThe diagram illustrates that logic unit 342 includes a NOR gate NR31 and an inverter IN31. The two inputs of the NOR gate NR31 are used to receive the digital signal EN1 and the voltage signal VSS, respectively. The output of the NOR gate NR31 is used to output the control signal S31. The input of the inverter IN31 is used to receive the control signal S31. The output of the inverter IN31 is used to output the control signal S31B. Therefore, the control signal S31 has a first voltage level to turn on switch TM1 when the digital signal EN1 has a bit value of 1.

[0068] like Figure 3A The diagram illustrates that logic unit 344 includes a NOR gate NR32 and an inverter IN32. The two inputs of the NOR gate NR32 are used to receive the digital signal EN0 and the voltage signal VSS, respectively. The output of the NOR gate NR32 is used to output a control signal S32. The input of the inverter IN32 is used to receive the control signal S32. The output of the inverter IN32 is used to output a control signal S31B. Therefore, the control signal S32 has a first voltage level to turn on switch TM2 when the digital signal EN0 has a bit value of 1.

[0069] In various embodiments, logic units 342 and 344 have various configurations and include various logic components. For example, in some alternative embodiments, logic units 342 and / or 344 have... Figure 3B The configuration is similar to that of the logic unit 301 shown.

[0070] Figure 3B For some embodiments according to this disclosure, the corresponding Figure 3A The circuit diagram of logic unit 342 and logic unit 301 of 344 is shown. Figure 3B As illustrated, logic unit 301 includes an OR gate RB and an inverter INB.

[0071] In some embodiments, logic unit 342 has a similar configuration to logic unit 301. In such embodiments, the two inputs of OR gate RB are used to receive the digital signal EN1 and the voltage signal VSS, respectively. The output of OR gate RB is used to output the control signal S31B. The input of inverter INB is used to receive the control signal S31B. The output of inverter INB is used to output the control signal S31.

[0072] Similarly, in some embodiments, the logic unit 344 has a configuration similar to the logic unit 301. In such embodiments, the two inputs of the OR gate RB are used to receive the digital signal EN0 and the voltage signal VSS, respectively. The output of the OR gate RB is used to output the control signal S32B. The input of the inverter INB is used to receive the control signal S32B. The output of the inverter INB is used to output the control signal S32.

[0073] Figure 4 For corresponding to the memory 100 shown in Figure 1 the circuit diagram of the memory 400 is shown. As Figure 4 illustratively shown in Figure 1 , Figure 3A and Figure 4 , the memory 400 is an embodiment of the memory 100 and an alternative embodiment of the memory 300. The memory device 410, the reading device 420, the readout device 430 and the feedback device 440 correspond to the memory device 310, the reading device 320, the readout device 330 and the feedback device 340, respectively. Therefore, some descriptions are not repeated for the sake of brevity.

[0074] As illustratively shown in Figure 4 , the memory device 410 is used to receive the voltage signal VSS and is coupled to the node N42. The reading device 420 includes reading circuits 422 and 424. Referring to Figure 4 and Figure 3A , the reading circuits 422 and 424 are alternative embodiments of the reading circuits 322 and 324. Therefore, some descriptions are not repeated for the sake of brevity.

[0075] As illustratively shown in Figure 4 , the reading circuit 422 is used to receive the voltage signal VDD at the node N44, and the reading circuit 424 is coupled to the node N42. In some embodiments, the reading circuits 422 and 424 are used to cooperate with each other to generate the voltage signals VS1, VS2 and VMSB at the node N41.

[0076] As illustratively shown in Figure 4 , the reading circuit 422 includes transistors P41-P46 and switches TG1, TG2. In some embodiments, the transistors P41-P46 are implemented as PMOS transistors, and the switches TG1, TG2 are implemented as transmission gates.

[0077] As illustratively shown in Figure 4The first ends of the transistors P41-P44 are coupled to node N44, and the second ends of the transistors P41-P44 are coupled to node N41, as illustratively shown in FIG. 4B. In other words, the transistors P41-P44 are coupled in parallel between nodes N41 and N44. The control terminals of the transistors P43-P44 are to receive the enable voltage signal VP.

[0078] As illustratively shown in FIG. 4B, one end of the transistor P45 is to receive the voltage signal VDD, another end of the transistor P45 is coupled to the control terminal of the transistor P41 at node N45, and the control terminal of the transistor P45 is to receive the control signal S41B. One end of the switch TG1 is coupled to node N45, another end of the switch TG1 is to receive the enable voltage signal VP, the control terminal of the switch TG1 is to receive the control signal S41B, and another control terminal of the switch TG1 is to receive the control signal S41. In some embodiments, the control signal S41 and the control signal S41B are complementary. Figure 4 As illustratively shown in FIG. 4B, one end of the transistor P46 is to receive the voltage signal VDD, another end of the transistor P46 is coupled to the control terminal of the transistor P42 at node N46, and the control terminal of the transistor P46 is to receive the control signal S42B. One end of the switch TG2 is coupled to node N46, another end of the switch TG2 is to receive the enable voltage signal VP, the control terminal of the switch TG2 is to receive the control signal S42B, and another control terminal of the switch TG2 is to receive the control signal S42. In some embodiments, the control signal S42 and the control signal S42B are complementary.

[0079] Figure 4 The operation of the transistors P41, P45, and the switch TG1 based on the control signals S41 and S41B is similar to the operation of the transistors P31, P33, and the switch TM1 based on the control signals S31 and S31B as illustratively shown in FIG. 3B. The operation of the transistors P42, P46, and the switch TG2 based on the control signals S42 and S42B is similar to the operation of the transistors P31, P33, and the switch TM1 based on the control signals S31 and S31B as illustratively shown in FIG. 3B.

[0080] The operation of the transistors P41, P45, and the switch TG1 based on the control signals S41 and S41B is similar to the operation of the transistors P31, P33, and the switch TM1 based on the control signals S31 and S31B as illustratively shown in FIG. 3B. The operation of the transistors P42, P46, and the switch TG2 based on the control signals S42 and S42B is similar to the operation of the transistors P31, P33, and the switch TM1 based on the control signals S31 and S31B as illustratively shown in FIG. 3B. Figure 3A Figure 3A The operation of the transistors P41, P45, and the switch TG1 based on the control signals S41 and S41B is similar to the operation of the transistors P31, P33, and the switch TM1 based on the control signals S31 and S31B as illustratively shown in FIG. 3B. The operation of the transistors P42, P46, and the switch TG2 based on the control signals S42 and S42B is similar to the operation of the transistors P31, P33, and the switch TM1 based on the control signals S31 and S31B as illustratively shown in FIG. 3B. Therefore, some descriptions are not repeated for the sake of brevity.

[0081] As illustratively shown in FIG. 4B, the read circuit 424 includes transistors M41-M47 and switches TG3-TG5. In some embodiments, the transistors M41-M47 are implemented as NMOS transistors, and the switches TG3-TG5 are implemented as transmission gates. Figure 4 As illustratively shown in FIG. 4B, the read circuit 424 includes transistors M41-M47 and switches TG3-TG5. In some embodiments, the transistors M41-M47 are implemented as NMOS transistors, and the switches TG3-TG5 are implemented as transmission gates.

[0082] Figure 4 ​​​As illustratively shown, a first end of transistors M41-M44 is coupled to node N42, and a second end of transistors M41-M44 is coupled to node N41. In other words, transistors M41-M44 are coupled in parallel between nodes N41 and N42. A control end of transistor M44 is to receive an enable voltage signal VN.

[0083] As illustratively shown, a first end of transistors M41-M44 is coupled to node N42, and a second end of transistors M41-M44 is coupled to node N41. In other words, transistors M41-M44 are coupled in parallel between nodes N41 and N42. A control end of transistor M44 is to receive an enable voltage signal VN. Figure 4 As illustratively shown, a first end of transistors M41-M44 is coupled to node N42, and a second end of transistors M41-M44 is coupled to node N41. In other words, transistors M41-M44 are coupled in parallel between nodes N41 and N42. A control end of transistor M44 is to receive an enable voltage signal VN.

[0084] As illustratively shown, a first end of transistors M41-M44 is coupled to node N42, and a second end of transistors M41-M44 is coupled to node N41. In other words, transistors M41-M44 are coupled in parallel between nodes N41 and N42. A control end of transistor M44 is to receive an enable voltage signal VN. Figure 4 As illustratively shown, a first end of transistors M41-M44 is coupled to node N42, and a second end of transistors M41-M44 is coupled to node N41. In other words, transistors M41-M44 are coupled in parallel between nodes N41 and N42. A control end of transistor M44 is to receive an enable voltage signal VN.

[0085] As illustratively shown, a first end of transistors M41-M44 is coupled to node N42, and a second end of transistors M41-M44 is coupled to node N41. In other words, transistors M41-M44 are coupled in parallel between nodes N41 and N42. A control end of transistor M44 is to receive an enable voltage signal VN. Figure 4 As illustratively shown, a first end of transistors M41-M44 is coupled to node N42, and a second end of transistors M41-M44 is coupled to node N41. In other words, transistors M41-M44 are coupled in parallel between nodes N41 and N42. A control end of transistor M44 is to receive an enable voltage signal VN.

[0086] Transistors M41, M45, and switch TG3 operate based on control signals S44 and S44B similarly to transistors M31, M33, and switch TM2 operating based on control signals S32 and S32B as shown in FIG. 3. Figure 3A Transistors M42, M46, and switch TG4 operate based on control signals S43 and S43B similarly to transistors M31, M33, and switch TM2 operating based on control signals S32 and S32B as shown in FIG. 3. Figure 3AThe operation of the control signals S32 and S32B shown in FIG. 32 is similar. The operation of the transistors M43, M47 and the switch TG5 based on the control signals S43 and S43B is similar to the operation of the transistors M31, M33 and the switch TM2 based on the control signals S31 and S31B Figure 3A The operation of the control signals S32 and S32B shown in FIG. 32 is similar. Therefore, some descriptions are not repeated for the sake of brevity.

[0087] In various embodiments, each of the read circuits 422 and 424 includes various numbers of transistors according to the electrical characteristics of the transistors and the specifications of the read circuits 422 and 424.

[0088] As Figure 4 As illustratively shown in FIG. 34, the readout device 430 is to read out the voltage signal VMSB to generate the digital signals EN00, EN01, EN10 and EN11. In Figure 4 In the embodiment shown in FIG. 34, the voltage signal VMSB carries two MSBs of the data DT. Each of the two MSBs has a bit value of 0 or 1. The two MSBs have a bit value of 00, 01, 10 or 11. In response to the two MSBs having a bit value of 00, the digital signal EN00 has a bit value of 1, and each of the digital signals EN01, EN10 and EN11 has a bit value of 0. In response to the MSBs having a bit value of 01, the digital signal EN01 has a bit value of 1, and each of the digital signals EN00, EN10 and EN11 has a bit value of 0. In response to the MSBs having a bit value of 10, the digital signal EN10 has a bit value of 1, and each of the digital signals EN00, EN01 and EN11 has a bit value of 0. In response to the MSBs having a bit value of 11, the digital signal EN11 has a bit value of 1, and each of the digital signals EN00, EN10 and EN01 has a bit value of 0.

[0089] Referring to Figure 4 and Figure 2 When the two MSBs have a bit value of 11 or 10, the bit value of the data DT is greater than the bit value PB, and when the two MSBs have a bit value of 00 or 01, the bit value of the data DT is less than the bit value PB. Therefore, the feedback device 440 adjusts the voltage signal VS1 along the arrow A21 when the two MSBs have a bit value of 00 or 01, and adjusts the voltage signal VS1 along the arrow A22 when the two MSBs have a bit value of 11 or 10.

[0090] As Figure 4The feedback device 440 is illustratively shown to include logic units 442, 444, 446, and 448. The logic unit 442 is to generate control signals S41 and S41B based on the digital signal EN11 and the voltage signal VSS. The logic unit 444 is to generate control signals S44 and S44B based on the digital signal EN00 and the voltage signal VSS. In some embodiments, the voltage signal VSS has a bit value of 0. As Figure 4 The logic unit 446 is illustratively shown to generate control signals S42 and S42B based on the digital signals EN11 and EN10. The logic unit 448 is to generate control signals S43 and S43B based on the digital signals EN00 and EN01. Referring to Figure 4 and Figure 1 The control signals S41, S41B, S42, and S42B are embodiments of the control signal S12, and the control signals S43, S43B, S44, and S44B are embodiments of the control signal S11.

[0091] As Figure 4 The logic unit 442 is illustratively shown to include a NOR gate NR41 and an inverter IN41. Two inputs of the NOR gate NR41 are to receive the digital signal EN11 and the voltage signal VSS, respectively. An output of the NOR gate NR41 is to output the control signal S41. An input of the inverter IN41 is to receive the control signal S41. An output of the inverter IN41 is to output the control signal S41B. Thus, the control signal S41 has a first voltage level to turn on the switch TG1 when the digital signal EN11 has a bit value of 1.

[0092] As Figure 4 The logic unit 444 is illustratively shown to include a NOR gate NR44 and an inverter IN44. Two inputs of the NOR gate NR44 are to receive the digital signal EN00 and the voltage signal VSS, respectively. An output of the NOR gate NR44 is to output the control signal S44. An input of the inverter IN44 is to receive the control signal S44. An output of the inverter IN44 is to output the control signal S44B. Thus, the control signal S44 has a first voltage level to turn on the switch TG3 when the digital signal EN00 has a bit value of 1.

[0093] As Figure 4As illustratively shown in FIG. 44, logic unit 446 includes a NOR gate NR42 and an inverter IN42. Two inputs of NOR gate NR42 are to receive digital signals EN11 and EN10, respectively. An output of NOR gate NR42 is to output a control signal S42. An input of inverter IN42 is to receive control signal S42. An output of inverter IN42 is to output a control signal S42B. Thus, control signal S42 has a first voltage level to turn on switch TG2 when one of digital signals EN11 and EN10 has a bit value of 1.

[0094] As illustratively shown in FIG. 44, logic unit 446 includes a NOR gate NR42 and an inverter IN42. Two inputs of NOR gate NR42 are to receive digital signals EN11 and EN10, respectively. An output of NOR gate NR42 is to output a control signal S42. An input of inverter IN42 is to receive control signal S42. An output of inverter IN42 is to output a control signal S42B. Thus, control signal S42 has a first voltage level to turn on switch TG2 when one of digital signals EN11 and EN10 has a bit value of 1. Figure 4 As illustratively shown in FIG. 44, logic unit 446 includes a NOR gate NR42 and an inverter IN42. Two inputs of NOR gate NR42 are to receive digital signals EN11 and EN10, respectively. An output of NOR gate NR42 is to output a control signal S42. An input of inverter IN42 is to receive control signal S42. An output of inverter IN42 is to output a control signal S42B. Thus, control signal S42 has a first voltage level to turn on switch TG2 when one of digital signals EN11 and EN10 has a bit value of 1.

[0095] In various embodiments, logic units 442, 444, 446, and 448 have various configurations and include various logic components. For example, in some alternative embodiments, logic units 442, 444, 446, and / or 448 have configurations similar to logic unit 301 shown in FIG. 3. Figure 3B

[0096] Further details of the operation of memory 400 are described below with respect to the embodiments shown in FIGS. 44-48. Figure 5 Figure 6A Figure 6B Figure 6C Figure 6D Further details of the operation of memory 400 are described below with respect to the embodiments shown in FIGS. 44-48.

[0097] Figure 5 A flowchart of a method 500 of generating voltage signal VS2 for memory 100, 300, and 400 shown in FIGS. 1, 3, and 44-48, respectively, according to some embodiments of the present disclosure is shown in FIG. 51. As illustratively shown in FIG. 51, method 500 includes operations OP51-OP58. Figure 1 Figure 3A Figure 4 A flowchart of a method 500 of generating voltage signal VS2 for memory 100, 300, and 400 shown in FIGS. 1, 3, and 44-48, respectively, according to some embodiments of the present disclosure is shown in FIG. 51. As illustratively shown in FIG. 51, method 500 includes operations OP51-OP58. Figure 5

[0098] In operation OP51, a voltage signal VMSB corresponding to one or more MSBs of data DT is generated. In operation OP52, digital signals EN00, EN01, EN10, and EN11 are generated based on voltage signal VMSB.

[0099] ​​​​​​​​In response to the voltage signal VMSB having the bit value 00 or 01, operations OP53-OP55 are performed. In response to the voltage signal VMSB having the bit value 11 or 10, operations OP56-OP58 are performed.

[0100] In operation OP53, control signals S43 and S44 are generated to turn on at least one of transistors M41-M43. As a result, the resistance of the read circuit 424 is reduced.

[0101] In operation OP54, a voltage signal VS2 is generated by at least one of transistors M41-M43, the voltage signal VS2 having a voltage level lower than the voltage level of the voltage signal VS1. As a result, in operation OP55, the voltage distribution curve of the voltage signal VS2 is shifted along the arrow A21 shown in FIG. 6B. Figure 2

[0102] In operation OP56, control signals S41 and S42 are generated to turn on at least one of transistors P41-P42. As a result, the resistance of the read circuit 422 is reduced.

[0103] In operation OP57, a voltage signal VS2 is generated by at least one of transistors P41-P42, the voltage signal VS2 having a voltage level higher than the voltage level of the voltage signal VS1. As a result, in operation OP58, the voltage distribution curve of the voltage signal VS2 is shifted along the arrow A22 shown in FIG. 6B. Figure 2

[0104] Figure 6A and Figure 6B FIGS. 600A and 600B are diagrams showing voltage distribution curves representing the relationship between the voltage levels of the voltage signals VS1, VS2 and the bit values of the data DT shown in FIG. 6B, in accordance with some embodiments of the present disclosure. Referring to Figure 4 , Figure 5 , Figure 6A and Figure 6B , FIGS. 600A and 600B describe further details of operation OP53.

[0105] As illustratively shown in Figure 6A and Figure 6B , each of FIGS. 600A and 600B includes a horizontal axis corresponding to the bit values of the data DT and a vertical axis corresponding to the voltage levels of the voltage signals VS1 and VS2.

[0106] As illustratively shown in Figure 6A , FIG. 600A includes voltage distribution curves C61 and C62. The voltage distribution curves C61 and C62 correspond to the voltage signals VS1 and VS2, respectively. In some embodiments, the voltage distribution curve C62 corresponds to the case where both MSBs of the data DT have the bit value 11.​​

[0107] In the embodiment shown in Figure 6A , the data DT has a bit value B6A that is greater than the bit value B61. In some embodiments, the bit value B61 is the largest bit value with MSB 10, and the bit value PB is the largest bit value with MSB 01. For example, if the data has four bits, the bit value B61 is 1011, the bit value PB is 0111, and the bit value B6A is greater than 1011.

[0108] Referring to Figure 6A and Figure 4 , in response to the voltage signal VMSB having the bit value 11, the digital signal EN11 has the bit value 1, and each of the digital signals EN00, EN10, and EN01 has the bit value 0, such that the control signals S41 and S42 have the first voltage level, and the control signals S43 and S44 have the second voltage level. As a result, the transistors P41 and P42 are turned on, while the transistors M41-M43 are turned off. The transistors P41-P44 and M44 generate the voltage signal VS2 corresponding to the voltage distribution curve C62.

[0109] As illustratively shown in Figure 6B , the graph 600B includes the voltage distribution curve C61 and the voltage distribution curve C63. The voltage distribution curve C63 corresponds to the voltage signal VS2. In some embodiments, the voltage distribution curve C63 corresponds to the case where both MSBs of the data have the bit value 10.

[0110] In the embodiment shown in Figure 6B , the data DT has a bit value B6B that is less than or equal to the bit value B61 and greater than the bit value PB. For example, if the data has four bits, the bit value B61 is 1011 and the bit value PB is 0111, and the bit value B6A is greater than 0111 and less than or equal to 1011.

[0111] Referring to Figure 6B and Figure 4 , in response to the voltage signal VMSB having the bit value 10, the digital signal EN10 has the bit value 1, and each of the digital signals EN00, EN11, and EN01 has the bit value 0, such that the control signal S42 has the first voltage level, and the control signals S41, S43, and S44 have the second voltage level. As a result, the transistor P42 is turned on, while the transistors P41, M41-M43 are turned off. The transistors P42-P44 and M44 generate the voltage signal VS2 corresponding to the voltage distribution curve C63.

[0112] Referring to Figure 4 , Figure 6A and Figure 6BThe resistance of the read circuit 422 corresponding to the graph 600A is less than the resistance of the read circuit 422 corresponding to the graph 600B. Thus, the voltage level of the voltage distribution curve C62 is greater than the voltage level of the voltage distribution curve C63. In other words, the degree to which the voltage distribution curve C62 is shifted from the voltage distribution curve C61 is greater than the degree to which the voltage distribution curve C63 is shifted from the voltage distribution curve C61.

[0113] Figure 6C and Figure 6D FIGS. 600C and 600D are graphs illustrating voltage distribution curves representing a relationship between voltage levels of voltage signals VS1, VS2 and bit values of data DT shown in Figure 4 Figure 5 Figure 6C and Figure 6D FIGS. 600C and 600D describe further details of the operation OP56.

[0114] As illustratively shown in Figure 6C and Figure 6D Each of the graphs 600C and 600D includes a horizontal axis corresponding to bit values of the data DT and a vertical axis corresponding to voltage levels of the voltage signals VS1 and VS2.

[0115] As illustratively shown in Figure 6C The graph 600C includes voltage distribution curves C61 and C64. The voltage distribution curves C61 and C64 correspond to the voltage signals VS1 and VS2, respectively. In some embodiments, the voltage distribution curve C64 corresponds to a case where both MSBs of the data have bit values of 00.

[0116] In the embodiment shown in Figure 6C The data DT has a bit value B6C that is less than a bit value B62. In some embodiments, the bit value B62 is a smallest bit value having MSB 01, and the bit value PB is a largest bit value having MSB 01. For example, if the data has four bits, the bit value B62 is 0100, the bit value PB is 0111, and the bit value B6C is less than 0100.

[0117] Referring to Figure 6C and Figure 4 ​​In response to the voltage signal VMSB having the bit value 00, the digital signal EN00 has the bit value 1, and each of the digital signals EN11, EN10, and EN01 has the bit value 0, such that the control signals S43 and S44 have the first voltage level, and the control signals S41 and S42 have the second voltage level. Thus, the transistors M41-M43 are turned on, while the transistors P41-P42 are turned off. The transistors P43-P44 and M41-M44 generate the voltage signal VS2 corresponding to the voltage distribution curve C64.

[0118] As illustratively shown in Figure 6D FIG. 600D, the voltage distribution curve C61 and the voltage distribution curve C65 are included. The voltage distribution curve C65 corresponds to the voltage signal VS2. In some embodiments, the voltage distribution curve C65 corresponds to the case where both MSBs of the data have the bit value 01.

[0119] In the embodiment shown in Figure 6D , the data DT has the bit value B6D, which is less than or equal to the bit value PB and greater than or equal to the bit value B62. For example, if the data has four bits, the bit value B62 is 0100 and the bit value PB is 0111, and the bit value B6A is greater than or equal to 0100 and less than or equal to 0111.

[0120] Referring to Figure 6D and Figure 4 , in response to the voltage signal VMSB having the bit value 01, the digital signal EN01 has the bit value 1, and each of the digital signals EN00, EN11, and EN10 has the bit value 0, such that the control signal S43 has the first voltage level, and the control signals S41, S42, and S44 have the second voltage level. Thus, the transistors M42 and M43 are turned on, while the transistors P41-P42 and M41 are turned off. The transistors P43-P44 and M42-M43 generate the voltage signal VS2 corresponding to the voltage distribution curve C65.

[0121] Referring to Figure 4 , Figure 6C and Figure 6D , the resistance corresponding to the read circuit 424 of FIG. 600C is less than the resistance corresponding to the read circuit 422 of FIG. 600D. Thus, the voltage level of the voltage distribution curve C64 is less than the voltage level of the voltage distribution curve C65. In other words, the voltage distribution curve C64 is shifted from the voltage distribution curve C61 to a greater extent than the voltage distribution curve C65 is shifted from the voltage distribution curve C61.

[0122] In summary, the voltage signal VS2 is adjusted to different extents depending on the different bit values of the MSBs of the data, such that the corresponding voltage distribution curves C62-C65 are shifted to different extents.

[0123] Also disclosed is a memory including a memory device, a read device, and a feedback device. The memory device is to store a plurality of bits. The read device includes a first read circuit and a second read circuit. The first read circuit is coupled to the memory device. The second read circuit is coupled to the memory device and to the first read circuit at a first node. The first read circuit and the second read circuit are to cooperate with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device is to adjust at least one of the first read circuit and the second read circuit based on the first voltage signal. The first read circuit and the second read circuit are to generate a second voltage signal corresponding to the plurality of bits after the at least one of the first read circuit and the second read circuit is adjusted by the feedback device, the second voltage signal being different from the first voltage signal. In some embodiments, the feedback device is further to adjust the first read circuit in response to the at least one first bit having a first bit value and to adjust the second read circuit in response to the at least one first bit having a second bit value different from the first bit value. In some embodiments, the feedback device is further to adjust a resistance of at least one of the first read circuit and the second read circuit to adjust a voltage level of the first node. In some embodiments, the feedback device includes a first logic cell to generate a first control signal in response to the first voltage signal having a first bit value, and the first read circuit includes a first transistor coupled to the first node and to be controlled by the first control signal. In some embodiments, the feedback device further includes a second logic cell to generate a second control signal in response to the first voltage signal having a second bit value different from the first bit value, and the second read circuit includes a second transistor coupled to the first node and to be controlled by the second control signal, wherein the first transistor and the second transistor are different types of transistors. In some embodiments, the feedback device further includes a second logic cell to generate a second control signal in response to the first voltage signal having a second bit value different from the first bit value, and the first read circuit further includes a second transistor coupled to the first node and to be controlled based on the second control signal, wherein the first transistor and the second transistor are a same type of transistor. In some embodiments, the first logic cell is further to generate a second control signal complementary to the first control signal, and the first read circuit further includes a transmission gate, wherein a first end of the transmission gate is coupled to a control end of the first transistor, two control ends of the transmission gate are to receive the first control signal and the second control signal, respectively. In some embodiments, the first read circuit further includes a second transistor, wherein a first end of the second transistor is coupled to a control end of the first transistor, a second end of the second transistor is to receive a disable voltage signal, and a control end of the second transistor is to receive the second control signal.In some embodiments, the first logic unit comprises: an OR gate to receive the first voltage signal and to output a first control signal; and an inverter to receive the first control signal and to output a second control signal complementary to the first control signal.

[0124] Also disclosed is a memory including a memory device, a reading device, a reading-out device, and a feedback device. The reading device is coupled to the memory device and is used to read data stored in the memory device to generate first voltage signals, the first voltage signals corresponding to a first voltage distribution curve. The reading-out device is used to read the first voltage signals and to generate digital signals corresponding to the read first voltage signals. The feedback device is used to generate at least one control signal in response to the digital signals for controlling the reading device to generate second voltage signals corresponding to a second voltage distribution curve different from the first voltage distribution curve. In some embodiments, a first one of the first voltage signals has a first voltage level different from a second voltage level of a second one of the second voltage signals, and the first voltage signals and the second voltage signals correspond to data having a same bit value. In some embodiments, the reading device includes a first transistor of a first type and a second transistor of a second type different from the first type, and the feedback device is further used to turn on the first transistor to increase the second voltage level in response to the same bit value being greater than a first predetermined bit value, and to turn on the second transistor to decrease the second voltage level in response to the same bit value being less than the first predetermined bit value. In some embodiments, the reading device includes a third transistor of the first type coupled in parallel with the first transistor, and the feedback device is further used to turn on the first transistor and the third transistor in response to the same bit value being greater than a second predetermined bit value greater than the first predetermined bit value, and to turn on the first transistor and turn off the third transistor in response to the same bit value being between the second predetermined bit value and the first predetermined bit value. In some embodiments, a first voltage level difference between a first voltage level and a second voltage level of the second voltage distribution curve is greater than a second voltage level difference between a first voltage level and a second voltage level of the first voltage distribution curve, the first voltage level of the second voltage distribution curve and the first voltage level of the first voltage distribution curve corresponding to data having a first bit value, and the second voltage level of the second voltage distribution curve and the second voltage level of the first voltage distribution curve corresponding to data having a second bit value different from the first bit value. In some embodiments, the feedback device includes a plurality of logic units used to receive the digital signals respectively to generate the at least one control signal, wherein a first portion of the logic units is used to control at least one transistor of a first type in the reading device, and a second portion of the logic units is used to control at least one transistor of a second type in the reading device.In some embodiments, the first portion of the logic unit comprises: a first logic unit to receive a first digital signal of the digital signals; and a second logic unit to receive the first digital signal and a second digital signal of the digital signals, wherein the first digital signal and the second digital signal correspond to a first bit value and a second bit value, respectively, of the data, and the second bit value is less than the first bit value.

[0125] Also disclosed is a method of operating a memory, comprising: generating, by a complementary metal oxide semiconductor (CMOS) circuit, a first voltage signal associated with data stored in a memory device, wherein a voltage level of the first voltage signal corresponds to a first voltage distribution curve; reading out the first voltage signal to generate a digital signal associated with at least one first bit of the data; and controlling the CMOS circuit to generate a second voltage signal in accordance with the digital signal, wherein the second voltage signal corresponds to the data, and a voltage level of the second voltage signal corresponds to a second voltage distribution curve, the second voltage distribution curve having a shift from the first voltage distribution curve or having a different profile from the first voltage distribution curve. In some embodiments, controlling the complementary metal oxide semiconductor circuit comprises: increasing the voltage level of the second voltage signal in response to a bit value of the at least one first bit being greater than a first predetermined bit value; and decreasing the voltage level of the second voltage signal in response to the bit value being less than the first predetermined bit value. In some embodiments, decreasing the voltage level of the second voltage signal further comprises: decreasing the voltage level of the second voltage signal by a first amount in response to the bit value being less than the first predetermined bit value; and decreasing the voltage level of the second voltage signal by a second amount greater than the first amount in response to the bit value being less than a second predetermined bit value, the second predetermined bit value being less than the first predetermined bit value. In some embodiments, controlling the complementary metal oxide semiconductor circuit comprises: increasing a voltage level difference between a first voltage level and a second voltage level of the first voltage distribution curve to generate the second voltage distribution curve, wherein the first voltage level corresponds to a first bit value of the data, and the second voltage level corresponds to a second bit value adjacent to the first bit value.

[0126] The foregoing outlines features of a few embodiments so that a those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that changes can be made in the process and structures disclosed herein without departing from the scope of the disclosure.

Claims

1. A memory, comprising: Comprising: a memory device to store a plurality of bits; a reading device, comprising: a first reading circuit; and a second reading circuit coupled to the memory device and to the first reading circuit at a first node, wherein the first reading circuit and the second reading circuit are to cooperate with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits; and a feedback device to adjust at least one of the first reading circuit and the second reading circuit based on the first voltage signal, wherein the first reading circuit and the second reading circuit are to generate a second voltage signal corresponding to the plurality of bits after the at least one of the first reading circuit and the second reading circuit is adjusted by the feedback device, the second voltage signal being different from the first voltage signal.

2. The memory of claim 1, wherein, wherein the feedback device is further to adjust the first reading circuit in response to the at least one first bit having a first bit value and to adjust the second reading circuit in response to the at least one first bit having a second bit value different from the first bit value.

3. The memory of claim 1, wherein, wherein the feedback device is further to adjust a resistance of the at least one of the first reading circuit and the second reading circuit to adjust a voltage level of the first node.

4. The memory of claim 1, wherein, wherein the feedback device comprises: a first logic unit to generate a first control signal in response to the first voltage signal having a first bit value; and the first reading circuit comprises: a first transistor coupled to the first node and to be controlled by the first control signal.

5. The memory of claim 4, wherein, wherein the feedback device further comprises: a second logic unit to generate a second control signal in response to the first voltage signal having a second bit value different from the first bit value; and the second reading circuit comprises: a second transistor coupled to the first node and to be controlled by the second control signal, wherein the first transistor and the second transistor are different types of transistors.

6. The memory of claim 4, wherein, wherein the feedback device further comprises: a second logic unit to generate a second control signal in response to the first voltage signal having a second bit value different from the first bit value; and the first reading circuit further comprises: a second transistor coupled to the first node and to be controlled based on the second control signal, wherein the first transistor and the second transistor are a same type of transistor.

7. The memory of claim 4, wherein, wherein the first logic unit is further to generate a second control signal complementary to the first control signal; and the first reading circuit further comprises: a transmission gate, wherein a first end of the transmission gate is coupled to a control end of the first transistor, two control ends of the transmission gate are to receive the first control signal and the second control signal, respectively.

8. The memory of claim 7, wherein, wherein the first reading circuit further comprises: a second transistor, wherein a first end of the second transistor is coupled to a control end of the first transistor, a second end of the second transistor is to receive a disable voltage signal, and a control end of the second transistor is to receive the second control signal.

9. The memory of claim 4, wherein, wherein the first logic unit comprises: an AND or NAND gate to receive the first voltage signal and to output the first control signal; and an inverter to receive the first control signal and to output a second control signal complementary to the first control signal.

10. A memory, comprising: comprise: a memory device; a reading device coupled to the memory device and to read data stored in the memory device to generate a plurality of first voltage signals corresponding to a first voltage distribution curve; a reading-out device to read out the plurality of first voltage signals and to generate a plurality of digital signals corresponding to the read-out plurality of first voltage signals; and a feedback device to generate at least one control signal in response to the plurality of digital signals for controlling the reading device to generate a plurality of second voltage signals corresponding to a second voltage distribution curve different from the first voltage distribution curve.

11. The memory of claim 10, wherein, wherein a first voltage signal of the plurality of first voltage signals has a first voltage level different from a second voltage level of a second voltage signal of the plurality of second voltage signals, and the first voltage signal and the second voltage signal correspond to the data having a same bit value.

12. The memory of claim 11, wherein, wherein the reading device comprises: a first transistor of a first type; and a second transistor of a second type different from the first type, and the feedback device is further to turn on the first transistor to increase the second voltage level in response to the same bit value being greater than a first predetermined bit value, and turn on the second transistor to decrease the second voltage level in response to the same bit value being less than the first predetermined bit value.

13. The memory of claim 12, wherein, wherein the reading device comprises: a third transistor of the first type coupled in parallel with the first transistor, and the feedback device is further to turn on the first transistor and the third transistor in response to the same bit value being greater than a second predetermined bit value greater than the first predetermined bit value, and turn on the first transistor and turn off the third transistor in response to the same bit value being between the second predetermined bit value and the first predetermined bit value.

14. The memory of claim 10, wherein, wherein a first voltage level difference between a first voltage level and a second voltage level of the second voltage distribution curve is greater than a second voltage level difference between a first voltage level and a second voltage level of the first voltage distribution curve, the first voltage level of the second voltage distribution curve and the first voltage level of the first voltage distribution curve correspond to the data having a first bit value, and the second voltage level of the second voltage distribution curve and the second voltage level of the first voltage distribution curve correspond to the data having a second bit value different from the first bit value.

15. The memory of claim 10, wherein, wherein the feedback device comprises: a plurality of logic units to receive the plurality of digital signals respectively to generate the at least one control signal, wherein a first portion of the plurality of logic units is to control at least one transistor of a first type in the reading device, and A second portion of the plurality of logic units is to control at least one transistor of a second type in the reading device.

16. The memory of claim 15, wherein, The first portion of the plurality of logic units includes: a first logic unit to receive a first digital signal of the plurality of digital signals; and a second logic unit to receive the first digital signal and a second digital signal of the plurality of digital signals, wherein the first digital signal and the second digital signal correspond to a first bit value and a second bit value of the data, respectively, and the second bit value is less than the first bit value.

17. A method of operating a memory, comprising: comprises: generating, by a complementary metal-oxide-semiconductor circuit, a first voltage signal associated with data stored in a memory device, wherein voltage levels of the first voltage signal correspond to a first voltage distribution curve; reading out the first voltage signal to generate a plurality of digital signals associated with at least one first bit of the data; and controlling, according to the plurality of digital signals, the complementary metal-oxide-semiconductor circuit to generate a second voltage signal, wherein the second voltage signal corresponds to the data, and voltage levels of the second voltage signal correspond to a second voltage distribution curve, the second voltage distribution curve having a shift from the first voltage distribution curve or having a different profile from the first voltage distribution curve.

18. The method of claim 17, wherein, wherein controlling the complementary metal-oxide-semiconductor circuit comprises: in response to a bit value of the at least one first bit being greater than a first predetermined bit value, increasing the voltage levels of the second voltage signal; and in response to the bit value being less than the first predetermined bit value, decreasing the voltage levels of the second voltage signal.

19. The method of claim 18, wherein, wherein decreasing the voltage levels of the second voltage signal further comprises: in response to the bit value being less than the first predetermined bit value, decreasing the voltage levels of the second voltage signal by a first degree; and in response to the bit value being less than a second predetermined bit value, decreasing the voltage levels of the second voltage signal by a second degree greater than the first degree, the second predetermined bit value being less than the first predetermined bit value.

20. The method of claim 17, wherein, wherein controlling the complementary metal-oxide-semiconductor circuit comprises: increasing a voltage level difference between a first voltage level and a second voltage level of the first voltage distribution curve to generate the second voltage distribution curve, wherein the first voltage level corresponds to a first bit value of the data, and the second voltage level corresponds to a second bit value adjacent to the first bit value.

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