Wafer package and method of manufacturing the same

Abstract

A wafer package and a method of manufacturing the same are provided. The wafer package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first insulating layer, and a lower ground conductive pad. The substrate has opposite top and bottom surfaces, a via penetrating the top and bottom surfaces, and a sidewall surrounding the via. The first insulating layer is on the top surface of the substrate, and the lower ground conductive pad is in the via. The redistribution layer extends from the bottom surface of the substrate along the sidewall to the lower ground conductive pad. The redistribution layer covers the entire bottom surface of the substrate and electrically connects the lower ground conductive pad. The lower ground conductive pad is electrically connected to a circuit board through the redistribution layer without wire bonding, which avoids interference and interference with wire bonding on other functional conductive pads.

Description

TECHNICAL FIELD

[0001] The present invention relates to a wafer package and a method for manufacturing a wafer package. BACKGROUND

[0002] Generally, the top surface of a wafer package with a silicon substrate or a Silicon On Insulator (SOI) substrate has a plurality of conductive pads. When the wafer package is bonded to a circuit board, these conductive pads can be electrically connected to the circuit board by wire bonding. Some of these conductive pads are related to the ground function of the wafer package, and the others are related to the functions of the wafer package itself (e.g. power handling, fingerprint recognition, image processing, etc.).

[0003] However, if the conductive pads for grounding and the conductive pads for other functions are all connected to the circuit board by wire bonding, interference and interference can easily occur, and the higher resistance due to the longer transmission distance can affect the performance. In addition, since the area of the wafer package is limited, it is not conducive to miniaturization design to arrange the ground conductive pads on the top surface of the wafer package. SUMMARY

[0004] One technical aspect of the present invention is a wafer package.

[0005] According to some embodiments of the present invention, a wafer package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first insulating layer, and a lower ground conductive pad. The substrate has opposite top and bottom surfaces, a through-hole penetrating the top and bottom surfaces, and a sidewall surrounding the through-hole. The first insulating layer is on the top surface of the substrate, and the lower ground conductive pad is in the through-hole. The redistribution layer extends from the bottom surface of the substrate along the sidewall to the lower ground conductive pad. The redistribution layer covers the entire bottom surface of the substrate and is electrically connected to the lower ground conductive pad.

[0006] In some embodiments, the included angle between the first insulating layer and the lower ground conductive pad of the above-mentioned semiconductor structure is greater than or equal to 90 degrees.

[0007] In some embodiments, the above-mentioned substrate further includes an inner insulating layer, and a portion of the substrate is between the first insulating layer and the inner insulating layer.

[0008] In some embodiments, the thickness of the portion of the above-mentioned substrate is less than half the sum of the thicknesses of the first insulating layer and the inner insulating layer.

[0009] In some embodiments, the above-mentioned semiconductor structure further includes a second insulating layer. The second insulating layer is on the first insulating layer and surrounds the lower ground conductive pad.

[0010] In some embodiments, the above-mentioned semiconductor structure further includes a third insulating layer. The third insulating layer is on the second insulating layer.

[0011] In some implementations, the semiconductor structure further includes an upper ground conductive pad. The upper ground conductive pad is embedded in the third insulating layer and electrically connected to the lower ground conductive pad.

[0012] In some implementations, the semiconductor structure further includes a fourth insulating layer. The fourth insulating layer is on the third insulating layer and has an opening, wherein the upper ground conductive pad is in the opening.

[0013] In some implementations, the upper ground conductive pad overlaps the lower ground conductive pad in a vertical direction.

[0014] In some implementations, the upper ground conductive pad is free of a wire thereon.

[0015] In some implementations, the semiconductor structure further includes a functional conductive pad. The functional conductive pad is embedded in the third insulating layer and electrically insulated from the lower ground conductive pad.

[0016] In some implementations, the first insulating layer is a buffer layer, and the substrate further includes a semiconductor layer and another buffer layer, and the semiconductor layer is between the two buffer layers.

[0017] A method of fabricating a wafer package.

[0018] According to some implementations of the present disclosure, a method of fabricating a wafer package includes: bonding a carrier to a semiconductor structure using a temporary adhesive layer, wherein the semiconductor structure has a substrate, a first insulating layer, and a lower ground conductive pad, the substrate has opposite top and bottom surfaces; etching the substrate to form a through-hole that penetrates the top and bottom surfaces, such that the substrate has a sidewall around the through-hole; etching the first insulating layer in the through-hole to expose the lower ground conductive pad; forming a redistribution layer that extends from the bottom surface of the substrate along the sidewall to the lower ground conductive pad, wherein the redistribution layer covers the entire bottom surface of the substrate and is electrically connected to the lower ground conductive pad; and removing the temporary adhesive layer and the carrier.

[0019] In some implementations, the method further includes: after the carrier is bonded to the semiconductor structure, grinding the bottom surface of the substrate.

[0020] In some implementations, the method further includes: after the through-hole is formed, etching the substrate again to laterally enlarge the through-hole.

[0021] In some implementations, the method further includes: after the first insulating layer in the through-hole is etched, forming a seed layer that extends from the bottom surface of the substrate along the sidewall to the lower ground conductive pad; and forming a photoresist on the seed layer on the bottom surface of the substrate.

[0022] In some implementations, the forming the redistribution layer includes electroplating on the seed layer that is not covered by the photoresist.

[0023] In some embodiments, the method further comprises removing the photoresist after forming the redistribution layer.

[0024] In some embodiments, the method further comprises forming an oxidation resistant layer on the redistribution layer after removing the photoresist.

[0025] In some embodiments, the semiconductor structure further comprises an inner insulating layer, and a portion of the substrate is between the first insulating layer and the inner insulating layer, and the method further comprises etching the inner insulating layer, the portion of the substrate, and the first insulating layer in the via after etching the substrate to form the via to expose the lower ground conductive pad.

[0026] In some embodiments, the method further comprises dicing the semiconductor structure after removing the temporary adhesive layer and the carrier.

[0027] In the above embodiments of the present application, since the redistribution layer covers the entire bottom surface of the substrate and is electrically connected to the lower ground conductive pad, the lower ground conductive pad can be electrically connected to the circuit board through the redistribution layer without wire bonding, which can avoid interference and interference with wire bonding on other functional conductive pads. In addition, since the lower ground conductive pad is connected to the circuit board through the redistribution layer, the transmission distance is short and the resistance is low, which can improve the efficiency. The wafer package can use a thinner substrate or thin the thicker substrate, which is beneficial to miniaturization design and shortens the transmission distance. In addition, the redistribution layer can also improve the thermal conductivity, which is helpful for heat dissipation of the wafer package. BRIEF DESCRIPTION OF DRAWINGS

[0028] When read in conjunction with the accompanying Figure One The nature of the application can be more readily understood from the following detailed description of various implementations when considered in connection with the accompanying drawings. Note that the various features are not necessarily drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for the clarity of discussion.

[0029] Figure 1 A top view of a wafer package mounted on a circuit board according to an embodiment of the present application is shown.

[0030] Figure 2 A cross-sectional view of the wafer package and the circuit board along line 2-2 of Figure 1

[0031] A bottom view of the wafer package of Figure 3 Figure 1

[0032] Figure 4 A cross-sectional view of a wafer package according to another embodiment of the present application is shown.

[0033] Figure 5 A cross-sectional view of the wafer package and the circuit board along line 2-2 of Figure 2 ​​A partial enlarged view of a wafer package in a manufacturing process according to another embodiment of the present application.

[0034] Figure 6 A partial enlarged view of a wafer package in a manufacturing process according to another embodiment of the present application.

[0035] Figures 7 to 18 A partial enlarged view of a wafer package in a manufacturing process according to another embodiment of the present application.

[0036] Brief descriptions of the symbols in the drawings are as follows:

[0037] 100, 100a: wafer package; 105, 105a: semiconductor structure; 110: substrate; 111: portion (semiconductor layer); 112: top surface; 113: inner insulating layer (buffer layer); 114: bottom surface; 116: sidewall; 120: first insulating layer (buffer layer); 120a: second insulating layer; 120b: third insulating layer; 120c: fourth insulating layer; 130: lower ground conductive pad; 130a: upper ground conductive pad; 140: redistribution layer; 141: titanium layer; 142: seed layer; 143: diffusion barrier layer; 144: oxidation-resistant layer; 150, 150a: functional conductive pad; 160: temporary adhesive layer; 170: carrier; 200: circuit board; 210: ground conductive pad; 220: functional conductive pad; 230: insulator; 300: support layer; 2-2: line segment; L: line; O1: through hole; O2: opening; P1, P2: photoresist; T1, T2, T3: thickness; W: wire; θ: included angle. DETAILED DESCRIPTION

[0038] The implementation described below provides many different embodiments or examples of different features for implementing the provided solutions. Specific examples of elements and arrangements are described to facilitate the understanding of this case. Of course, these examples are merely examples and are not intended to be limiting. Moreover, elements and / or letters can be repeated in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself designate a relationship between the various embodiments and / or arrangements discussed.

[0039] Spatially relative terms such as "under", "below", "lower", "on", "upper" and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] Figure 1A top view of a wafer package 100 mounted on a circuit board 200 according to an embodiment of the present invention is shown. Figure 2 Draw Figure 1 A cross-sectional view of the chip package 100 and circuit board 200 along line segment 2-2. See also... Figure 1 and Figure 2 The wafer package 100 includes a semiconductor structure 105 and a redistribution layer 140. The semiconductor structure 105 has a substrate 110, a first insulating layer 120, and a lower ground conductive pad 130. The substrate 110 has opposing top and bottom surfaces 112 and 114, a through-hole O1 penetrating the top and bottom surfaces 114, and a sidewall 116 surrounding the through-hole O1. In this embodiment, the substrate 110 may be a silicon substrate; in other embodiments, the substrate 110 may be a silicon-on-insulator (SOI) substrate, and this is not intended to limit the invention. The first insulating layer 120 is located on the top surface 112 of the substrate 110, and the lower ground conductive pad 130 is in the through-hole O1. The redistribution layer 140 extends from the bottom surface 114 of the substrate 110 along the sidewall 116 to the lower ground conductive pad 130. The redistribution layer 140 may be a combination of multiple metal layers; this is simplified for clarity.

[0041] Figure 3 Draw Figure 1 A bottom view of the chip package 100. See also: Figure 2 and Figure 3 The redistribution layer 140 covers the bottom surface 114 of the entire substrate 110 and is electrically connected to the grounding conductive pad 130.

[0042] Since the redistribution layer 140 covers the entire bottom surface 114 of the substrate 110 and is electrically connected to the lower grounding conductive pad 130, the lower grounding conductive pad 130 can be electrically connected to the circuit board 200 through the redistribution layer 140 without the need for wire bonding, thus avoiding interference with the wires W on other functional conductive pads 150. Furthermore, because the lower grounding conductive pad 130 is connected to the circuit board 200 through the redistribution layer 140, the transmission distance is shorter and the resistance is lower, improving performance. The chip package 100 can use a thinner substrate 110 or a thinner version of a thicker substrate 110, which is beneficial for miniaturization and shortening the transmission distance. In addition, the redistribution layer 140 can also improve thermal conductivity, which helps with heat dissipation of the chip package 100.

[0043] In this embodiment, wafer package 100 further comprises a second insulating layer 120a, a third insulating layer 120b, and an upper ground conductive pad 130a. Second insulating layer 120a is located on first insulating layer 120 and surrounds lower ground conductive pad 130. Third insulating layer 120b is located on second insulating layer 120a. The materials of first insulating layer 120, second insulating layer 120a, and third insulating layer 120b can be the same without apparent interface. Upper ground conductive pad 130a is embedded in third insulating layer 120b and electrically connected to lower ground conductive pad 130. Upper ground conductive pad 130a overlaps lower ground conductive pad 130 in vertical direction. During manufacturing process, upper ground conductive pad 130a can be used to test whether the connection between lower ground conductive pad 130 and redistribution layer 140 is normal. In addition, upper ground conductive pad 130a is free of wire W and can be used to mark the position of lower ground conductive pad 130.

[0044] Semiconductor structure 105 further comprises a functional conductive pad 150. Functional conductive pad 150 is embedded in third insulating layer 120b and electrically insulated from lower ground conductive pad 130 which is electrically connected to redistribution layer 140. Functional conductive pad 150 is wire-bonded, thus one end of wire W is located on functional conductive pad 150 and the other end is located on circuit board 200. Functional conductive pad 150 can mean a conductive pad used for purposes other than grounding.

[0045] In addition, semiconductor structure 105 can also have a functional conductive pad 150a in first insulating layer 120 and second insulating layer 120a, but functional conductive pad 150a is not electrically connected to redistribution layer 140.

[0046] In this embodiment, circuit board 200 has a ground conductive pad 210, a functional conductive pad 220, and an insulator 230. Ground conductive pad 210 and functional conductive pad 220 can be electrically insulated by insulator 230. Ground conductive pad 210 and functional conductive pad 220 can be electrically connected to redistribution layer 140 and functional conductive pad 150 of wafer package 100 respectively. Redistribution layer 140 can directly contact ground conductive pad 210, which is beneficial to electrical conduction and heat conduction. Functional conductive pad 150 is connected to functional conductive pad 220 of circuit board 200 through wire W.

[0047] Figure 4 A cross-sectional view of wafer package 100a according to another embodiment of the present application is shown. Wafer package 100a comprises semiconductor structure 105 and redistribution layer 140. This embodiment is similar to that of wafer package 100, and the same reference numerals are used to denote the same elements. The difference between wafer package 100 and wafer package 100a is that wafer package 100a further comprises a functional conductive pad 150a in first insulating layer 120 and second insulating layer 120a. Functional conductive pad 150a is not electrically connected to redistribution layer 140. Figure 2The difference in the implementation method lies in that the lower grounding conductive pad 130 on the right side of the chip package 100a has a functional conductive pad 150 above it that requires wire bonding, and this lower grounding conductive pad 130 is electrically connected to the lower grounding conductive pad 130 on the left side via the redistribution layer 140. This design allows a single redistribution layer 140 to electrically connect multiple lower grounding conductive pads 130, which can significantly save the time and cost of traditional grounding wire bonding.

[0048] Figure 5 Draw Figure 2 A partially enlarged view of the wafer package 100 during the manufacturing process. After etching the substrate 110 and the first insulating layer 120 to form a through-hole O1, the lower ground conductive pad 130 is exposed from the through-hole O1. The included angle θ between the first insulating layer 120 and the lower ground conductive pad 130 of the semiconductor structure 105 is greater than or equal to 90 degrees, which avoids the subsequent formation of the redistribution layer 140 (see...). Figure 2 The line breaks at the turning point.

[0049] Figure 6 A partially enlarged view of a wafer package 100 according to another embodiment of the present invention during its manufacturing process is shown. Figure 5 The difference in implementation methods lies in Figure 6 The substrate 110a of the semiconductor structure 105a also includes an inner insulating layer 113, and a portion 111 of the substrate 110a is located between the first insulating layer 120 and the inner insulating layer 113. The thickness T1 of this portion 111 of the substrate 110a is less than half the sum of the thicknesses of the first insulating layer 120 and the inner insulating layer 113 (i.e., the sum of thicknesses T2 and T3). With this design, because the portion 111 of the substrate 110a is very thin, it can be etched together with the inner insulating layer 113 and the first insulating layer 120. Furthermore, the angle θ between the first insulating layer 120 and the lower ground conductive pad 130 is greater than or equal to 90 degrees, which avoids the subsequent formation of the redistribution layer 140 (see...). Figure 2 The wire breaks at the turning point. In some embodiments, the first insulating layer 120 is a buffer layer, and the substrate 110a also includes a semiconductor layer 111 and another buffer layer 113, with the semiconductor layer 111 located between the two buffer layers 120 and 113.

[0050] The following description will explain the manufacturing method of the wafer package.

[0051] Figures 7 to 18 Cross-sectional views are shown at each step of a method for manufacturing a wafer package according to an embodiment of the present invention. (See also...) Figure 7 and Figure 8First, a temporary adhesive layer 160 is used to bond the carrier 170 to a semiconductor structure 105, wherein the semiconductor structure 105 has a substrate 110, a first insulating layer 120, a second insulating layer 120a, a third insulating layer 120b, a lower ground conductive pad 130, and an upper ground conductive pad 130a. The substrate 110 is exemplified by a silicon substrate. The substrate 110 has opposing top surfaces 112 and bottom surfaces 114. In this embodiment, the semiconductor structure 105 further includes a fourth insulating layer 120c. The fourth insulating layer 120c is located on the third insulating layer 120b and has an opening O2, in which the upper ground conductive pad 130a is located. The fourth insulating layer 120c is selective. After the carrier 170 is bonded to the semiconductor structure 105, the bottom surface 114 of the substrate 110 can be ground to thin the substrate 110.

[0052] See Figure 9 and Figure 10 Subsequently, a patterned photoresist P1 can be formed on the bottom surface 114 of the substrate 110. Then, the substrate 110 is etched to form a through-hole O1 penetrating the top surface 112 and the bottom surface 114, giving the substrate 110 sidewalls 116 surrounding the through-hole O1. In some embodiments, the substrate 110 can be etched again to laterally enlarge the through-hole O1, such as... Figure 11 As shown. After the perforation O1 is formed, the photoresist P1 can be removed.

[0053] See Figure 12 ,treat Figure 11 After the via O1 is formed on the substrate 110, the first insulating layer 120 in the via O1 can be etched to expose the lower grounding conductive pad 130. When the substrate 110 is a silicon-on-insulator (SOI) substrate, refer to [reference needed]. Figure 6 After forming the through hole O1 in the etched substrate 110a, the inner insulating layer 113, part 111 of the substrate 110a and the first insulating layer 120 in the through hole O1 can be further etched to expose the lower grounding conductive pad 130.

[0054] See Figure 13 After etching the first insulating layer 120 in the through hole O1, a seed layer 142 can be formed extending from the bottom surface 114 of the substrate 110 along the sidewall 116 to the lower grounding conductive pad 130. The seed layer 142 can be made of copper. Before forming the seed layer 142, a titanium layer 141 can be formed as a buffer layer.

[0055] See Figure 14 and Figure 15After the seed layer 142 is formed, photoresist P2 can be formed on the seed layer 142 on the bottom surface 114 of the substrate 110. Next, a redistribution layer 140 can be formed extending from the bottom surface 114 of the substrate 110 along the sidewall 116 to the lower grounding conductive pad 130, wherein the redistribution layer 140 covers the entire bottom surface 114 of the substrate 110 and is electrically connected to the lower grounding conductive pad 130. In this embodiment, the redistribution layer 140 is formed by electroplating on the seed layer 142, which is not covered by photoresist P2. The redistribution layer 140 and the seed layer 142 can be made of the same material without a clear interface; hereinafter, it will only be referred to as the redistribution layer 140. Furthermore, after forming the redistribution layer 140, a diffusion barrier layer 143 can be formed on the redistribution layer 140. The material of the diffusion barrier layer 143 can be nickel, but is not limited thereto.

[0056] See Figure 16 and Figure 17 Next, the photoresist P2 and its covering seed layer 142 can be removed (see...). Figure 14 An antioxidant layer 144 is formed on the redistribution layer 140. More specifically, the antioxidant layer 144 is formed on the diffusion barrier layer 143 and covers the sidewalls of the titanium layer 141, the redistribution layer 140, and the diffusion barrier layer 143. The antioxidant layer 144 can be made of gold, but is not limited thereto.

[0057] See Figure 18 In subsequent processes, it can be Figure 17 The structure is attached to the support layer 300 (e.g., cut adhesive tape), then the temporary adhesive layer 160 and the carrier 170 can be removed, and the semiconductor structure 105 is cut along line L to form a structure as shown in the figure. Figure 2 The chip package 100. In some implementations, Figure 2 The chip package 100 may also have Figure 18 The fourth insulating layer 120c.

[0058] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person skilled in the art can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims of this application.

Claims

1. A wafer package, characterized by, comprising: a semiconductor structure having a substrate, a first insulating layer, a second insulating layer, a third insulating layer, an upper ground conductive pad and a lower ground conductive pad, wherein the substrate has opposite top and bottom surfaces, a through-hole penetrating the top and bottom surfaces and a sidewall surrounding the through-hole, the first insulating layer is on the top surface of the substrate, and the lower ground conductive pad is in the through-hole, the second insulating layer is on the first insulating layer and surrounds the lower ground conductive pad, the third insulating layer is on the second insulating layer, the entire upper ground conductive pad is in the third insulating layer without a portion protruding out of the third insulating layer, the upper ground conductive pad is electrically connected to the lower ground conductive pad and the upper ground conductive pad is free of a wire thereon, the upper ground conductive pad is configured to mark a position of the lower ground conductive pad; and a redistribution layer extending from the bottom surface of the substrate along the sidewall to the lower ground conductive pad, wherein the redistribution layer covers the entire bottom surface of the substrate and is electrically connected to the lower ground conductive pad.

2. The wafer package of claim 1, wherein, An included angle between the first insulating layer and the lower ground conductive pad of the semiconductor structure is greater than or equal to 90 degrees.

3. The wafer package of claim 1, wherein, The substrate further comprises an inner insulating layer, and a portion of the substrate is between the first insulating layer and the inner insulating layer.

4. The wafer package of claim 3, wherein, A thickness of the portion of the substrate is less than half of a sum of thicknesses of the first insulating layer and the inner insulating layer.

5. The wafer package of claim 1, wherein, The semiconductor structure further comprises: a fourth insulating layer on the third insulating layer and having an opening, wherein the upper ground conductive pad is in the opening.

6. The wafer package of claim 1, wherein, The upper ground conductive pad overlaps the lower ground conductive pad in a vertical direction.

7. The wafer package of claim 1, wherein, The semiconductor structure further comprises: a functional conductive pad embedded in the third insulating layer and electrically insulated from the lower ground conductive pad.

8. The wafer package of claim 1, wherein, The first insulating layer is a buffer layer, the substrate further comprises a semiconductor layer and another buffer layer, and the semiconductor layer is between the buffer layer and the another buffer layer.

9. A method of manufacturing a wafer package, characterized by, comprising: bonding a carrier to a semiconductor structure using a temporary adhesive layer, wherein the semiconductor structure has a substrate, a first insulating layer, a second insulating layer, a third insulating layer, an upper ground conductive pad and a lower ground conductive pad, the substrate has opposite top and bottom surfaces, the second insulating layer is on the first insulating layer and surrounds the lower ground conductive pad, the third insulating layer is on the second insulating layer, the entire upper ground conductive pad is in the third insulating layer without a portion protruding out of the third insulating layer, the upper ground conductive pad is electrically connected to the lower ground conductive pad and the upper ground conductive pad is free of a wire thereon, the upper ground conductive pad is configured to mark a position of the lower ground conductive pad; etching the substrate to form a through-hole penetrating the top and bottom surfaces, so that the substrate has a sidewall surrounding the through-hole; etching the first insulating layer in the through-hole to expose the lower ground conductive pad; forming a redistribution layer extending from the bottom surface of the substrate along the sidewall to the lower ground conductive pad, wherein the redistribution layer covers the entire bottom surface of the substrate and is electrically connected to the lower ground conductive pad; and removing the temporary adhesive layer and the carrier.

10. The method of claim 9, further comprising: after the carrier is bonded to the semiconductor structure, grinding the bottom surface of the substrate.

11. The method of claim 9, further comprising: After forming the via, etching the substrate again to laterally enlarge the via.

12. The method of claim 9, further comprising: after etching the first insulating layer in the via, forming a seed layer extending from the bottom surface of the substrate along the sidewall to the lower ground conductive pad; and forming photoresist on the seed layer on the bottom surface of the substrate.

13. The method of manufacturing a wafer package as claimed in claim 12, wherein, forming the redistribution layer includes forming by electroplating on the seed layer not covered by the photoresist.

14. The method of claim 13, further comprising: after forming the redistribution layer, removing the photoresist.

15. The method of claim 14, further comprising: after removing the photoresist, forming an oxidation resistant layer on the redistribution layer.

16. The method of manufacturing a wafer package as claimed in claim 9, wherein, the semiconductor structure further comprises an inner insulating layer, and a portion of the substrate is between the first insulating layer and the inner insulating layer, the method further comprising: after etching the carrier to form the via, etching the inner insulating layer in the via, the portion of the substrate, and the first insulating layer to expose the lower ground conductive pad.

17. The method of claim 9, further comprising: after removing the temporary adhesive layer and the carrier, dicing the semiconductor structure.

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