Semiconductor packaging device, frame product and manufacturing method thereof

Abstract

The present application relates to the field of semiconductor device processing technology, and provides a semiconductor packaging device, comprising a packaging layer, a chip disposed within the packaging layer, a die-bonding island extending along a first preset direction, the chip disposed on the die-bonding island; a plurality of functional pins disposed on the packaging layer, the plurality of functional pins being electrically connected to the chip and / or the die-bonding island; wherein the functional pins comprise: a pin body disposed within the packaging layer and partially exposed from the surface of the packaging layer; a first groove and a second groove, respectively disposed on two opposite sides of the pin body along the first preset direction; a first step and a second step, respectively disposed on two opposite sides of the pin body along a second preset direction, wherein the second preset direction is perpendicular to the first preset direction; and the packaging layer is filled with the first groove, the second groove, the first step, and the second step. The present application solves the problem in the prior art of poor pin bonding, which results in easy detachment and loosening.

Description

Technical Field

[0001] The present application relates to the field of semiconductor component processing technology, and more specifically, to a semiconductor packaging device, a frame product, and a manufacturing method thereof. Background Art

[0002] Currently, consumer products are developing towards miniaturization and high integration. Existing semiconductor packaging structures such as DFN or QFN are flat packaging structures and are widely used due to their superior performance and applicability.

[0003] However, the DFN or QFN series packaging structures currently used in the market have the following problems: the functional pins of traditional DFN or QFN series packages are cylindrical and smooth in shape, and the bonding between them and the plastic packaging material (packaging layer) is poor. The functional pins are easily detached or loosened due to the force during the dicing process, which seriously affects the quality of semiconductor packaging devices.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor packaging device, a frame product and a manufacturing method thereof, so as to solve the problem in the prior art that the functional pins of the package are cylindrical and smooth in shape, and the bonding between them and the plastic packaging material is poor, resulting in easy falling off and loosening.

[0006] To achieve the above objectives, the technical solution adopted in this application is:

[0007] The present application provides a semiconductor package device, comprising a package layer and a chip disposed within the package layer, wherein the semiconductor package device further comprises:

[0008] A wafer-bonding base island is provided extending along a first preset direction, and the chip is provided on the wafer-bonding base island;

[0009] as well as

[0010] A plurality of functional pins are provided on the packaging layer, wherein the plurality of functional pins are electrically connected to the chip and / or the adhesive base island;

[0011] The functional pins include: a pin body, which is located in the packaging layer and partially exposed on the surface of the packaging layer;

[0012] A first groove and a second groove, the first groove and the second groove are respectively arranged on two opposite side surfaces of the pin body along a first preset direction;

[0013] a first step and a second step, the first step and the second step being respectively arranged on two opposite side surfaces of the pin body along a second preset direction, wherein the second preset direction is perpendicular to the first preset direction;

[0014] The packaging layer fills the first groove, the second groove, the first step and the second step.

[0015] In one embodiment, the lead body comprises:

[0016] External welding part, the external welding part is exposed on the surface of the packaging layer;

[0017] The middle part is located in the packaging layer and is fixedly connected to the outer welding part;

[0018] A lead connection portion, the lead connection portion is fixedly connected to the middle portion and is located within the packaging layer;

[0019] A first groove and a second groove are formed between the outer welding portion and the lead connecting portion, and the first groove and the second groove are respectively located on both sides of the middle portion along a first preset direction.

[0020] In one embodiment, the first step and the second step are respectively located on both sides of the middle portion along the second preset direction;

[0021] The first step and the second step make the cross-section of the pin body perpendicular to the first preset direction into a Z shape;

[0022] The first step and the second step are respectively provided on two opposite sides of the middle portion, and the step opening of the first step and the step opening of the second step are provided in opposite directions in the vertical direction;

[0023] The outer welding portion is configured as a rectangular parallelepiped, and the lead connection portion is configured as a T-shape.

[0024] In one embodiment, the back surface of the adhesive base island has a half-etched surface, and the encapsulation layer covers the half-etched surface of the adhesive base island;

[0025] An embedded groove is provided in the half-etched surface;

[0026] The four corners of the adhesive base island are provided with through holes.

[0027] In one embodiment, the inner wall of the embedded groove has a concave-convex structure layer.

[0028] In one embodiment, the lead body and the adhesive base island are independently spaced apart;

[0029] or

[0030] The adhesive base island is fixedly connected to at least one lead body.

[0031] In one embodiment, the plurality of functional pins are located at the edge of the packaging layer and are evenly distributed on both sides of the adhesive base island along the second preset direction;

[0032] or

[0033] The surface of the adhesive base island and the surface of the functional pin are both provided with a metal plating layer.

[0034] On the other hand, a frame product for a semiconductor package device includes a frame body, and a plurality of semiconductor package devices as described above disposed on the frame body;

[0035] A plurality of semiconductor packaged devices are arranged in an array and spaced apart and connected to the frame body.

[0036] In a third aspect, a method for manufacturing a semiconductor package device is provided, for manufacturing a frame product of the semiconductor package device as described above, comprising the steps of:

[0037] A substrate with a preset thickness is provided, and a frame body and a plurality of frame units having grooves and steps, functional pins, and adhesive base islands are formed by cutting, planned etching, ion striking, etc., wherein the functional pins are connected to the frame body, and the edges of the adhesive base islands are connected to the frame body;

[0038] A protective film is attached to the bottom of the frame, and the protective film can be a polymer protective film;

[0039] In each frame unit, the adhesive material is applied at a predetermined position on the surface of the adhesive base island by printing, spraying or dipping;

[0040] In each frame unit, a chip is provided, and the chip is placed in the middle of the adhesive material through position recognition and then cured at high temperature;

[0041] In each frame unit, the chip's bonding area is welded to the functional pins or the die-bonding islands via wires, and the welding process is carried out in an environment where the sealed track is filled with a mixed gas of N2-H2.

[0042] The die-bonding island, functional pins, chip, and leads are encapsulated by injection molding to form an encapsulation layer, and then demoulded to form a semi-finished product after curing;

[0043] The semi-finished product is subjected to a heat aging reaction to solidify the encapsulation layer and release the residual stress inside;

[0044] The protective film is removed, so that a tin layer is deposited on the surface of the functional pins through a chemical replacement reaction;

[0045] Each frame unit is diced and cut at half the cost to obtain a single semiconductor package device.

[0046] In one embodiment, in the step of providing a substrate:

[0047] The substrate material is: C7025 or C194;

[0048] or

[0049] Provide the chip, place it in the middle of the adhesive material through position recognition, and perform high-temperature curing:

[0050] The chip is connected to the adhesive base island through the adhesive material and continuously cured by heating in an oven. The curing temperature is set between 160℃ and 180℃, and the curing time is 3 hours ± 10 minutes.

[0051] or

[0052] The welding process is carried out in a sealed rail in an environment filled with N2-H2 mixed gas in the following steps:

[0053] The lead wire is gold wire, copper wire or palladium copper alloy wire, and the H2 content in the N2-H2 mixed gas is 5%-7%;

[0054] or

[0055] In the step of subjecting the semi-finished product to a heat aging reaction:

[0056] The heat aging temperature is 170±10℃, and the heat aging time is 300±20 minutes.

[0057] The present application provides a semiconductor package device, frame product, and manufacturing method thereof, which have at least the following beneficial effects: by providing a first groove and a second groove on a functional pin, a groove structure is etched in the middle of the side of the pin body, forming an I-shaped side structure of the pin body in a first predetermined direction. Furthermore, by providing a first groove and a second groove on either side of the pin body, the functional pin forms a Z-shaped structure in a second predetermined direction. After encapsulation by the encapsulation layer, the first groove, the second groove, the first step, and the second step are filled with a sealing compound. The packaging layer is fixed by an "I"-shaped structure in a first preset direction, and a "Z"-shaped structure in a second preset direction. Furthermore, the first groove, second groove, first step, and second step located on the four sides of the pin body form a staggered slot structure. Through the different slots in the first and second preset directions, a staggered fixed connection is formed for the packaging layer, enhancing the bonding performance between the functional pin and the plastic encapsulation material. At the same time, the "I"-shaped structure on the side ensures the soldering area on the upper side of the pin body while increasing the soldering area on the lower side of the pin body, improving the pin's load-bearing soldering performance. The first and second steps at both ends form a "Z"-shaped structure on the pin body, which not only effectively enhances the clamping ability of the packaging layer and prevents it from falling off due to poor stretching during the cutting process, but also increases the wiring distribution range at the bottom of the semiconductor packaging device due to the upward concavity of the step surface on the inner side of the pin body, improving the applicability of subsequent circuit applications and the feasibility of design operations. The structure of this semiconductor packaging device prevents the functional pins from falling off or loosening during the dicing process, thereby improving product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0059] Figure 1 is a perspective view of a frame product of a semiconductor packaging device according to an embodiment of the present invention;

[0060] Figure 2 is a perspective view of a semiconductor package device according to an embodiment of the present invention;

[0061] Figure 3 yes Figure 2 A cross-sectional view of the section at AA;

[0062] Figure 4 yes Figure 2 A cross-sectional view of the section at BB;

[0063] Figure 5 This is a schematic structural diagram of functional pins of a semiconductor package device according to an embodiment of the present invention;

[0064] Figure 6 yes Figure 2 Cross-sectional view of the section at CC;

[0065] Figure 7 1 is a schematic diagram of the back side of a die-bonding island of a semiconductor packaging device according to an embodiment of the present invention;

[0066] Figure 8 yes Figure 7 Cross-sectional view of the section at EE;

[0067] Figure 9 is a perspective view of another structure of a semiconductor package device according to an embodiment of the present invention;

[0068] Figure 10 The present invention is a flowchart of a process for manufacturing a semiconductor packaging device according to an embodiment of the present invention.

[0069] Among them, the reference numerals in the figures are:

[0070] 100, packaging layer; 200, chip; 210, lead; 300, adhesive base island; 310, half-etched surface; 320, embedded groove; 321, concave-convex structure layer; 330, through-hole; 400, functional pin; 410, pin body; 411, first groove; 412, second groove; 413, first step; 414, second step; 420, external welding part; 430, middle part; 440, lead connection part; 441, horizontal part; 442, longitudinal part; 500, frame body; 510, frame unit. DETAILED DESCRIPTION

[0071] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0072] It should be noted that when a component is referred to as being "fixed on" or "disposed on" another component, it may be located directly or indirectly on the other component. When a component is referred to as being "connected to" another component, it may be directly or indirectly connected to the other component. The directions or positions indicated by the terms "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions or positions shown in the accompanying drawings and are only for the convenience of description and cannot be understood as limitations on this technical solution. The terms "first" and "second" are only used for the purpose of convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0073] The DFN or QFN series packaging frames currently used on the market not only have the problem of functional pins being easily loose and detached, but also the conventional design of the adhesive base island of the traditional DFN or QFN series packaging frame is semi-encapsulated outside the packaging layer, that is, the bottom of the adhesive base island is exposed outside the packaging layer, thereby forming a heat sink structure of the product. However, when the semiconductor device of this design is used in high-frequency circuits or when high-frequency circuits need to be laid out on the bottom PCB surface, there will be mutual interference and even short circuit problems. It is not suitable for use in high-frequency circuits and has limited scope of use. Moreover, in conventional designs, the bonding surface delamination is likely to occur when the adhesive base island is combined with the packaging layer, or the adhesive base island is likely to shift poorly during dicing and separation. Therefore, this embodiment proposes a new semiconductor packaging device to improve the above-mentioned problems.

[0074] See also Figure 1 , Figure 2 ; This embodiment provides a semiconductor packaging device, including a packaging layer 100, a chip 200 arranged in the packaging layer 100, a wafer base island 300 extending along a first preset direction, and a plurality of functional pins 400 arranged on the packaging layer 100. Usually, the horizontal outline of the wafer base island 300 is a rectangle; therefore, the structure is described with the long side of the rectangle as the first preset direction (front-to-back direction) and the short side as the second preset direction (left-to-right direction). The second preset direction is perpendicular to the first preset direction, and the direction perpendicular to the horizontal plane is the up-down direction. Figure 2 、 Figure 4 As shown, the chip 200 is fixedly arranged on the upper surface of the adhesive base island 300, and a plurality of functional pins 400 are electrically connected to the chip 200 and / or the adhesive base island 300 (the chip 200 can be directly bonded to the adhesive base island 300 to form an electrical connection with the adhesive base island 300, and then the adhesive base island 300 and the functional pins 400 are electrically connected through a cable; or the chip 200 and the functional pins 400 are directly electrically connected through a cable); Figure 2 、 Figure 3 、 Figure 4 As shown, each functional pin 400 in this embodiment can be spaced apart and independently arranged from the adhesive base island 300; the functional pin 400 in this embodiment specifically includes a pin body 410, a first groove 411 and a second groove 412, and a first step 413 and a second step 414. The pin body 410 is located in the packaging layer 100 and partially exposes the surface of the packaging layer 100; specifically, the lower surface and side surfaces of the pin body 410 can expose the surface of the packaging layer 100, thereby facilitating soldering on an external circuit board and installation in a functional circuit. Figure 3 、 Figure 5 As shown, the first groove 411 and the second groove 412 are respectively arranged on two opposite sides of the pin body 410 along the first preset direction. Figure 4 、 Figure 5 As shown, the first step 413 and the second step 414 are respectively provided on two opposite sides of the lead body 410 along the second preset direction. The packaging layer 100 fills the first groove 411 , the second groove 412 , the first step 413 and the second step 414 .

[0075] In the above embodiment, by providing a first groove 411 and a second groove 412 on the functional pin 400, a groove structure is etched in the middle of the side surface of the pin body 410, forming an I-shaped side surface structure of the pin body 410 in a first predetermined direction. Furthermore, providing a first groove 411 and a second groove 412 on both sides of the pin body 410 forms a Z-shaped structure with a right-angled bend in the second predetermined direction. After encapsulation by the encapsulation layer 100, the encapsulation glue fills the first groove 411, the second groove 412, the first step 413, and the second step 414. Thus, the packaging layer 100 is fixed by the "I"-shaped structure in the first preset direction, and the "Z"-shaped structure in the second preset direction. In addition, the first groove 411, the second groove 412, the first step 413 and the second step 414 on the four sides of the pin body 410 form a staggered slot structure. Through the different slots in the first preset direction and the second preset direction, a staggered fixed connection is formed for the packaging layer 100, thereby enhancing the bonding performance between the functional pin 400 and the plastic packaging material. At the same time, the "I"-shaped structure on the side is adopted to ensure the pin body is fixed. The soldering area on the upper side of the body 410 is increased, while the soldering area on the lower side of the pin body 410 is also increased, improving the pin's load-bearing soldering performance. The first step 413 and the second step 414 at both ends form a right-angled "Z"-shaped structure on the bent portion of the pin body 410, which not only effectively enhances the clamping ability of the packaging layer 100 and prevents it from falling off due to poor stretching during the cutting process; the inner side of the pin body 410 is recessed upward due to the stepped surface, increasing the wiring distribution range at the bottom of the semiconductor package device, improving the applicability of subsequent circuit applications and the feasibility of design operations. Through the structure of this semiconductor package device, the functional pins 400 will not fall off or loosen during the dicing process, thereby improving product quality.

[0076] like Figure 3 、 Figure 5As shown, the pin body 410 of this embodiment specifically includes: an outer welding portion 420, an intermediate portion 430, and a lead connection portion 440. The lead connection portion 440, the intermediate portion 430, and the outer welding portion 420 are arranged in sequence from top to bottom. The lower surface of the outer welding portion 420 is exposed on the surface of the packaging layer 100, the intermediate portion 430 is located in the packaging layer 100, and is fixedly connected to the outer welding portion 420; the lead connection portion 440 is fixedly connected to the intermediate portion 430 and is located in the packaging layer 100, and the lead connection portion 440 is used to weld the lead 210. A first groove 411 and a second groove 412 are formed between the outer welding portion 420 and the lead connection portion 440, and the first groove 411 and the second groove 412 are respectively located on both sides of the intermediate portion 430 along the first preset direction (front and back). The top surface of the lead connection portion 440, encapsulated within the packaging layer 100, is configured as a T-shaped plane. The end of the T-shaped plane facing the wafer-mounted island 300 is a transverse portion 441, extending in the front-to-back direction. Transverse portion 441 is used for soldering to the lead 210. Extending transverse portion 441 in the front-to-back direction increases the surface area of the packaging layer 100 without increasing the surface area. This allows transverse portion 441 to provide sufficient soldering space for the lead, enabling stable soldering. The transverse portion is rectangular, with a soldering area of 0.35 mm by 0.2 mm and a thickness of 0.06 mm. This area ensures stable soldering of the lead to the transverse portion. The end of the T-shaped plane facing away from the wafer-mounted island 300 is a longitudinal portion 442, extending in the left-right direction. This longitudinal portion 442 extends outward, facilitating connection to the intermediate portion 430. The middle layer is arranged in an up-and-down direction, firmly connecting the lead connection portion 440 at the top and the external soldering portion 420 at the bottom (formed integrally by etching). This etching shape gives the external soldering portion 420 a rectangular horizontal projection with dimensions of 0.3mm by 0.25mm and a thickness of 0.06mm. The external soldering portion 420 serves as the lead for the semiconductor component and can be connected to an external circuit, such as by soldering to a circuit board.

[0077] like Figure 4 、 Figure 5As shown, in this embodiment, the first step 413 and the second step 414 are respectively located on either side of the middle portion 430 along the second preset direction, that is, the first step 413 and the second step 414 are located in the left-right direction. The first step 413 and the second step 414 give the pin body 410 a Z-shaped cross-section perpendicular to the first preset direction; specifically, the Z-shape is formed with a right-angled bend. The first step 413 and the second step 414 are respectively provided on opposite sides of the middle portion 430, with the step opening of the first step 413 and the step opening of the second step 414 facing in opposite directions. The first step 413 is formed by etching downward from the upper side of the middle portion 430 and extending to the left-right outer side, with its opening facing upward and the left-right outer side; or the first step 413 is formed by etching inward from the left-right outer side and extending to the upper side. A first step 413 is etched upward from the lower side of the middle portion 430 and extends to the inner side in the left-right direction, with its opening facing downward and the inner side in the left-right direction. Alternatively, the first step 413 is etched outward from the inner side in the left-right direction and extends to the lower side. By providing the first step 413 and the second step 414, the sealing layer can fill the first step 413 and the second step 414 during the sealing process, so that the Z-shaped structure is embedded in the sealing layer, thereby stably limiting the pin body 410 in the left-right direction. Therefore, the pin body 410 is limited in the left-right direction by the packaging layer 100, preventing the pin from loosening or detaching.

[0078] The upper left side of the functional pin 400 (encapsulated in the plastic packaging material of the packaging layer 100) adopts a downward concave etching design with an etching depth of 0.1mm, a width of 0.08mm, and a length of 0.25mm. The lower right side of the functional pin 400 (encapsulated in the plastic packaging material of the packaging layer 100) adopts an upward concave etching design in the opposite direction of the left end, with an etching depth of 0.1mm, a width of 0.08mm, and a length of 0.35mm. These two groove designs form a "Z"-shaped structure with the main body of the functional pin 400. In this way, a bending structure is formed on the right side to be stably fixedly connected to the packaging layer 100, and a step structure is formed on the left side to be stably connected to the packaging layer 100. Through the stable connection on the left and right sides, the functional pin 400 can be stably fixed in the packaging layer 100, so that the functional pin 400 is stably fixed inside the packaging layer 100 and is not easy to loosen.

[0079] In this embodiment, the functional pins 400 are generally designed to have 6, 8, or even multiples thereof. The functional pins 400 are symmetrically distributed on the left and right sides of the adhesive base island 300. Multiple functional pins 400 are located at the edges of the packaging layer 100 and are evenly distributed on both sides of the adhesive base island 300 along the second predetermined direction (left-right direction). One end of the functional pins 400 is connected to the frame body 500. During the etching process to form the functional pins 400, etching is typically performed on a copper plate. After the functional pins 400 are formed, they are still connected to the frame body 500, and the positions of the functional pins 400 are relatively fixed. The packaging layer 100 is then sealed internally with a molding compound. By mirroring the left and right sides of the functional pins 400 about the centerline, the forces acting on the functional pins 400 on both sides are symmetrical, ensuring that the entire semiconductor package device is balanced when subjected to forces.

[0080] like Figure 9 As shown, in another structure, during the process of etching the functional pins 400 and the wafer-bonding island 300 on the substrate, the wafer-bonding island 300 can be fixedly connected to at least one pin body 410. This connection between the wafer-bonding island 300 and the at least one pin body 410 secures the position of the wafer-bonding island 300 and the functional pin 400 body, thereby making the wafer-bonding island 300 more firmly fixed to the frame 500. The position of the wafer-bonding island 300 and the functional pin 400 body is fixed, and thus, it is not easily displaced during the process of injection molding the packaging layer 100.

[0081] like Figure 2 、 Figure 4 、 Figure 6As shown, the backside of the adhesive island 300 in this embodiment has a half-etched surface 310, and the encapsulation layer 100 covers the half-etched surface 310 of the adhesive island 300. When etching the adhesive island 300, typically only the outer shape of the adhesive island 300 is etched. Connecting portions are provided at the front and rear ends of the adhesive island 300 to connect the adhesive island 300 to the substrate frame. After the adhesive seal is applied, the backside of the adhesive island 300 is not covered by the sealant. Because the adhesive island 300 is a metal component and is used to support the chip 200, its area is relatively large. Therefore, after conventional semiconductor molding, the backside of the adhesive island 300 is not covered by the sealant to form a heat sink structure. This can cause interference and even short circuit problems when the product is used in high-frequency circuits or when high-frequency circuits are required on the bottom PCB surface. In this embodiment, the backside of the adhesive island 300 is etched to form a half-etched surface 310, reducing the thickness of the adhesive island 300 to half that of conventional methods, with an etching depth of 0.1 mm. During the sealant application, the sealant completely covers the half-etched surface 310, positioning the bottom surface of the adhesive island 300 within the sealant layer. This transforms the original exposed copper structure into a fully encapsulated structure, effectively isolating the conductive and signal components, meeting the requirements of later high-frequency circuits. This allows for circuit layout at the bottom of the device in finished applications, preventing issues such as signal shorts and interference.

[0082] like Figure 7 、 Figure 8 As shown, in this embodiment, an embedded groove 320 is provided within the half-etched surface 310. Because the embedded groove 320 is located on the half-etched surface at the bottom of the adhesive base island 300, during the sealing process, the glue flows into the embedded groove 320, thereby filling the embedded groove 320. The formed encapsulation layer 100 is locked into the embedded groove 320, thus preventing the adhesive base island 300 from loosening and shifting within the encapsulation layer 100. In this embodiment, the embedded groove 320 is configured as a square structure, but it can also be configured as a different shape such as a circle. The square embedded groove 320 measures 0.15mm*0.15mm*0.05mm. The square structure facilitates etching and molding. Through holes 330 are provided at the four corners of the adhesive base island 300. Through-vias 330 are located at the four corners of the die-bonding area of the die-bonding island 300, near the edge. The minimum diameter of these through-vias 330 is 0.07 mm; in this implementation, these through-vias 330 are 0.1 mm. The sealant enters these through-vias, connecting the formed encapsulation layer 100 to the through-vias 330. The four corner through-vias 330 ensure stable fixation of the die-bonding island 300 within the encapsulation layer 100.

[0083] like Figure 8As shown, the inner wall of the embedded groove 320 in this embodiment has a concave-convex structure layer 321. The embedded groove 320 is subsequently treated by surface roughening, which can be done by selective localized etching, light processing, or electrostatic impact to form the concave-convex structure layer 321. Therefore, the inner surface of the groove is set to a frosted concave-convex surface to increase its adhesion to the encapsulation layer 100, thereby enhancing the bonding effect with the molding compound.

[0084] In this embodiment, the surface of the wafer-bonding island 300 and the surface of the functional pins 400 are both provided with a metal plating layer (not shown in the figure).

[0085] like Figure 1 As shown, based on the same concept, the present application also proposes a frame product for a semiconductor package device, which includes a frame body 500 and a plurality of semiconductor package devices as described above, disposed on the frame body 500. The plurality of semiconductor package devices are arranged at intervals and connected to the frame body 500. During the production process, multiple semiconductor package devices can be produced at a time, and the plurality of semiconductor package devices are molded on the frame body 500. This allows multiple small semiconductor package devices to be fixed on a large frame body 500, thereby enabling better transportation and subsequent peeling process.

[0086] like Figure 10 As shown, based on the same concept, the present application also proposes a method for manufacturing a semiconductor package device, which is used to manufacture a frame product of the semiconductor package device as above, comprising the steps of:

[0087] Step S100: Provide a substrate with a preset thickness, and form a frame body and a plurality of frame units having functional pins and adhesive base islands by cutting (rough cutting), etching, and ion blasting, wherein the functional pins are connected to the frame body, and the edges of the adhesive base islands are connected to the frame body.

[0088] The substrate is made of copper material, such as C7025 or C194, and the frame is manufactured. It is cut into a suitable thickness by stamping (the copper material used in this embodiment has a thickness of 0.2 mm), and then cut into a separate row according to the appropriate size to form the outer contour of the frame body 500. (The length and width of the frame body 500 of this embodiment are set to: 270 mm * 83 mm). An etching mold is prepared, and the copper plate is etched on the substrate according to the structural requirements. After etching, the copper plate is formed into a plurality of frame units 510 with functional pins 400 and adhesive base islands 300. The frame body 500 serves as a frame, and the functional pins 400 and adhesive base islands 300 are connected to the frame body 500. Multiple frame units 510 are connected to the frame body 500 at intervals, so that multiple frame units 510 can be produced on one frame body 500, and each frame unit 510 can form a semiconductor package device.

[0089] Step S200: affix a protective film to the bottom of the frame.

[0090] In the specific process, the protective film can be a high-temperature protective film. The purpose of the high-temperature protective film is to protect the outer pin surface of the functional pin from leaking during the plastic sealing process, so that the outer pin surface will not be sticky with the plastic sealing material of the packaging layer and affect the appearance or even the solderability of the pin in the later stage; at the same time, the affixed high-temperature protective film provides a molding surface for the plastic sealing material of the packaging layer, ensuring the flatness of the appearance of the plastic sealing layer.

[0091] Step S300: In each frame unit, a bonding material is applied to a predetermined position on the surface of the bonding base island by printing, spraying or dipping.

[0092] In the specific process, at a specific position of the adhesive base island, the adhesive material is coated on the surface of the adhesive base island using adhesive, scribing or brushing technology. Commonly used adhesive materials include conductive silver glue, insulating glue, solder or tin paste.

[0093] Step S400: Provide a chip in each frame unit, place the chip in the middle of the adhesive material through position recognition, and perform high-temperature curing.

[0094] In the specific process, for the incoming whole wafer, the wafer is cut using appropriate cutting tools and dicing processes to obtain the required chips mentioned above. During the dicing process, a comprehensive assessment is made based on information such as the chip's cutting path size, chip thickness, and chip size to determine whether the chip dicing process uses slotting or double-blade dicing, as well as whether a double-blade process is used. At the same time, the dicing knife speed is controlled to ensure that the chip dicing effect does not suffer from defects such as breakage or damage. After the chip is sucked from the film by the bonding equipment, the position is identified by the position recognition device and the chip is placed in the center of the bonding material. The frame unit after the bonding action is completed is then subjected to high-temperature curing to complete the bonding action of the frame unit. During the high-temperature curing process, the chip is connected to the bonding base island through the bonding material and continuously cured by heating in an oven. The curing temperature is set between 160°C and 180°C, and the curing time is 3 hours ± 10 minutes. The optimal temperature is set at 175±5°C, and the curing time is 3 hours ± 10 minutes.

[0095] Step S500: In each frame unit, the bonding area of the chip is welded to the functional pins or the die-bonding islands via wires, wherein the welding process is performed in an environment where a sealed track is filled with a mixed gas of N2-H2.

[0096] During the specific process, the chip's solder pads are electrically connected to the corresponding functional pins on the frame unit, based on the connection method of the design output. Specifically, soldering methods can include normal, BSOB, reverse, and reinforced wire connection modes. The leads are gold, copper, or palladium-copper alloy wires, and the H2 content in the N2-H2 mixture is 5%-7%.

[0097] The welding process is controlled by a sealed rail control process. The welding process is divided into three temperature stages, including a preheating zone: a heating process from room temperature (25°C) to 150°C. This stage gradually heats the frame unit and chip to prevent sudden high temperatures from causing material mismatch or quality problems. Molecular motion increases with temperature; therefore, a gradual heating process prevents sudden intense motion. The temperature range in the welding zone is 150°C to 180°C. This high-temperature welding process provides the necessary temperature for wire bonding. It is also important to note that higher welding temperatures are not necessarily better; higher temperatures increase oxidation. Currently, a sealed rail is used and welding is performed in an N2-H2 mixed gas, effectively reducing the welding temperature and preventing oxidation in the weld area. The cooling zone temperature range is 180°C to 100°C, allowing the product to gradually cool after welding, effectively releasing residual welding stress. During the process of this solution, compared with the maximum welding temperature of 220°C of the conventional open bottom furnace structure, the welding temperature of this solution is reduced to 180°C, which is 40°C lower than the existing technology; at the same time, the sealed track is filled with a mixed gas of N2-H2 (H2 content 5%-7%). Filling the mixed gas reduces the oxygen content in the welding space and lowers the welding temperature at the same time, thereby reducing the problem of solder joint oxidation and improving product welding reliability.

[0098] Step S600: The die-bonding island, functional pins, chip, and leads are encapsulated by injection molding to form an encapsulation layer, and then demolded to form a semi-finished product after curing.

[0099] In the specific process, the structure obtained through the above steps is injected into the mold, and the polymer plastic material is dissolved at high temperature and pressed into the mold to encapsulate the adhesive base island, functional pins, chips, leads, etc. After curing, the semi-finished product is demolded.

[0100] Step S700 : subjecting the semi-finished product to a thermal aging reaction to solidify the encapsulation layer and release residual stress inside.

[0101] In the specific process, the semi-finished product formed after the plastic encapsulation in the above step is placed in a baking device for thermal aging reaction, thereby more effectively solidifying the plastic encapsulation material inside the plastic encapsulation layer, releasing the internal plastic encapsulation stress, and improving the reliability of the product in subsequent use. The thermal aging temperature is preferably 170±10°C and the thermal aging time is 300±20 minutes.

[0102] Step S800 : removing the protective film, so that a tin layer is deposited on the surface of the functional pins through a chemical replacement reaction.

[0103] The specific process involves removing the protective film by a de-materialization method, allowing a tin layer to be deposited on the surface of the functional pins (external pin surfaces) that were originally bonded to the protective film through a chemical replacement reaction. The de-materialization process involves de-burring, high-pressure water spraying - air knife - de-oxidation - air knife - pure water cleaning - air knife - pre-preg - air knife - matte finishing - air knife - pure water cleaning - air knife - neutralization - air knife - spraying - air knife - hot pure water cleaning - air knife - blow-drying - and baking. This process allows a dense tin layer to be plated on the external pin surfaces of the functional pins, with a thickness of 7-15μm.

[0104] Step S900 , dicing each frame unit at half the cost to obtain a single semiconductor package device.

[0105] In the specific process, the finished product after plastic sealing, deoxidation and brightening is cut with a dicing knife at the connecting reinforcement position of the frame body to form the product separately.

[0106] In summary, the present application provides a semiconductor packaging device, a frame product, and a manufacturing method thereof, wherein, for the functional pins, a combination of etching from the side to form an "I" shape and grooves at both ends to form a "Z"-shaped positioning is adopted. During the plastic packaging process, the plastic packaging material completely penetrates into the etching position, forming a full positioning encapsulation around the functional pins. In addition, the back of the adhesive base island adopts a half-etching, the etching surface adopts a concave-convex design, and the adhesive base island adopts a via design, which can effectively achieve full encapsulation of the plastic packaging material and enable wiring at the bottom of the device; strengthen the bonding performance of the plastic packaging material and the adhesive base island to prevent delamination; the structure of the semiconductor packaging device of the present application solves the problem that the functional pins in the existing lead frame are easily stretched during the production process and misaligned and delaminated. The functional pins and the plastic packaging material form a mutual bite effect, which better protects the functional pins during the molding and separation process to avoid delamination caused by pin misalignment caused by cutting stress or failure caused by broken wires. By semi-etching the copper material on the back of the adhesive island (embedded grooves), the plastic encapsulation layer fully encapsulates the adhesive island, ensuring the product meets the practical needs of high-frequency applications. This allows circuit layout on the PCB surface on the back of the device in high-frequency circuits, avoiding signal interference or even short circuits during application. Furthermore, by providing a concave-convex structure layer within the embedded grooves, a frosted effect is achieved on the bonding surface, enhancing the bonding strength between the plastic encapsulation layer and the adhesive island. Furthermore, four reinforced vias are provided at the four corners of the adhesive island. After plastic encapsulation, the plastic encapsulation layer passes through the vias to achieve compression between the upper and lower surfaces of the adhesive island, ensuring the upper and lower traction of the adhesive island, preventing delamination caused by thermal expansion and contraction during use, and improving product reliability.

[0107] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor packaging device comprising a packaging layer and a chip disposed within the packaging layer, characterized in that: The semiconductor package device further includes: a wafer-bonding island extending along a first preset direction, wherein the chip is disposed on the wafer-bonding island; and A plurality of functional pins are provided on the packaging layer, wherein the plurality of functional pins are electrically connected to the chip and / or the adhesive base island; Wherein, the functional pin includes: a pin body, the pin body is located in the packaging layer and partially exposed on the surface of the packaging layer; a first groove and a second groove, wherein the first groove and the second groove are respectively arranged on two opposite side surfaces of the pin body along the first preset direction, so that the pin body forms an I-shaped side structure in the first preset direction; a first step and a second step, wherein the first step and the second step are respectively arranged on two opposite side surfaces of the pin body along a second preset direction, wherein the second preset direction is perpendicular to the first preset direction; The first groove and the second groove are provided on both sides of the pin body, so that the functional pin forms a "Z"-shaped structure with a right-angled bent portion in the second preset direction; The encapsulation layer fills the first groove, the second groove, the first step, and the second step.

2. The semiconductor package device according to claim 1, wherein The pin body comprises: an external welding portion, wherein the external welding portion is exposed on a surface of the packaging layer; a middle portion, the middle portion being located within the packaging layer and fixedly connected to the outer welding portion; a lead connecting portion, the lead connecting portion being fixedly connected to the middle portion and located within the packaging layer; The first groove and the second groove are formed between the outer welding portion and the lead connecting portion. The first groove and the second groove are respectively located on both sides of the middle portion along a first preset direction.

3. The semiconductor package device according to claim 2, wherein: The first step and the second step are respectively located on both sides of the middle portion along a second preset direction; The first step and the second step enable the cross-section of the pin body perpendicular to the first preset direction to be Z-shaped.

4. The semiconductor package device according to claim 1, wherein The back side of the adhesive base island has a half-etched surface, and the encapsulation layer covers the half-etched surface of the adhesive base island; An embedded groove is provided in the half-etched surface; The four corners of the adhesive base island are provided with through holes.

5. The semiconductor package device according to claim 4, wherein: An irregular concave-convex structure layer is provided on the inner wall of the embedded groove.

6. The semiconductor package device according to claim 4, wherein: The pin body and the adhesive base island are independently spaced apart and arranged; or The adhesive base island is fixedly connected to at least one of the lead bodies.

7. The semiconductor package device according to claim 1, wherein: The plurality of functional pins are all located at the edge of the packaging layer and are evenly distributed on both sides of the adhesive base island along the second preset direction; or The surface of the adhesive base island and the surface of the functional pin are both provided with a metal plating layer.

8. A frame product for a semiconductor packaging device, characterized in that: comprising a frame body, and a plurality of semiconductor package devices according to any one of claims 1 to 7 arranged on the frame body; A plurality of the semiconductor package devices are arranged in an array and spaced apart from each other and connected to the frame body.

9. A method for manufacturing a semiconductor package device, characterized in that: The frame product for manufacturing the semiconductor package device according to claim 8 comprises the steps of: A substrate with a preset thickness is provided, and a frame body and a plurality of frame units having grooves and steps, functional pins, and adhesive base islands are formed by cutting, planned etching, and ion striking, wherein the functional pins are connected to the frame body, and the edges of the adhesive base islands are connected to the frame body; A protective film is attached to the bottom of the frame; In each frame unit, an adhesive material is applied to a predetermined position on the surface of the adhesive base island by printing, spraying or gluing; In each frame unit, a chip is provided, and the chip is placed in the middle of the adhesive material through position recognition and then cured at high temperature; In each frame unit, the chip's bonding area is welded to the functional pins or the die-bonding islands via wires, wherein the welding process is performed in an environment where a sealed track is filled with a mixed gas of N2-H2; Injection-molding the adhesive base island, the functional pins, the chip, and the leads to form an encapsulation layer, and then demoulding the resultant to form a semi-finished product after curing; The semi-finished product is subjected to a heat aging reaction to solidify the encapsulation layer and release residual stress inside; Removing the protective film so that a tin layer is deposited on the surface of the functional pin through a chemical replacement reaction; Slicing is performed on each of the frame units to obtain individual semiconductor packaged devices.

10. The semiconductor package device according to claim 9, wherein In the step of providing a substrate: The substrate material is: C7025 material or C194 material; or The step of providing a chip, placing the chip in the middle of the adhesive material through position identification, and performing high-temperature curing: The chip is connected to the adhesive base island by an adhesive material and is continuously cured by heating in an oven. The curing temperature is set between 160° C. and 180° C., and the curing time is 3 hours ± 10 minutes. or The welding process is carried out in a sealed rail in an environment filled with a mixed gas of N2-H2: The lead wire is a gold wire, a copper wire or a palladium copper alloy wire, and the H2 content in the N2-H2 mixed gas is 5%-7%; or In the step of subjecting the semi-finished product to a heat aging reaction: The heat aging temperature is 170±10℃, and the heat aging time is 300±20 minutes.

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