Array substrate and display panel

Abstract

The embodiment of the present application provides an array substrate and a display panel. The array substrate comprises a first active layer, a gate electrode, a gate insulating layer, a second active layer and a source / drain metal layer, and the first active layer is connected in parallel with the second active layer through the conductor layer. Through the parallel active layer structure of two layers, the on-state current and the carrier mobility of the device are effectively improved, and the comprehensive performance of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panel manufacturing, and in particular to an array substrate and a display panel. BACKGROUND

[0002] With the development of display panel manufacturing technology, people have put forward higher requirements on the display effect and comprehensive performance of display panels and display devices.

[0003] In a display panel, a low-temperature polysilicon thin-film transistor is a key component in active driving, peripheral circuit, and the like, in a display device such as a liquid crystal display (LCD) and an organic light emitting diode (OLED). In order to improve the performance of the thin-film transistor, in the prior art, a light-doped drain and a raised source-drain structure are usually prepared inside the thin-film transistor. The light-doped drain and the raised source-drain structure are used to improve the stability and reliability of the thin-film transistor device. Therefore, the device prepared by the above structure can improve the performance of the thin-film transistor to a certain extent. However, the above structure also introduces a new series resistance structure, which easily leads to a decrease in the on-state current and the equivalent carrier mobility in the thin-film transistor, thereby affecting the performance of the thin-film transistor and being not conducive to further improvement of the comprehensive performance of the thin-film transistor.

[0004] In summary, in the prior art display panel, the on-state current and the equivalent carrier mobility of the thin-film transistor inside the display panel are low, which is not conducive to further improvement of the comprehensive performance of the display panel. SUMMARY

[0005] Embodiments of the present application provide an array substrate and a display panel. The on-state current and the carrier mobility of the thin-film transistor inside the display panel are effectively improved, and the comprehensive performance of the device is improved.

[0006] To solve the above technical problems, the present application provides an array substrate and a display panel. The array substrate comprises:

[0007] a substrate;

[0008] a first active layer disposed on the substrate, the first active layer comprising a first channel region and first doped regions disposed on both sides of the first channel region;

[0009] a gate disposed on the first active layer;

[0010] a gate insulating layer disposed on the first active layer and covering the gate;

[0011] a second active layer disposed on the gate insulating layer, the second active layer comprising a second channel region and second doped regions disposed on both sides of the second channel region; and

[0012] a source / drain metal layer disposed on the second active layer;

[0013] wherein the first doped regions and the second doped regions are disposed correspondingly, the source / drain metal layer is electrically connected with the second active layer in the second doped regions, and the first active layer in the first doped regions is correspondingly electrically connected with the second active layer in the second doped regions.

[0014] According to an embodiment of the present application, the length of the orthographic projection of the second doped regions on the substrate is greater than the length of the orthographic projection of the first doped regions on the substrate.

[0015] According to an embodiment of the present application, the first doped regions and the second doped regions each comprise a heavily doped region and a lightly doped region, the lightly doped region is adjacent to the heavily doped region, and the heavily doped region is disposed away from the channel region;

[0016] wherein the heavily doped region of the first active layer corresponds to the heavily doped region of the second active layer, the lightly doped region of the first active layer corresponds to the lightly doped region of the second active layer, and the source / drain metal layer is electrically connected with the corresponding second active layer in the heavily doped region.

[0017] According to an embodiment of the present application, the array substrate further comprises a first via and a second via, the heavily doped region of the first active layer is connected with the heavily doped region of the second active layer through the first via and the second via.

[0018] According to an embodiment of the present application, the array substrate further comprises a conductor layer, the conductor layer is disposed in the first via and the second via, and the first active layer is connected with the second active layer in parallel through the conductor layer.

[0019] According to an embodiment of the present application, the material of the conductor layer is the same as the material of the corresponding second active layer in the heavily doped region.

[0020] According to an embodiment of the present application, the array substrate further comprises a third via and a fourth via, the source / drain metal layer is disposed on the surface of the heavily doped region of the second active layer, and the source / drain metal layer is electrically connected with the heavily doped region of the first active layer through the third via and the fourth via.

[0021] According to an embodiment of the present application, the third via and the fourth via penetrate the heavily doped region of the second active layer.

[0022] According to an embodiment of the present application, the source / drain metal layer is arranged on the upper surface of the heavily doped region of the second active layer, and the source / drain metal layer is electrically connected with the second active layer and electrically connected with the first active layer through the corresponding via hole.

[0023] According to an embodiment of the present application, the array substrate further comprises a connecting metal layer, which is arranged in the corresponding film layer between the first active layer and the second active layer.

[0024] According to an embodiment of the present application, the connecting metal layer is arranged in the same layer as the gate, and the connecting metal layer is electrically connected with the source / drain metal layer and the heavily doped region of the first active layer.

[0025] According to an embodiment of the present application, the connecting metal layer is made of the same material as the gate.

[0026] According to an embodiment of the present application, the length of the lightly doped region of the first active layer is less than the length of the lightly doped region of the second active layer.

[0027] According to an embodiment of the present application, the first channel region and the second channel region are arranged correspondingly to the gate.

[0028] According to an embodiment of the present application, the orthographic projection of the second channel region on the substrate is located within the orthographic projection of the first channel region on the substrate.

[0029] According to an embodiment of the present application, the array substrate further comprises a light shielding layer, which is arranged on the substrate, and the first active layer is arranged on the light shielding layer.

[0030] According to an embodiment of the present application, the orthographic projection of the first channel region of the first active layer on the substrate is located within the orthographic projection of the light shielding layer on the substrate.

[0031] According to a second aspect of the embodiments of the present application, a display panel is further provided, comprising:

[0032] an array substrate; and

[0033] a pixel expression layer arranged on the array substrate;

[0034] wherein at least two active layers are arranged in the array substrate, the active layers are connected in parallel, and the array substrate is the array substrate provided in the embodiments of the present application.

[0035] The beneficial effects of this invention are as follows: Compared with the prior art, this application provides an array substrate and a display panel. The array substrate includes a first active layer, a gate, a gate insulating layer, a second active layer, and source / drain metal layers. The array substrate also includes a conductor layer disposed between the first and second active layers, and the first active layer is connected in parallel with the second active layer through the conductor layer. In this application, by setting a two-layer parallel active layer structure, the on-state current and carrier mobility of the thin-film transistor are effectively improved. Furthermore, in this application, the vertical arrangement of the two-layer parallel active layer structure effectively reduces the layout area of ​​the active layers, further improving the overall performance of the array substrate. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the film layer structure of an array substrate provided in an embodiment of this application;

[0038] Figure 2 This is a schematic diagram of a portion of the film layer structure of the array substrate provided in an embodiment of this application;

[0039] Figure 3 A schematic diagram of the film structure of another array substrate provided in an embodiment of this application;

[0040] Figure 4 A schematic diagram of the film structure of another array substrate provided in an embodiment of this application;

[0041] Figure 5 A schematic diagram of the film structure of another array substrate provided in an embodiment of this application;

[0042] Figure 6 This is a schematic diagram of the film layer structure of an array substrate provided in an embodiment of this application;

[0043] Figures 7-13 These are schematic diagrams of the film structure corresponding to different preparation processes provided in the embodiments of this application;

[0044] Figure 14 for Figure 1 A simplified planar schematic diagram of some film layers in the array substrate provided in the diagram;

[0045] Figure 15 for Figure 1 The side view of the array substrate provided. Detailed Implementation

[0046] The following description, in conjunction with the accompanying drawings of the embodiments of the present invention, provides different implementation methods or examples to realize different structures of the present invention. To simplify the present invention, the components and arrangements of specific examples are described below. Furthermore, the various specific processes and materials provided in the present invention are examples that those skilled in the art will recognize for the application of other processes. All other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0047] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0048] With the continuous development of display panel manufacturing technology, people have put forward higher requirements for the performance and display effect of display panels and display devices.

[0049] The performance of a display device is closely related to the performance of its internal components. In the existing technology, the thin-film transistors (TFTs) fabricated within the display panel often exhibit suboptimal performance, such as unsatisfactory on-state current and carrier mobility. This reduces device quality and effectiveness, hindering the improvement of the overall performance of the display device.

[0050] This application provides an array substrate and a display panel to effectively improve the overall performance of the display panel.

[0051] like Figure 1 As shown, Figure 1 This is a schematic diagram of the film layer structure of an array substrate provided in an embodiment of this application. The array substrate provided in this embodiment has a multi-film layer structure. Specifically, it includes a substrate 101, a light-shielding layer 110, a buffer layer 102, a first active layer 31, a first gate insulating layer 103, a gate 222, a second gate insulating layer 104, a second active layer 32, an interlayer insulating layer 105, and a source 201 and a drain 202.

[0052] Specifically, the light shielding layer 110 is disposed on the substrate 101, and the buffer layer 102 is disposed on the substrate 101 and covers the light shielding layer 110 completely. The first active layer 31 is disposed on the buffer layer 102, and the first gate insulating layer 103 is disposed on the first active layer 31 and covers the first active layer 31 completely.

[0053] Meanwhile, the gate 222 is disposed on the first gate insulating layer 103, the second gate insulating layer 104 is disposed on the first gate insulating layer 103 and covers the gate 222 completely, the second active layer 32 is disposed on the second gate insulating layer 104, the interlayer insulating layer 105 is disposed on the second gate insulating layer 104 and covers the second active layer 32 completely.

[0054] And the source 201 and the drain 202 disposed on the interlayer insulating layer 105. The source 201 and the drain 202 correspond to the source / drain metal layer of the thin film transistor in the array substrate. That is, the source / drain metal layer in the embodiment of the application corresponds to the source 201 and the drain 202 respectively. Specifically, the source 201 and the drain 202 are disposed at positions corresponding to the first active layer 31 and the second active layer 32 respectively, and the source 201 and the drain 202 are electrically connected to the second active layer 32 at least through corresponding vias.

[0055] Further, the array substrate further comprises a planarization layer 106 disposed on the interlayer insulating layer 105 and covering the source 201 and the drain 202 completely. And the first electrode layer 107 and the passivation layer 108 disposed on the planarization layer 106. The first electrode layer 107 is disposed on the planarization layer 106 and the passivation layer 108 covers the first electrode layer 107 completely, wherein the first electrode layer 107 can be a first pixel electrode.

[0056] Meanwhile, the array substrate further comprises a second electrode layer 109 disposed on the passivation layer 108 and electrically connected to the drain 202 through corresponding vias, wherein the second electrode layer 109 can be a second pixel electrode.

[0057] In the embodiment of the application, in the array substrate, the first active layer 31, the gate 222, the second active layer 32, the source 201, the drain 202 and the corresponding interlayer dielectric layers form a thin film transistor 203. The thin film transistor 203 is used to provide driving and control signals to the display device. Meanwhile, in the thin film transistor 203, the first active layer 31 and the second active layer 32 are included and the first active layer 32 and the second active layer 32 are in parallel connection, thereby effectively improving the on-state current and other performances of the thin film transistor 203.

[0058] In the following specific embodiments, the thin film transistor 203 is formed by at least two active layers in parallel, and the active layers are exemplified by a first active layer 31 and a second active layer 32. The two active layers are arranged in a stacked structure between the film layers, for example, the orthographic projections of the active layers on the substrate correspond to each other or are located in the same region.

[0059] Preferably, the orthographic projection of the second active layer 32 on the substrate is located in the region corresponding to the orthographic projection of the first active layer 31 on the substrate. For example, the orthographic projections of the two are completely coincident. Alternatively, the orthographic projection of the second active layer is located in the region of the orthographic projection of the first active layer. When the orthographic projection of the first active layer 31 and the orthographic projection of the second active layer 32 are completely coincident, the second active layer 32 is arranged directly above the first active layer 31, thereby effectively saving the layout space of different active layers in the array substrate to improve the performance of the device.

[0060] Further, in the embodiments of the present application, the first active layer 31 includes a first doped region 316 and a first channel region 313, and the first doped region 316 is correspondingly arranged at both sides of the first channel region 313. The second active layer 32 includes a second doped region 317 and a second channel region 323, and the second doped region 317 is correspondingly arranged at both sides of the second channel region 323. The first doped region 316 and the second doped region 317 are correspondingly arranged, and the first channel region 313 and the second channel region 323 are correspondingly arranged. Preferably, the second doped region 317 is arranged at a position directly above the first doped region 316, and the second channel region 323 is arranged at a position directly above the first channel region 313.

[0061] The projection length of the orthographic projection of the second doped region 317 on the substrate is greater than the projection length of the orthographic projection of the first doped region 316 on the substrate.

[0062] In the embodiments of the present application, the first doped region 316 of the first active layer 31 and the second doped region 317 of the second active layer 32 can be the doped regions of the active layer. In the following embodiments, the first doped region 316 and the second doped region 317 are exemplified by doped regions.

[0063] Specifically, in the first active layer 31, the first doped region 316 includes a lightly doped region 312 and a heavily doped region 311 of the first active layer 31. The lightly doped region 312 and the heavily doped region 311 are arranged adjacent to each other, and the lightly doped region 312 is arranged at one side close to the first channel region 313. Preferably, the lightly doped region 312 and the heavily doped region 311 of the first active layer 31 are symmetrically arranged with respect to the first channel region 313.

[0064] Meanwhile, in the second active layer 32, the second doped region 317 includes a lightly doped region 322 and a heavily doped region 321 of the second active layer 32. The lightly doped region 322 is arranged adjacent to the heavily doped region 321, and the lightly doped region 322 is arranged on a side close to the second channel region 323. Preferably, the lightly doped region 322 and the heavily doped region 321 are symmetrically arranged relative to the second channel region 323.

[0065] In the embodiment, the lightly doped region 312 of the first active layer 31 is arranged corresponding to the lightly doped region 322 of the second active layer 32, and the heavily doped region 311 of the first active layer 31 is arranged corresponding to the heavily doped region 321 of the second active layer 32. Preferably, both are arranged at positions directly above the corresponding regions.

[0066] The source / drain metal layer is arranged at a position corresponding to the second doped region 317 and is electrically connected to the second active layer 32. Specifically, the source electrode 201 is arranged above the heavily doped region 321 of the second doped region 317, and the drain electrode 202 is arranged above the heavily doped region 321 of the other second doped region 317.

[0067] Specifically, the array substrate further includes a first via hole 250 and a second via hole 251. The first via hole 250 and the second via hole 251 are arranged above the doped region of the first active layer 31, and the first via hole 250 and the second via hole 251 penetrate the second active layer 32 and form a through-hole structure in the doped region 321 of the second active layer 32.

[0068] In the embodiment, the source / drain metal layer is electrically connected to the first active layer 31 and the second active layer 32 through the first via hole 250 and the second via hole 251. Thus, the first active layer 31 and the second active layer 32 form a parallel structure.

[0069] Further, as shown in Figure 14 and Figure 15 , the array substrate provided in the embodiment is a plane simplified schematic view corresponding to part of the film layers in the array substrate, Figure 14 is a side view of the array substrate provided in the embodiment. Details are shown in Figure 1 , the gate electrode 222 in the thin film transistor is arranged above the first active layer. Specifically, the first active layer includes a heavily doped region 311, a lightly doped region 312, and a channel region 313. Meanwhile, the gate electrode 222 is arranged above the channel region 313. Details are shown in Figure 15 , when the first active layer 31, the second active layer 32, and the light shielding layer 110 are arranged, the three can be located in the same vertical direction. Figure 1 Figure 14 Specifically, as shown in Figure 15 , the first active layer 31, the second active layer 32, and the light shielding layer 110 are arranged in the same vertical direction.

[0070] Specifically, as shown in Figure 2 ​As shown, Figure 2 A schematic diagram of a partial film layer structure of an array substrate provided in an embodiment of the present application is shown.

[0071] In the embodiment of the present application, a conductor layer 45 is further provided in the array substrate. The conductor layer 45 is provided in a corresponding film layer between the first active layer 31 and the second active layer 32, and the first active layer 31 is connected to the second active layer 32 through the conductor layer 45, and the first active layer 31 and the second active layer 32 form a parallel structure.

[0072] Specifically, in the embodiment of the present application, the conductor layer 45 is taken as an example of a first conductor layer 451 and a second conductor layer 452. The first conductor layer 451 and the second conductor layer 452 are respectively provided in a region between the heavily doped region 311 of the first active layer 31 and the heavily doped region 321 of the second active layer 32. Meanwhile, one end of the first conductor layer 451 is electrically connected to the heavily doped region 311 of the first active layer 31, and the other end of the first conductor layer 451 is electrically connected to the heavily doped region 321 of the second active layer 32. And both ends of the second conductor layer 452 are electrically connected to the heavily doped regions of the active layers on the other side.

[0073] Preferably, in the embodiment of the present application, when the conductor layer is electrically connected to the second active layer 32, it can be connected through direct contact. That is, the conductor layer is directly provided at the position of the heavily doped region of the second active layer 32, and a via hole is etched in other film layers to be electrically connected to the first active layer 31 at the bottom.

[0074] Meanwhile, the conductor layer 45 can also be directly provided in the first via hole and the second via hole. Preferably, the first conductor layer 451 is provided in the first via hole 250, and the second conductor layer 452 is provided in the second via hole 251. In the formation of the first via hole 250 and the second via hole 251, they can be formed through one-time etching, and the conductor layer can be directly filled in the via hole, thereby effectively simplifying the preparation process and improving the performance of the device.

[0075] In the embodiment of the present application, the first via hole 250 and the second via hole 251 can be symmetrically provided relative to the second channel region 323, and preferably, the first via hole 250 and the second via hole 251 are respectively provided at the middle positions of the heavily doped regions 321.

[0076] Further, in the embodiment of the present application, the first via hole 250 and the second via hole 251, when penetrating through the first active layer 31, divide the corresponding heavily doped region into two parts, such as the first part 3211 and the second part 3212 on the other side. In the embodiment of the present application, the doping concentration of the first part 3211 and the doping concentration in the second part 3212 can be different, such as the ion doping concentration in the second part 3212 on the outside is greater than the ion doping concentration in the first part 3211, so as to form different concentration differences, so as to further improve the mobility of the carriers in the device.

[0077] Preferably, the first part 3211 can also form another concentration difference with the lightly doped region, and the ion concentration in the first part 3211 is greater than the ion concentration in the lightly doped region, so as to further improve the performance of the device. Specifically, the concentration difference in different regions can be set according to the actual product, which will not be described in detail here.

[0078] When the first via hole 250 and the second via hole 251 are arranged in the active layer 32, the corresponding conductor layer can extend into the via hole and be electrically connected to the second active layer 32 through the via hole.

[0079] Meanwhile, the materials of the first conductor layer 451 and the second conductor layer 452 can be the same material, such as any one of Ti, Al, Mo and Ti / Al composite material, or other metal materials with good electrical properties. Further, the material of the conductor layer can also be the same as the material in the heavily doped region of the first active layer 31. When the material of the conductor layer is the same as the material in the heavily doped region of the first active layer 31, the material of the conductor layer is N-type heavily doped material or P-type heavily doped material.

[0080] Specifically, as shown in Figure 1 In the embodiment of the present application, the via hole corresponding to the source / drain metal layer is etched directly from the interlayer dielectric layer 105 to the corresponding position of the first active layer 31. In this way, the conductor layer is equivalent to part of the source / drain metal layer, and the parallel structure of the first active layer 31 and the second active layer 32 is realized through the source / drain metal layer. Thus, the process of the thin film transistor is effectively simplified and the overall performance of the device is improved.

[0081] Further, in the embodiment of the present application, when the first active layer 31 and the second active layer 32 are arranged, the length of the first active layer 31 can be greater than or equal to the length of the second active layer 32. That is, the length of the orthogonal projection of the first active layer 31 on the substrate is greater than or equal to the length of the orthogonal projection of the second active layer 32 on the substrate.

[0082] Meanwhile, in order to ensure the performance of the thin film transistor, in the embodiment of the present application, when the first active layer 31 and the second active layer 32 are arranged, the length of the first channel region 313 of the first active layer 31 is greater than the length of the channel region 323 of the second active layer 32. Meanwhile, the length of the lightly doped region 312 of the first active layer 31 is less than the length of the lightly doped region 322 of the second active layer 32.

[0083] Preferably, the length of the first channel region 313 of the first active layer 31 is set to 2.1um-3.1um, and the length of the second channel region 323 of the second active layer 32 is set to 1.5um-2.5um. Correspondingly, the length of the first channel region 313 of the first active layer 31 is 0.4um-1.6um longer than the length of the second channel region 323 of the second active layer 32. For example, the length of the first channel region 313 of the first active layer 31 is 0.6um longer than the length of the second channel region 323 of the second active layer 32.

[0084] Meanwhile, the length of the lightly doped region 322 of each side of the second active layer 32 is set to 1.0um-2.0um. Preferably, the length of the lightly doped region 322 of one side of the second active layer 32 is set to 1.5um. Meanwhile, the length of the lightly doped region 312 of each side of the first active layer 31 is set to 0.7um-1.7um. Preferably, the length of the lightly doped region 312 of one side of the first active layer 31 is set to 1.2um. At this time, the length of the lightly doped region 312 of the first active layer 31 is 0.3um shorter than the length of the lightly doped region 322 of the second active layer 32.

[0085] Further, in the embodiment of the present application, the length of the heavily doped region of each side of the first active layer 31 and the second active layer 32 is set to 2.5um-3.2um, for example, 3um. In the embodiment of the present application, by setting the different functional regions in the first active layer 31 and the second active layer 32 to different parameters, the performance of the thin film transistor is effectively improved, and the upper active layer is prevented from being offset to affect the performance of the lower active layer when different active layers are prepared.

[0086] In the embodiment of the present application, when the gate 222 of the thin film transistor is arranged, the length of the gate 222 is not less than the length of the channel region of the first active layer 31, and the length of the gate 222 is not less than the length of the channel region of the second active layer 32.

[0087] Further, as shown in Figure 3 , Figure 3 Another array substrate film layer structure schematic diagram provided by the embodiment of the present application. Meanwhile, in combination with Figures 1-2The array substrate can further include a connecting metal layer 46. The connecting metal layer 46 is arranged at the corresponding film layer between the first active layer 31 and the second active layer 32. In the following embodiments, the connecting metal layer 46 is arranged on the first gate insulating layer 103, and the connecting metal layer 46 is arranged in the same layer as the gate 222.

[0088] In the following embodiments, the connecting metal layer 46 is taken as an example of a first connecting metal layer 461 and a second connecting metal layer 462, which are arranged at the corresponding positions of the two heavy doped regions, respectively. In the embodiments, the connecting metal layer corresponds to a transition connecting film layer of the conductor layer, and the connecting metal layer is arranged to reduce the via depths of the first via and the second via, thereby improving the stability of the connection between devices and further improving the comprehensive performance of the thin film transistor.

[0089] Specifically, in the embodiments, the heavy doped region 321 of the second active layer 32 is provided with a via structure, and the source 201 and the drain 202 of the thin film transistor are electrically connected to the corresponding connecting metal layer through the via structure. Specifically, the source 201 is electrically connected to the second active layer 32 through a via, and one end of the source 201 is further electrically connected to the first connecting metal layer 461. The drain 202 is electrically connected to the second active layer 32 through another via, and one end of the drain 202 is further electrically connected to the second connecting metal layer 462. Thus, the first active layer 31 and the second active layer 32 are connected in parallel through the source / drain metal layer and the connecting metal layer.

[0090] Preferably, the first connecting metal layer 461 and the second connecting metal layer 462 each include an extension part 4611 and a main part 4612. The extension part 4611 is arranged at the edge position of the main part 4612, for example, as a planar structure. The projection of the extension part 4611 on the substrate is located within the orthographic projection of the heavy doped region 321 on the substrate. Thus, the performance of the thin film transistor is ensured.

[0091] In the embodiments, the via corresponding to the connecting metal layer can be arranged corresponding to the first via and the second via. Thus, the source / drain metal layer and the connecting metal layer are located in the same vertical plane, thereby reducing the complexity of the process.

[0092] In the embodiments, the material of the connecting metal layer 46 can be the same as that of the gate. The connecting metal layer and the gate are prepared in the same layer, thereby further simplifying the preparation process of the device. For example, both of them are made of metal Mo or other metal materials with good electrical properties, which will not be described in detail here.

[0093] As shown in FIG. 4, the first connecting metal layer 461 and the second connecting metal layer 462 are arranged at the corresponding positions of the two heavy doped regions, respectively. Figure 4 Figure 4 ​Another array substrate film layer structure schematic view provided by the embodiment of the present application. In the embodiment of the present application, the first via hole 250 and the second via hole 251 are arranged between the first active layer 31 and the second active layer 32. The heavily doped region 311 of the first active layer 31 is electrically connected to the heavily doped region 321 of the second active layer 32 through the first via hole and the second via hole.

[0094] Specifically, when the connection is made, the material in the first via hole 250 and the second via hole 251 can be the same as the material of the heavily doped region of the second active layer 32, for example, the material can correspond to N-type heavily doped material or P-type heavily doped material.

[0095] Compared with the deep via hole structure corresponding to the source / drain metal layer, in the embodiment of the present application, the first via hole 250 and the second via hole 251 are directly arranged between the first active layer 31 and the second active layer 32, thereby effectively reducing the depth of the via hole structure, simplifying the preparation process, and effectively improving the stability of the connection. Figure 1

[0096] Preferably, as shown in FIG. 2, the first via hole 250 and the second via hole 251 are arranged in the array substrate 10. Figure 5 Figure 5 Another array substrate film layer structure schematic view provided by the embodiment of the present application. Meanwhile, in combination with the film layer structure in FIG. 1, in the embodiment of the present application, the array substrate is provided with a third via hole 271 and a fourth via hole 272. The third via hole 271 and the fourth via hole 272 are arranged at positions corresponding to the heavily doped regions. The third via hole 271 and the fourth via hole 272 penetrate the second active layer 32 and other film layers and extend to the surface of the first active layer 31. At this time, the third via hole 271 and the fourth via hole 272 can be obtained through one photomask processing, thereby simplifying the preparation process. Figures 1-4 In the embodiment of the present application, the source electrode 201 is arranged in the third via hole 271, and the drain electrode 202 is arranged in the fourth via hole 272. The source electrode 201 is arranged in the via hole corresponding to the second active layer and extends to the surface of the first active layer 31. The drain electrode 202 is arranged in the via hole corresponding to the second active layer and extends to the surface of the first active layer 31.

[0097] Further, in the embodiment of the present application, the source electrode 201 and the drain electrode 202 are directly arranged on the surface of the second active layer 32. The source electrode 201 and the drain electrode 202 are electrically connected to the second active layer 32 and the first active layer 31 through the third via hole 271 and the fourth via hole 272, respectively, thereby realizing the parallel structure of the first active layer 31 and the second active layer 32.

[0098]

[0099] ​​​In the embodiment, the source 201 and the drain 202 are directly arranged on the surface of the second active layer 32, so that the source / drain metal layer and the active layer are in surface contact, and the contact surface is large, and the source / drain metal layer is directly arranged on the second active layer 32, so that a layer of interlayer dielectric layer can be omitted. Therefore, the array substrate prepared in the embodiment can effectively improve the connection stability between the source / drain metal layer and the active layer and the comprehensive performance of the device.

[0100] Further, as shown in Figure 6 , Figure 6 is a schematic diagram of a film layer structure of an array substrate provided in the embodiment. In combination with the film layer structure in the embodiment, Figure 3 in the embodiment, when the source / drain metal layer and the connection metal layer 46 are arranged, the source / drain metal layer is directly arranged on the second active layer 31, and the source 201 and the drain 202 are arranged in the third via hole 271 and the fourth via hole 272, respectively.

[0101] In the embodiment, the first connection metal layer 461 and the second connection metal layer 462 can be prepared in the same layer as the gate 222, so as to simplify the preparation process. Preferably, the materials of the first connection metal layer 461 and the second connection metal layer 462 can be the same as the material of the gate 222, and can be selected as metal Mo.

[0102] Further, when the via hole structure in the corresponding position is arranged, the fifth via hole 611 and the sixth via hole 612 are further arranged on the first gate insulating layer 103 and penetrate the layer. The fifth via hole 611 and the sixth via hole 611 are arranged correspondingly to the third via hole 271 and the fourth via hole 272, the first connection metal layer 461 is arranged in the fifth via hole 611 and is electrically connected to the first active layer 31, and the second connection metal layer 462 is arranged in the sixth via hole 612 and is electrically connected to the first active layer 32.

[0103] In combination with the structure in Figure 1 , in the embodiment, the connection metal layer and the via hole are arranged in the film layer between the first active layer 31 and the second active layer 32, so as to reduce the depth of the via hole and simplify the preparation process, and effectively improve the performance of the via hole inside the device and the stability of the connection between the devices.

[0104] At this time, the corresponding source / drain metal layer and the connection metal layer in the first gate insulating layer 103 and the second gate insulating layer 104 form a parallel structure of the first active layer and the second active layer.

[0105] Further, in the embodiment, when the above film layer structure is arranged, in order to reduce the thickness of the formed display panel as much as possible, the thicknesses of the first active layer 31 and the second active layer 32 are set to Meanwhile, the thickness of the first gate insulating layer 103 and the second gate insulating layer 104 is set to The corresponding material can be insulating SiO x , etc. The thickness of the interlayer insulating layer 105 is set to The corresponding material can be SiO x , SiN x , or at least one of them. Or it is set according to the specifications of the actual product, which is not described here.

[0106] Preferably, the application also provides a preparation method of an array substrate. In the following embodiments, the preparation process corresponding to the film layer structure provided in Figure 1 is taken as an example for description. As shown in Figures 7-13 , the film layer structure corresponding to different preparation processes provided in the application is shown in the following figures. Figures 7-13

[0107] Specifically, first, a substrate 101 is provided, and a light shielding layer 110 is prepared on the substrate 101. At the same time, a buffer layer 102 is prepared on the light shielding layer 110. And a semiconductor layer is prepared on the buffer layer 102.

[0108] After preparation, the semiconductor layer is subjected to conductorization treatment, and forms a heavily doped region 311, a lightly doped region 312, and a first channel region 313. In the application, the first channel region 313 can correspond to a polysilicon layer subjected to ion doping. And the first active layer 31 in the application is formed.

[0109] As shown in Figure 9 , after the preparation of the first active layer 31 is completed, a first gate insulating layer 103 is prepared on the first active layer 31, at the same time, a gate 222 is prepared on the first gate insulating layer 103, and a second gate insulating layer 104 is prepared on the gate 222. In the application, the first gate insulating layer 103 completely covers the first active layer 31, and the second gate insulating layer 104 completely covers the gate 222. And a second active layer 31 is prepared on the second gate insulating layer 104.

[0110] In the application, the light shielding layer 110, the first active layer 31 and the second active layer 32, and the gate 222 can be correspondingly set, that is, the above-mentioned film layers can be set in the same vertical plane, and the length of the light shielding layer 110 is greater than the total length of the first channel region 313 and the lightly doped region 312 of the first active layer 31. At the same time, the material of the light shielding layer 110 can be the same as that of the connecting metal layer, the conductor layer or the source / drain metal layer.

[0111] As shown in Figure 10 ​In the forming of the second active layer 32, a semiconductor layer is prepared on the second gate insulating layer 104, and ion doping is performed on the semiconductor layer, and finally the second active layer 32 in the embodiment of the present application is formed. The second active layer 32 also includes a heavily doped region 321, a lightly doped region 322 and a second channel region 323. In the embodiment of the present application, the ion concentration in the heavily doped region 321 and the lightly doped region 322 can be set according to actual products.

[0112] As shown in Figure 11 After the preparation of the second active layer 32, a planarization layer 106 is prepared on the second active layer 32. In the embodiment of the present application, the planarization layer 106 completely covers the second active layer 32. After the preparation of the planarization layer 106, a hole is opened at the position corresponding to the active layer of the thin film transistor.

[0113] Specifically, the first third via hole 271 and the fourth via hole 272 are arranged at the positions corresponding to the first active layer 31 and the second active layer 32. At this time, the third via hole 271 penetrates the heavily doped region 321 of the second active layer 32, and at the same time penetrates the planarization layer 106, the first gate insulating layer 103 and the second gate insulating layer 104, and exposes part of the first active layer 31.

[0114] At this time, since the third via hole 271 and the fourth via hole 272 have a relatively deep depth, they can be etched by two etching processes. In the first etching process, the third via hole 271 is etched to the surface of the second gate insulating layer 104, and then in the second etching process, it is etched from the surface of the second gate insulating layer 104 to the surface of the first active layer 31, and finally the via hole structure provided in the embodiment of the present application is formed.

[0115] In the embodiment of the present application, the via hole in the second active layer 31 coincides with the corresponding third via hole 271 or fourth via hole 272. At the same time, the size of the via hole in the active layer 31 can be determined according to the specifications of the actual product, and when etching, the via hole is located at the center region of the heavily doped region.

[0116] As shown in Figure 12 After the etching of the third via hole 271 and the fourth via hole 272, a source electrode 201 is prepared in the third via hole 271, and a drain electrode 202 is prepared in the fourth via hole 272, and the source electrode 201 and the drain electrode 202 are electrically connected with the first active layer 31 and the second active layer 32.

[0117] After the source / drain metal layer is prepared, a planarization layer 106 is prepared on the interlayer insulating layer 105, and at the same time, a via hole 725 is formed by etching the planarization layer 106 at a position corresponding to the drain electrode 202. The surface of the drain electrode 202 is exposed through the via hole 725. Meanwhile, a first electrode layer 107 is prepared on the planarization layer 106.

[0118] For details Figure 13 After the first electrode layer 107 is prepared, a passivation layer 108 is prepared on the planarization layer 106, and the passivation layer 108 completely covers the first electrode layer 107.

[0119] At the same time, the passivation layer 108 is etched at a position corresponding to the via hole 725, and a via hole 726 is formed in the via hole 725, and the aperture of the via hole 726 is smaller than the aperture of the via hole 725.

[0120] A second electrode layer 109 is prepared on the passivation layer 108, and the second electrode layer 109 fills the via hole 726 and is electrically connected to the drain electrode 202.

[0121] In the embodiment of the present application, a double-layer active layer parallel structure is prepared. When the thin film transistor in the array substrate works normally, the parallel structure can effectively improve the on-state current in the device, and further improve the carrier migration efficiency of the device.

[0122] At the same time, in the embodiment of the present application, the first active layer and the second active layer are arranged in a double-layer vertical structure, thereby effectively reducing the layout area of the device in the array substrate. Moreover, when the array substrate and the corresponding display panel are prepared, the preparation can be performed in the existing process, which is compatible with the existing process. At the same time, the preparation method and process provided in the present application are simpler, and the comprehensive performance of the device can be further improved.

[0123] Further, the embodiment of the present application also provides a display panel. The display panel can include an array substrate and a pixel expression layer arranged on the array substrate. In the embodiment of the present application, the pixel expression layer can include a liquid crystal layer, an organic light-emitting functional film layer, an electrophoretic layer, etc. The pixel expression layer is used to realize or assist to realize the light-emitting display of the display panel. The thin film transistor of the display panel provided in the embodiment of the present application adopts a double-layer parallel structure, thereby effectively improving the light-emitting efficiency and the comprehensive performance of the display panel.

[0124] The display panel can be a mobile phone, a computer, an electronic paper, a display, a notebook computer, a digital photo frame, or any product or component having a display function and a touch function, and the specific type is not limited.

[0125] In summary, the array substrate and the display panel provided by the embodiment of the present application are described in detail above, the principle and the implementation manner of the present application are described by applying specific examples in this paper, and the above embodiment is only used to help understand the technical scheme of the present application and the core idea thereof; although the present application is disclosed as above with the preferred embodiment, the above preferred embodiment is not used to limit the present application, and various changes and modifications can be made by those skilled in the art without departing from the spirit and the scope of the present application, so the protection scope of the present application is based on the range defined by the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; A first active layer is disposed on the substrate, the first active layer including a first channel region and first doped regions disposed on both sides of the first channel region; A gate is disposed above the first active layer; A gate insulating layer is disposed on the first active layer and covers the gate; The second active layer is disposed on the gate insulating layer, and the second active layer includes a second channel region and second doped regions disposed on both sides of the second channel region; as well as, A source / drain metal layer is disposed on the second active layer and includes a source and a drain. The first doped region and the second doped region are respectively provided, the source / drain metal layer is electrically connected to the second doped region, and the first active layer in the first doped region is electrically connected to the second active layer in the second doped region. The first active layer, the corresponding gate, the corresponding gate insulating layer, the corresponding second active layer, and the corresponding source / drain metal layer form a corresponding thin film transistor, and the first active layer and the second active layer in the thin film transistor are arranged in parallel. The array substrate further includes a first via and a second via, which are disposed above the first doped region and penetrate the gate insulating layer and the second active layer. The source and the drain are electrically connected to the first doped region and the second doped region through the first via and the second via, respectively. The first via and the second via penetrate the second active layer to divide the corresponding second doped region into a first part and a second part located on both sides of the first via or the second via, and the doping concentration of the first part and the doping concentration of the second part are different.

2. The array substrate according to claim 1, characterized in that, The length of the orthographic projection of the second doped region on the substrate is greater than the length of the orthographic projection of the first doped region on the substrate.

3. The array substrate according to claim 1, characterized in that, Both the first doped region and the second doped region include a heavily doped region and a lightly doped region, wherein the lightly doped region is adjacent to the heavily doped region, and the heavily doped region is disposed away from the channel region; Wherein, the heavily doped region of the first active layer corresponds to the heavily doped region of the second active layer, the lightly doped region of the first active layer corresponds to the lightly doped region of the second active layer, and the source / drain metal layer is electrically connected to the corresponding second active layer within the heavily doped region.

4. The array substrate according to claim 3, characterized in that, The heavily doped region of the first active layer is connected to the heavily doped region of the second active layer through the first via and the second via.

5. The array substrate according to claim 4, characterized in that, The array substrate further includes a conductor layer disposed within the first via and the second via, and the first active layer is connected in parallel with the second active layer through the conductor layer.

6. The array substrate according to claim 5, characterized in that, The material of the conductor layer is the same as the material of the second active layer corresponding to the heavily doped region.

7. The array substrate according to claim 3, characterized in that, The array substrate further includes a third via and a fourth via. The source / drain metal layer is disposed on the surface of the heavily doped region of the second active layer, and the source / drain metal layer is electrically connected to the heavily doped region of the first active layer through the third via and the fourth via.

8. The array substrate according to claim 7, characterized in that, The third and fourth vias penetrate the heavily doped region of the second active layer.

9. The array substrate according to claim 3, characterized in that, The source / drain metal layer is disposed on the upper surface of the heavily doped region of the second active layer. The source / drain metal layer is electrically connected to the second active layer and electrically connected to the first active layer through corresponding vias.

10. The array substrate according to claim 3, characterized in that, The array substrate further includes a connecting metal layer, which is disposed within a corresponding film layer between the first active layer and the second active layer.

11. The array substrate according to claim 10, characterized in that, The connecting metal layer is disposed on the same layer as the gate, and the connecting metal layer is electrically connected to the source / drain metal layer and the heavily doped region of the first active layer.

12. The array substrate according to claim 11, characterized in that, The connecting metal layer is made of the same material as the gate.

13. The array substrate according to claim 3, characterized in that, The length of the lightly doped region in the first active layer is less than the length of the lightly doped region in the second active layer.

14. The array substrate according to claim 1, characterized in that, The first channel region and the second channel region are respectively disposed corresponding to the gate.

15. The array substrate according to claim 14, characterized in that, The orthographic projection of the second channel region onto the substrate lies within the orthographic projection of the first channel region onto the substrate.

16. The array substrate according to claim 1, characterized in that, The array substrate further includes a light-shielding layer disposed on the substrate, and the first active layer is disposed on the light-shielding layer.

17. A display panel, characterized in that, include: Array substrate; as well as, A pixel representation layer is disposed on the array substrate; The array substrate has at least two active layers, which are connected in parallel, and the array substrate is the array substrate as described in any one of claims 1-16.

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