Display substrate and method of manufacturing the same

Abstract

The present disclosure provides a display substrate and a preparation method thereof, and belongs to the technical field of display. The display substrate of the present disclosure comprises: a substrate, having a connecting via hole penetrating through the thickness direction thereof; the substrate comprises a first surface and a second surface oppositely arranged along the thickness direction thereof; a pixel driving circuit arranged on the first surface; a signal trace arranged on the second surface; a connecting structure arranged in the connecting via hole, and the connecting structure electrically connects the signal trace and the pixel driving circuit; wherein part of the connecting via hole is filled with the connecting structure.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display substrate and a preparation method thereof. BACKGROUND

[0002] With the development of integrated circuit technology, the voice of the end of Moore's law is getting stronger and stronger, and the planar integrated circuit is facing severe challenges. The emergence of 2.5D integration technology expands the integrated space to the third dimension, which significantly improves the utilization of space. Compared with the traditional planar integration technology, the 2.5D integration technology transmits signals through a vertical interconnection structure, has the advantages of high integration, low power consumption, flexible design, and easy implementation of heterogeneous integration. SUMMARY

[0003] The present application aims to at least solve one of the technical problems existing in the prior art, and provides a display substrate and a preparation method thereof.

[0004] The present disclosure provides a display substrate, which comprises:

[0005] A substrate has a connection via penetrating through its thickness direction; the substrate comprises a first surface and a second surface oppositely arranged along its thickness direction;

[0006] A pixel driving circuit is arranged on the first surface;

[0007] A signal trace is arranged on the second surface;

[0008] A connection structure is arranged in the connection via, and the connection structure electrically connects the signal trace and the pixel driving circuit; part of the connection via is filled with the connection structure.

[0009] The connection structure comprises a first substructure arranged on the side wall of the connection via, and a second substructure connected with the first substructure, and the outer contour of the second substructure is fitted with the first substructure.

[0010] The second substructure comprises a third surface and a fourth surface oppositely arranged along its thickness direction; the third surface is flush with the first surface, and the fourth surface is arranged on a plane which has a certain distance with the plane on which the second surface is arranged; or, the fourth surface is flush with the second surface, and the third surface is arranged on a plane which has a certain distance with the plane on which the first surface is arranged; or, the third surface is arranged on a plane which has a certain distance with the plane on which the first surface is arranged, and the fourth surface is arranged on a plane which has a certain distance with the plane on which the second surface is arranged.

[0011] The second substructure includes a first part and a second part; the outer contour of the first part and the outer contour of the second part are both fitted with the first substructure, and the first part and the second part have a certain spacing.

[0012] The surface of the first part away from the second part is flush with the first surface; the surface of the second part away from the first part is flush with the second surface.

[0013] The second substructure includes a third surface and a fourth surface oppositely arranged along the thickness direction thereof; the third surface is a curved surface and protrudes towards the fourth surface; and / or, the fourth surface is a curved surface and protrudes towards the third surface.

[0014] The second substructure includes a third surface and a fourth surface oppositely arranged along the thickness direction thereof; the third surface is a folded surface and protrudes towards the fourth surface; and / or, the fourth surface is a folded surface and protrudes towards the third surface.

[0015] The connecting structure is arranged in the connecting via to define a containing space; and the containing space is filled with a filling structure.

[0016] A first protective layer is covered on the sidewall of the connecting via, and the first protective layer is located between the sidewall of the connecting via and the connecting structure.

[0017] A first connection pad is further arranged on the second surface, and the signal trace is electrically connected with the connecting structure through the first connection pad.

[0018] The display substrate is prepared by the method.

[0019] A substrate is provided, which has a connecting via penetrating through along the thickness direction thereof; the substrate includes a first surface and a second surface oppositely arranged along the thickness direction thereof.

[0020] The connecting structure is formed in the connecting via of the substrate, a pixel driving circuit is formed on the first surface of the substrate, and a signal trace is formed on the second surface of the substrate; the connecting structure electrically connects the signal trace with the pixel driving circuit; and the connecting structure does not fill the connecting via.

[0021] The connecting structure includes a first substructure arranged on the sidewall of the connecting via, and a second substructure connected with the first substructure; the formation of the connecting structure includes:

[0022] Form a first conductive film on the first surface, the second surface and the sidewall of the connecting via as a seed layer, and sequentially perform plating and patterning processes to form the connecting structure; wherein the seed layer on the sidewall of the connecting via is the first substructure, and the structure in the connecting via and connected with the first substructure is the second substructure.

[0023] The second substructure includes a third surface and a fourth surface oppositely arranged along a thickness direction of the second substructure; the third surface is flush with the first surface, and the fourth surface is arranged on a plane having a certain distance from a plane on which the second surface is arranged; or the fourth surface is flush with the second surface, and the third surface is arranged on a plane having a certain distance from a plane on which the first surface is arranged; or the third surface is arranged on a plane having a certain distance from a plane on which the first surface is arranged, and the fourth surface is arranged on a plane having a certain distance from a plane on which the second surface is arranged.

[0024] The second substructure includes a first part and a second part, and the first part and the second part have a certain distance therebetween.

[0025] The surface of the first part away from the second part is flush with the first surface, and the surface of the second part away from the first part is flush with the second surface.

[0026] The second substructure includes a third surface and a fourth surface oppositely arranged along a thickness direction of the second substructure; the third surface is an arc surface and protrudes toward the fourth surface; and / or the fourth surface is an arc surface and protrudes toward the third surface.

[0027] The second substructure includes a third surface and a fourth surface oppositely arranged along a thickness direction of the second substructure; the third surface is a folded surface and protrudes toward the fourth surface; and / or the fourth surface is a folded surface and protrudes toward the third surface.

[0028] The preparation method further includes filling a filling structure in a containing space defined by the connecting structure formed in the connecting via.

[0029] The preparation method further includes forming a first protective layer on at least the sidewall of the connecting via before the step of forming the connecting via.

[0030] The preparation method further includes forming a first connecting pad on the second surface, and the signal trace is electrically connected with the connecting structure through the first connecting pad. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1A schematic view of a display substrate according to an embodiment of the present disclosure.

[0032] Figure 2 A schematic view of an intermediate product formed in step S11 of the first example of the disclosed embodiment.

[0033] Figure 3 A schematic view of an intermediate product formed in step S12 of the first example of the disclosed embodiment.

[0034] Figure 4 A schematic view of an intermediate product formed in step S13 of the first example of the disclosed embodiment.

[0035] Figure 5 A schematic view of an intermediate product formed in step S14 of the first example of the disclosed embodiment.

[0036] Figure 6 A schematic view of an intermediate product formed in step S15 of the first example of the disclosed embodiment.

[0037] Figure 7 A schematic view of an intermediate product formed in step S16 of the first example of the disclosed embodiment.

[0038] Figure 8 A schematic view of an intermediate product formed in step S17 of the first example of the disclosed embodiment.

[0039] Figure 9 A partial schematic view of a display substrate according to a second example of the disclosed embodiment.

[0040] Figure 10 A partial schematic view of a display substrate according to a third example of the disclosed embodiment.

[0041] Figure 11 A partial schematic view of a display substrate according to a fourth example of the disclosed embodiment.

[0042] Figure 12 A partial schematic view of a display substrate according to a fifth example of the disclosed embodiment.

[0043] Figure 13 A partial schematic view of a display substrate according to a sixth example of the disclosed embodiment. DETAILED DESCRIPTION

[0044] In order to enable a person skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0045] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning commonly understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" do not denote a quantity restriction, but mean that there is at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0046] The display substrate provided by the embodiments of the present disclosure includes a substrate 10, a pixel driving circuit, a signal trace 21, and a connecting structure 23. The substrate 10 has a connecting via 11 penetrating through the thickness direction of the substrate 10, and the substrate 10 includes a first surface and a second surface oppositely arranged along the thickness direction of the substrate 10. The pixel driving circuit is arranged on the first surface of the substrate 10, the signal trace 21 is arranged on the second surface of the substrate 10, and the connecting structure 23 is arranged in the connecting via 11. The signal trace 21 provides a driving signal for the pixel driving circuit through the connecting structure 23, that is, the signal trace 21 is electrically connected to the pixel driving circuit through the connecting structure 23. In particular, in the embodiments of the present disclosure, only part of the connecting via 11 is filled with the connecting structure 23, that is, the connecting structure 23 does not fill the connecting via 11 completely, so that the side wall burr of the connecting via 11 can be relieved, and the thermal stress caused by the mismatch of the thermal expansion coefficients of the substrate 10 and the connecting structure 23 due to the difference in materials can be avoided, thereby improving the yield and reliability level of the display substrate prepared and formed.

[0047] It should be noted that the connecting structure 23 fills part of the connecting via 11, and the outer contour of the connecting structure 23 needs to be in abutment with the side wall of the connecting via 11. When the connecting structure 23 is an integral structure, the connecting structure is a solid structure; when the connecting structure 23 is a split structure (that is, it includes multiple components), each part of the connecting structure 23 is a solid structure, and the outer contour of each part is in abutment with the side wall of the connecting via 11.

[0048] In some examples, the display substrate in the embodiments of the present disclosure can be applied to a liquid crystal display panel, an organic electroluminescence diode display panel, and a multi-part light distribution independent control light emitting diode backlight source.

[0049] Further, when the display substrate is applied to a liquid crystal display panel, the display substrate not only includes the above structure but also can include gate lines and data lines arranged on the first surface of the substrate 10, the gate lines and the data lines are arranged to cross to define a plurality of pixel units, each of the pixel units includes a pixel driving circuit and a pixel electrode, the pixel driving circuit includes a thin film transistor, a gate of the thin film transistor is connected to the gate line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor is connected to the pixel electrode. For example, when the electric field mode of the display panel is a horizontal electric field, a common electrode can also be arranged in each of the pixel units, and voltages are loaded to the pixel electrode and the common electrode to form an electric field to drive liquid crystal molecules in the display panel to deflect, so as to realize display of each pixel unit in a corresponding gray scale.

[0050] When the display substrate is applied to an organic electroluminescence diode display panel, the display substrate not only includes the above structure but also can include gate lines and data lines arranged on the first surface of the substrate 10, the gate lines and the data lines are arranged to cross to define a plurality of pixel units, each of the pixel units includes a pixel driving circuit and an organic electroluminescence diode electrically connected to the pixel driving circuit. The pixel driving circuit can be a typical 2T1C (2 thin film transistors and 1 storage capacitor), 7T1C (7 thin film transistors and 1 storage capacitor) or the like, each of the pixel driving circuits is connected to the corresponding gate line and data line, the working state of the pixel driving circuit is controlled by a switch voltage written on the gate line, and the organic electroluminescence diode is controlled by the size of a data voltage loaded on the data line, so as to realize display in different gray scales.

[0051] When applied to a multi-zone light distribution independently controlled light emitting diode backlight, the display substrate not only includes the above structure but also can include gate lines and data lines arranged on the first surface of the substrate 10, the gate lines and the data lines are arranged to cross to define a plurality of pixel units, each of the pixel units includes a pixel driving circuit and a multi-zone light distribution independently controlled light emitting diode electrically connected to the pixel driving circuit. The pixel driving circuit includes a thin film transistor, a gate of the thin film transistor is connected to the gate line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor is connected to an anode of the multi-zone light distribution independently controlled light emitting diode. The working state of the thin film transistor is controlled by a switch voltage written on the gate line, and whether the multi-zone light distribution independently controlled light emitting diode is lighted is controlled by the size of a data voltage loaded on the data line, so as to realize partitioned light control of the display panel.

[0052] In the embodiments of the present disclosure, the display substrate is not limited to the above three, and the above is only an exemplary description and does not constitute a limitation on the protection scope of the embodiments of the present disclosure. In addition, Figure 1 Only the display substrate is taken as an example of the display substrate of the multi-zone light distribution independently controlled light emitting diode. Among them, Figure 1Taking a bottom-gate thin-film transistor (TFT) as an example in the pixel driving circuit, a gate insulating layer 60 is disposed between the active layer and the gate of the TFT. A first signal line 102 is disposed on the gate layer of the TFT, and a second signal line 103 is disposed on the source and drain layers of the TFT. The first signal line 102 and the second signal line 103 are electrically connected through a via penetrating the gate insulating layer 60, and the first signal line is electrically connected to the connection structure 23. The electrical connection between the first and second signal lines is used to transmit the control signal input from the signal trace 21 to the pixel driving circuit. (Continue referring to...) Figure 1 A first interlayer insulating layer (ILS) is disposed on the source and drain layers of the thin-film transistor (TFT). A first power supply terminal (VDD), a second power supply terminal (VSS), and a transition electrode (101) are disposed on the first ILS 70. The first power supply terminal (VDD) is connected to the source of the TFT through a via penetrating the first ILS 70, and the transition electrode (101) is connected to the drain of the TFT through a via penetrating the first ILS 70. A second ILS 80 and a third ILS 90 are sequentially disposed on the first power supply terminal (VDD), the second power supply terminal (VSS), and the transition electrode (101). The anode of the light-emitting device (LED) 100 is electrically connected to the transition electrode (101) through a via penetrating the second ILS 80 and the third ILS 90, and the cathode of the LED 100 is electrically connected to the second power supply terminal (VSS) through a via penetrating the second ILS 80 and the third ILS 90.

[0053] In some examples, the connection structure 23 can be formed using an electroplating process, taking copper as an example. A first conductive film 20 is formed on the sidewall of the connection via 11 as a seed layer. The material of the first conductive film 20 is copper. Then, by placing the substrate 10 in an electroplating solution containing copper ions, the electroplating process fills the connection via 11 with copper and thickens the surface copper, forming the connection structure 23. It can be seen that the connection structure 23 located in the connection via 11 includes two parts: one part is the first substructure 231, i.e., the seed layer, disposed on the sidewall of the connection via 11; the other part is the structure thickened on the seed layer by the electroplating process, i.e., the second substructure 232. Since it is formed by the electroplating process, the first substructure 231 and the second substructure 232 are connected as a single structure.

[0054] In some examples, a first protective layer 30 is provided between the first substructure 231 of the connection structure 23 and the sidewall of the connection via 11 to protect the sidewall of the connection via 11. Of course, the first protective layer 30 also covers the first and second surfaces of the substrate 10, thereby avoiding damage to the first and second surfaces of the substrate 10 when electrical components are subsequently formed on the first and second surfaces of the substrate 10.

[0055] In this embodiment of the disclosure, the connection structure 23 is formed by electroplating as an example. The following specific examples will be used to describe the display substrate of this embodiment of the disclosure.

[0056] First example: such as Figure 1 As shown, the connection structure 23 in the display substrate includes a first substructure 231 and a second substructure 232. The first substructure 231 is disposed on the sidewall of the connection via 11 on the substrate 10, and the outer contour of the second substructure 232 is attached to and connected to the first substructure 231 to form an integral structure. The second substructure 232 has a third surface and a fourth surface disposed opposite to each other along its thickness direction. The third surface of the second substructure 232 is flush with the first surface of the substrate 10, and there is a certain distance between the plane containing the fourth surface of the second substructure 232 and the plane containing the second surface of the substrate 10.

[0057] In some examples, a first connection pad 22 is also formed on the second surface of the substrate 10. The first connection pad 22 is connected to the first connection structure 23 via a signal trace 21. In this way, after the driver chip is bonded to the first connection pad 22, a driving signal can be provided to the pixel driving circuit. Furthermore, the signal trace 21 and the first connection pad 22 can be integrally formed. Even further, the signal trace 21, the first connection pad 22, and the connection structure 23 can be an integral structure. For example, the first substructure 231 of the signal trace 21, the first connection pad 22, and the connection structure 23 can be an integral structure. That is, after forming a first conductive layer (seed layer) on the substrate 10 and electroplating to form the second substructure 232, the first conductive layer on the second surface of the substrate 10 can be patterned to form the signal trace 21 and the first connection pad 22 electrically connected to the first substructure 231.

[0058] In some examples, since there is a certain distance between the plane where the fourth surface of the second substructure 232 is located and the plane where the second surface of the substrate 10 is located, the connecting structure 23 is disposed in the connecting via 11 to define an accommodating space 111 (the remaining space in the connecting via 11 excluding the connecting structure 23). The accommodating space 111 is filled with a filling structure 40, which can be a resin material. The filling structure 40 not only has a supporting function, but also prevents the connecting structure 23 from oxidizing.

[0059] Furthermore, while forming the filling structure 40 within the accommodating space 111, a second protective layer 50 can also be formed on the side of the signal trace 21 facing away from the substrate 10 to prevent corrosion of the signal trace 21. It should be understood that since the first connection pad 22 needs to be bonded to the driver chip, the second protective layer 50 exposes the first connection pad 22.

[0060] In some examples, since the connection structure 23 is formed by an electroplating process, a first protective layer 30 is formed on the side of the connection structure 23 and the connection via 11 to protect the sidewall of the connection via 11. The material of the first protective layer 30 includes, but is not limited to, alumina, silicon oxide, etc.

[0061] against Figure 1 The following describes a method for fabricating the display substrate shown. Figure 2 A schematic diagram of the intermediate product formed in step S11 of the first example of the disclosed embodiment; Figure 3 A schematic diagram of the intermediate product formed in step S12 of the first example of the disclosed embodiment; Figure 4 A schematic diagram of the intermediate product formed in step S13 of the first example of the disclosed embodiment; Figure 5 A schematic diagram of the intermediate product formed in step S14 of the first example of the disclosed embodiment; Figure 6 A schematic diagram of the intermediate product formed in step S15 of the first example of the disclosed embodiment; Figure 7 A schematic diagram of the intermediate product formed in step S16 of the first example of the disclosed embodiment; Figure 8 This is a schematic diagram of the intermediate product formed in step S17 of the first example of the disclosed embodiment. (In conjunction with...) Figures 1-8 As shown, the method for fabricating this display substrate includes the following steps:

[0062] S11. A substrate 10 is provided, which has a through-hole 11 extending through its thickness direction. The substrate 10 includes a first surface and a second surface disposed opposite to each other along its thickness direction.

[0063] In some examples, the substrate 10 includes, but is not limited to, a glass substrate. In this embodiment, a glass substrate is used as an example. Step S11 may include forming the interconnect via 11 using methods such as sandblasting, photosensitive glass method, focused discharge method, plasma etching method, laser ablation method, electrochemical method, and laser-induced etching method.

[0064] The process of forming the connecting via 11 is explained below using laser-induced etching as an example.

[0065] (1) Cleaning: The glass substrate is put into the cleaning machine for cleaning.

[0066] In some examples, the thickness of the glass substrate is around 0.1mm-1.1mm.

[0067] (2) Laser drilling: a laser is used to form a plurality of connection vias 11 on the glass substrate by vertically incident laser beams on the surface of the glass substrate. Specifically, when the laser beams interact with the glass substrate, the atoms in the glass substrate are ionized and ejected from the surface of the glass substrate due to the high energy of the laser photons, and the drilled hole gradually deepens over time until the entire glass substrate is drilled through, i.e., a plurality of connection vias 11 are formed. The commonly used laser wavelengths are 532 nm, 355 nm, 266 nm, 248 nm, 197 nm, etc., the pulse width of the laser can be 1-100 fs, 1-100 ps, 1-100 ns, etc., and the type of laser can be a continuous laser or a pulsed laser. The laser drilling method can include but is not limited to the following two methods. The first method is to fix the relative position of the laser beam and the glass substrate when the spot diameter is large, and to directly drill through the glass substrate by high energy. At this time, the shape of the connection via 11 formed is a reverse circular truncated cone, and the diameter of the reverse circular truncated cone decreases from top to bottom (from the direction of the second surface to the first surface). The second method is to draw a circle on the glass substrate when the spot diameter is small, the focusing point of the spot is constantly changing, and the focusing depth is also constantly changing. A spiral line is drawn from the lower surface (the first surface) of the glass substrate to the upper surface (the second surface) of the glass substrate, and the spiral radius decreases from bottom to top. The glass substrate is cut into a circular truncated cone by the laser, and falls down due to gravity, and the connection via 11 is formed. The shape of the connection via 11 is a circular truncated cone.

[0068] In some examples, the aperture of the formed connection via 11 is about 10 μm-1 mm.

[0069] (3) HF etching: During the laser drilling process, a stress zone is formed in the area about 5-20 microns away from the hole on the inner wall of the first connection via 11. The surface of the glass substrate in this area is uneven and has a molten state with multiple burrs, and there are a large number of microcracks and macrocracks, and there is residual stress. At this time, a 2%-20% HF etching solution is used to perform wet etching at an appropriate temperature for a certain period of time to etch the glass in the stress zone, smooth the inside and the area near the hole on the surface of the connection via 11, and completely etch the stress zone.

[0070] S12, forming a first protective layer 30 on the first surface, the second surface of the substrate substrate 10 and the sidewall of the connection via 11.

[0071] In some examples, step S12 can use ALD (atomic layer deposition method) to form a first protective layer 30 covering the first surface, the second surface of the substrate substrate 10 and the sidewall of the connection via 11 to protect the sidewall of the connection via 11. The material of the first protective layer 30 includes but is not limited to aluminum oxide or silicon oxide, etc.

[0072] S13, forming the first conductive film 20 on the first surface, the second surface of the substrate 10 with the first protective layer 30 and the sidewall of the connecting via 11, the first conductive layer as a seed layer to form the connecting structure 23.

[0073] In some examples, step S13 can include using magnetron sputtering to deposit the first conductive film 20 as a seed layer on the first surface of the substrate 10, in the process, the first conductive film 20 is also deposited on the sidewall of the connecting via 11, then the substrate 10 is turned over, and the first conductive film 20 is also formed on the second surface of the substrate 10 using magnetron sputtering, of course, the first conductive film 20 on the second surface also serves as a seed layer.

[0074] In some examples, the material of the first conductive film 20 includes but is not limited to at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag).

[0075] S14, forming the signal line 21 and the first connecting pad 22 through a patterning process.

[0076] In some examples, step S14 can include coating photoresist on the second surface of the substrate 10, and then forming the signal line 21 and the first connecting pad 22 through exposure, development, and etching.

[0077] S15, forming the conductive film layer 200 by thickening the first conductive film 20 on the first surface of the substrate 10 and the part of the first conductive film 20 in the connecting via 11 through an electroplating process.

[0078] In some examples, step S15 can include placing the substrate 10 on the electroplating machine carrier, pressing the power pad, and placing it in the hole-filling electroplating tank (special hole-filling electrolyte is used in the tank). Add current, and keep the electroplating solution flowing rapidly on the surface of the substrate 10. The cations in the electroplating solution obtain electrons on the sidewall of the connecting via 11 to become atoms deposited on the inner wall. Through special matching of the special hole-filling electrolyte, it can be achieved that the copper is mainly deposited at a high speed in the first connecting hole (deposition speed 0.5-3um / min), while the first surface and the second surface of the substrate 10 are flat areas, and the deposition speed of copper on these two surfaces is extremely small (0.005-0.05um / min). With the increase of time, the copper on the sidewall of the connecting via 11 gradually thickens.

[0079] S16, removing the thickened first conductive film 20 on the first surface of the substrate 10, at this time, the connecting structure 23 in the connecting via 11 and the signal line 21 and the first connecting pad 22 on the second surface are formed.

[0080] In some examples, step S16 can use a chemical mechanical polishing (CMP) method to remove the structure of the excess first conductive thin film 20 on the first surface. Among them, the seed layer located in the connection via hole 11 is the first sub-structure 231 of the connection structure 23, and the long-thick first conductive thin film 20 part is the second sub-structure 232.

[0081] S17, filling the filling structure 40 in the accommodation space 111 defined by the connection structure 23 formed in the connection via hole 11.

[0082] In some examples, the second protective layer 50 covering the signal wire 21 can also be formed while filling the accommodation space 111. Among them, the filling structure 40 and the second protective layer 50 are an integral structure, and the material includes but is not limited to resin material.

[0083] S18, forming a pixel driving circuit (thin film transistor, etc.), a light emitting device and the like structure on the first surface of the substrate 10 after the above steps are completed.

[0084] For forming a pixel driving circuit, a light emitting device can adopt the manner in the prior art, so it will not be described in detail here.

[0085] Second example: Figure 9 A partial schematic view of a display substrate of a second example of the embodiments of the present disclosure; as Figure 9 shown, the display substrate is substantially the same as the first example, and the difference is only that in this example, the second sub-structure 232 of the connection structure 23 is close to the side of the second surface of the substrate 10. That is, the fourth surface of the second sub-structure 232 is flush or substantially flush with the second surface of the substrate 10.

[0086] The preparation method of the display substrate of the second example is substantially the same as that of the first example, and the difference is only that when the connection structure 23 is formed by electroplating process, by controlling the process parameters, the fourth surface of the second sub-structure 232 can be flush or substantially flush with the second surface of the substrate 10. For the remaining steps, they can be the same as the first example, so they will not be repeated here.

[0087] Third example: Figure 10 A partial schematic view of a display substrate of a third example of the embodiments of the present disclosure; as Figure 10 shown, the display substrate is substantially the same as the first example, and the difference is only that in this example, the second sub-structure 232 of the connection structure 23 is located in the middle of the connection via hole 11, that is, the plane where the third surface of the second sub-structure 232 is located and the plane where the first surface of the substrate 10 is located have a certain spacing, and the plane where the fourth surface of the second sub-structure 232 is located and the plane where the second surface of the substrate 10 is located have a certain spacing.

[0088] The preparation method of the display substrate of the third example is substantially the same as that of the first example, and the difference is that when the connection structure 23 is formed by the electroplating process, by controlling the process parameters, a certain spacing can be formed between the plane where the third surface of the second sub-structure 232 is located and the plane where the first surface of the substrate 10 is located, and a certain spacing can be formed between the plane where the fourth surface of the second sub-structure 232 is located and the plane where the second surface of the substrate 10 is located. The remaining steps can be the same as those of the first example, and thus are not repeated here.

[0089] The fourth example: Figure 11 A partial schematic view of a display substrate of the fourth example of the present disclosure is shown in FIG. 4. As shown in FIG. 4, the display substrate of this example is substantially the same as that of the first example, and the difference is that in this example, the second sub-structure 232 of the connection structure 23 comprises a first part 2321 and a second part 2322; the outer contour of the first part 2321 and the outer contour of the second part 2322 are both fitted with the first sub-structure 231, and the first part 2321 and the second part 2322 have a certain spacing therebetween. Further, the surface of the first part 2321 facing away from the second part 2322 is flush with the first surface; the surface of the second part 2322 facing away from the first part 2321 is flush with the second surface. Figure 11 The spacing between the first part 2321 and the second part 2322 of the first sub-structure 231 of the display substrate of the fourth example cannot be filled with the filling structure 40.

[0090] The preparation method of the display substrate of the fourth example is substantially the same as that of the first example, and the difference is that when the connection structure 23 is formed by the electroplating process, by controlling the process parameters, the second sub-structure 232 composed of the first part 2321 and the second part 2322 can be formed. Of course, the first part 2321 and the second part 2322 of the second sub-structure 232 can also be formed by two electroplating processes. Only the parameters of the electroplating process need to be controlled. The remaining steps can be the same as those of the first example, and thus are not repeated here.

[0091] The fifth example:

[0092] A partial schematic view of a display substrate of the fifth example of the present disclosure is shown in FIG. 5. As shown in FIG. 5, the display substrate of this example is substantially the same as that of the first example, and the difference is that in this example, the third surface of the second sub-structure 232 of the connection structure 23 is a folded surface and protrudes towards the fourth surface; and / or, the fourth surface of the second sub-structure 232 is a folded surface and protrudes towards the third surface. Figure 12 Figure 12

[0093] ​​The preparation method of the display substrate of the fifth example is substantially the same as that of the first example, and the only difference is that when the connection structure 23 is formed by the electroplating process, the third surface and the fourth surface of the second sub-structure 232 can be made into a fold surface by controlling the process parameters. The remaining steps can be the same as those of the first example, and thus are not repeated here.

[0094] The sixth example: Figure 13 A partial schematic view of a display substrate of the sixth example of the embodiments of the present disclosure is shown in FIG. 6. As shown in FIG. 6, the display substrate of this example is substantially the same as that of the first example, and the only difference is that in this example, the third surface of the second sub-structure 232 of the connection structure 23 is an arc surface and protrudes towards the fourth surface, and / or the fourth surface of the second sub-structure 232 is an arc surface and protrudes towards the third surface. Figure 13

[0095] The preparation method of the display substrate of the sixth example is substantially the same as that of the first example, and the only difference is that when the connection structure 23 is formed by the electroplating process, the third surface and the fourth surface of the second sub-structure 232 can be made into an arc surface by controlling the process parameters. The remaining steps can be the same as those of the first example, and thus are not repeated here.

[0096] It should be noted that only several exemplary structures of the display substrate are given above, but any modification based on the above is within the protection scope of the embodiments of the present disclosure.

[0097] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.​

Claims

1. A display substrate, comprising: The substrate has a through-hole extending through its thickness direction; The substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction; A pixel driving circuit is disposed on the first surface; Signal traces are disposed on the second surface; A connection structure is disposed within the connection via, and the connection structure electrically connects the signal trace to the pixel driving circuit; wherein, a portion of the connection via is filled by the connection structure; the connection structure defines an accommodating space within the connection via; a filling structure, which is a resin material, is filled in the accommodating space; the connection structure includes a first substructure disposed on the sidewall of the connection via, and a second substructure connected to the first substructure, wherein the outer contour of the second substructure fits against the first substructure; The signal trace is integral with the first substructure, and the signal trace is electrically connected to the pixel driving circuit through the first substructure.

2. The display substrate according to claim 1, wherein, The second substructure includes a third surface and a fourth surface disposed opposite to each other along its thickness direction; the third surface is flush with the first surface, and there is a certain distance between the plane containing the fourth surface and the plane containing the second surface; or, the fourth surface is flush with the second surface, and there is a certain distance between the plane containing the third surface and the plane containing the first surface; or, there is a certain distance between the plane containing the third surface and the plane containing the first surface, and a certain distance between the plane containing the fourth surface and the plane containing the second surface.

3. The display substrate according to claim 1, wherein, The second substructure includes a first part and a second part; the outer contours of the first part and the second part are both fitted to the first substructure, and there is a certain distance between the first part and the second part.

4. The display substrate according to claim 3, wherein, The surface of the first portion that is opposite to the second portion is flush with the first surface; the surface of the second portion that is opposite to the first portion is flush with the second surface.

5. The display substrate according to claim 1, wherein, The second substructure includes a third surface and a fourth surface disposed opposite to each other along its thickness direction; the third surface is an arc surface and protrudes toward the fourth surface; and / or, the fourth surface is an arc surface and protrudes toward the third surface.

6. The display substrate according to claim 1, wherein, The second substructure includes a third surface and a fourth surface disposed opposite to each other along its thickness direction; the third surface is a folded surface and protrudes toward the fourth surface; and / or, the fourth surface is a folded surface and protrudes toward the third surface.

7. The display substrate according to claim 1, wherein, A first protective layer is provided on the sidewall of the connection via, and the first protective layer is located between the sidewall of the connection via and the connection structure.

8. The display substrate according to claim 1, wherein, A first connection pad is also provided on the second surface, and the signal trace is electrically connected to the connection structure through the first connection pad.

9. A method for preparing a display substrate, comprising: A substrate is provided, the substrate having a through-hole extending along its thickness direction; The substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction; A connection structure is formed within a connection via on the substrate. A pixel driving circuit is formed on a first surface of the substrate, and a signal trace is formed on a second surface of the substrate. The connection structure electrically connects the signal trace to the pixel driving circuit. The connection structure does not completely fill the connection via. The connection structure includes a first substructure disposed on the sidewall of the connection via and a second substructure connected to the first substructure. Forming the connection structure includes: A first conductive film is formed on the first surface, the second surface, and the sidewall of the connection via of the substrate as a seed layer, and electroplating and patterning processes are performed sequentially to form the connection structure; wherein, the seed layer located on the sidewall of the connection via is the first substructure, and the structure located in the connection and connected to the first substructure is the second substructure; wherein, signal traces are formed by patterning the first conductive film on the second surface, and the signal traces are electrically connected to the pixel driving circuit through the first substructure; A filling structure, which is made of resin material, is filled within the accommodating space defined in the connection through hole of the connection structure.

10. The method for preparing a display substrate according to claim 9, wherein, The second substructure includes a third surface and a fourth surface disposed opposite to each other along its thickness direction; the third surface is flush with the first surface, and there is a certain distance between the plane containing the fourth surface and the plane containing the second surface; or, the fourth surface is flush with the second surface, and there is a certain distance between the plane containing the third surface and the plane containing the first surface; or, there is a certain distance between the plane containing the third surface and the plane containing the first surface, and a certain distance between the plane containing the fourth surface and the plane containing the second surface.

11. The method for preparing a display substrate according to claim 9, wherein, The second substructure includes a first part and a second part, with a certain distance between the first part and the second part.

12. The method for preparing a display substrate according to claim 11, wherein, The surface of the first portion that is opposite to the second portion is flush with the first surface; the surface of the second portion that is opposite to the first portion is flush with the second surface.

13. The method for preparing a display substrate according to claim 12, wherein, The second substructure includes a third surface and a fourth surface disposed opposite to each other along its thickness direction; the third surface is an arc surface and protrudes toward the fourth surface; and / or, the fourth surface is an arc surface and protrudes toward the third surface.

14. The method for preparing a display substrate according to claim 9, wherein, The second substructure includes a third surface and a fourth surface disposed opposite to each other along its thickness direction; the third surface is a folded surface and protrudes toward the fourth surface; and / or, the fourth surface is a folded surface and protrudes toward the third surface.

15. The method for preparing a display substrate according to claim 9, wherein, Prior to the step of forming the connection via, a first protective layer is formed on at least the sidewall of the connection via.

16. The method for preparing a display substrate according to claim 9, wherein, Also includes: A first connection pad is formed on the second surface, and the signal trace is electrically connected to the connection structure through the first connection pad.

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