Driving backplane and display panel

Abstract

The present application provides a driving backplane and a display panel, wherein the driving backplane is provided with a plurality of oxide semiconductor thin film transistors with different channel widths and different mobilities to reduce the space occupied by the thin film transistors, thereby reducing the frame of the display panel and meeting the market demand for narrow-frame display panels; at the same time, a plurality of oxide semiconductor thin film transistors with different current driving capabilities are also provided to ensure that the corresponding circuit has the actually required functions and improve the display quality of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving backplane and a display panel. Background Art

[0002] In large-scale displays, especially for current-driven display panels represented by active matrix OLED (AMOLED) display panels, achieving mass production requires dual considerations of current driving capability and large-area process uniformity. Currently, thin-film transistors (TFTs) made of oxide semiconductor materials have higher mobility than TFTs made of amorphous silicon or polycrystalline silicon materials. Oxide semiconductor TFTs can operate at higher speeds and have higher current driving capabilities. Therefore, oxide semiconductor TFTs have become an important component in the mass production of large-scale AMOLED display panels.

[0003] On the one hand, different circuits have varying requirements for TFTs, and even within the same circuit, the requirements for individual TFTs vary. Some TFTs function solely as switches, thus requiring less stringent current drive capability. On the other hand, the market demand for narrow-bezel display panels is even stronger.

[0004] Therefore, it is necessary to provide a display panel that meets the requirement of a narrow frame and also has multiple oxide semiconductor TFTs with different current driving capabilities. Summary of the Invention

[0005] In order to solve the above technical problems, the present application provides a driving backplane and a display panel, which has multiple oxide semiconductor TFTs of different sizes and different mobilities. While reducing the frame, it provides multiple oxide semiconductor TFTs with different current driving capabilities to ensure that the corresponding circuit has the actual required functions.

[0006] In a first aspect, the present application provides a driving backplane, comprising:

[0007] substrate;

[0008] A thin film transistor layer is provided on the substrate, and includes at least one first transistor and at least one second transistor; wherein,

[0009] The first transistor includes a first oxide semiconductor channel, the second transistor includes a second oxide semiconductor channel, the width of the first oxide semiconductor channel is smaller than the width of the second oxide semiconductor channel, and the mobility of the first oxide semiconductor channel is smaller than the mobility of the second oxide semiconductor channel.

[0010] In the driving backplane provided in the present application, the width of the first oxide semiconductor channel is less than a preset value, and the width of the second oxide semiconductor channel is greater than or equal to the preset value, and the preset value is between 15 microns and 25 microns.

[0011] In the driving backplane provided in this application, the preset value is 20 microns.

[0012] In the driving backplane provided in the present application, the thin film transistor layer includes a first oxide semiconductor layer, a first insulating layer, a second oxide semiconductor layer and a second insulating layer stacked in sequence; wherein,

[0013] The first oxide semiconductor layer includes the first oxide semiconductor channel, and the second oxide semiconductor layer includes the second oxide semiconductor channel;

[0014] The first insulating layer includes a first insulating portion, and the second insulating layer includes a second insulating portion. The first insulating portion is disposed on a side of the first oxide semiconductor channel away from the substrate, and the second insulating portion is disposed on a side of the second oxide semiconductor channel away from the substrate.

[0015] In the driving backplane provided in the present application, the second insulating layer further includes a third insulating portion, and the third insulating portion is provided on a side of the first insulating portion away from the substrate.

[0016] In the driving backplane provided in the present application, the first insulating layer further includes a fourth insulating portion, and the fourth insulating portion is provided on a side of the second oxide semiconductor channel close to the substrate.

[0017] In the driving backplane provided in the present application, the hydrogen content of the first insulating layer is greater than the hydrogen content of the second insulating layer.

[0018] In the driving backplane provided in the present application, the second oxide semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer;

[0019] The first sub-semiconductor layer is arranged on a side of the second insulating portion close to the substrate, and the second sub-semiconductor layer is arranged on a side of the first sub-semiconductor layer close to the substrate, and the mobility of at least one of the first sub-semiconductor layer and the second sub-semiconductor layer is greater than the mobility of the first oxide semiconductor layer.

[0020] In the driving backplane provided in the present application, the first sub-semiconductor layer covers the second sub-semiconductor layer.

[0021] In the driving backplane provided in the present application, the second sub-semiconductor layer includes a first portion and a second portion arranged around the first portion; wherein,

[0022] The orthographic projection of the first portion on the substrate coincides with the orthographic projection of the first sub-semiconductor layer on the substrate, and the second portion is provided with a source-drain contact region or the first sub-semiconductor layer is provided with the source-drain contact region.

[0023] In a second aspect, the present application further provides a display panel, which includes any one of the above driving backplanes.

[0024] The driving backplane and display panel provided in the present application, by setting up multiple oxide semiconductor TFTs with different channel widths and different mobilities, reduce the space occupied by TFTs to achieve a reduction in the border, thereby meeting the market demand for narrow borders; at the same time, multiple oxide semiconductor TFTs with different current driving capabilities are also provided to ensure that the corresponding circuits have the actual required functions, thereby improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the first structure of the driver backplane provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of the second structure of the driver backplane provided in an embodiment of the present application;

[0027] Figure 3 A third structural diagram of the driver backplane provided in an embodiment of the present application;

[0028] Figure 4 A fourth structural schematic diagram of the driver backplane provided in an embodiment of the present application;

[0029] Figure 5 A fifth structural diagram of the driver backplane provided in an embodiment of the present application;

[0030] Figure 6 A sixth structural diagram of the driver backplane provided in an embodiment of the present application;

[0031] Figure 7 A seventh structural diagram of the driver backplane provided in an embodiment of the present application;

[0032] Figures 8A to 8J express Figure 3 A cross-sectional view showing the process of preparing the driving backplane provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0034] In addition, the terms "first," "second," and so on in the specification and claims of this application are used to distinguish different objects, not to describe a specific order. The terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. Because the source and drain of the transistors used in this application are symmetrical, their source and drain are interchangeable. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the output end as the drain.

[0035] See also Figure 1 , Figure 1 This is a schematic diagram of the first structure of the driver backplane provided in the embodiment of the present application. Figure 1 As shown, the driving backplane 100 provided in this embodiment includes a substrate 10 and a thin film transistor layer 30 .

[0036] The substrate 10 is a transparent and insulating substrate, such as a glass substrate, a silicon substrate, a plastic substrate with good heat resistance, etc.

[0037] The thin film transistor layer 30 is provided on the substrate 10 and includes a plurality of thin film transistors (hereinafter referred to as TFTs) and signal lines. The plurality of TFTs include at least oxide semiconductor TFTs and may also include one or both of low-temperature polysilicon TFTs and amorphous silicon TFTs. The plurality of TFTs include at least top-gate TFTs and may also include bottom-gate TFTs.

[0038] The thin film transistor layer 30 includes at least one first transistor 301 and at least one second transistor 302 .

[0039] The first transistor 301 and the second transistor 302 are oxide semiconductor TFTs. Compared to amorphous silicon TFTs or low-temperature polysilicon TFTs, oxide semiconductor TFTs can operate at a higher speed and have a higher current driving capability.

[0040] The first transistor 301 and the second transistor 302 are top-gate TFTs. Compared to bottom-gate TFTs, top-gate TFTs have better current drive characteristics. If bottom-gate TFTs are used in current-driven display panels, such as AMOLED display panels, they generate large parasitic capacitance, affecting the display panel's drive characteristics and contradicting the high current drive capability required of AMOLED display panels.

[0041] Specifically, the first transistor 301 includes a first oxide semiconductor channel 311, and the second transistor 302 includes a second oxide semiconductor channel 331. The width of the first oxide semiconductor channel 311 is smaller than the width of the second oxide semiconductor channel 331, and the mobility of the first oxide semiconductor channel 311 is smaller than the mobility of the second oxide semiconductor channel 331.

[0042] The multiple TFTs included in the driver backplane 100 can be divided into two types based on their function: switching TFTs and current-supply TFTs. During operation, the on-current flowing through the switching TFTs is relatively low, so the current driving capability of the switching TFTs is not demanding. However, the on-current flowing through the current-supply TFTs is relatively high, ensuring that the current-supply TFTs can be fully charged within a predetermined time period. Therefore, certain driving capabilities are required for the current-supply TFTs.

[0043] The formula that determines the on-state current of TFT is: I=W / 2LuC(Vgs-Vth) 2 , where I is the on-current of the TFT, W is the channel width of the TFT, L is the channel length of the TFT, u is the carrier mobility of the semiconductor channel of the TFT, C is the insulation layer capacitance per unit area, Vgs is the voltage of the gate of the TFT relative to the source, and Vth is the threshold voltage of the TFT.

[0044] As can be seen, u, W, and L are the main factors affecting the on-current of a TFT. In a TFT, changes in L can significantly affect the switching voltage and stability of the TFT. Furthermore, a too small L value can easily lead to a short circuit between the source and drain metals. Therefore, adjusting the TFT channel length to increase the on-current is not advisable. Therefore, adjusting the TFT channel width and carrier mobility (hereinafter referred to as mobility) is a feasible method to increase the on-current.

[0045] Therefore, in the driving backplane 100 provided in this embodiment, by providing first transistors 301 and second transistors 302 with different channel widths, oxide semiconductor TFTs with different current driving capabilities are provided. Specifically, the channel width of the first transistor 301 is smaller than the channel width of the second transistor 302, that is, the width of the first oxide semiconductor channel 311 is smaller than the width of the second oxide semiconductor channel 331. Compared with the second transistor 302, the current driving capability of the first transistor 301 is weaker, so the first transistor 301 can be used as a switching TFT, and the second transistor 302 as a current supply TFT.

[0046] Furthermore, by providing a first transistor 301 and a second transistor 302 with different mobilities, oxide semiconductor TFTs with different current drive capabilities are provided. Specifically, the mobility of the first oxide semiconductor channel 311 is smaller than the mobility of the second oxide semiconductor channel 331. This configuration is intended to increase the mobility of the first oxide semiconductor channel 311 while reducing its width.

[0047] Due to the reduction in channel width, the size of the TFT can be reduced, which can reduce the space occupied by the TFT in the driver backplane 100. The current-driving TFT is often located in the non-display area, and its size affects the size of the non-display area. Therefore, the mobility of the second oxide semiconductor channel 331 is greater than that of the first oxide semiconductor channel 311, which helps meet the market demand for narrow bezels.

[0048] In some embodiments, the width of the first oxide semiconductor channel 311 is less than a preset value, and the width of the second oxide semiconductor channel 331 is greater than or equal to the preset value, and the preset value is between 15 microns and 25 microns. Thus, when the semiconductor channel width of the TFT is greater than or equal to the preset value, the semiconductor channel of the TFT uses an oxide semiconductor material with high mobility; when the semiconductor channel width of the TFT is less than the preset value, the semiconductor channel of the TFT uses an oxide semiconductor material with relatively low mobility. Specifically, the preset value can be one of 15 microns, 17 microns, 20 microns, 23 microns, and 25 microns.

[0049] In some embodiments, the preset value is 20 microns, that is, when the semiconductor channel width of the TFT is greater than or equal to 20 microns, the semiconductor channel of the TFT adopts an oxide semiconductor material with high mobility; when the semiconductor channel width of the TFT is less than 20 microns, the semiconductor channel of the TFT adopts an oxide semiconductor material with relatively low mobility.

[0050] In this embodiment, the first oxide semiconductor channel 311 may be made of indium gallium zinc oxide (IGZO). Specifically, the main component ratio of the first oxide semiconductor channel 311 may be In:Ga:Zn:O=1:1:1:4. The thickness of the first oxide semiconductor channel 311 is between 100 angstroms and 1000 angstroms.

[0051] In this embodiment, the second oxide semiconductor channel 331 can be made of indium gallium zinc tin oxide (IGZTO) material. To improve the current driving capability of the second transistor 302, a material with a high indium content is used. Specifically, the ratio of indium to other metal elements in the second oxide semiconductor channel 331 is greater than 1:1. The thickness of the second oxide semiconductor channel 331 is between 100 angstroms and 1000 angstroms.

[0052] Please continue to see Figure 1 In some embodiments, the thin film transistor layer 30 includes a first oxide semiconductor layer 31, a first insulating layer 32, a second oxide semiconductor layer 33, a second insulating layer 34, a gate layer 35, an interlayer dielectric layer 36 and a source / drain metal layer 37, which are stacked in sequence.

[0053] The first oxide semiconductor layer 31 includes a first oxide semiconductor channel 311 , and the second oxide semiconductor layer 33 includes a second oxide semiconductor channel 331 .

[0054] The first insulating layer 32 includes a first insulating portion 321 , and the second insulating layer 34 includes a second insulating portion 341 . The first insulating portion 321 is arranged on a side of the first oxide semiconductor channel 311 away from the substrate 10 , and the second insulating portion 341 is arranged on a side of the second oxide semiconductor channel 331 away from the substrate 10 .

[0055] It should be noted that in the embodiment provided herein, the hydrogen content of the first insulating layer 32 is greater than the hydrogen content of the second insulating layer 34. The first insulating portion 321 serves as the gate insulating portion of the first transistor 301, and the second insulating portion 341 serves as the gate insulating portion of the second transistor 302. The hydrogen content of the gate insulating portion can cause changes in the threshold voltage and reliability of the TFT due to hydrogen diffusion.

[0056] In the driving backplane 100 provided in this embodiment, by arranging the second insulating portion 341 with a lower hydrogen content on the side of the second oxide semiconductor channel 331 with a higher mobility away from the substrate 10, the phenomenon of hydrogen atoms in the second insulating portion 341 diffusing into the second oxide semiconductor channel 331 can be effectively reduced, thereby effectively avoiding the negative threshold voltage bias problem of the second transistor 302 due to hydrogen diffusion; by arranging the first insulating portion 321 with a higher hydrogen content on the side of the first oxide semiconductor channel 311 with a lower mobility away from the substrate 10, it is beneficial to the passivation of some additional oxygen defects in the first oxide semiconductor channel 311, and the reliability of the first transistor 301 can be effectively improved.

[0057] The first insulating layer 32 may be made of silicon oxide material with a thickness of 300 angstroms to 1000 angstroms; the second insulating layer 34 may be made of silicon oxide material with a thickness of 500 angstroms to 2000 angstroms.

[0058] The gate layer 35 includes a first gate portion 351 and a second gate portion 352. The first gate portion 351 is disposed on a side of the first insulating portion 321 away from the substrate 10, and the second gate portion 352 is disposed on a side of the second insulating portion 341 away from the substrate 10.

[0059] The gate layer 35 may have a single-layer or double-layer structure. The gate layer 35 may have a single-layer structure, and its material may be copper (Cu) or aluminum (Al), with a thickness between 1000 angstroms and 5000 angstroms. The gate layer 35 may have a double-layer structure, and the first sub-gate layer close to the substrate 10 may be a transition metal material, such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), and alloys of the above metals, with a thickness of 50 angstroms to 500 angstroms; the second sub-gate layer arranged on the side of the first sub-gate layer away from the substrate 10 may be a metal material, such as copper (Cu) or aluminum (Al), with a thickness between 1000 angstroms and 5000 angstroms.

[0060] The interlayer dielectric layer 36 is disposed on the side of the gate layer 35 away from the substrate 10 and covers the first oxide semiconductor layer 31, the first insulating layer 32, the second oxide semiconductor layer 33, the second insulating layer 34, and the gate layer 35. The interlayer dielectric layer 36 can be made of one or a combination of silicon oxide materials, silicon nitride materials, high-k dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.), and organic dielectric materials. The interlayer dielectric layer 36 is provided with first and second source-drain contact holes. The first oxide semiconductor layer 31 is exposed through the first source-drain contact hole, and the second oxide semiconductor layer 33 is exposed through the second source-drain contact hole.

[0061] Among them, the source-drain metal layer 37 is arranged on the side of the interlayer dielectric layer 36 away from the substrate 10, and the source-drain metal layer 37 includes a first source-drain metal portion and a second source-drain metal portion. The first source-drain metal portion is overlapped with the first oxide semiconductor layer 31 through a first source-drain contact hole, and the second source-drain metal portion is overlapped with the second oxide semiconductor layer 33 through a second source-drain contact hole.

[0062] Please continue to see Figure 1 In some embodiments, the driving backplane 100 further includes a buffer layer 20 and a passivation layer 40 .

[0063] The buffer layer 20 is disposed between the substrate 10 and the thin-film transistor layer 30, providing a buffer and protective layer for the thin-film transistor layer 30. The buffer layer 20 can be a single layer or a multilayer structure, and can be made of one or more of silicon nitride, silicon oxide, and silicon nitride oxide. The thickness of the buffer layer 20 ranges from 2000 angstroms to 5000 angstroms.

[0064] The passivation layer 40 is disposed on the side of the thin film transistor layer 30 away from the substrate 10, and provides insulation and protection for the thin film transistor layer 30. The passivation layer 40 can be a silicon oxide thin film with a thickness ranging from 1000 angstroms to 5000 angstroms.

[0065] In some embodiments, see Figure 2 , Figure 2 This is a schematic diagram of the second structure of the driver backplane provided in the embodiment of the present application. Figure 2 As shown, this embodiment differs from the previous embodiment in that the second insulating layer 34 further includes a third insulating portion 342. The third insulating portion 342 is disposed on the side of the first insulating portion 321 away from the substrate 10. In other words, the third insulating portion 342 serves as the gate insulating portion of the first transistor 301 and is located on the side of the first insulating portion 321 away from the substrate 10. Therefore, the first transistor 301 has two gate insulating portions, which are stacked, and the hydrogen content of the first insulating portion 321 is lower than that of the third insulating portion 342.

[0066] In the driving backplane 100 provided in this embodiment, the thickness of the gate insulating portion of the first transistor 301 is the sum of the thicknesses of the first insulating portion 321 and the third insulating portion 342, and the thickness of the gate insulating portion of the second transistor 302 is the thickness of the second insulating portion 341, and the second insulating portion 341 and the third insulating portion 342 are both formed by the second insulating layer 34, that is, the thickness of the second insulating portion 341 is equal to the thickness of the third insulating portion 342.

[0067] Therefore, on the one hand, the gate insulating portion of the first transistor 301 is thicker than the gate insulating portion of the second transistor 302, thereby enabling the first transistor 301 to have a higher gate withstand voltage than the second transistor 302, thereby increasing the threshold voltage of the first transistor 301 and thereby enhancing the stability of the first transistor 301. On the other hand, the gate insulating portion of the second transistor 302 is thinner than the gate insulating portion of the first transistor 301, thereby enabling the second transistor 302 to have a lower gate withstand voltage than the first transistor 301, thereby further improving the current driving capability of the second transistor 302.

[0068] See Figure 3 , Figure 3 This is a schematic diagram of the third structure of the driver backplane provided in the embodiment of the present application. Figure 3 As shown, the difference between this embodiment and the previous embodiment is that the first insulating layer 32 further includes a fourth insulating portion 322 . The fourth insulating portion 322 is disposed on a side of the second oxide semiconductor channel 331 close to the substrate 10 .

[0069] In the driver backplane 100 provided in this embodiment, the fourth insulating portion 322 is disposed on the side of the second oxide semiconductor channel 331 closest to the substrate 10. This fourth insulating portion 322 not only provides a buffer and insulation for the second transistor 302, but also elevates the second oxide semiconductor channel 331. This means that after depositing the first insulating layer 32 entirely, there is no need to remove the portion of the first insulating layer 32 corresponding to the second transistor 302. This eliminates the need for a photomask and photolithography process, thereby reducing manufacturing costs.

[0070] See Figure 4 , Figure 4 This is a fourth structural diagram of the driver backplane provided in the embodiment of the present application. Figure 4 As shown, the difference between this embodiment and the previous embodiment is that the second oxide semiconductor layer 33 includes a first sub-semiconductor layer 3301 and a second sub-semiconductor layer 3302 .

[0071] The first sub-semiconductor layer 3301 is disposed on a side of the second insulating portion 341 close to the substrate 10, and the second sub-semiconductor layer 3302 is disposed on a side of the first sub-semiconductor layer 3301 close to the substrate 10. The mobility of at least one of the first sub-semiconductor layer 3301 and the second sub-semiconductor layer 3302 is greater than the mobility of the first oxide semiconductor layer 31. Thus, the mobility of the second transistor 302 is further adjusted by the double-layer semiconductor structure.

[0072] In some specific embodiments, the mobility of the first sub-semiconductor layer 3301 is greater than the mobility of the first oxide semiconductor layer 31 , and the mobility of the second sub-semiconductor layer 3302 is consistent with the mobility of the first oxide semiconductor layer 31 .

[0073] In this embodiment, the semiconductor layer with relatively high mobility is closer to the second insulating portion 341 , that is, the semiconductor layer with relatively high mobility is closer to the gate insulating layer, so that the second transistor 302 has a more prominent high mobility characteristic.

[0074] In some specific embodiments, the mobility of the second sub-semiconductor layer 3302 is greater than the mobility of the first oxide semiconductor layer 31 , and the mobility of the first sub-semiconductor layer 3301 is consistent with the mobility of the first oxide semiconductor layer 31 .

[0075] In this embodiment, the semiconductor layer with relatively high mobility is farther away from the second insulating portion 341 , that is, the semiconductor layer with relatively high mobility is farther away from the gate insulating layer, so that the second transistor 302 has high mobility characteristics while ensuring stability.

[0076] In some specific embodiments, the mobility of the first sub-semiconductor layer 3301 and the mobility of the second sub-semiconductor layer 3302 may both be greater than the mobility of the first oxide semiconductor layer 31 .

[0077] It's worth noting that achieving a mobility difference between the first semiconductor sub-layer 3301 and the second semiconductor sub-layer 3302 can be achieved by, firstly, adjusting the ratio of In to one or more metal elements, such as Zn, Ga, and Sn. A ratio greater than 1 increases mobility, while a ratio less than 1 decreases mobility. Secondly, using a crystalline semiconductor layer, while maintaining the same semiconductor material composition, can also improve mobility to a certain extent.

[0078] See Figure 5 , Figure 5 This is a fifth structural diagram of the driving backplane provided in the embodiment of the present application. Figure 5 As shown, this embodiment differs from the previous embodiment in that the first sub-semiconductor layer 3301 covers the second sub-semiconductor layer 3302. Consequently, the orthographic projection of the second sub-semiconductor layer 3302 on the substrate 10 completely falls within the orthographic projection of the first sub-semiconductor layer 3301 on the substrate 10. This structural arrangement is intended to protect the second sub-semiconductor layer 3302. In some specific embodiments, the width of the first sub-semiconductor layer 3301 must exceed the width of the second sub-semiconductor layer 3302 by at least 2 microns.

[0079] It is worth mentioning that, in this embodiment, the source-drain contact region only needs to be formed on the side of the first sub-semiconductor layer 3301 away from the substrate.

[0080] See Figure 6 , Figure 6 This is a sixth structural diagram of the driving backplane provided in the embodiment of the present application. Figure 6 As shown, this embodiment differs from the previous embodiment in that the second sub-semiconductor layer 3302 includes a first portion and a second portion disposed around the first portion; the orthographic projection of the first portion on the substrate 10 coincides with the orthographic projection of the first sub-semiconductor layer 3301 on the substrate 10. Furthermore, a source-drain contact region is provided on a side of the second portion away from the substrate 10, such that the source-drain metal layer 37 contacts the second portion of the second sub-semiconductor layer 3302 through the source-drain contact holes.

[0081] Specifically, the mobility of the second sub-semiconductor layer 3302 may be higher than the mobility of the first sub-semiconductor layer 3301 , so that disposing the source-drain contact region on the second portion may be beneficial to improving the source-drain contact characteristics.

[0082] See Figure 7 , Figure 7 This is a seventh structural diagram of the driving backplane provided in the embodiment of the present application. Figure 7 As shown, the difference between this embodiment and the previous embodiment is that a source-drain contact region is provided on the side of the first sub-semiconductor layer 3301 away from the substrate 10, so that the source-drain metal layer 37 contacts the first sub-semiconductor layer 3301 through the source-drain contact hole.

[0083] Specifically, the mobility of the first sub-semiconductor layer 3301 may be higher than the mobility of the second sub-semiconductor layer 3302 , so that disposing the source-drain contact region on the first sub-semiconductor layer 3301 may be beneficial to improving the source-drain contact characteristics.

[0084] In the second aspect, this application also provides a method for manufacturing a driving backplane, see Figures 8A to 8J . Figures 8A to 8J express Figure 3 The cross-sectional view of the process of preparing the driving backplane provided by the embodiment of the present application is shown. Figure 3 The driving backplane structure is shown for exemplary description.

[0085] See Figure 8A In step 1, a substrate 10 is provided, and a buffer layer 20 is deposited on the substrate 10 using a plasma enhanced chemical vapor deposition (PECVD) process.

[0086] See Figure 8BIn step 2, a first oxide semiconductor layer 31 is deposited on a side of the buffer layer 20 away from the substrate 10 , and the first oxide semiconductor layer 31 is patterned to form a first oxide semiconductor channel 311 by etching.

[0087] See Figure 8C In step three, a first insulating layer 32 is deposited on the entire surface of the first oxide semiconductor layer 31 away from the substrate 10 using a PECVD process to cover the first oxide semiconductor channel 311 .

[0088] See Figure 8D In step four, a second oxide semiconductor layer 33 is deposited on a side of the first insulating layer 32 away from the substrate 10, and the second oxide semiconductor layer 33 is patterned to etch and form a second oxide semiconductor channel 331, so that the width of the second oxide semiconductor channel 331 is greater than the width of the first oxide semiconductor channel 311.

[0089] See Figure 8E In step five, a second insulating layer 34 is deposited on the entire surface of the second oxide semiconductor layer 33 away from the substrate 10 using a PECVD process to cover the second oxide semiconductor channel 331 .

[0090] See Figure 8F In step six, a gate layer 35 is deposited on a side of the second insulating layer 34 away from the substrate and patterned. The gate layer 35 is wet-etched to form a first gate portion 351 and a second gate portion 352, so that the first gate portion 351 is arranged on a side of the first insulating layer 32 away from the substrate 10, and the second gate portion 352 is arranged on a side of the second insulating layer 34 away from the substrate 10.

[0091] See Figure 8G In step seven, a top gate self-alignment process is adopted, that is, the patterns of the first gate portion 351 and the second gate portion 352 are used as etching masks, and plasma is used to etch the second insulating layer 34 and the first insulating layer 32 to pattern the second insulating layer 34 and the first insulating layer 32 to form a first insulating portion 321, a second insulating portion 341, a third insulating portion 342 and a fourth insulating portion 322.

[0092] See Figure 8H In step eight, a PECVD process is used to deposit an interlayer dielectric layer 36, and patterning is performed to form a first source-drain contact hole and a second source-drain contact hole, so that the first oxide semiconductor layer 31 is exposed through the first source-drain contact hole, and the second oxide semiconductor layer 33 is exposed through the second source-drain contact hole.

[0093] See Figure 8IIn step nine, a source / drain metal layer 37 is deposited on the side of the interlayer dielectric layer 36 facing away from the substrate 10 and patterned to form a first source / drain metal portion and a second source / drain metal portion. A wet etching process is used to form the source / drain pattern. The first source / drain metal portion is thereby connected to the first oxide semiconductor layer 31 through the first source / drain contact hole, and the second source / drain metal portion is connected to the second oxide semiconductor layer 33 through the second source / drain contact hole.

[0094] See Figure 8J In step 10, a passivation layer 40 is deposited on the side of the interlayer dielectric layer 36 away from the substrate 10 using a PECVD process. Figure 3 The driving backplane shown includes a first transistor 301 and a second transistor 302 of a top-gate structure.

[0095] Thirdly, the present application also provides a display panel comprising any of the above-described drive backplanes. The display panel provided by the present application, by providing multiple oxide semiconductor TFTs with different channel widths and mobilities, reduces the space occupied by the TFTs to achieve a narrow frame, thereby meeting the market demand for narrow frame displays. Furthermore, multiple oxide semiconductor TFTs with different current drive capabilities are provided to ensure that the corresponding circuits have the required functions, thereby improving the display quality of the display panel.

[0096] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A driving backplane, characterized in that: include: substrate; A thin film transistor layer is provided on the substrate, and includes at least one first transistor and at least one second transistor; wherein, The first transistor includes a first oxide semiconductor channel, the second transistor includes a second oxide semiconductor channel, the width of the first oxide semiconductor channel is smaller than the width of the second oxide semiconductor channel, and the mobility of the first oxide semiconductor channel is smaller than the mobility of the second oxide semiconductor channel, the width of the first oxide semiconductor channel is smaller than a preset value, and the width of the second oxide semiconductor channel is greater than or equal to the preset value, and the preset value is between 15 microns and 25 microns.

2. The driving backplane according to claim 1, characterized in that: The preset value is 20 microns.

3. The driving backplane according to claim 1, characterized in that: The thin film transistor layer includes a first oxide semiconductor layer, a first insulating layer, a second oxide semiconductor layer and a second insulating layer stacked in sequence; wherein, The first oxide semiconductor layer includes the first oxide semiconductor channel, and the second oxide semiconductor layer includes the second oxide semiconductor channel; The first insulating layer includes a first insulating portion, and the second insulating layer includes a second insulating portion. The first insulating portion is disposed on a side of the first oxide semiconductor channel away from the substrate, and the second insulating portion is disposed on a side of the second oxide semiconductor channel away from the substrate.

4. The driving backplane according to claim 3, characterized in that: The second insulating layer further includes a third insulating portion, and the third insulating portion is disposed on a side of the first insulating portion away from the substrate.

5. The driving backplane according to claim 3 or 4, characterized in that: The first insulating layer further includes a fourth insulating portion, and the fourth insulating portion is disposed on a side of the second oxide semiconductor channel close to the substrate.

6. The driving backplane according to claim 3, characterized in that: The hydrogen content of the first insulating layer is greater than the hydrogen content of the second insulating layer.

7. The driving backplane according to claim 3, characterized in that: The second oxide semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer; The first sub-semiconductor layer is arranged on a side of the second insulating portion close to the substrate, and the second sub-semiconductor layer is arranged on a side of the first sub-semiconductor layer close to the substrate, and the mobility of at least one of the first sub-semiconductor layer and the second sub-semiconductor layer is greater than the mobility of the first oxide semiconductor layer.

8. The driving backplane according to claim 7, characterized in that: The first sub-semiconductor layer covers the second sub-semiconductor layer.

9. The driving backplane according to claim 7, characterized in that: The second sub-semiconductor layer includes a first portion and a second portion arranged around the first portion; wherein, The orthographic projection of the first portion on the substrate coincides with the orthographic projection of the first sub-semiconductor layer on the substrate, and the second portion is provided with a source-drain contact region or the first sub-semiconductor layer is provided with the source-drain contact region.

10. A display panel, characterized in that: The drive backplane comprises the drive backplane according to any one of claims 1 to 9.

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