Low voltage ferroelectric memory cell sensing

Abstract

This application is directed to low voltage ferroelectric memory cell sensing. As part of an access operation for a memory cell, the gates of two common source common gate structures can be biased to compensate for an associated threshold voltage. A signal extracted corresponding to a charge stored in the memory cell can be passed through a first common source common gate structure to charge a first capacitor. Similarly, a reference signal formed at a dummy digit line can be passed through a second common source common gate structure to charge a second capacitor. By comparing the reference signal formed at the dummy digit line to the signal extracted from a memory cell, the effect of variations in memory cell performance on the sensing window can be reduced. Additionally, based on the biasing of the gates of the common source common gate structures, the difference between the signals compared at the sensing component can be low compared to other sensing schemes.

Description

[0001] Cross-referencing

[0002] This patent application is a national application of International Patent Application No. PCT / US2021 / 012300, filed January 6, 2021, entitled “Low Voltage Ferroelectric Memory Cell Sensing,” filed by Vimercati. It claims priority to U.S. Patent Application No. 16 / 746,626, filed January 17, 2020, also entitled “Low Voltage Ferroelectric Memory Cell Sensing,” both of which are assigned to this assignee and are expressly incorporated herein by reference in their entirety. Technical Field

[0003] The technical field relates to low-voltage ferroelectric memory cell sensing. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. For example, volatile memory devices like DRAM may lose their stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memory but can have non-volatile characteristics because it uses ferroelectric capacitors as storage devices. Summary of the Invention

[0006] A method is described. The method may include, as a portion of an access operation of a ferroelectric memory cell, applying a first gate of a first cascode structure to a first voltage to compensate for a first threshold voltage of the first cascode structure, the first cascode structure being coupled to a digital line associated with the ferroelectric memory cell; applying a second gate of a second cascode structure to a second voltage to compensate for a second threshold voltage of the second cascode structure, the second cascode structure being coupled to a voltage source for providing a reference signal during the access operation; based on applying the first gate of the first cascode structure to the first voltage, transmitting a third voltage associated with the ferroelectric memory cell through the first cascode structure to a first capacitor; based on applying the second gate of the second cascode structure to the second voltage, transmitting a fourth voltage associated with the reference signal through the second cascode structure to a second capacitor; and determining a logic state stored in the ferroelectric memory cell based on the third voltage transmitted to the first capacitor and the fourth voltage transmitted to the second capacitor.

[0007] Describe a device. The device may include a ferroelectric memory cell; a first cascode structure selectively coupled to the ferroelectric memory cell; a first capacitor coupled to the first cascode structure and operable to receive a first voltage from the ferroelectric memory cell through the first cascode structure; a voltage source operable to provide a reference signal; a second cascode structure selectively coupled to the voltage source; a second capacitor coupled to the second cascode structure and operable to receive a second voltage from the voltage source through the second cascode structure; and a sensing component coupled to the first capacitor and the second capacitor and operable to determine a logic state stored in the ferroelectric memory cell based at least in part on the first voltage received by the first capacitor and the second voltage received by the second capacitor.

[0008] Describe a device. The device may include an array of ferroelectric memory cells; and a controller coupled to the memory cell array and operable to cause the device to perform the following operations as part of an access operation of the ferroelectric memory cells in the array: biasing a first gate of a first cascode structure to a first voltage to compensate for a first threshold voltage of the first cascode structure, the first cascode structure being coupled to a digital line associated with the ferroelectric memory cell; biasing a second gate of a second cascode structure to a second voltage to compensate for a second threshold voltage of the second cascode structure, the second cascode structure being coupled to a voltage source for providing a reference signal during the access operation; based on biasing the first gate of the first cascode structure to the first voltage, transmitting a third voltage associated with the ferroelectric memory cell through the first cascode structure to a first capacitor; based on biasing the second gate of the second cascode structure to the second voltage, transmitting a fourth voltage associated with the reference signal through the second cascode structure to a second capacitor; and determining the logic state stored in the ferroelectric memory cell based on the third voltage transmitted to the first capacitor and the fourth voltage transmitted to the second capacitor. Attached Figure Description

[0009] Figure 1 This document describes examples of systems that support low-voltage ferroelectric memory cell sensing, based on the examples disclosed herein.

[0010] Figure 2 This document describes an example of a memory die that supports low-voltage ferroelectric memory cell sensing, based on the examples disclosed herein.

[0011] Figure 3 This document describes an example of a circuit that supports low-voltage ferroelectric memory cell sensing, based on the examples disclosed herein.

[0012] Figure 4 This document describes an example of a timing diagram supporting low-voltage ferroelectric memory cell sensing, based on the examples disclosed herein.

[0013] Figure 5 A block diagram is shown of a memory array supporting low-voltage ferroelectric memory cell sensing according to an example disclosed herein.

[0014] Figures 6 to 8 A flowchart illustrating one or more methods for supporting low-voltage ferroelectric memory cell sensing according to the examples disclosed herein is shown. Detailed Implementation

[0015] Memory devices can use various components to bias the access lines of a memory die to access the memory cells of the memory die. For example, as part of different operations performed on the memory die, one or more cascode structures can be biased to different voltage levels. The cascode structure can share charge or voltage with the access lines of the memory die (e.g., digital lines, word lines, board lines, etc.) to activate the access lines and access information stored in the memory cells coupled to the access lines.

[0016] As part of the access operation, a signal (e.g., voltage) corresponding to the charge stored in the memory cell can be extracted via a first cascode structure. The extracted signal can charge a capacitor (e.g., an amplifying capacitor (AMPCAP)). A sensing component (e.g., a latch) can compare the extracted signal with a reference signal to determine the logic state (e.g., logic 1 or logic 0) stored in the memory cell.

[0017] In some instances, the performance of a memory cell can vary over time based on one or more factors (e.g., temperature, humidity, materials, etc.), which can affect the extracted signal. However, the reference voltage may not change with the performance of the memory cell, and therefore, the reference signal can remain constant. The variation in memory cell performance and the fixed reference voltage can reduce the sensing window used to determine the logic state stored in the memory cell. This reduced sensing window can therefore introduce errors when performing access operations (e.g., read operations, write operations, etc.).

[0018] According to the techniques described herein, the reference signal at the sensing component can be based on the charge stored in a capacitor. The memory device may include a pre-charge voltage source for pre-charging digital lines coupled to memory cells and dummy digital lines coupled to a reference signal source to a pre-charge voltage. As part of the access operation, the gates of two cascode structures can be biased to compensate for associated threshold voltages. The cascode structures can be isolated from the access lines during the biasing operation. After the biasing operation, a signal corresponding to the extracted charge stored in the memory cell can be transmitted via the first cascode structure to charge the first AMPCAP. Similarly, a reference signal based on the dummy digital line can be transmitted via the second cascode structure to charge the second AMPCAP. That is, the extracted signal and the reference signal can be formed based on charge sharing through the respective cascode structures. By comparing the reference signal formed at the dummy digital line with the signal extracted from the memory cell, the effect of variations in memory cell performance on the sensing window can be reduced. Furthermore, based on the biasing of the gates of the cascode structures, the difference between the compared signals at the sensing component can be low compared to other sensing schemes. When using a memory device, the bias voltage can therefore reduce power consumption associated with access operations and / or improve the sensing window of the memory device.

[0019] Initially, in reference Figure 1-2 The features of this disclosure are described in the context of the memory system and the die. (See references...) Figure 3-4 The features of this disclosure are described in the context of the circuits and timing diagrams described herein. These and other features of this disclosure are derived from references to [references provided]. Figure 5-8 The device diagrams and flowcharts for sensing low-voltage ferroelectric memory cells are further illustrated and described with reference to the device diagrams and flowcharts.

[0020] Figure 1 This document describes an example of a system 100 supporting low-voltage ferroelectric memory cell sensing, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0021] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, networked devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0022] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or other fixed or portable electronic device, and other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0023] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various physical package dimensions for host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0024] Memory device 110 may be operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0025] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0026] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0027] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0028] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0029] The memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may contain a single memory array 170. A 3D memory die 160 may contain two or more memory arrays 170, which may be stacked one on top of the other or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in the 3D memory die 160 may be referred to as a stack, hierarchy, layer, or die. The 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two-high stacked memory arrays, three-high stacked memory arrays, four-high stacked memory arrays, five-high stacked memory arrays, six-high stacked memory arrays, seven-high stacked memory arrays, eight-high stacked memory arrays). In some 3D memory dies 160, different stacks may share at least one common access line, such that some stacks may share at least one of word lines, digital lines, and / or board lines.

[0030] In some instances, one or more memory dies 160 may each include a sensing component for retrieving and determining data stored in memory cells of memory array 170, for example, as part of an access operation based on commands from a memory controller (e.g., local memory controller 165, device memory controller 155, external memory controller 120, etc.). The sensing component may be coupled to an access line via a cascode structure. As part of the access operation, the gate of the cascode structure may be biased to compensate for the threshold voltage of the cascode structure. One or more access lines may then be activated, enabling access to one or more memory cells. Activating one or more access lines may include pre-charging digital lines and dummy digital lines. A signal corresponding to the charge stored in the memory cell may be retrieved via a first cascode structure, and a reference signal based on the dummy digital line may be transmitted via a second cascode structure. The retrieved signal and the reference signal may each charge a corresponding capacitor (e.g., AMPCAP), and the sensing component may compare the retrieved signal and the reference signal to determine a logic state (e.g., logic 1 or logic 0) stored in the memory cell. By comparing the reference signal formed at the dummy digital line with the signal retrieved from the memory cell, the effect of memory cell performance variations on the sensing window at the sensing component can be reduced. Furthermore, based on the bias voltage applied to the gate of the cascode structure, the difference between the compared signals at the sensing component can be low compared to other sensing schemes. This bias voltage thus reduces power consumption associated with access operations.

[0031] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0032] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0033] A local memory controller 165 (e.g., local to memory die 160) may be operable to control the operation of memory die 160. In some instances, the local memory controller 165 may be used to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0034] External memory controller 120 can be used to enable the transfer of one or more of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0035] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0036] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0037] Figure 2 This document describes an example of a memory die 200 supporting low-voltage ferroelectric memory cell sensing, based on the examples disclosed herein. The memory die 200 may be a reference. Figure 1 Examples of memory die 160 described herein. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, as described in the reference. Figure 1 The memory array 170 is described.

[0038] Memory cell 205 may store states (e.g., polarization states or dielectric charges) representing programmable states in a capacitor. In a FeRAM architecture, memory cell 205 may include capacitor 240, which comprises ferroelectric material to store charges and / or polarizations representing programmable states. Memory cell 205 may include logic storage components, such as capacitor 240 and switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0039] The memory die 200 may include access lines (e.g., word lines 210, digital lines 215, and board lines 220) arranged in a pattern such as a grid. Access lines may be wires coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, bit lines, or board lines, or the like, are interchangeable without loss of understanding or operation. Memory cells 205 may be located at the intersections of word lines 210, digital lines 215, and / or board lines 220.

[0040] Operations such as reading and writing can be performed on memory cells 205 by activating or selecting access lines such as word line 210, digital line 215, and / or board line 220. A single memory cell 205 can be accessed at its intersection by biasing the word line 210, digital line 215, and board line 220 (e.g., applying a voltage to the word line 210, digital line 215, or board line 220). Activating or selecting a word line 210, digital line 215, or board line 220 may involve applying a voltage to the corresponding line.

[0041] Access to memory cell 205 can be controlled via row decoder 225, column decoder 230, and board driver 235. For example, row decoder 225 receives a row address from local memory controller 265 and activates word line 210 based on the received row address. Column decoder 230 receives a column address from local memory controller 265 and activates digital line 215 based on the received column address. Board driver 235 receives a board address from local memory controller 265 and activates board line 220 based on the received board address.

[0042] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 245. Capacitor 240 can be electrically connected to digital line 215 using switch assembly 245. For example, when switch assembly 245 is deactivated, capacitor 240 can be isolated from digital line 215, and when switch assembly 245 is activated, capacitor 240 can be coupled to digital line 215.

[0043] Word line 210 may be a conductive line for electronic communication with memory cell 205 to perform access operations on memory cell 205. In some architectures, word line 210 may be in electronic communication with the gate of switching component 245 of memory cell 205, and may be operable to control the switching component 245 of memory cell 205. In some architectures, word line 210 may be in electronic communication with the node of capacitor of memory cell 205, and memory cell 205 may not include a switching component.

[0044] Digital line 215 may be a wire connecting memory cell 205 to sensing component 250. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 245 of memory cell 205 may be operable to selectively couple and / or isolate memory cell 205 and digital line 215. In some architectures, memory cell 205 may be in electronic communication (e.g., constant) with digital line 215.

[0045] Board line 220 may be a wire for electronic communication with memory cell 205, used to perform access operations on memory cell 205. Board line 220 may be in electronic communication with a node (e.g., bottom of cell) of capacitor 240. Board line 220 is configured to cooperate with digital line 215 to bias capacitor 240 during access operations of memory cell 205.

[0046] Sensing component 250 can determine the state (e.g., polarization state or charge) stored on capacitor 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. Sensing component 250 may include one or more sensing amplifiers to amplify the signal output from memory cell 205. Sensing component 250 can compare the signal received from memory cell 205 across digital line 215 with reference 255 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 250 (e.g., provided to input / output 260) and may indicate the detected logic state to another component of memory device 110 including memory die 200.

[0047] The local memory controller 265 can control the operation of the memory cell 205 through various components (e.g., row decoder 225, column decoder 230, board driver 235, and sensing component 250). The local memory controller 265 can be a reference. Figure 1 Examples of the described local memory controller 165. In some instances, one or more of the row decoder 225, column decoder 230, board driver 235, and sensing components 250 may be located in the same location as the local memory controller 265. The local memory controller 265 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of one or more operations. The local memory controller 265 may generate row signals and column address signals to activate target word line 210, target digital line 215, and target board line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the magnitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0048] The local memory controller 265 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 265 in response to various access commands (e.g., from the host device 105). The local memory controller 265 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0049] Local memory controller 265 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of memory die 200. During a read operation, a logical state stored on the memory cells 205 of memory die 200 can be determined. Local memory controller 265 can identify a target memory cell 205 on which a read operation will be performed. Local memory controller 265 can identify a target word line 210, a target digital line 215, and a target board line 220 coupled to the target memory cell 205. Local memory controller 265 can activate the target word line 210, the target digital line 215, and the target board line 220 (e.g., by applying a voltage to the word line 210, the digital line 215, or the board line 220) to access the target memory cell 205. The target memory cell 205 can transmit a signal to sensing component 250 in response to applying a bias voltage to the access line. Sensing component 250 can amplify the signal. The local memory controller 265 can activate the sensing component 250 (e.g., a latching sensing component) and then compare the signal received from the memory cell 205 with a reference 255. Based on the comparison, the sensing component 250 can determine the logic state stored in the memory cell 205.

[0050] In some instances, sensing component 250 may be coupled to access lines (e.g., word line 210, digital line 215, board line 220, etc.) via a cascode structure. As part of the access operation, the gate of the cascode structure may be biased to compensate for the threshold voltage of the cascode structure. One or more access lines may then be activated, for example, by precharging digital line 215 and a dummy digital line (not shown) associated with a reference signal using a precharge voltage source. A signal corresponding to the charge stored in memory cell 205 may be extracted via a first cascode structure, and a reference signal based on the dummy digital line may be transmitted via a second cascode structure. The extracted signal and the reference signal may each charge a corresponding capacitor (e.g., AMPCAP), and sensing component 250 may compare the signal extracted from the memory cell with the signal extracted from the reference signal source to determine the logic state (e.g., logic 1 or logic 0) stored in memory cell 205. By comparing the reference signal formed at the dummy digital line with the signal extracted from the memory cell, the effect of changes in memory cell performance on the sensing window at the sensing component may be reduced. Furthermore, by applying a bias voltage to the gate of the cascode structure, the difference between the signals compared at the sensing element can be low compared to other sensing schemes. This bias voltage can therefore reduce power consumption associated with access operations.

[0051] Figure 3This document describes an example of a circuit 300 supporting low-voltage ferroelectric memory cell sensing, based on the examples disclosed herein. In some examples, circuit 300 may implement aspects of system 100 or memory die 200. For example, circuit 300 may include memory cell 305, word line 310, digital line 315, board line 320, and sensing component 350, which may be referenced. Figure 1 and 2 Examples of the corresponding components described. Circuit 300 may also include selection component 325, cascode structure 330, switches 331 to 336, gate capacitor 340, precharge voltage source 345, reference voltage source 355, ground voltage source 360, reference capacitor 365, bias voltage source 370, AMPCAP 375, and dummy digital line 316.

[0052] In some memory systems, a static reference signal can be compared with a signal retrieved from a memory cell. The signal retrieved from the memory cell can vary over time, which can narrow the sensing window used for access operations and introduce errors into the data. Alternatively, the static nature of the reference signal and the dynamic nature of the signal retrieved from the memory cell can introduce timing constraints into the access operation. For example, if the sensing component is activated too early or too late, the sensing window can be smaller than its original size.

[0053] The memory device can be configured to form a reference signal using techniques similar to those used to form signals from memory cell 305. For example, circuit 300 may include capacitor 375-b, a cascode structure 330-b, dummy digital lines 316, and one or more switches (e.g., switches 331-b, 332-b, 333-b, 334-b, 335, and 336-b), configured to form a signal based on a reference signal that may be static. By using techniques similar to those used to form signals from memory cells to form the signal associated with the reference signal, the trajectory (in time) of the signal formed from the reference signal can be similar to that of the signal formed from the memory cell, and timing constraints associated with access operations can be reduced. Alternatively or additionally, by using techniques similar to those used to form signals from memory cells to form the signal associated with the reference signal, the signal formed from the reference signal can exhibit changes similar to those formed from memory cell 305 as the memory device wears down during use (e.g., as the memory device ages). In some instances, the dummy digital line 316 may be an example of a digital line in a memory device that is not used to represent data stored by the host device. In such cases, this type of digital line can be used to form a signal from a static reference signal.

[0054] A cascode structure (e.g., cascode structure 330-a or cascode structure 330-b) can be an example of a two-stage amplifier comprising two transistors. For example, a common-emitter stage (e.g., a first transistor) may be fed into a common-base stage (e.g., a second transistor). Compared to a single-stage amplifier, a cascode structure can have higher input-output isolation, higher input impedance, higher output impedance, higher bandwidth, or a combination thereof.

[0055] Prior to an access operation (e.g., during an idle period of circuit 300), switch 336 (e.g., the transistor associated with switch 336 may be conductive) may be activated, and switch 335 may be activated to couple reference voltage source 355 to reference capacitor 365. In some instances, reference voltage source 355 may provide a reference voltage VSAEF (e.g., 2.2 volts (V)), and reference capacitor 365 may be referred to as reference capacitor CREF (e.g., a capacitance having 3.8 nanofarads (fF)).

[0056] Prior to the access operation, switches 331 and 332 can be activated to couple bias voltage sources 370 to the gate capacitors 340 of the cascode structures 330-a and 330-b. In some instances, each bias voltage source 370 can provide a voltage of 2.8V. In some instances, each gate capacitor 340 may be referred to as a voltage threshold capacitor VthCap associated with the corresponding cascode structure 330. Based on the bias voltage source 370-a and the gate capacitor 340-a, charge can be stored in the gate capacitor 340-a to bias the gate of the cascode structure 330-a to a voltage that compensates for the threshold voltage of the cascode structure 330-a. Based on a similar bias operation, the gate of the cascode structure 330-b can be biased to a voltage that compensates for the threshold voltage of the cascode structure 330-b. During biased operation, switches 333 and 334 can be deactivated (e.g., the transistors associated with switches 333 and 334 may not conduct electricity) to isolate components of circuit 300.

[0057] In some instances, access operations can be initiated based on commands (e.g., from a memory controller or host device). Switch 334 can be activated to couple digital line 315 (e.g., via selection component 325) and dummy digital line 316 to a precharge voltage source 345. The precharge voltage source 345 can precharge digital line 315 (e.g., by storing charge in the parasitic capacitance of digital line 315) and dummy digital line 316 to a precharge voltage (e.g., 1.5V). In some instances, dummy digital line 316 may include a capacitor DL#cap, which may be referred to as an analog capacitor.

[0058] After precharging digital line 315 and dummy digital line 316, the bias voltage source 370 can be isolated from other components of circuit 300 by deactivating switch 331. Switch 333 can be activated to initiate sampling of the corresponding threshold voltage for each cascode structure 330. That is, the gate of cascode structure 330-a can be coupled to digital line 315 through cascode structure 330-a and switch 333-a, and the gate of cascode structure 330-b can be coupled to dummy digital line 316 through cascode structure 330-b and switch 333-b. Based on this coupling, the voltage on the gate of the corresponding cascode structure 330 can be set to compensate for the individual threshold voltage on each cascode structure 330. After sampling, switch 334 can be deactivated to isolate digital line 315 and dummy digital line 316 from precharge voltage source 345.

[0059] After isolating digital line 315 and dummy digital line 316 from precharge voltage source 345, charge sharing can be initiated to extract charge stored in memory cell 305. Switches 332 and 333 can be deactivated to isolate digital line 315 and dummy digital line 316 from cascode structure 330 and gate capacitor 340. Switch 335 can be activated to couple reference capacitor 365 to ground voltage source 360. In some instances, the ground voltage source may be a dummy ground or have a voltage of zero (0)V. Word line 310 can be activated to couple digital line 315 to memory cell 305. Charge sharing between digital line 315 and memory cell 305 allows signals associated with logic states stored in memory cell 305 to be transmitted to digital line 315. Additionally, switch 331 can be activated during charge sharing.

[0060] After charge sharing, a signal associated with the logic state can be extracted for sensing at sensing component 350. Activation switch 331 can be deactivated to isolate components of circuit 300 from bias voltage source 370. Switch 333 can be activated to couple digital line 315 to cascode structure 330-a and dummy digital line 316 to cascode structure 330-b. The extracted signal can be transmitted from digital line 315 through cascode structure 330-a and charge AMPCAP 375-a. Similarly, a reference signal can be transmitted from dummy digital line 316 through cascode structure 330-b and charge AMPCAP 375-b.

[0061] After signal extraction, activation switch 336 can be deactivated to isolate AMPCAP 375 and sensing component 350 from other components of circuit 300. Sensing component 350 can then compare the extracted signal with a reference signal (e.g., based on the charge stored in AMPCAP 375) to determine the logic state (e.g., logic 1 or logic 0) stored in memory cell 305. By comparing the reference signal formed at dummy digital line 316 with the signal extracted from memory cell 305, the effect of variations in memory cell performance on the sensing window at sensing component 350 can be reduced. Furthermore, based on the bias voltage applied to the gate of the cascode structure 330, the difference between the compared signals at sensing component 350 can be low compared to other sensing schemes. This bias voltage can therefore reduce power consumption associated with access operations.

[0062] Figure 4 This document illustrates an example of a timing diagram 400 supporting low-voltage ferroelectric memory cell sensing, based on the examples disclosed herein. Timing diagram 400 illustrates the sensing operations associated with the memory cell. Timing diagram 400 shows a reference... Figure 3 The circuit 300 is described with its components and nodes associated with various voltage levels (e.g., voltage signals that vary over time) to illustrate the performance of the sensing operation. Additionally, Table 401 illustrates the component states at times t0 to t6 identified in the timing diagram 400. For example, Table 401 may illustrate the corresponding states of word line 410 and switches 431 to 436, which can be used as a reference. Figure 3 An example of the corresponding device described. Figure 4 The time and voltage scales used are for illustrative purposes and may not depict specific values ​​in some cases.

[0063] Time t0 may correspond to an idle period, such as an idle period before or between access operations. Switch 436 (which may be indicated as "On" in Table 401) may be activated, and switch 435 may be activated to couple the reference voltage VSARF (e.g., 2.2V) to the reference capacitor. Switches 431 and 432 may be activated to bias the gate of each cascode structure to the corresponding bias voltage that compensates for the voltage threshold of the cascode structure. Switches 433 and 434 and word line 410 (which may be indicated as "Off" in Table 401) may be deactivated to isolate components.

[0064] In some instances, an access operation may be initiated based on a command (e.g., from a memory controller or host device). At time tl, as part of the access operation and / or based on the received command, the access line may be precharged. Switch 434 may be activated to couple digital line 315 (e.g., by selecting a component) and dummy digital line 316 to a precharge voltage source 345. The precharge voltage source may precharge the digital line (e.g., by storing charge in the parasitic capacitance of the digital line) and the dummy digital line to a precharge voltage (e.g., 1.5V). Based on precharging the digital line, digital line signal 416 may be increased from 0V (e.g., ground voltage, dummy ground, or relative ground) to voltage Vread. Digital line signal 416 may refer to a signal on digital line 315 or dummy digital line 316.

[0065] After pre-charging, the corresponding threshold voltage for each cascode structure can be sampled starting at time t2. In some instances, time t2 may occur 15 nanoseconds (ns) after time t1. Switch 431 can be deactivated to isolate the bias voltage source 370 from the cascode structure 330. Signals at the sensing components (e.g., the first AMPCAP signal 406 and the second AMPCAP signal 426) can each be at voltage VHSA. Switch 433 can be activated such that the first gate of the first cascode structure 330-a is coupled to the digital line 315 through the first cascode structure, and the second gate of the second cascode structure 330-b is coupled to the dummy digital line 316 through the second cascode structure. The voltages of the digital line 315 and the dummy digital line 316 can be balanced with the voltage through the cascode structure 330 based on this coupling. As the sampling ends at time t3, the activation switch 434 can be deactivated to isolate digital line 315 and dummy digital line 316 from the pre-charge voltage source 345. In some instances, time t3 may occur 5 ns after time t2.

[0066] After isolating the digital line and dummy digital line from the pre-charge voltage source, charge sharing can be initiated at time t4 to extract charge stored in the memory cell. In some instances, time t4 may occur 1 ns or less after time t3. Switches 432 and 433 can be deactivated to isolate digital line 315 and dummy digital line 316 from the cascode structure 330. Switch 435 can be activated to couple the reference capacitor to a ground voltage source. In some instances, the ground voltage source may be a dummy ground or have a voltage of zero (0) V. Word line 410 can be activated to couple the digital line to memory cell 305. Activating word line 410 may involve applying a voltage to increase word line signal 411 to the pumped common collector voltage VCCP. Charge sharing between digital line 315 and memory cell 305 allows signals associated with logic states stored in memory cell 305 to be transmitted to digital line 315. The decrease in digital line signal 416 after time t4 reflects charge sharing between memory cell 305 and digital line 315. Figure 400 illustrates two separate digital line signals after t4. One of the digital line signals (e.g., digital line signal 416-a) occurs when logic '1' is stored on memory cell 305. The other digital line signal (e.g., digital line signal 416-b) occurs when logic '0' is stored on memory cell 305. Similarly, signal splitting for the first AMPCAP signal 406 is also illustrated. Additionally, switch 431 can be activated during charge sharing. Board line voltage 421 can be kept low (e.g., at or near 0V) during charge sharing, which reduces power consumption associated with access operations.

[0067] Following charge sharing, at time t5, a signal associated with the logic state can be extracted for sensing at sensing component 350. In some instances, time t5 may occur 15 ns after time t4. Switch 431 can be deactivated to isolate the component from the bias voltage source 370. Switch 433 can be activated to couple digital line 315 to the first cascode structure 330-a and to couple dummy digital line 316 to the second cascode structure 330-b. The extracted signal can be transmitted between digital lines 315 through the first cascode structure 330-a and the first AMPCAP 375-a, which may cause the first AMPCAP signal 406 to decrease. Figure 400 illustrates two separate first AMPCAP signals 406 after t5. One of the first AMPCAP signals (e.g., first AMPCAP signal 406-a) occurs when logic '1' is stored in memory cell 305. Another of the first AMPCAP signals (e.g., the first AMPCAP signal 406-b) occurs when logic '0' is stored on memory cell 305. Similarly, a reference signal can be transmitted between dummy digital lines 316 via the second cascode structure 330-b and the second AMPCAP 375-b, which can cause the second AMPCAP signal 426 to decrease. Between time t5 and time t6, the formation trajectories of the first AMPCAP signal 406 and the second AMPCAP signal 426 are consistent. In this case, the sensing window used to read data in this type of circuit and operation can be more robust and less susceptible to timing effects when the sensing component 350 is activated or started. Alternatively or additionally, by using the dummy digital lines 316, the cascode structure 330-b and AMPCAP 375-b, and other components, the variation differences between the signal from the memory cell and the signal from the reference signal that may occur as the memory device ages can be reduced in order to form the second AMPCAP signal 426 based on the static reference signal. In such cases, the memory device may have circuitry that generates a differential operation, where changes (attributed to memory device aging) can affect both the signal from the memory cell and the signal from the reference signal in a similar manner.

[0068] After the signal is extracted, at time t6, the activation switch 436 can be deactivated to isolate the AMPCAP 375 and sensing component 350 from other components (e.g., cascode structures, digital lines, etc.). Sensing component 350 can then compare the first AMPCAP signal 406 (e.g., based on the extracted signal) with the second AMPCAP signal 426 (e.g., based on a reference signal) to determine the logic state (e.g., logic 1 or logic 0) stored in memory cell 305. For example, if the first AMPCAP signal 406 is less than the second AMPCAP signal 426, then the sensing component can determine that the memory cell stores a first logic state (e.g., logic 0 or logic 1). On the other hand, if the first AMPCAP signal 406 is greater than the second AMPCAP signal 426, then the sensing component can determine that the memory cell stores a second logic state different from the first logic state (e.g., logic 1 or logic 0).

[0069] By comparing the signal based on the reference signal formed at the dummy digital line 316 with the signal extracted from the memory cell 305, the effect of variations in the performance of the memory cell 305 on the sensing window at the sensing component 350 can be reduced. Furthermore, based on the bias applied to the gate of the cascode structure, the difference between the first AMPCAP signal 406 and the second AMPCAP signal 426 can be lower than the signal at the sensing component in other sensing schemes. This bias can therefore reduce power consumption associated with access operations.

[0070] Figure 5 A block diagram 500 illustrates a memory array 505 supporting low-voltage ferroelectric memory cell sensing according to an example disclosed herein. The memory array 505 may be used as a reference. Figures 1 to 4 Examples of aspects of the described memory array. Memory array 505 may include a first cascode bias manager 510, a second cascode bias manager 515, a memory cell signal manager 520, a reference signal manager 525, a sensing manager 530, a precharge manager 535, a first cascode threshold manager 540, and a second cascode threshold manager 545. Each of these electronic modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0071] As part of the access operation of the ferroelectric memory cell, the first cascode structure bias manager 510 can bias the first gate of the first cascode structure to a first voltage to compensate for the first threshold voltage of the first cascode structure, which is coupled to the digital line associated with the ferroelectric memory cell.

[0072] The second cascode bias manager 515 can bias the second gate of the second cascode structure to a second voltage to compensate for the second threshold voltage of the second cascode structure, the second cascode structure being coupled to a voltage source for providing a reference signal during access operations.

[0073] The memory cell signal manager 520 can transfer a third voltage associated with the ferroelectric memory cell to a first capacitor through the first cascode structure by biasing the first gate of the first cascode structure to a first voltage. In some instances, the memory cell signal manager 520 can select a word line such that the ferroelectric memory cell becomes coupled to a digital line. In some instances, the memory cell signal manager 520 can initiate charge sharing between the ferroelectric memory cell and the first capacitor based on the selected word line, wherein the transfer of the third voltage to the first capacitor is based on charge sharing.

[0074] In some instances, the memory cell signal manager 520 may isolate the second cascode structure from the voltage source using transistors based on the select word line. In some instances, the memory cell signal manager 520 may isolate the first cascode structure from the digital line using transistors before the select word line. In some instances, the memory cell signal manager 520 may couple the first cascode structure to the digital line using transistors after the select word line and based on initiating charge sharing.

[0075] The reference signal manager 525 can transmit a fourth voltage associated with the reference signal to the second capacitor through the second cascode structure by biasing the second gate of the second cascode structure to a second voltage.

[0076] The sensing manager 530 can determine the logic state stored in the ferroelectric memory cell based on a third voltage delivered to the first capacitor and a fourth voltage delivered to the second capacitor. In some instances, the sensing manager 530 can use a first transistor to isolate the first capacitor from a first cascode structure. In some instances, the sensing manager 530 can use a second transistor to isolate the second capacitor from a second cascode structure. In some instances, the sensing manager 530 can activate a sensing component after isolating the first and second capacitors, the sensing component being configured to sense the logic state stored in the ferroelectric memory cell. In some instances, the sensing manager 530 can use the sensing component to compare the third voltage delivered to the first capacitor and the fourth voltage delivered to the second capacitor. In some cases, the sensing component may include a latch.

[0077] As part of the access operation, the precharge manager 535 can precharge the digital lines and dummy digital lines associated with a reference signal to a precharge voltage, wherein biasing the first gate of the first cascode structure and the second gate of the second cascode structure is based on precharging the digital lines and dummy digital lines. In some instances, the precharge manager 535 can activate a set of transistors to couple a precharge voltage source to the digital lines and dummy digital lines. In some instances, the precharge manager 535 can use transistors to isolate the first gate of the first cascode structure from the digital lines during at least a portion of the precharge operation. In some instances, the precharge manager 535 can use one or more transistors to couple the first gate of the first cascode structure to a second voltage source to bias the first gate, based on isolating the first gate from the digital lines using transistors. In some cases, the dummy digital lines may include analog capacitors.

[0078] The first cascode threshold manager 540 can store a first charge associated with a first voltage threshold in a first gate capacitor coupled to the first gate of the first cascode structure, wherein compensation of the first voltage threshold is based on storing the first charge.

[0079] The second cascode threshold manager 545 can store a second charge associated with a second voltage threshold in a second gate capacitor coupled to the second gate of the second cascode structure, wherein compensation of the second voltage threshold is based on storing the second charge.

[0080] Figure 6 A flowchart illustrating one or more methods 600 for supporting low-voltage ferroelectric memory cell sensing according to examples disclosed herein is shown. Operation of method 600 may be implemented by a memory array or its components as described herein. For example, operation of method 600 may be performed by reference to... Figure 5 The described memory array performs the functions described. In some instances, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the described functions. Alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0081] At 605, as part of an access operation of a ferroelectric memory cell, the memory array can bias the first gate of the first cascode structure to a first voltage to compensate for a first threshold voltage of the first cascode structure, which is coupled to a digital line associated with the ferroelectric memory cell. The operation at 605 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The first common-source cascode structure described herein, along with the bias manager, performs the operation of 605.

[0082] At 610, the memory array can bias the second gate of the second cascode structure to a second voltage to compensate for the second threshold voltage of the second cascode structure, which is coupled to a voltage source for providing a reference signal during access operations. Operation of 610 can be performed according to the method described herein. In some instances, a reference voltage can be used... Figure 5 The second common-source cascode structure described herein is used to perform the operation of 610 by a bias manager.

[0083] At 615, the memory array can transfer a third voltage associated with the ferroelectric memory cell through the first cascode structure to the first capacitor based on biasing the first gate of the first cascode structure to a first voltage. Operation at 615 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The described memory cell signal manager performs the operation of 615.

[0084] At 620, the memory array can transfer a fourth voltage associated with a reference signal through the second cascode structure to the second capacitor based on biasing the second gate of the second cascode structure to a second voltage. Operation at 620 can be performed according to the method described herein. In some instances, the reference voltage can be... Figure 5 The described aspect of the reference signal manager performing the operation of 620.

[0085] At 625, the memory array can determine the logic state stored in the ferroelectric memory cell based on the third voltage applied to the first capacitor and the fourth voltage applied to the second capacitor. The operation of 625 can be performed according to the method described herein. In some instances, it can be determined by reference... Figure 5 The described sensor manager performs the operations of 625.

[0086] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features (e.g., a controller, processor, etc., operable to cause the device to perform one or more methods), means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: as part of an access operation of a ferroelectric memory cell, biasing a first gate of a first cascode structure to a first voltage to compensate for a first threshold voltage of the first cascode structure, the first cascode structure being coupled to a digital line associated with the ferroelectric memory cell; biasing a second gate of a second cascode structure to a second voltage to compensate for a first threshold voltage of the second cascode structure. Two threshold voltages, the second cascode structure coupled to a voltage source for providing a reference signal during access operations; a third voltage associated with a ferroelectric memory cell transmitted through the first cascode structure to a first capacitor based on biasing the first gate of the first cascode structure to a first voltage; a fourth voltage associated with a reference signal transmitted through the second cascode structure to a second capacitor based on biasing the second gate of the second cascode structure to a second voltage; and determining the logic state stored in the ferroelectric memory cell based on the third voltage transmitted to the first capacitor and the fourth voltage transmitted to the second capacitor.

[0087] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: as part of the access operation, pre-charging the digital lines and dummy digital lines associated with the reference signal to a pre-charge voltage, wherein biasing the first gate of the first cascode structure and biasing the second gate of the second cascode structure may be based on pre-charging the digital lines and the dummy digital lines. In some examples of the method 600 and apparatus described herein, pre-charging the digital lines and the dummy digital lines may additionally include operations, features, means, or instructions for: activating a transistor set to couple a pre-charge voltage source to the digital lines and the dummy digital lines.

[0088] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: isolating the first gate of the first cascode structure from the digital line using a transistor during at least a portion of a precharge operation; and, based on isolating the first gate from the digital line using the transistor, coupling the first gate of the first cascode structure to a second voltage source using one or more transistors to bias the first gate. In some examples of the method 600 and apparatus described herein, the dummy digital line includes a third capacitor.

[0089] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: isolating the first capacitor from the first cascode structure using a first transistor; isolating the second capacitor from the second cascode structure using a second transistor; and activating a sensing component after isolating the first capacitor and the second capacitor, the sensing component being configured to sense the logic state stored in the ferroelectric memory cell, wherein determining the logic state may be based on activating the sensing component. Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: comparing the third voltage delivered to the first capacitor and the fourth voltage delivered to the second capacitor using the sensing component, wherein determining the logic state may be based on comparing the third voltage and the fourth voltage. In some examples of the method 600 and apparatus described herein, the sensing component includes a latch.

[0090] Some examples of the methods 600 and apparatus described herein may additionally include operations, features, means, or instructions for: storing a first charge associated with a first threshold voltage in a first gate capacitor coupled to the first gate of the first cascode structure, based on biasing the first gate to the first voltage, wherein compensating the first threshold voltage may be based on storing the first charge; and storing a second charge associated with the second threshold voltage in a second gate capacitor coupled to the second gate of the second cascode structure, based on biasing the second gate to the second voltage, wherein compensating the second threshold voltage may be based on storing the second charge. Some examples of the methods 600 and apparatus described herein may additionally include operations, features, means, or instructions for: biasing a word line to couple the ferroelectric memory cell to the digital line; and initiating charge sharing between the ferroelectric memory cell and the first capacitor based on biasing the word line, wherein transferring the third voltage to the first capacitor may be based on initiating the charge sharing.

[0091] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: isolating the second cascode structure from the voltage source using a transistor based on biasing the word line, wherein initiating the charge sharing may be based on isolating the transistor. Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: isolating the first cascode structure from the digital line using a transistor before biasing the word line; and coupling the first cascode structure to the digital line using the transistor after biasing the word line and based on initiating the charge sharing.

[0092] Figure 7 The diagram illustrates one or more methods 700 for supporting low-voltage ferroelectric memory cell sensing according to examples disclosed herein. Operation of method 700 may be implemented by a memory array or its components as described herein. For example, operation of method 700 may be performed by reference to... Figure 5 The described memory array performs the functions described. In some instances, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the described functions. Alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0093] At 705, as part of an access operation, the memory array can precharge the digital lines and the dummy digital lines associated with the reference signal to a precharge voltage. The operation of 705 can be performed according to the method described herein. In some instances, this can be achieved by a reference... Figure 5 The precharge manager described performs the operation of 705.

[0094] At 710, as part of the access operation of the ferroelectric memory cell, the memory array can bias the first gate of the first cascode structure to a first voltage to compensate for a first threshold voltage of the first cascode structure, the first cascode structure being coupled to a digital line associated with the ferroelectric memory cell, wherein the biasing of the first gate of the first cascode structure is based on pre-charging the digital line and the dummy digital line. The operation of 710 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The first common-source cascode structure described herein is used to perform the operation of 710 by a bias manager.

[0095] At 715, the memory array can bias the second gate of the second cascode structure to a second voltage to compensate for the second threshold voltage of the second cascode structure, which is coupled to a voltage source for providing a reference signal during access operations. The biasing of the second gate of the second cascode structure is based on pre-charging the digital lines and dummy digital lines. Operation of 715 can be performed according to the method described herein. In some instances, a reference signal can be used. Figure 5 The second common-source cascode structure described herein, along with the bias manager, performs the operation of 715.

[0096] At 720, the memory array can transfer a third voltage associated with the ferroelectric memory cell through the first cascode structure to the first capacitor based on biasing the first gate of the first cascode structure to a first voltage. Operation at 720 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The described aspect of the memory cell signal manager performing the operation of 720.

[0097] At 725, the memory array can be biased to a second voltage by applying a second gate to the second cascode structure, and a fourth voltage associated with a reference signal can be transferred to the second capacitor through the second cascode structure. Operation of 725 can be performed according to the method described herein. In some instances, the reference signal can be... Figure 5 The described reference signal manager performs the operation of 725.

[0098] At 730, the memory array can determine the logic state stored in the ferroelectric memory cell based on the third voltage applied to the first capacitor and the fourth voltage applied to the second capacitor. The operation of 730 can be performed according to the method described herein. In some instances, it can be determined by reference... Figure 5 The described aspect of the sensor manager performing the operation of 730.

[0099] Figure 8 A flowchart illustrating one or more methods 800 for supporting low-voltage ferroelectric memory cell sensing according to examples disclosed herein is shown. Operation of method 800 may be implemented by a memory array or its components as described herein. For example, operation of method 800 may be performed as described in reference... Figure 5 The described memory array performs the functions described. In some instances, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the described functions. Alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0100] At 805, as part of the access operation of the ferroelectric memory cell, the memory array can bias the first gate of the first cascode structure to a first voltage to compensate for the first threshold voltage of the first cascode structure, which is coupled to the digital line associated with the ferroelectric memory cell. The operation of 805 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The first common-source cascode structure described herein is used to perform the operation of the 805 with a bias manager.

[0101] At 810, the memory array can bias the second gate of the second cascode structure to a second voltage to compensate for the second threshold voltage of the second cascode structure, which is coupled to a voltage source for providing a reference signal during access operations. Operation of 810 can be performed according to the method described herein. In some instances, a reference voltage can be used... Figure 5 The second common-source cascode structure described herein is used to perform the operation of the 810 by a bias manager.

[0102] At 815, the memory array can transfer a third voltage associated with the ferroelectric memory cell through the first cascode structure to the first capacitor based on biasing the first gate of the first cascode structure to a first voltage. Operation of 815 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The described memory cell signal manager performs the operation of 815.

[0103] At 820, the memory array can be biased to a second voltage by applying a second gate to the second cascode structure, and a fourth voltage associated with a reference signal can be transferred to a second capacitor through the second cascode structure. Operation of 820 can be performed according to the method described herein. In some instances, the reference signal can be used to... Figure 5 The described aspects of the reference signal manager performing the operation of 820.

[0104] At 825, the memory array can use a first transistor to isolate the first capacitor from the first cascode structure. Operation of 825 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The described sensor manager performs the operations of the 825.

[0105] At 830, the memory array can use a second transistor to isolate the second capacitor from the second cascode structure. Operation of 830 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The described aspect of the sensor manager performing the operations of 830.

[0106] At 835, the memory array can activate a sensing component after isolating the first and second capacitors. This sensing component is configured to sense the logic state stored in the ferroelectric memory cells. Operation of 835 can be performed according to the method described herein. In some instances, it can be referenced... Figure 5 The described sensor manager performs aspects of the 835's operations.

[0107] At 840, the memory array can determine the logic state stored in the ferroelectric memory cell based on the third voltage applied to the first capacitor and the fourth voltage applied to the second capacitor. Operation of 840 can be performed according to the method described herein. In some instances, it can be determined by reference... Figure 5 The described aspect of the sensor manager performing the operations of 840.

[0108] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0109] Describe an apparatus. The apparatus may include: a ferroelectric memory cell; a first cascode structure selectively coupled to the ferroelectric memory cell; a first capacitor coupled to the first cascode structure and operable to receive a first voltage from the ferroelectric memory cell through the first cascode structure; a voltage source operable to provide a reference signal; a second cascode structure selectively coupled to the voltage source; a second capacitor coupled to the second cascode structure and operable to receive a second voltage from the voltage source through the second cascode structure; and a sensing component coupled to the first capacitor and the second capacitor and operable to determine a logic state stored in the ferroelectric memory cell based on the first voltage received by the first capacitor and the second voltage received by the second capacitor.

[0110] Some instances of the device may include digital lines that are selectively coupled to the ferroelectric memory cells and the first cascode structure. Some instances of the device may include a precharge voltage source operable to precharge the digital lines and a dummy digital line associated with the reference signal to a precharge voltage; and a transistor set operable to couple the precharge voltage source to the digital lines and the dummy digital lines.

[0111] Some examples of the device may include a transistor that isolates the first gate of the first cascode structure from the digital line during at least a portion of the precharge operation; and one or more transistors operable to couple the first gate of the first cascode structure to a second voltage source to bias the first gate based on the isolation of the first gate from the digital line using the transistor. In some examples, the dummy digital line includes a third capacitor.

[0112] Some examples of the device may include a first transistor operable to isolate the first capacitor from the first cascode structure; and a second transistor operable to isolate the second capacitor from the second cascode structure, wherein the sensing component may be operable to sense the logic state stored in the ferroelectric memory cell after isolating the first and second capacitors. Some examples of the device may include a transistor operable to isolate the second cascode structure from the voltage source.

[0113] In some instances, a first threshold voltage of the first cascode structure can be compensated before the first voltage can be transmitted through the first cascode structure, and a second threshold voltage of the second cascode structure can be compensated before the second voltage can be transmitted through the second cascode structure. Some examples of the device may include a first gate capacitor coupled to a first gate of the first cascode structure and operable to store a third voltage associated with the first threshold voltage, wherein compensation of the first threshold voltage may be based on storing the third voltage; and a second gate capacitor coupled to a second gate of the second cascode structure and operable to store a fourth voltage associated with the second threshold voltage, wherein compensation of the second threshold voltage may be based on storing the fourth voltage.

[0114] Describe a device. The device may include an array of ferroelectric memory cells; and a controller coupled to the memory cell array and operable to cause the device to: bias a second gate of a second cascode structure to a second voltage to compensate for a second threshold voltage of the second cascode structure, the second cascode structure being coupled to a voltage source for providing a reference signal during the access operation; based on biasing the first gate of a first cascode structure to the first voltage, transmit a third voltage associated with the ferroelectric memory cell through the first cascode structure to a first capacitor; based on biasing the second gate of the second cascode structure to the second voltage, transmit a fourth voltage associated with the reference signal through the second cascode structure to a second capacitor; and determine a logic state stored in the ferroelectric memory cell based on the third voltage transmitted to the first capacitor and the fourth voltage transmitted to the second capacitor.

[0115] Some instances may additionally include, as part of the access operation, pre-charging the digital lines and dummy digital lines associated with the reference signal to a pre-charge voltage, wherein biasing the first gate of the first cascode structure and the second gate of the second cascode structure may be based on pre-charging the digital lines and the dummy digital lines. Some instances may additionally include activating a set of transistors to couple a pre-charge voltage source to the digital lines and the dummy digital lines.

[0116] Some examples may further include using a first transistor to isolate the first capacitor from the first cascode structure; using a second transistor to isolate the second capacitor from the second cascode structure; and activating a sensing component after isolating the first capacitor and the second capacitor, the sensing component being configured to sense the logic state stored in the ferroelectric memory cell, wherein determining the logic state may be based on activating the sensing component.

[0117] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0118] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0119] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path; in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0120] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, it prevents signals from flowing between the components using previously permitted conductive paths.

[0121] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0122] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0123] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0124] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0125] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0126] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0127] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…”) indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0128] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: As part of the access operation of the ferroelectric memory cell, the first gate of the first cascode structure is biased to a first voltage to compensate for the first threshold voltage of the first cascode structure, the first cascode structure being coupled to the digital line associated with the ferroelectric memory cell; The second gate of the second cascode structure is biased to a second voltage to compensate for the second threshold voltage of the second cascode structure, the second cascode structure being coupled to a voltage source for providing a reference signal during the access operation; At least in part, the third voltage associated with the ferroelectric memory cell is transmitted to the first capacitor through the first cascode structure by biasing the first gate of the first cascode structure to the first voltage. At least in part, the fourth voltage associated with the reference signal is transmitted to the second capacitor through the second cascode structure by biasing the second gate of the second cascode structure to the second voltage. and The logic state stored in the ferroelectric memory cell is determined at least in part based on the third voltage delivered to the first capacitor and the fourth voltage delivered to the second capacitor, wherein the fourth voltage delivered to the second capacitor is different from the voltage associated with the voltage source.

2. The method of claim 1, further comprising: As part of the access operation, the digital lines and the dummy digital lines associated with the reference signal are precharged to a precharge voltage, wherein the bias applied to the first gate of the first cascode structure and the bias applied to the second gate of the second cascode structure are at least partially based on the precharging of the digital lines and the dummy digital lines.

3. The method of claim 2, wherein precharging the digital line and the dummy digital line further comprises: Activate the transistor set to couple the precharge voltage source to the digital line and the dummy digital line.

4. The method of claim 2, further comprising: During at least a portion of the precharge operation, a transistor is used to isolate the first gate of the first cascode structure from the digital line; and At least in part, based on using the transistor to isolate the first gate from the digital line, one or more transistors are used to couple the first gate of the first cascode structure to a second voltage source to bias the first gate.

5. The method of claim 2, wherein the dummy digital line includes a third capacitor.

6. The method of claim 1, further comprising: The first transistor is used to isolate the first capacitor from the first common-source, common-gate structure. The second transistor is used to isolate the second capacitor from the second cascode structure; and After isolating the first capacitor and the second capacitor, a sensing component is activated, the sensing component being configured to sense the logic state stored in the ferroelectric memory cell, wherein the determination of the logic state is based at least in part on the activation of the sensing component.

7. The method of claim 6, further comprising: The sensing component is used to compare the third voltage delivered to the first capacitor and the fourth voltage delivered to the second capacitor, wherein the logic state is determined at least in part based on the comparison of the third voltage and the fourth voltage.

8. The method of claim 6, wherein the sensing component includes a latch.

9. The method of claim 1, further comprising: At least in part, the first threshold voltage is compensated by storing a first charge associated with the first threshold voltage in a first gate capacitor coupled to the first gate of the first cascode structure, based on biasing the first gate to the first voltage, wherein the compensation of the first threshold voltage is based at least in part on storing the first charge. and At least in part, the second threshold voltage is biased to the second voltage, and a second charge associated with the second threshold voltage is stored in a second gate capacitor coupled to the second gate of the second cascode structure, wherein compensation of the second threshold voltage is at least in part based on storing the second charge.

10. The method of claim 1, further comprising: A bias voltage is applied to the word line to couple the ferroelectric memory cell to the digital line; and Charge sharing between the ferroelectric memory cell and the digital line is initiated at least in part based on biasing the word line, wherein the transfer of the third voltage to the first capacitor is at least in part based on initiating the charge sharing.

11. The method of claim 10, further comprising: Before biasing the word line, a transistor is used to isolate the second cascode structure from the third capacitor; and After biasing the word line and at least partially based on initiating the charge sharing, the transistor couples the second cascode structure to the third capacitor.

12. The method of claim 10, further comprising: Before biasing the word lines, a transistor is used to isolate the first cascode structure from the digital lines; and After biasing the word line and at least in part based on initiating the charge sharing, the transistor is used to couple the first cascode structure to the digital line.

13. An apparatus comprising: Ferroelectric memory cell; A first common-source, common-gate structure is selectively coupled to the ferroelectric memory cell; A first capacitor is coupled to the first cascode structure and is operable to receive a first voltage from the ferroelectric memory cell through the first cascode structure; A voltage source that is operable to provide a reference signal; The second common-source cascode structure can be selectively coupled to the voltage source; A second capacitor is coupled to the second cascode structure and is operable to receive a second voltage from the voltage source through the second cascode structure; and A sensing component coupled to the first capacitor and the second capacitor and operable to determine, at least in part, the logic state stored in the ferroelectric memory cell based on the first voltage received by the first capacitor and the second voltage received by the second capacitor, wherein the second voltage received by the second capacitor is different from the voltage associated with the voltage source.

14. The device according to claim 13, further comprising: Digital lines, which may be selectively coupled to the ferroelectric memory cell and the first cascode structure.

15. The device according to claim 14, further comprising: A pre-charge voltage source operable to pre-charge the digital lines and the dummy digital lines associated with the reference signal to a pre-charge voltage; and A transistor set operable to couple the precharge voltage source to the digital line and the dummy digital line.

16. The device according to claim 15, further comprising: A transistor that isolates the first gate of the first cascode structure from the digital line during at least a portion of the precharge operation; and One or more transistors operable to, at least in part, isolate the first gate from the digital line using the transistors, couple the first gate of the first cascode structure to a second voltage source to bias the first gate.

17. The device of claim 15, wherein the dummy digital line includes a third capacitor.

18. The device according to claim 13, further comprising: A first transistor is operable to isolate the first capacitor from the first cascode structure; and The second transistor is operable to isolate the second capacitor from the second cascode structure, wherein the sensing component is operable to sense the logic state stored in the ferroelectric memory cell after isolating the first capacitor and the second capacitor.

19. The device according to claim 13, further comprising: A transistor operable to isolate the second cascode structure from the voltage source.

20. The device according to claim 13, wherein: The first threshold voltage of the first cascode structure is compensated before the first voltage is transmitted through the first cascode structure; and The second threshold voltage of the second cascode structure is compensated before the second voltage is transmitted through the second cascode structure.

21. The device according to claim 20, further comprising: A first gate capacitor is coupled to a first gate of the first cascode structure and operable to store a third voltage associated with the first threshold voltage, wherein compensation of the first threshold voltage is based at least in part on storing the third voltage; and A second gate capacitor is coupled to the second gate of the second cascode structure and is operable to store a fourth voltage associated with the second threshold voltage, wherein compensation of the second threshold voltage is based at least in part on storing the fourth voltage.

22. An apparatus comprising: Ferroelectric memory cell array; and A controller, coupled to the memory cell array and operable to cause the device to perform the following operations: As part of the access operation of the ferroelectric memory cell in the array, the first gate of the first cascode structure is biased to a first voltage to compensate for the first threshold voltage of the first cascode structure, the first cascode structure being coupled to the digital line associated with the ferroelectric memory cell; The second gate of the second cascode structure is biased to a second voltage to compensate for the second threshold voltage of the second cascode structure, the second cascode structure being coupled to a voltage source for providing a reference signal during the access operation; At least in part, the third voltage associated with the ferroelectric memory cell is transmitted to the first capacitor through the first cascode structure by biasing the first gate of the first cascode structure to the first voltage. At least in part, the fourth voltage associated with the reference signal is transmitted to the second capacitor through the second cascode structure by biasing the second gate of the second cascode structure to the second voltage. and The logic state stored in the ferroelectric memory cell is determined at least in part based on the third voltage delivered to the first capacitor and the fourth voltage delivered to the second capacitor, wherein the fourth voltage delivered to the second capacitor is different from the voltage associated with the voltage source.

23. The device of claim 22, wherein the controller is further operable to cause the device to perform the following operations: As part of the access operation, the digital lines and the dummy digital lines associated with the reference signal are precharged to a precharge voltage, wherein the bias applied to the first gate of the first cascode structure and the bias applied to the second gate of the second cascode structure are at least partially based on the precharging of the digital lines and the dummy digital lines.

24. The device of claim 23, wherein the controller is further operable to cause the device to perform the following operations: Activate the transistor set to couple the precharge voltage source to the digital line and the dummy digital line.

25. The device of claim 22, wherein the controller is further operable to cause the device to perform the following operations: The first transistor is used to isolate the first capacitor from the first common-source, common-gate structure. The second transistor is used to isolate the second capacitor from the second cascode structure; and After isolating the first capacitor and the second capacitor, a sensing component is activated, the sensing component being configured to sense the logic state stored in the ferroelectric memory cell, wherein the determination of the logic state is based at least in part on the activation of the sensing component.

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