Plasma processing device and plasma processing method

Abstract

A plasma processing device comprises: a sample stage having a mounting surface for mounting a semiconductor wafer; a dielectric ring having an annular thin film electrode arranged around the sample stage; and a dielectric base ring covering the thin film electrode, wherein the thin film electrode comprises: a first portion located at a position lower than the back surface of the semiconductor wafer; a second portion located at a position higher than the main surface of the semiconductor wafer; and a third portion connecting the first portion and the second portion, wherein the first portion of the thin film electrode has an overlapping area overlapping the semiconductor wafer when observed from above.

Description

Technical Field

[0001] The present invention relates to a plasma processing device and a plasma processing method, and in particular to a plasma processing device and a plasma processing method suitable for processing a workpiece such as a semiconductor wafer. Background Art

[0002] In semiconductor manufacturing processes, dry etching using plasma is generally performed. Various types of plasma processing apparatuses are used for dry etching.

[0003] In general, a plasma processing apparatus is composed of a vacuum processing chamber, a gas supply device connected thereto, a vacuum exhaust system for maintaining the pressure in the vacuum processing chamber at a desired value, an electrode for mounting a semiconductor wafer as a workpiece, a plasma generating unit for generating plasma in the vacuum processing chamber, etc. The plasma generating unit converts the processing gas supplied from a shower plate or the like into a plasma state in the vacuum processing chamber, thereby performing etching processing on the semiconductor wafer held by the wafer mounting electrode.

[0004] In recent years, as the integration of semiconductor devices has increased, circuit structures have become more miniaturized, and therefore, micromachining, i.e., improved machining accuracy, has been required. Furthermore, in order to increase the yield of good semiconductor devices per semiconductor wafer, a plasma processing device that can manufacture good semiconductor devices up to the peripheral portion of the semiconductor wafer is sought.

[0005] In order to suppress the degradation of the performance at the peripheral portion of the semiconductor wafer, it is important to reduce the concentration of the electric field in the peripheral region of the semiconductor wafer placed on the sample stage. For example, in the case of etching processing, it is necessary to suppress the rapid increase of the processing speed (etching rate) at the peripheral portion of the semiconductor wafer. Therefore, it is necessary to make the thickness of the sheath formed above the semiconductor wafer uniform from the center portion of the semiconductor wafer to the peripheral region during the processing of the semiconductor wafer.

[0006] The following technology is disclosed in JP Patent Gazette No. 2020-43100 (Patent Document 1): a conductive thin film electrode is provided on a portion of an insulating ring arranged around the periphery of a sample stage on which a semiconductor chip is placed, a first high-frequency power is applied to the sample stage, and a second high-frequency power is applied to the thin film electrode, thereby improving the uniformity of plasma processing up to the peripheral portion of the semiconductor chip.

[0007] The following technology is disclosed in JP Patent Gazette No. 2010-283028 (Patent Document 2): a dielectric ring arranged to surround the outer periphery of a sample table on which a semiconductor chip is placed, and a conductive ring provided thereon, wherein the conductive ring is integrally formed by an outer ring having an upper surface higher than the chip and an inner ring having an upper surface lower than the chip, and by applying a DC voltage to the conductive ring, the ion incident angle is controlled, thereby improving the balance between the reduction of deposits and the processing results.

[0008] Prior art literature

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent Application Publication No. 2020-43100

[0011] Patent Document 2: Japanese Patent Application Publication No. 2010-283028 Summary of the invention

[0012] Problems to be solved by the invention

[0013] In Patent Document 1, in order to suppress electrical interference with high-frequency power of other systems applied to the sample stage, an insulating ring formed with a thin-film electrode to which high-frequency power is applied is provided with a structure other than a sample stage mounting surface covered by a base ring made of a dielectric material. Therefore, the inner peripheral end of the thin-film electrode cannot be brought close to the end of the wafer, and further research is required for appropriate electric field control around the end of the wafer.

[0014] In addition, since there is no guard ring covering the periphery of the conductive ring in Patent Document 2, the temperature of the conductive ring rises due to the contact of the conductive ring with plasma. It is necessary to study the fact that the reliability of the device is impaired due to this influence, and the fact that the temperature of the processed wafer is uneven due to the influence of heat, resulting in a deviation in the processed shape.

[0015] That is, a plasma processing method is provided for improving the reliability of a plasma processing apparatus or improving the yield of semiconductor wafers to be processed.

[0016] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0017] Means for solving problems

[0018] A plasma processing device in one embodiment comprises: a sample stage, which has a mounting surface having a first circle when viewed from above and on which a semiconductor chip is mounted; a dielectric ring, which has a ring-shaped thin film electrode that surrounds the sample stage in an outer peripheral area of ​​the sample stage and includes an inner peripheral end and an outer peripheral end when viewed from above; and a base ring that is mounted on the dielectric ring and covers the thin film electrode, and is made of dielectric, wherein the semiconductor chip includes: a main surface and a back surface having a second circle when viewed from above; and an end portion of the arc portion of the main surface, wherein the first radius of the first circle is smaller than the second radius of the second circle, and the thin film electrode includes between the inner peripheral end and the outer peripheral end: a first portion located at a position lower than the back surface of the semiconductor chip; a second portion located at a position higher than the main surface of the semiconductor chip; and a third portion connecting the first portion and the second portion, wherein the first portion of the thin film electrode has an overlapping region that overlaps with the semiconductor chip when viewed from above.

[0019] In addition, a plasma processing method in one embodiment includes the following steps: (a) preparing a plasma processing device having a sample stage, a ring-shaped thin film electrode arranged on the outer periphery of the sample stage, and a high-frequency power supply; (b) placing a semiconductor chip having a main surface and a back surface on the sample stage; and (c) performing plasma processing on the main surface of the semiconductor chip, wherein the thin film electrode comprises: a first part located at a lower position than the back surface of the semiconductor chip; a second part located at a higher position than the main surface of the semiconductor chip; and a third part connecting the first part and the second part, wherein the first part of the thin film electrode has an overlapping area overlapping with the semiconductor chip when observed from above, and in step (c), high-frequency power is supplied to the sample stage and the thin film electrode from the high-frequency power supply.

[0020] Effects of the Invention

[0021] According to one embodiment, the reliability of a plasma processing device can be improved. In addition, the yield rate of objects to be processed in plasma processing can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a cross-sectional view schematically showing the structure of a plasma processing apparatus according to one embodiment.

[0023] Figure 2 This is a cross-sectional view showing the periphery of a wafer placement electrode of a plasma processing apparatus according to an embodiment.

[0024] Figure 3 This is a plan view showing a wafer mounting electrode of a plasma processing apparatus according to an embodiment.

[0025] Figure 4 yes Figure 3 Cross-sectional view of line XX.

[0026] Figure 5 This is a cross-sectional view showing the periphery of a wafer mounting electrode of a plasma processing apparatus according to Modification 1.

[0027] Figure 6 This is a cross-sectional view schematically showing the structure of a plasma processing apparatus according to Modification 2. DETAILED DESCRIPTION

[0028] The following detailed description of the embodiment is based on the accompanying drawings. In addition, in all the figures used to illustrate the embodiment, the same reference numerals are used to mark the components with the same functions, and their repeated descriptions are omitted. In addition, in the following embodiments, the description of the same or identical parts is not repeated in principle except when it is particularly necessary.

[0029] (Implementation Method)

[0030] <Plasma processing equipment>

[0031] The following uses Figure 1 to Figure 4 The plasma processing apparatus according to this embodiment will be described. Figure 1 is a schematic cross-sectional view schematically showing the structure of a plasma processing apparatus according to this embodiment. Figure 2 1 is a cross-sectional view showing the periphery of a wafer placement electrode of a plasma processing apparatus according to the present embodiment. Figure 3 FIG. 1 is a plan view showing a wafer mounting electrode of the plasma processing apparatus according to the present embodiment. Figure 4 yes Figure 3 Cross-sectional view of line XX.

[0032] Figure 1 The plasma etching device 100 is an example of a plasma processing device. The plasma etching device 100 uses the electric field of microwaves as the electric field for forming plasma, induces ECR (Electron Cyclotron Resonance) of the electric field and magnetic field of microwaves to form plasma, and uses the plasma to etch substrate-shaped samples such as semiconductor wafers.

[0033] The plasma etching device 100 has a vacuum container 101, which has a processing chamber 104 in which plasma is formed. The processing chamber 104 has a cylindrical shape on the upper part thereof, and a disc-shaped dielectric window 103 (for example, made of quartz) is installed as a cover member, which constitutes a part of the vacuum container 101. A sealing member such as an O-ring is arranged between the cylindrical vacuum container 101 and the dielectric window 103 to ensure the airtightness of the inside of the vacuum container 101 or the processing chamber 104.

[0034] In addition, a vacuum exhaust port 110 connected to the processing chamber 104 is arranged at the lower part of the vacuum container 101, and is connected to a vacuum exhaust device (not shown) arranged below the vacuum container 101. Furthermore, a shower plate 102 constituting a circular top plate surface of the processing chamber 104 is provided below the dielectric window 103. The shower plate 102 has a circular plate shape with a plurality of gas introduction holes 102a arranged through the center, and the gas for etching processing is introduced into the processing chamber 104 through the gas introduction holes 102a. The shower plate 102 is made of a dielectric material such as quartz.

[0035] An electric field / magnetic field forming unit 160 for forming an electric field and a magnetic field for generating plasma 116 is arranged above the vacuum container 101. The electric field / magnetic field forming unit 160 includes a waveguide 105 and an electric field generating power supply 106. A high-frequency electric field oscillated from the electric field generating power supply 106 is transmitted inside the waveguide 105 and introduced into the processing chamber 104. For example, a microwave of 2.45 GHz is used as the frequency of the electric field.

[0036] Magnetic field generating coils 107 are disposed around the lower end of the waveguide 105 and around the vacuum container 101. The magnetic field generating coils 107 are composed of an electromagnet and a yoke that are supplied with a direct current to form a magnetic field.

[0037] When the gas for processing is introduced into the processing chamber 104 from the gas inlet hole 102a of the shower plate 102, the electric field of the microwave oscillated by the electric field generating power supply 106 propagates inside the waveguide 105, passes through the dielectric window 103 and the shower plate 102, and is supplied from the top to the processing chamber 104 downward. Furthermore, the magnetic field caused by the direct current supplied to the magnetic field generating coil 107 is supplied to the processing chamber 104, so that it interacts with the electric field of the microwave, and induces ECR (Electron Cyclotron Resonance). Through ECR, the atoms or molecules of the gas for processing are excited, dissociated or ionized, and a high-density plasma 116 is generated in the processing chamber 104.

[0038] A wafer placement electrode 120 is disposed below the space where the plasma 116 is formed. The wafer placement electrode 120 has a cylindrical protrusion (convex) portion whose upper surface is higher than the outer peripheral side at the center of the upper portion, and a placement surface 120a on which a semiconductor wafer (hereinafter also simply referred to as a wafer) 109 as a sample (processing object) is placed is disposed on the upper surface of the convex portion. The placement surface 120a is disposed to face the shower plate 102 or the dielectric window 103.

[0039] like Figure 2As shown, the wafer mounting electrode 120 includes an electrode substrate 108 , a dielectric film 140 provided on the electrode substrate 108 , an insulating plate 150 and a ground plate 151 provided under the electrode substrate 108 , a dielectric ring 139 , and a susceptor ring 113 .

[0040] The electrode substrate 108 includes a convex portion (protrusion) 108p and a concave portion (depressed portion) 108d. The circular convex portion 108p is located in the central portion of the electrode substrate 108 when viewed from above, and the annular concave portion 108d is located around it. The convex portion 108p includes a circular upper surface 108a when viewed from above, and the upper surface 108a is covered with a dielectric film 140. In addition, the dielectric film 140 includes a mounting surface 120a, and the semiconductor wafer 109 is mounted on the mounting surface 120a. The mounting surface 120a has a circular shape when viewed from above, and its radius is equal to the radius of the upper surface 108a, and the centers of the two circles overlap each other.

[0041] A plurality of conductive films, namely, conductive films 111, are arranged inside the dielectric film 140. Figure 1 As shown in FIG. 1 , the conductor film 111 is connected to a DC power source 126 via a high frequency filter 125. When DC power is supplied to the conductor film 111, the semiconductor wafer 109 is adsorbed on the mounting surface 120a via the dielectric film 140 on the conductor film 111. The conductor film 111 is an electrode for electrostatic adsorption. For convenience, the convex portion (protrusion) 108p of the electrode substrate 108 and the dielectric film 140 including the conductor film 111 are referred to as a sample stage ST.

[0042] The electrode substrate 108 is connected to the high frequency power source 124 via the junction box 127 and the matching device 129. The high frequency power source 124 and the matching device 129 are arranged closer to the distance between the high frequency filter 125 and the conductor film 111. The high frequency power source 124 is connected to the ground 112.

[0043] During the processing of the semiconductor wafer 109, a high frequency power of a given frequency is supplied to the electrode substrate 108 (i.e., the sample stage ST) from the high frequency power supply 124. A bias potential having a distribution corresponding to the difference between the potential of the plasma 116 and the potential of the electrode substrate 108 is formed above the semiconductor wafer 109 adsorbed and held on the mounting surface 120a via the dielectric film 140.

[0044] In order to cool the wafer mounting electrode 120, the electrode substrate 108 is provided with a refrigerant flow path 152 that is arranged in a spiral or concentric manner in multiple layers around the central axis of the electrode substrate 108 in the vertical direction. The inlet and outlet of the wafer mounting electrode 120 are connected to a temperature regulator that has a refrigeration cycle (not shown) and regulates the temperature of the refrigerant to a given range through heat transfer through a pipeline, and the refrigerant that flows through the refrigerant flow path 152 and changes in temperature through heat exchange flows out from the outlet, passes through the pipeline and passes through the flow path inside the temperature regulator to be set to a given temperature range, and is then supplied to the refrigerant flow path 152 in the electrode substrate 108 for circulation.

[0045] An annular dielectric ring 139 surrounding the convex portion 108p is mounted on the concave portion 108d of the electrode substrate 108, and a base ring 113 is mounted on the dielectric ring 139. The dielectric ring 139 and the base ring 113 are made of a dielectric material such as ceramics such as quartz or alumina. The side surface of the electrode substrate 108 and the bottom surface of the concave portion 108b are at least covered by the dielectric ring 139 or the base ring 113, which can prevent the electrode substrate 108 from being damaged by plasma. In addition, the surface of the dielectric ring 139 in contact with the base ring 113 is, for example, a rough surface with a surface roughness Ra of 1.0 or more. In this way, heat transfer from the base ring 113, which is in contact with plasma and becomes high temperature, to the dielectric ring 139 is suppressed.

[0046] The dielectric ring 139 is composed of a dielectric ring 139a and a thin film electrode 139b, and the thin film electrode 139b is formed on the stepped upper surface of the dielectric ring 139a. The thin film electrode 139b is connected to the junction box 127 via the load impedance variable box 130. That is, the electrode substrate 108 of the sample stage ST on which the semiconductor wafer 109 is mounted and the thin film electrode 139b of the dielectric ring 139 are connected to the high frequency power supply 124 as a single power supply, and the high frequency power supply 124 supplies high frequency power to the electrode substrate 108 and the thin film electrode 139b.

[0047] The chip mounting electrode 120 includes: an insulating plate 150 which is arranged in contact with the lower surface of the electrode substrate 108 and is in the shape of a disk; and a grounding plate 151 which is a member made of a conductive disk and arranged in contact with the lower surface of the insulating plate 150 and is set to a ground potential.

[0048] like Figure 1 As shown, the electric field generating power supply 106, the magnetic field generating coil 107, the high frequency power supply 124, the high frequency filter 125, the DC power supply 126, the junction box 127, the matching device 129, the load impedance variable box 130 and the controller 170 are connected to each other via wired or wireless communication.

[0049] use Figure 3 A top view of Figure 4 The mounting surface 120a, the semiconductor wafer 109 and the thin film electrode 139b of the sample stage ST are explained by using a cross-sectional view. Figure 4 As shown, the semiconductor wafer 109 has a main surface 109 a subjected to plasma treatment, a rear surface 109 b in contact with the mounting surface 120 a , and an end portion 109 e which is an arc portion of the main surface 109 a .

[0050] like Figure 3 As shown, the mounting surface 120a has a circular shape with a radius R1 from the center OS. The annular thin film electrode 139b has: an inner peripheral end 139bie of a circle with a radius R3 from the center OS; and an outer peripheral end 139boe of a circle with a radius R4 from the center OS. In addition, the main surface 109a of the semiconductor chip 109 (in other words, the end 109e) has a circular shape with a radius R2 from the center OU. In addition, due to the "matching deviation" when the semiconductor chip 109 is mounted on the mounting surface 120a, there is a situation where the center OU deviates from the center OS, but Figure 3 The same situation is shown in the figure. Even if there is a "matching deviation", plasma processing is performed as long as it is within the allowable range. The radius R2 of the main surface 109a of the semiconductor chip 109 is larger than the radius R1 of the mounting surface 120a (R2>R1). In addition, the radius R4 of the outer peripheral end 139boe of the thin film electrode 139b is larger than the radius R3 of the inner peripheral end 139bie (R4>R3). The characteristic point of this embodiment is that the radius R3 of the inner peripheral end 139bie of the thin film electrode 139b is smaller than the radius R2 of the end 109e of the semiconductor chip 109 (R3<R2). That is, when viewed from above, the thin film electrode 139b and the semiconductor chip 109 have an "overlapping area ( Figure 3 Moreover, the “overlapping area” covers the entire arc-shaped end 109e of the semiconductor chip 109. Assuming that the aforementioned “matching deviation” occurs and the center OU deviates from the center OS, the “overlapping area” is also ensured over the entire arc-shaped end 109e of the semiconductor chip 109.

[0051] like Figure 4As shown in the figure, the upper surface of the dielectric ring 139a includes a first surface 139a1, a third surface 139a3, and a second surface 139a2 arranged in a step shape. The first surface 139a1 and the second surface 139a2 are horizontal surfaces parallel to the main surface 109a or the mounting surface 120a of the semiconductor wafer 109, and the third surface 139a3 is a surface connecting the first surface 139a1 and the second surface 139a2, and is a surface perpendicular to the main surface 109a or the mounting surface 120a of the semiconductor wafer 109. In addition, a thin film electrode 139b is provided on the upper surface of the dielectric ring 139a. In addition, an insulating film may be provided on the upper surface of the dielectric ring 139a, and the thin film electrode 139b may be formed thereon.

[0052] The thin film electrode 139b is composed of a conductive film such as a thermal spray film of tungsten. The annular thin film electrode 139b has a ring width from the inner peripheral end 139bie to the outer peripheral end 139boe, and has a first part 139b1, a third part 139b3 and a second part 139b2 in the width direction. The first part 139b1, the third part 139b3 and the second part 139b2 are formed corresponding to the first surface 139a1, the third surface 139a3 and the second surface 139a2 of the upper surface of the dielectric ring 139a, respectively. Therefore, the first part 139b1 and the second part 139b2 are horizontal planes parallel to the main surface 109a or the mounting surface 120a of the semiconductor wafer 109, and the third part 139b3 is a vertical plane connecting the first part 139b1 and the second part 139b2. In addition, the first portion 139b1 is located at a position lower than the back surface 109b of the semiconductor wafer 109 in the vertical direction, and the inner peripheral end 139bie is located below the semiconductor wafer 109 and overlaps with the semiconductor wafer 109. The first portion 139b1 is arranged to be separated from the back surface 109b of the semiconductor wafer 109 by a distance A in the vertical direction, and has an "overlapping area" with the semiconductor wafer 109 when viewed from above. The second portion 139b2 is located at a position higher than the main surface 109a of the semiconductor wafer 109 in the entire region. In addition, the third portion 139b3 is separated from the end 109e of the semiconductor wafer 109 by a distance B in the horizontal direction. The present embodiment is characterized in that the distance A is smaller than the distance B. The so-called horizontal direction is a direction orthogonal to the vertical direction, and is a direction parallel to the mounting surface 120a or the main surface 109a of the semiconductor wafer 109.

[0053] In addition, if Figure 2 As shown, the first portion 139b1, the third portion 13963, and the second portion 13962 of the thin film electrode 139b have their surfaces (upper surfaces) covered by the susceptor ring 113. The susceptor ring 113 has a surface higher than the main surface 109a of the semiconductor wafer 109 above the second portion 139b2.

[0054] <Plasma treatment method>

[0055] Next, a plasma processing method using the aforementioned plasma etching apparatus 100 will be described.

[0056] First, the aforementioned plasma etching apparatus 100 is prepared.

[0057] Next is the process of carrying in the semiconductor wafer 109. The side wall of the vacuum container 101 is connected to a vacuum transport chamber that is decompressed to the same pressure as the processing chamber 104. The semiconductor wafer 109 is placed on the front end of the arm of the wafer transport robot arranged in the vacuum transport chamber and carried into the processing chamber 104. Next, the semiconductor wafer 109 is placed on the mounting surface 120a and is held on the sample stage ST by electrostatic adsorption.

[0058] Next is the etching gas introduction process. After the transport robot exits into the vacuum transport chamber, the interior of the processing chamber 104 is sealed. In this state, the gas for etching treatment is supplied to the processing chamber 104. The introduced gas is introduced into the processing chamber 104 through the gas introduction hole 102a of the shower plate 102. The gas and particles inside the processing chamber 104 are exhausted through the vacuum exhaust port 110 by the action of the vacuum exhaust device connected to the vacuum exhaust port 110. Corresponding to the balance between the supply amount of gas from the gas introduction hole 102a of the shower plate 102 and the exhaust amount from the vacuum exhaust port 110, the processing chamber 104 is adjusted to a given pressure suitable for the processing of the semiconductor wafer 109.

[0059] Next is the plasma etching (plasma treatment) process. Although the details are omitted, after adjusting the temperature of the semiconductor wafer 109 as needed, the electric field and magnetic field of microwaves are supplied to the processing chamber 104, and the plasma 116 is generated using gas. When the plasma 116 is formed, high-frequency (RF) power is supplied to the electrode substrate 108 from the high-frequency power supply 124, and a bias potential is formed above the main surface 109a of the semiconductor wafer 109, and the ions and other charged particles in the plasma 116 are induced to the main surface 109a of the semiconductor wafer 109 in accordance with the potential difference with the potential of the plasma 116. Furthermore, the charged particles collide with the surface of the film layer of the processing object pre-configured on the main surface 109a of the semiconductor wafer 109, thereby performing etching processing. In addition, as Figure 2 to Figure 4 As described in the figure, high frequency (RF) power is supplied from the high frequency power supply 124 to the thin film electrode 139b provided in the dielectric ring 139 via the matching circuit 129, the junction box 127 and the load impedance variable box 130. In addition, during the etching process, the process gas introduced into the process chamber 104 and the particles of the reaction product generated during the process are exhausted from the vacuum exhaust port 110.

[0060] Next is the step of carrying out the semiconductor wafer 109 . The semiconductor wafer 109 after the etching process is supported by the front end of the arm of the aforementioned transport robot and carried out of the processing chamber 104 .

[0061] <Features of this embodiment>

[0062] In the plasma processing apparatus of this embodiment, high-frequency power is supplied from a single high-frequency power supply 124 to the electrode substrate 108 of the sample stage ST and the thin-film electrode 139b provided on the dielectric ring 139 during the processing of the semiconductor wafer 109. The high-frequency power output from the high-frequency power supply 124 is supplied to the thin-film electrode 139b provided on the inner side of the susceptor ring 113 via the load impedance variable box 130 provided on the power supply path that electrically connects the junction box 127 and the thin-film electrode 139b. At this time, by adjusting the impedance on the power supply path to a value within an appropriate range in the load impedance variable box 130, the impedance value to the high-frequency power from the high-frequency power supply 124 through the junction box 127 and through the electrode substrate 108 to the peripheral edge of the semiconductor wafer 109 becomes relatively low with respect to the relatively high impedance portion of the upper portion of the susceptor ring 113. Thus, high frequency power can be effectively supplied to the peripheral portion and the outer peripheral region of the semiconductor wafer 109, and the concentration of the electric field in the peripheral portion and the outer peripheral region of the semiconductor wafer 109 can be alleviated to make the height distribution of the equipotential surface of the bias potential above these regions uniform. Therefore, the reliability of the plasma processing device is improved, and the yield rate of the plasma processing of the semiconductor wafer 109 can be improved.

[0063] In addition, the thin film electrode 139b includes: a first portion 139b1 located at a lower position than the back surface 109b of the semiconductor wafer 109; a second portion 13962 located at a higher position than the main surface 109a of the semiconductor wafer 109; and a third portion 139b3 connecting the first portion 139b1 and the second portion 139b2. In addition, the first portion 139b1 has an "overlapping region" overlapping with the semiconductor wafer 109 when viewed from above. In addition, the first portion 139b1 is arranged to be separated from the back surface 109b by a distance A in the vertical direction, and the third portion 139b3 is arranged to be separated from the end 109e of the semiconductor wafer 109 by a distance B in the horizontal direction, and the distance A is smaller than the distance B.

[0064] The sheath potential distribution of the outer peripheral area of ​​the semiconductor wafer 109 obtained by supplying high-frequency power to the thin film electrode 139b is mainly formed by the first part 139b1 and the second part 139b2. By making the first part 139b1 and the second part 139b2 close to the semiconductor wafer 109, the potential distribution can enhance the electric field strength and expand the control domain of the sheath potential. However, if the third part 139b3 is too close to the semiconductor wafer 109, the sheath potential distribution will become a steep slope along the shape of the base ring 113 near the end 109e of the semiconductor wafer 109, which becomes inappropriate as a control domain. On the other hand, when the first part 139b1 is close to the back side 109b of the semiconductor wafer 109, the influence is only shown in the sheath potential distribution near the end 109e of the semiconductor wafer 109, and the controllability becomes better than the case where the third part 139b3 is too close. As described above, in order to have an appropriate sheath potential control domain, it is desirable that the distance A is smaller than the distance B (A<B).

[0065] In addition, the dielectric ring 139 having the thin film electrode 139b has its upper surface covered by the dielectric susceptor ring 113 and does not contact the plasma 116, so that an excessive temperature rise can be suppressed. Furthermore, since the surface of the dielectric ring 139 in contact with the susceptor ring 113 is composed of a rough surface (for example, the surface roughness Ra is 1.0 or more), heat transfer from the susceptor ring 113 that has become high temperature due to contact with the plasma to the dielectric ring 139 can be suppressed. Therefore, the reliability of the plasma processing device can be improved, and further, since the occurrence of processing shape deviation can be suppressed, the manufacturing yield of the semiconductor wafer 109 can be improved.

[0066] Furthermore, by supplying high-frequency power from the single high-frequency power source 124 to the electrode substrate 108 of the sample stage ST and the thin-film electrode 139b provided on the dielectric ring 139, electrical mutual interference between the high-frequency power applied to the electrode substrate 108 and the high-frequency power applied to the thin-film electrode 139b can be suppressed. Under the back surface 109b of the semiconductor wafer 109, the inner peripheral end 139bie of the thin-film electrode 139b can be brought close to the sample stage ST, and the first portion 139b1 and the second portion 139b2 of the thin-film electrode 139b can be brought close to the semiconductor wafer 109. As a result, since appropriate electric field control and sheath potential control can be performed at the peripheral portion and the outer peripheral region of the semiconductor wafer 109, the reliability of the plasma processing apparatus can be improved and the yield rate of the semiconductor wafer 109 can be improved.

[0067] (Variant 1)

[0068] Figure 5 This is a cross-sectional view showing the periphery of a wafer mounting electrode of a plasma processing apparatus according to Modification 1. Figure 5 yes Figure 4A variation of .

[0069] The shape of the dielectric ring 139' is similar to that of the above-mentioned embodiment. Figure 4 The upper surface of the dielectric ring 139a' includes a first surface 139a1, a third surface 139a3', and a second surface 139a2. The third surface 139a3' has an inclination greater than 90° with respect to the first surface 139a1 and the second surface 139a2. The third surface 139a3' has an inclination approaching the sample stage ST along the vertical direction.

[0070] The annular thin film electrode 139b' has a ring width from the inner peripheral end 139bie to the outer peripheral end 139boe, and has a first portion 139b1, a third portion 139b3', and a second portion 139b2 in the width direction. The first portion 139b1, the third portion 139b3', and the second portion 139b2 are formed corresponding to the first surface 139a1, the third surface 139a3', and the second surface 139a2 of the upper surface of the dielectric ring 139a', respectively. Therefore, the third portion 139b3' has an inclination close to the sample stage ST along the vertical direction.

[0071] In the first modification, similarly to the above-described embodiment, in a plan view, the first portion 139b1 has an "overlapping region" with the semiconductor wafer 109. In addition, the first portion 139b1 is disposed at a distance A apart from the back surface 109b in the vertical direction, and the third portion 139b3' is disposed at a distance B' apart from the end 109e of the semiconductor wafer 109 in the horizontal direction, and the distance A is smaller than the distance B'.

[0072] According to Modification 1, compared with the above embodiment, the lower portion of the third portion 139b3' can be brought closer to the end 109e of the semiconductor wafer 109. Therefore, the sheath potential distribution around the end 109e of the semiconductor wafer 109 is affected, and the sheath potential control region can be changed.

[0073] (Variant 2)

[0074] Figure 6 2 is a cross-sectional view schematically showing the structure of a plasma processing device according to a second modification. Figure 2 In the second modification, the high frequency power source 124 is connected to the conductor film 111 via the matching device 129 and the junction box 127 .

[0075] exist Figure 6 In the structure, the load impedance is corrected from Figure 2 The sheath potential distribution of the peripheral portion and the outer peripheral region of the semiconductor wafer 109 formed by the conductive film 111 becomes similar to Figure 2 The sheath potential distribution in the case of is the same, and the same effect as the above-mentioned embodiment can be obtained.

[0076] In addition, in the above-mentioned embodiment or modification, the etched film pre-arranged on the main surface of the semiconductor wafer 109 before processing is a silicon oxide film, and tetrafluoromethane gas, oxygen gas, and trifluoromethane gas are used as a processing gas for etching and a cleaning gas for cleaning. In addition, as the etched film, not only silicon oxide films can be used, but also polysilicon films, photoresist films, anti-reflection organic films, anti-reflection inorganic films, organic materials, inorganic materials, silicon oxide films, silicon nitride oxide films, silicon nitride films, Low-k materials, High-k materials, amorphous carbon films, Si substrates, metal materials, etc. can be used, and the same effect can be obtained in these cases.

[0077] In addition, as the processing gas for etching, chlorine gas, hydrogen bromide gas, tetrafluoromethane gas, trifluoromethane gas, difluoromethane gas, argon gas, helium gas, oxygen, nitrogen gas, carbon dioxide gas, carbon monoxide gas, hydrogen gas, etc. can be used. Furthermore, as the processing gas for etching, ammonia gas, octafluoropropane gas, nitrogen trifluoride gas, sulfur hexafluoride gas, methane gas, silicon tetrafluoride gas, silicon tetrachloride gas, neon gas, krypton gas, xenon gas, radon gas, etc. can be used.

[0078] The invention made by the inventors has been specifically described above based on the embodiment, but the present invention is not limited to the embodiment, and it is self-evident that various changes can be made within the scope of the gist thereof. For example, the wafer mounting electrode 120 may include a heater for adjusting the temperature of the semiconductor wafer 109 inside the dielectric film 140 or inside the substrate electrode 108. In addition, for such temperature adjustment, at least one temperature sensor that can be arranged to communicate with the controller 170 and detect the temperature may be provided inside the substrate electrode 108.

[0079] In the above embodiment, the following structure is described: an electric field of microwaves with a frequency of 2.45 GHz and a magnetic field capable of forming ECR are supplied to the processing chamber 104, so that the processing gas is discharged to form plasma. However, the structure described in the above embodiment can also play the same role and effect as described in the above embodiment, etc., when other discharges (UHF discharge with magnetic field, capacitive coupling discharge, inductive coupling discharge, magnetron discharge, surface wave excitation discharge, transfer coupling discharge) are used to form plasma. In addition, the above embodiment and Modifications 1 and 2 can also play the same role and effect when applied to a wafer mounting electrode arranged in other plasma processing devices for plasma processing, such as a plasma CVD device, an ashing device, a surface modification device, etc.

[0080] Description of Reference Numerals

[0081] OS Center

[0082] OU Center

[0083] ST Sample Stage

[0084] 100 Plasma Etching Device

[0085] 101 Vacuum Container

[0086] 102 Shower Panel

[0087] 102a Gas inlet hole

[0088] 103 Dielectric Window

[0089] 104 Processing Room

[0090] 105 Waveguide

[0091] 106 Power supply for generating electric field

[0092] 107 Magnetic field generating coil

[0093] 108 Electrode substrate

[0094] 108a Upper surface

[0095] 108d concave part (recessed part)

[0096] 108p convex part (protruding part)

[0097] 109 Semiconductor wafer

[0098] 109a Main surface

[0099] 109b Back

[0100] 109e End (arc part)

[0101] 110 Vacuum exhaust port

[0102] 111 Conductive film

[0103] 112 Ground

[0104] 113 Base ring

[0105] 116 Plasma

[0106] 120 Wafer mounting electrode

[0107] 120a Loading surface

[0108] 120b Upper surface

[0109] 124 High frequency power supply

[0110] 125 High frequency filter

[0111] 126 DC power supply

[0112] 127 Junction Box

[0113] 129 Matcher

[0114] 130 Load impedance variable box

[0115] 139 Dielectric Ring

[0116] 139a Dielectric Ring

[0117] 139a1 Page 1

[0118] 139a2 Page 2

[0119] 139a3 Page 3

[0120] 139a3′ Page 3

[0121] 139b Thin Film Electrode

[0122] 139b1 Part 1

[0123] 139b2 Part 2

[0124] 139b3 Part 3

[0125] 139b3′ Part 3

[0126] 139bie inner peripheral end

[0127] 139boe Peripheral end

[0128] 140 Dielectric Film

[0129] 150 Insulation Board

[0130] 151 Ground Plate

[0131] 152 Refrigerant flow path

[0132] 160 Electric field / magnetic field forming unit

[0133] 170 controller.

Claims

1. A plasma processing device, characterized in that: have: (a) a sample stage disposed in a plasma-forming processing chamber in a vacuum processing apparatus, comprising a cylindrical protrusion having a first circular shape in a plan view and having a mounting surface on which a semiconductor wafer to be processed is mounted; (b) a dielectric ring disposed in an outer peripheral region of the sample stage so as to surround the protrusion, the dielectric ring including a ring-shaped thin film electrode having an inner peripheral end and an outer peripheral end in a plan view and supplied with high frequency power during processing of the semiconductor wafer; and (c) a base ring, which is mounted on the dielectric ring and covers the thin film electrode and is made of dielectric. The semiconductor wafer includes: a main surface and a back surface having a second circular shape in a plan view; and an end portion as a circumferential portion of the main surface. The first radius of the first circle is smaller than the second radius of the second circle, The thin film electrode includes: a first portion constituting the inner peripheral end and located at a position lower than the back surface of the semiconductor wafer; and a flat second portion arranged on the outer peripheral side of the first portion and located at a position higher than the main surface of the semiconductor wafer. and a third portion connecting the outer peripheral edge portion of the first portion and the inner peripheral edge portion of the second portion, The first portion of the thin film electrode has an overlapping region overlapping the semiconductor wafer when viewed from above. The base ring comprises: an inner peripheral end located below the end of the semiconductor chip when viewed from above when the semiconductor chip is placed on the mounting surface and covers the first part of the thin film electrode, an outer peripheral portion that is flat and covers the upper surface of the second part, and a portion that connects the inner peripheral end and the outer peripheral portion as a whole to cover the second part and constitute a step.

2. The plasma processing device according to claim 1, characterized in that: The overlapping region extends over the entire circumference of the semiconductor wafer.

3. The plasma processing device according to claim 1, characterized in that: The inner peripheral end of the thin-film electrode has a third circular shape with a third radius in a plan view, and the third radius is larger than the first radius and smaller than the second radius.

4. The plasma processing device according to claim 1, characterized in that: The plasma processing device comprises: A high-frequency power supply supplies high-frequency power to the sample stage.

5. The plasma processing device according to claim 4, characterized in that: The sample stage includes: a conductive electrode substrate electrically connected to the high-frequency power source; and a dielectric film disposed on the electrode substrate. The upper surface of the dielectric film constitutes the mounting surface.

6. The plasma processing device according to claim 4, characterized in that: The high-frequency power source supplies high-frequency power to the sample stage and the thin-film electrode.

7. The plasma processing device according to claim 5, characterized in that: The dielectric film includes a conductive film inside the dielectric film. The high-frequency power is supplied to the conductor film from the high-frequency power supply.

8. The plasma processing device according to claim 1, characterized in that: A first distance in a vertical direction between the back surface of the semiconductor wafer and the first portion of the thin-film electrode is smaller than a second distance in a horizontal direction between the end portion of the semiconductor wafer and the third portion of the thin-film electrode.

9. The plasma processing device according to claim 8, characterized in that: An upper surface of a portion of the susceptor ring that forms the step between the third portion of the thin-film electrode and the end portion of the semiconductor wafer forms an inclined surface whose height increases from the inner peripheral end toward the outer peripheral portion.

10. The plasma processing device according to claim 1, characterized in that: The first portion and the second portion of the thin film electrode have horizontal surfaces parallel to the main surface of the semiconductor wafer. The third portion of the thin-film electrode includes a vertical surface that is orthogonal to the main surface of the semiconductor wafer.

11. The plasma processing device according to claim 1, characterized in that: The first portion and the second portion of the thin film electrode have horizontal surfaces parallel to the main surface of the semiconductor wafer. The third portion of the thin-film electrode has an inclination approaching the sample stage along a vertical direction.

12. A plasma processing method for processing a semiconductor wafer in a processing chamber of a plasma processing device, characterized in that: The plasma processing device comprises: A sample stage is disposed in a plasma-forming processing chamber in a vacuum processing device, and includes a cylindrical convex portion having a mounting surface on which a semiconductor wafer to be processed is mounted; a dielectric ring disposed in an outer peripheral region of the sample stage so as to surround the protrusion, and including a ring-shaped thin film electrode having an inner peripheral end and an outer peripheral end in a plan view and supplied with high-frequency power during processing of the semiconductor wafer; a base ring, which is mounted on the dielectric ring, covers the thin film electrode and is made of dielectric; and High frequency power supply, The plasma treatment method comprises the following steps: The semiconductor wafer having a main surface and a back surface is placed on the sample stage; and performing plasma treatment on the main surface of the semiconductor wafer, The thin film electrode comprises: a first portion constituting the inner peripheral end and located at a position lower than the back surface of the semiconductor wafer; and a flat second portion arranged on the outer peripheral side of the first portion and located at a position higher than the main surface of the semiconductor wafer; and a third portion connecting the outer peripheral edge portion of the first portion and the inner peripheral edge portion of the second portion, The first portion of the thin film electrode has an overlapping region overlapping the semiconductor wafer when viewed from above. The base ring comprises: an inner peripheral end located below the end of the semiconductor wafer in a plan view when the semiconductor wafer is placed on the mounting surface while covering the first portion of the thin film electrode, an outer peripheral portion covering the flat upper surface of the second portion, and a portion that connects the inner peripheral end and the outer peripheral portion as a whole, covers the second portion, and forms a step. In the step of performing plasma processing on the main surface of the semiconductor wafer, high-frequency power is supplied from the high-frequency power supply to the thin-film electrode.

13. The plasma processing method according to claim 12, characterized in that: The main surface and the back surface of the semiconductor wafer have circular shapes, The overlapping region extends over the entire circumference of the semiconductor wafer.

14. The plasma processing method according to claim 12, characterized in that: A first distance in a vertical direction between the back surface of the semiconductor wafer and the first portion of the thin-film electrode is smaller than a second distance in a horizontal direction between the end portion of the semiconductor wafer and the third portion of the thin-film electrode.

15. The plasma processing method according to claim 12, characterized in that: In the step of performing plasma processing on the main surface of the semiconductor wafer, high frequency power is supplied to the sample stage.

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