Nanoplate transistors with asymmetric gate stacks

Abstract

Methods and resulting structures of nanosheet devices with asymmetric gate stacks are disclosed. A nanosheet stack (102) is formed on a substrate (104). The nanosheet stack (102) includes alternating semiconductor layers (108) and sacrificial layers (110). A sacrificial liner (202) is formed on the nanosheet stack (102), and a dielectric gate structure (204) is formed on the nanosheet stack (102) and on the sacrificial liner (202). First inner spacers (302) are formed on sidewalls of the sacrificial layers (110). Gates (112) are formed on channel regions of the nanosheet stack (102). The gates (112) include conductive bridges that extend on the substrate (104) in a direction orthogonal to the nanosheet stack (102). Second inner spacers (902) are formed on sidewalls of the gates (112). The first inner spacers (302) are formed before the gate (112) stack, and the second inner spacers (902) are formed after the gate stack, thus the gate (112) stack is asymmetric.

Description

BACKGROUND

[0001] The present invention relates generally to methods of fabrication and resulting structures for semiconductor devices, and more specifically, to improved processes and resulting structures for nanosheet transistors with asymmetric gate stacks.

[0002] Known metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication techniques include a process flow for constructing a planar field-effect transistor (FET). A planar FET includes a substrate (also referred to as a silicon plate), a gate formed on the substrate, source and drain regions formed on opposite ends of the gate, and a channel region located near the surface of the substrate beneath the gate. The channel region electrically connects the source region to the drain region, while the gate controls the current in the channel. The gate voltage controls whether the path from the drain to the source is an open circuit (“off”) or a resistive path (“on”).

[0003] In recent years, research has been directed toward the development of non-planar transistor architectures. For example, nanosheet FETs include a non-planar structure that provides increased device density and some increased performance over lateral devices. In a nanosheet FET, the channel is implemented as multiple stacked and spaced-apart nanosheets compared to a conventional planar FET. A gate stack surrounds the entire perimeter of each nanosheet, thus enabling more complete depletion in the channel region and also reducing short channel effects due to steeper subthreshold swing (SS) and smaller drain-induced barrier lowering (DIBL). SUMMARY

[0004] Embodiments of the present invention relate to a method for forming a nanosheet device with asymmetric gate stacks. A non-limiting example of the method includes forming a nanosheet stack on a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed on the nanosheet stack, and a dielectric gate structure is formed on the nanosheet stack and on the sacrificial liner. First inner spacers are formed on sidewalls of the sacrificial layers. The method includes forming a gate over a channel region of the nanosheet stack. The gate includes a conductive bridge extending on the substrate in a direction orthogonal to the nanosheet stack. Second inner spacers are formed on sidewalls of the gate. The gate stack is asymmetric.

[0005] Embodiments of the invention relate to a semiconductor structure. A non-limiting example of the semiconductor structure includes a nanosheet stack on a substrate and a gate over a channel region of the nanosheet stack. The gate includes a conductive bridge extending over the substrate in a direction orthogonal to the nanosheet stack. A dielectric gate structure is located over the nanosheet stack and the gate. A first inner spacer is located at a first end of the nanosheet stack and a second inner spacer is located at a second end of the nanosheet stack. The first inner spacer and the second inner spacer are formed during different parts of a workflow (one before the gate stack and the other after the gate stack), and as a result, the gate stack is asymmetric. The gate dielectric extends between the first inner spacer and the gate but does not extend between the second inner spacer and the gate.

[0006] Embodiments of the invention relate to a method for forming a nanosheet device with an asymmetric gate stack. A non-limiting example of the method includes forming a nanosheet stack on a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A spacer layer is formed on sidewalls of the nanosheet stack and a first dielectric gate structure is formed on the substrate and on sidewalls of the spacer layer. The method includes forming a sacrificial liner on the first dielectric gate structure and forming a second dielectric gate structure on the sacrificial liner. The sacrificial layers, the spacer layer, and the sacrificial liner are replaced with a gate. The gate includes a conductive bridge located between the first dielectric gate structure and the second dielectric gate structure.

[0007] Embodiments of the invention relate to a semiconductor structure. A non-limiting example of the semiconductor structure includes a nanosheet stack on a substrate. A first dielectric gate structure is located on the substrate. A gate is over a channel region of the nanosheet stack. The gate includes a conductive bridge extending over the substrate in a direction orthogonal to the nanosheet stack. The conductive bridge is located on a surface of the first dielectric gate structure. A second dielectric gate structure is on the conductive bridge.

[0008] Embodiments of the invention relate to a semiconductor structure. A non-limiting example of the semiconductor structure includes a first nanosheet stack on a substrate. A second nanosheet stack is located on the substrate and adjacent to the first nanosheet stack. The structure also includes a first dielectric gate structure on the substrate. The first dielectric gate structure is between the first nanosheet stack and the second nanosheet stack. The structure includes a gate having a first portion and a second portion. The first portion is over a channel region of the first nanosheet stack and the second portion is over a channel region of the second nanosheet stack. The gate includes a conductive bridge located between the first portion and the second portion. The conductive bridge is located on a surface of the first dielectric gate structure. A second dielectric gate structure is on the conductive bridge.

[0009] Additional technical features and benefits are realized through the techniques of the present application. Embodiments and aspects of the application are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] The specifics of the exclusive right described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the application are apparent from the following detailed descriptions, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A top view reference drawing is shown, along with cross-sectional views of the semiconductor structure along lines X and Y1 of the reference drawing, after an initial set of processing operations, in accordance with one or more embodiments of the application;

[0012] Figure 2 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0013] Figure 3 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0014] Figure 4 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0015] Figure 5 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0016] Figure 6 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0017] Figure 7 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0018] Figure 8 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0019] Figure 9 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0020] Figure 10 A cross-sectional view of a semiconductor structure along lines X and Y1 of a reference view is shown, in accordance with one or more embodiments of the application;

[0021] Figure 11 shows a cross-sectional view of the semiconductor structure along line Y2 of the reference view according to one or more embodiments of the application;

[0022] Figure 12 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view after an initial set of processing operations according to one or more embodiments of the application;

[0023] Figure 13 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0024] Figure 14 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0025] Figure 15 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0026] Figure 16 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0027] Figure 17 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0028] Figure 18 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0029] Figure 19 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0030] Figure 20 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0031] Figure 21 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0032] Figure 22 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0033] Figure 23 shows a cross-sectional view of the semiconductor structure along lines X and Yl of the reference view according to one or more embodiments of the application;

[0034] Figure 24 A flow diagram illustrating a method in accordance with one or more embodiments of the application is shown; and

[0035] Figure 25 A flow diagram illustrating a method in accordance with one or more embodiments of the application is shown.

[0036] The diagrams depicted herein are illustrative. Variations in the diagrams or operations described can be made in light of the above detailed description. For example, elements can be added or removed from the diagrams, or the order of the operations can be changed.

[0037] In the drawings and the following detailed description of embodiments of the application, various elements are numbered across the several drawings to aid in describing the drawings. Every effort has been made to consistently follow the San Francisco Bay Area Consensus (S.F.B.A.C.) for drawing numbering, but some variations can exist. DETAILED DESCRIPTION

[0038] It is to be understood in advance that, although the example embodiments of the application are described in relation to a specific transistor architecture, embodiments of the application are not limited to the specific transistor architecture or materials described in this specification. Rather, embodiments of the application are capable of being implemented in relation to any other type of transistor architecture or materials now known or later developed.

[0039] For the sake of brevity, conventional techniques related to semiconductor devices and integrated circuit (IC) fabrication can or can not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known and so have been omitted or described in a simple manner. For example, formation of known structures can be omitted or described in a simple manner.

[0040] Turning now to an overview of the technology more specifically related to aspects of the application, there are several candidates for scaling non-planar transistors beyond the 4nm node, but each is currently limited for various reasons.

[0041] One candidate is the nanosheet transistor structure. Nanosheets are able to maintain DC performance due to sufficient effective gate width, but AC performance is difficult due to relatively large parasitic capacitance between the source / drain contacts and the gate. Cell height scaling is another issue, due to gate stack patterning challenges associated with high nanosheet stacks. However, high nanosheet stacks are desirable because they provide the same effective length at a smaller footprint, directly enabling area scaling.

[0042] Turning now to an overview of aspects of the present application, one or more embodiments of the present application address the above-mentioned shortcomings of known nanosheet structures and fabrication techniques by providing a new nanosheet structure having an asymmetric gate stack, and a method of fabricating the nanosheet structure that addresses the above-mentioned difficulties of nanosheet, vertical transport field effect transistor (VTFET), and complementary field effect transistor (CFET) fabrication. The new nanosheet structure provides, according to embodiments of the present application, a high-k metal gate (HKMG) around a channel of a stack; a dielectric gate structure around the HKMG; an electrically conductive bridge connecting shared gate devices; and an asymmetric high-k dielectric film formed on an inner spacer.

[0043] The nanosheet structure formed in this way provides several technical benefits. Effective gate width scaling is relatively easy, and is already possible for 3nm, 2nm, and lnm nodes. The dielectric gate structure provides improved mechanical stability for the HKMG, allowing the number of nanosheets in the stack to be increased without introducing stability issues. Increasing the number of nanosheets directly increases the effective gate width. Capacitance is as good as a VTFET (similarly, the capacitance between the gate and source / drain epitaxy only is appreciable, the capacitance between the gate to silicide or gate to contact is minimal), because the amount of gate metal is minimal, there is no wasted gate metal that can be an additional source of parasitic gate to source / drain capacitance. Cell size scaling is better than nanosheet or VTFET, and is easily scaled to 3nm, 2nm, and lnm nodes. Process complexity is much easier than VTFET and CFET. Process control is much better than VTFET or CFET.

[0044] Turning now to a more detailed description of the fabrication operations and resulting structures according to aspects of the present application, Figures 1-11 A semiconductor structure 100 is depicted after various fabrication operations according to aspects of the present application. Although Figures 1-11 The cross-sectional views shown in Figs. 1-3 are two-dimensional, but it should be understood that Figures 1-11 The figures shown in Figs. 1-3 represent three-dimensional structures. Figure 1 The top-down reference view 101 shown in Fig. 1 provides a reference point for the various cross-sectional views: Figures 1-11 An X view (through the gate in the channel region), a Yl view (along the gate in the channel region), and a Y2 view (along the gate in the source / drain region) are shown in Figs. 2-3.

[0045] Figure 1 Cross-sectional views of a semiconductor structure 100 taken along lines X and Yl of the reference figure 101 after an initial set of fabrication operations have been applied as part of a method of fabricating a final semiconductor device according to one or more embodiments of the present application are depicted. In some implementations of the present application, one or more nanosheet stacks 102 are formed on a substrate 104.

[0046] The substrate 104 can be made of any suitable substrate material, such as single crystalline Si, silicon germanium (SiGe), III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulator (SOI). For example, III-V compound semiconductors include materials having at least one element from Group III and at least one element from Group V, such as one or more of aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlInAs), aluminum nitride (AIN), gallium antimonide (GaSb), gallium aluminum antimonide (GaAlSb), gallium arsenide (GaAs), gallium arsenide antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and alloy combinations including at least one of the above materials. The alloy combinations can include binary (two elements, e.g., gallium arsenide (GaAs)), ternary (three elements, e.g., InGaAs), and quaternary (four elements, e.g., aluminum indium gallium phosphide (AlInGaP)) alloys.

[0047] In some embodiments of the application, the substrate 104 can include a buried oxide layer 106 of a silicon-on-insulator (SOI) structure. The buried oxide layer 106 can be made of any suitable dielectric material, such as silicon oxide. In some embodiments of the application, the buried oxide layer 106 is formed to a thickness of about 10-200 nm, although other thicknesses are within the contemplation of the application. In some embodiments of the application, the semiconductor structure 100 can also be formed without the buried oxide layer 106. In this case, STI (shallow trench isolation) will be formed to isolate devices from devices.

[0048] In some embodiments of the application, the nanosheet stack 102 can include one or more semiconductor layers 108 alternating with one or more sacrificial layers 110. In some embodiments of the application, the semiconductor layers 108 and the sacrificial layers 110 are epitaxially grown layers. For ease of discussion, reference is made to operations performed on and to the nanosheet stack having six nanosheet layers (e.g., Figure 1The six semiconductor layers 108) alternate with six sacrificial layers (e.g., six sacrificial layers 110). However, it should be appreciated that the nanosheet stack 102 can include any number of nanosheets alternating with a corresponding number of sacrificial layers. For example, the nanosheet stack 102 can include two nanosheets, five nanosheets, eight nanosheets, 30 nanosheets (e.g., 3D NAND), or any number of nanosheets, along with a corresponding number of sacrificial layers (i.e., appropriately to form a nanosheet stack having a bottommost sacrificial layer below a bottommost nanosheet and a sacrificial layer between each pair of adjacent nanosheets).

[0049] The semiconductor layers 108 can be made of any suitable material, such as monocrystalline silicon or silicon germanium. In some embodiments of the application, the semiconductor layers 108 are silicon nanosheets. In some embodiments of the application, the semiconductor layers 108 have a thickness of about 4 nm to about 10 nm, such as 6 nm, although other thicknesses are within the contemplation of the application. In some embodiments of the application, the substrate 104 and the semiconductor layers 108 can be made of the same semiconductor material. In other embodiments of the application, the substrate 104 can be made of a first semiconductor material, while the semiconductor layers 108 can be made of a second semiconductor material.

[0050] The sacrificial layers 110 can be silicon or silicon germanium layers, depending on the material of the semiconductor layers 108 to meet the etch selectivity requirements. For example, in embodiments where the semiconductor layers 108 are silicon nanosheets, the sacrificial layers 110 can be silicon germanium layers. In embodiments where the semiconductor layers 108 are silicon germanium nanosheets, the sacrificial layers 110 can be silicon germanium layers having a greater germanium concentration than the germanium concentration in the semiconductor layers 108. For example, if the semiconductor layers 108 are silicon germanium having a 5% germanium concentration (sometimes referred to as SiGe5), the sacrificial layers 110 can be silicon germanium layers having a germanium concentration of about 25% (SiGe25), although other germanium concentrations are within the contemplation of the application. In some embodiments of the application, the sacrificial layers 110 have a thickness of about 8 nm to about 15 nm, such as 10 nm, although other thicknesses are within the contemplation of the application.

[0051] As shown in cross-sectional view Yl, portions of the nanosheet stack 102 can be removed (exposing a surface of the buried oxide layer 106) to define a nanosheet stack width. In some embodiments of the application, the nanosheet stack 102 has a width of about 10-100 nm, although other widths are within the contemplation of the application.

[0052] Figure 2A cross-sectional view of semiconductor structure 100 along lines X and Yl of reference Figure 101 after processing operations in accordance with one or more embodiments of the present application is shown. In some embodiments of the present application, a sacrificial liner 202 is formed on nanosheet stack 102 and buried oxide layer 106. In some embodiments of the present application, sacrificial liner 202 is conformally deposited on nanosheet stack 102. In some embodiments of the present application, sacrificial liner 202 has a thickness greater than sacrificial layer 110, for example, from about 20 nm to about 60 nm, although other thicknesses are within the contemplation of the present application.

[0053] In some embodiments of the present application, sacrificial liner 202 is formed using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metalorganic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, molecular beam epitaxy (MBE), or other similar processes in combination with a wet or dry etching process. Sacrificial liner 202 can be made of any suitable sacrificial material, for example, silicon germanium (SiGe), although other sacrificial materials are within the contemplation of the present application.

[0054] As shown in cross-sectional view Yl, a dielectric gate structure 204 is formed on sacrificial liner 202. Dielectric gate structure 204 can be made of any suitable dielectric material, for example, a low-k dielectric (a material having a small dielectric constant relative to silicon dioxide, i.e., less than about 3.9), an ultra-low-k dielectric (a material having a dielectric constant less than 3.0), a porous silicate, a carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide (SiC), or other dielectric materials. Any known means of forming dielectric gate structure 204 can be used, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectric, or PVD. In some embodiments of the present application, semiconductor structure 100 is planarized using, for example, a chemical mechanical planarization (CMP) process.

[0055] Figure 3A cross-sectional view of the semiconductor structure 100 along lines X and Yl of FIG. 101 after processing operations in accordance with one or more embodiments of the application is shown. In some embodiments of the application, the nanosheet stack 102, the dielectric gate structure 204, and the sacrificial layer 202 are patterned to expose the surface of the buried oxide layer 106. The nanosheet stack 102, the dielectric gate structure 204, and the sacrificial layer 202 can be patterned using, for example, a wet etch, a dry etch, or a combination of wet and / or dry etching. In some embodiments of the application, the nanosheet stack 102 is patterned using RIE.

[0056] In some embodiments of the application, the sacrificial layer 110 can be recessed, and an inner spacer 302 can be formed on the recessed sidewalls of the sacrificial layer 110. For example, the sidewalls of the sacrificial layer 110 can be recessed to form cavities (not shown) in the nanosheet stack 102. In some embodiments of the application, the inner spacer 302 is formed on the recessed sidewalls of the sacrificial layer 110 by filling these cavities with a dielectric material. In some embodiments of the application, portions of the inner spacer 302 that extend beyond the sidewalls of the nanosheet stack 102 are removed, for example, by an isotropic etching process. In this manner, the sidewalls of the inner spacer 302 are coplanar with the sidewalls of the semiconductor layer 108. In some embodiments of the application, the inner spacer 302 is formed using CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes in combination with a wet or dry etching process. The inner spacer 302 can be made of any suitable material, for example, a low-k dielectric, nitride, silicon nitride, silicon dioxide, SiON, SiC, SiOCN, or SiBCN.

[0057] Figure 4 A cross-sectional view of the semiconductor structure 100 along lines X and Yl of FIG. 101 after processing operations in accordance with one or more embodiments of the application is shown. In some embodiments of the application, source and drain regions 402 are formed on the exposed sidewalls of the semiconductor layer 108. The source and drain regions 402 can be epitaxially grown using, for example, vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. The source and drain regions 402 can be semiconductor materials epitaxially grown from gaseous or liquid precursors.

[0058] In some embodiments of the present application, the gas sources for epitaxial deposition of semiconductor materials include silicon-containing gas sources, germanium- containing gas sources, or combinations thereof. For example, a silicon layer can be epitaxially deposited (or grown) from a silicon gas source selected from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethylethylsilane, hexamethyldisilane, and combinations thereof. A germanium layer can be epitaxially deposited from a germanium gas source selected from germane, digermane, halogenated germane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Silicon-germanium alloy layers can be epitaxially formed using combinations of these gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. In some embodiments of the present application, the epitaxial semiconductor material includes carbon-doped silicon (Si:C). The Si:C layer can be grown in the same chamber used for other epitaxial steps, or in a dedicated Si:C epitaxial chamber. The Si:C can include carbon in the range of about 0.2% to about 3.0%.

[0059] Epitaxially grown silicon and silicon germanium can be doped by adding n-type dopants (e.g., P or As) or P-type dopants (e.g., Ga, B, BF2, or Al). In some embodiments of the present application, the source and drain regions 402 can be formed epitaxially and doped by various methods, such as in-situ doped epitaxy (doping during deposition), post-epitaxy doping, or by implantation and plasma doping. The dopant concentration in the doped region can be in the range of 1 x 1018cm-3to 2 x 1020cm-3, or between 1 x 1019cm-3and 1 x 1020cm-3. 19 cm -3 21 cm -3 20 cm -3 21 cm -3

[0060] In some embodiments of the present application, the source and drain regions 402 are made of silicon or silicon germanium. In some embodiments of the present application, the source and drain regions 402 are made of silicon germanium doped with boron, at a boron concentration of about 1% to about 15%, such as 2%, although other boron concentrations are within the contemplated scope of the present application.

[0061] In some embodiments of the present application, an interlayer dielectric (ILD) 404 is formed over the source and drain regions 402. The ILD 404 can be made of any suitable dielectric material, such as an oxide, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN. In some embodiments of the present application, the ILD 404 is deposited over the semiconductor structure 100, and then the semiconductor structure 100 is planarized using, for example, CMP.

[0062] Figure 5 ​​​​A cross-sectional view of the semiconductor structure 100 along lines X and Yl of FIG. 101 after processing operations in accordance with one or more embodiments of the application is shown. In some embodiments of the application, a gate cut 502 is formed by removing portions of the dielectric gate structure 204 and the sacrificial liner 202 to define a trench (not shown) that exposes a surface of the buried oxide layer 106. The trench is then filled with a dielectric material, such as a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN.

[0063] In some embodiments of the application, the dielectric gate structure 204 is recessed to expose sidewalls of the ILD 404. In some embodiments of the application, a spacer layer 504 is formed on the recessed surface of the dielectric gate structure 204. The spacer layer 504 can be made of any suitable dielectric material, such as a low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN. In some embodiments of the application, the spacer layer 504 is a conformal layer deposited on the semiconductor structure 100, followed by an anisotropic etch. The width of the spacer layer 504 will later define the gate length of the transistor.

[0064] As Figure 5 As further shown, portions of the sacrificial liner 202, the sacrificial layer 108, the sacrificial layer 110, and the dielectric gate structure 204 (sometimes referred to as a stack recess) can be removed to define a gate patterned trench 506 that exposes a surface of the buried oxide layer 106. The patterning can be achieved using, for example, a wet etch, a dry etch, or a combination of wet and / or dry etching. In some embodiments of the application, the semiconductor structure 100 is patterned using RIE.

[0065] Figure 6 A cross-sectional view of the semiconductor structure 100 along lines X and Yl of FIG. 101 after processing operations in accordance with one or more embodiments of the application is shown. In some embodiments of the application, the sacrificial liner 202 and the sacrificial layer 110 can be removed to form a cavity 602 that releases the semiconductor layer 108 (once released, the semiconductor layer 108 is often referred to as a nanosheet). The sacrificial liner 202 and the sacrificial layer 110 can be selectively removed with respect to the semiconductor layer 108. For example, when the semiconductor layer 108 is formed of silicon and the sacrificial liner 202 and the sacrificial layer 110 are formed of SiGe, SiGe can be selectively removed with respect to silicon using, for example, carboxylic acid / nitric acid / HF chemistry, citric acid / nitric acid / HF, and vapor phase HC1. In another example, when the semiconductor layer 108 is formed of SiGe and the sacrificial liner 202 and the sacrificial layer 110 are formed of silicon, silicon can be selectively removed with respect to SiGe using, for example, hydroxide aqueous solution chemistry including ammonium hydroxide and potassium hydroxide.

[0066] Figure 7 A cross-sectional view of the semiconductor structure 100 along lines X and Yl of reference view 101 after processing operations in accordance with one or more embodiments of the present application is shown. In some embodiments of the present application, the gate 112 (first shown in Figure 1 is formed in the cavity 602.

[0067] The gate 112 can be a high-k metal gate (HKMG) formed over a channel region of the nanosheet stack 102. The gate 112 can be referred to as a metal gate or a conductive gate. As used herein, a "channel region" refers to a portion of the semiconductor layer 108 over which the gate 112 is formed and through which current passes in the final device from the source to the drain. In some embodiments of the present application, the gate 112 is formed by depositing a high-k / metal gate material into the cavity 602 (shown in Figure 6 ).

[0068] In some embodiments of the present application, the gate 112 can include a gate dielectric 702 and a work function metal stack (not shown separately). In some embodiments, the gate 112 includes a body formed of a bulk conductive gate material.

[0069] In some embodiments of the present application, the gate dielectric 702 is a high-k dielectric film formed on an exposed surface of the semiconductor structure 100. In some embodiments of the present application, the high-k dielectric film is conformally deposited on the semiconductor structure 100. The high-k dielectric film can be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, a high-k material, or any combination of these materials. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material can further include dopants such as lanthanum and aluminum. In some embodiments of the present application, the high-k dielectric film can have a thickness of about 0.5 nm to about 4 nm. In some embodiments of the present application, the high-k dielectric film includes hafnium oxide and has a thickness of about 1 nm, although other thicknesses are within the contemplation of the present application. In some embodiments of the present application, after the gate dielectric 702 is deposited, the semiconductor structure 100 undergoes a reliability anneal.

[0070] In some embodiments of the application, the gate 112 includes one or more work function layers (sometimes referred to as work function metal stacks) formed on the gate dielectric 702 (if present, between the bulk gate material). In some embodiments of the application, the gate 112 includes one or more work function layers but does not include a bulk gate material. If present, the work function layers can be made of, for example, aluminum, lanthanum oxide, magnesium oxide, strontium titanate, strontium oxide, titanium nitride, tantalum nitride, hafnium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium silicon nitride, titanium aluminum nitride, tantalum silicon nitride, titanium aluminum carbide, tantalum carbide, and combinations thereof. The work function layers can be used to modify the work function of the gate 112 and enable adjustment of the device threshold voltage. The work function layers can be formed to a thickness of about 0.5 to 6 nm, although other thicknesses are within the contemplation of the application. In some embodiments of the application, each work function layer can be formed to a different thickness. In some embodiments of the application, the work function layers include a TiN / TiC / TiCAI stack.

[0071] In some embodiments, the gate 112 includes a body formed of a bulk conductive gate material deposited on the work function layers and / or the gate dielectric. The bulk gate material can include any suitable conductive material, such as a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), a conductive metal compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), conductive carbon, graphene, or any suitable combination of these materials. The conductive gate material can also include dopants incorporated during or after deposition.

[0072] As Figure 7 Further depicted in FIG. 1C, the work function layers and the body of the gate 112 can be recessed to define inner spacer cavities 704. In some embodiments of the application, the inner spacer cavities 704 are formed by laterally etching the work function layers and / or the body of the gate 112 selectively to the gate dielectric 702.

[0073] Figure 8 A cross-sectional view of the semiconductor structure 100 along lines X and Yl of FIG. 101 after a processing operation is shown in accordance with one or more embodiments of the application. In some embodiments of the application, exposed portions of the gate dielectric 702 are removed to expose portions of the semiconductor layer 108 as well as the surface of the buried oxide layer 106 and the dielectric gate structure 204. The gate dielectric 702 can be removed using any appropriate process, such as a wet etch, a dry etch, or a combination of wet and / or dry etching. In some embodiments of the application, the gate dielectric 702 is removed selectively to the semiconductor layer 108.

[0074] Figure 9The diagram shows a cross-sectional view of a semiconductor structure 100 according to one or more embodiments of the present invention along lines X and Y1 of FIG1 after processing operations. In some embodiments of the invention, an inner spacer cavity 704 is filled with a dielectric material to define an inner spacer 902. The inner spacer 902 may be made of a similar material to the inner spacer 302 and formed in a similar manner. In some embodiments of the invention, source and drain regions 904 are formed adjacent to the inner spacer 902. The source and drain regions 904 may be made of a similar material to the source and drain regions 402 and formed in a similar manner.

[0075] like Figure 9 As shown, inner spacer 902 and inner spacer 302 (e.g. Figure 3 (As shown) are formed separately. Specifically, the width of the inner spacer 902 is defined by the recess depth of the work function layer and the body of the gate 112 (when defining the inner spacer cavity 702), while the width of the inner spacer 302 is defined by the recess depth of the sacrificial layer 110 (when defining the cavity for the inner spacer 302). Note that the gate dielectric 702 is deposited on the inner spacer 302 because the inner spacer 302 is formed prior to the deposition of the gate dielectric 702 and is exposed during deposition (see...). Figure 7 However, the gate dielectric 702 is not formed over the inner spacer 902 because the inner spacer 902 is formed after the high-k / metal gate recess (see...). Figure 8 Therefore, the shape of the replacement gate stack 112 (a combination of gate dielectric 702 and work function metal) is asymmetrical.

[0076] Figure 10 The diagram shows a cross-sectional view of a semiconductor structure 100 according to one or more embodiments of the present invention along lines X and Y1 of reference FIG1 after a processing operation. In some embodiments of the invention, the spacer 504 may be removed, followed by additional ILD deposition and planarization, such as... Figure 10 The ILD 404 shown is extended.

[0077] In some embodiments of the invention, portions of the isolation dielectric 404 and the dielectric gate structure 204 are removed (patterned) to form source / drain contact trenches (not shown) and gate contact trenches (not shown). In some embodiments of the invention, the source / drain contact trenches expose the surfaces of the source and drain regions 402 and 904, and the gate contact trenches expose the surface of the gate 112. The isolation dielectric 404 and the dielectric gate structure 204 can be patterned using wet etching, dry etching, or a combination of sequential wet and / or dry etching.

[0078] In some embodiments of the application, the source / drain contacts 1002 are formed or deposited in the source / drain contact trenches, and the gate contacts 1004 are formed or deposited in the gate trenches. The source / drain contacts 1002 and the gate contacts 1004 can be formed of a material including copper or non-copper metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, aluminum, platinum), alloys thereof, conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, cobalt silicide, nickel silicide), conductive carbon, or any suitable combination of these materials. In some embodiments of the application, the source / drain contacts 1002 and the gate contacts 1004 are formed of the same conductive material, such as cobalt, copper, ruthenium, or tungsten. In some embodiments of the application, the source / drain contacts 1002 and the gate contacts 1004 are made of different conductive materials. For example, the source / drain contacts 1002 can be made of cobalt or ruthenium, and the gate contacts 1004 can be made of copper, or vice versa. In some embodiments of the application, the source / drain contacts 1002 and the gate contacts 1004 each include a barrier liner (sometimes referred to as a metal liner or barrier metal liner) to prevent diffusion into surrounding dielectrics (not shown).

[0079] Figure 11 Cross-sectional views of semiconductor structures 1100 and 1102, respectively, according to one or more embodiments of the application, are shown after processing operations along line Y2 (along the gate in the source / drain region) of FIG. 101. The semiconductor structure 1100 depicts a first embodiment of the interface between the source / drain contacts 1002 and the source and drain regions 904 discussed earlier with respect to the semiconductor structure 100.

[0080] As Figure 11 shown for the semiconductor structure 1100, in some embodiments of the application, the source and drain regions 904 are relatively wide (large), and the source / drain contacts 1002 extend into the top portions of the source and drain regions 904. Advantageously, the presence of the dielectric gate structure 204 (shown in the Yl cut of Figure 10 alleviates parasitic capacitance between the large source and drain regions 904 and the gate 112.

[0081] As Figure 11 shown for the semiconductor structure 1102, in some embodiments of the application, the source and drain regions 904 are relatively small, while the source / drain contacts 1002 are relatively large, extending over the sidewalls of the source and drain regions 904. Advantageously, the presence of the dielectric gate structure 204 (shown in the Yl cut of Figure 10 alleviates parasitic capacitance between the large source / drain contacts 1002 and the gate 112.

[0082] Figures 12-23 A cross-sectional view of semiconductor structure 1200 taken along lines X and Yl of FIG. 101 after processing operations in accordance with one or more embodiments of the application is shown. Semiconductor structure 1200 illustrates an alternative embodiment of semiconductor structure 100 shown in FIG. 101. Figures 1-11 As previously described, semiconductor structure 100 can substantially reduce undesirable gate-to-silicide and gate-to-contact capacitance. For the gate structure shown in semiconductor structure 100 (see FIG. 101), one potential concern is an increase in gate resistance of the top sheet of the nanosheet stack 102 due to an increase in the distance between the conductive bridge (i.e., the portion of the gate 112 extending under the gate contact 1004, sometimes referred to as a metal liner bridge) and the portion of the body gate that surrounds the topmost nanosheet. The potential for an increase in gate resistance is even greater as the number of sheets in the nanosheet stack increases. Figure 10

[0083] The embodiment shown with respect to semiconductor structure 1200 addresses the potential problem of an increase in gate resistance by further reducing gate-to-silicide and gate-to-contact capacitance and by repositioning the conductive bridge to balance the gate resistance. In this configuration, one side of the nanosheet is anchored directly to the dielectric, and the metal bridge is elevated to a more central position with respect to the nanosheet stack.

[0084] Figure 12 A cross-sectional view of semiconductor structure 1200 taken along lines X and Yl of FIG. 101 after applying an initial set of fabrication operations as part of a method of fabricating a final semiconductor device in accordance with one or more embodiments of the application is shown. Semiconductor structure 1200 can include one or more nanosheet stacks 102 and a buried oxide layer 106 formed on a substrate 104, configured and arranged as shown. The nanosheet stacks 102, substrate 104, and buried oxide layer 106 can be formed in a similar manner as discussed with respect to semiconductor structure 100 shown in FIG. 101. Figure 1 In some embodiments of the application, a hard mask 1202 is patterned on semiconductor structure 1200, and portions of the nanosheet stacks 102 are removed to expose a surface of the buried oxide layer 106.

[0085] Figure 13 A cross-sectional view of semiconductor structure 1200 taken along lines X and Yl of FIG. 101 after processing operations in accordance with one or more embodiments of the application is shown. In some embodiments of the application, a spacer layer 1302 is formed on the sidewalls of the nanosheet stacks 102. In some embodiments of the application, the spacer layer 1302 is a semiconductor layer (e.g., SiGe) that is epitaxially grown from the exposed sidewalls of the sacrificial layer 110 in the nanosheet stacks 102.

[0086] As previously described, semiconductor structure 100 can substantially reduce undesirable gate-to-silicide and gate-to-contact capacitance. For the gate structure shown in semiconductor structure 100 (see FIG. 101), one potential concern is an increase in gate resistance of the top sheet of the nanosheet stack 102 due to an increase in the distance between the conductive bridge (i.e., the portion of the gate 112 extending under the gate contact 1004, sometimes referred to as a metal liner bridge) and the portion of the body gate that surrounds the topmost nanosheet. The potential for an increase in gate resistance is even greater as the number of sheets in the nanosheet stack increases. Figure 13 ​Further shown, a first dielectric gate structure 1304 is formed on the buried oxide layer 106. In some embodiments of the application, the first dielectric gate structure 1304 is recessed to expose the sidewalls of the spacer layer 1302. The first dielectric gate structure 1304 can be made of any suitable dielectric material, such as oxide, low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN.

[0087] Figure 14 A cross-sectional view of the semiconductor structure 1200 along lines X and Yl of FIG. 101 after processing operations according to one or more embodiments of the application is shown. In some embodiments of the application, the spacer layer 1302 is recessed to the surface of the first dielectric gate structure 1304. The spacer layer 1302 can be recessed using, for example, wet etching, dry etching, or a combination of wet and / or dry etching. In some embodiments of the application, the spacer layer 1302 is recessed using isotropic etch-back (e.g., SiGe isotropic etch).

[0088] Figure 15 A cross-sectional view of the semiconductor structure 1200 along lines X and Yl of FIG. 101 after processing operations according to one or more embodiments of the application is shown. In some embodiments of the application, a sacrificial liner 1502 is formed on the sidewalls of the nanosheet stack 102 and on the surface of the first dielectric gate structure 1304. In some embodiments of the application, the sacrificial liner 1502 is a semiconductor layer (e.g., SiGe) deposited conformally on the semiconductor structure 1200, or a semiconductor layer epitaxially grown from the exposed sidewalls of the sacrificial layer 110 in the nanosheet stack 102.

[0089] Figure 16 A cross-sectional view of the semiconductor structure 1200 along lines X and Yl of FIG. 101 after processing operations according to one or more embodiments of the application is shown. In some embodiments of the application, an organic planarization layer (OPL) 1602 is formed on the sacrificial liner 1502.

[0090] In some embodiments, OPL 1602 may comprise a photosensitive organic polymer having a photosensitive material that is chemically altered when exposed to electromagnetic (EM) radiation and is therefore configured to be removed using a developing solvent. For example, the photosensitive organic polymer may be a polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). More generally, for example, OPL 1602 may comprise any organic polymer and a photoactive compound having a molecular structure that can be attached to the organic polymer. In some embodiments, the OPL 1602 material is selected to be compatible with an overlying antireflective coating (not shown) and / or an overlying photoresist (not shown). In some embodiments, OPL 1602 may be applied using a spin-coating technique, although other techniques are within the scope of this invention.

[0091] like Figure 16 As shown by line Y1, the OPL 1602 can be recessed using, for example, dry etching or a combination of sequential dry and / or wet etching. In some embodiments of the invention, the sacrificial liner 1502 is chamfered to the recessed surface of the OPL 1602.

[0092] Figure 17 A cross-sectional view of a semiconductor structure 1200 according to one or more embodiments of the present invention is shown along lines X and Y1 of reference FIG1 after a processing operation. In some embodiments of the invention, the OPL 1602 is removed and replaced with a second dielectric gate structure 1702. The second dielectric gate structure 1702 may be made of any suitable dielectric material, such as oxide, low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN.

[0093] In some embodiments of the invention, an ashing process is used to remove OPL 1602, although other techniques such as wet or dry etching are also within the scope of the invention. In some embodiments of the invention, a second dielectric gate structure 1702 is formed on the sacrificial substrate 1502, and the semiconductor structure 1200 is planarized (e.g., using CMP) onto the surface of the hard mask 1202. In some embodiments of the invention, the hard mask 1202 is removed after planarization.

[0094] Figure 18The diagram shows a cross-sectional view of a semiconductor structure 1200 according to one or more embodiments of the present invention along lines X and Y1 of reference FIG1 after a processing operation. In some embodiments of the invention, spacers 1802 may be formed on the nanosheet stack 102. The spacers 1802 may be made of any suitable dielectric material, such as oxides, low-k dielectrics, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN.

[0095] In some embodiments of the invention, the spacers 1802 may be patterned and portions of the nanosheet stack 102 may be removed (exposing the surface of the buried oxide layer 106) to define the width of the nanosheet stack. In some embodiments of the invention, the width of the nanosheet stack 102 is about 20 nm, although other widths are also within the scope of the invention.

[0096] Figure 19 A cross-sectional view of a semiconductor structure 1200 according to one or more embodiments of the present invention is shown along lines X and Y1 of reference FIG1 after processing operations. In some embodiments of the invention, spacers 1802 are removed, and dielectric regions 1902 are formed on the semiconductor structure 1200. The dielectric regions 1902 can be made of any suitable dielectric material, such as oxides, low-k dielectrics, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN. In some embodiments of the invention, the semiconductor structure 1200 is planarized after the formation of the dielectric regions 1902.

[0097] Figure 20 A cross-sectional view of a semiconductor structure 1200 according to one or more embodiments of the present invention is shown along lines X and Y1 of reference FIG1 after a processing operation. In some embodiments of the invention, a portion of the nanosheet stack 102 is removed (sometimes referred to as gate core patterning), the sacrificial layer 110 may be recessed, and inner spacers 2002 may be formed on the recessed sidewalls of the sacrificial layer 110. In some embodiments of the invention, source and drain regions 2004 are formed on the exposed sidewalls of the semiconductor layer 108, and an isolation dielectric 2006 is formed on the source and drain regions 2004. This can be achieved with... Figure 3 and 4 The internal spacer 302, source and drain regions 402, and isolation dielectric 404 of the semiconductor structure 100 shown are formed in a similar manner to those discussed. The internal spacer 2002, source and drain regions 2004, and isolation dielectric 2006 are formed in a similar manner to those discussed.

[0098] Figure 21 A cross-sectional view of a semiconductor structure 1200 according to one or more embodiments of the present invention is shown along lines X and Y1 of reference FIG1 after a processing operation. In some embodiments of the invention, it is used in conjunction with, for example...Figure 5 The dielectric gate structure 204 and the spacer layer 504 are recessed, and a spacer layer 2102 is formed on the recessed surface of the dielectric gate structure 204, in a similar manner as discussed with respect to the dielectric gate structure 1902.

[0099] As shown in FIG. 10B, the dielectric gate structure 204 and the spacer layer 504 are recessed, and a spacer layer 2102 is formed on the recessed surface of the dielectric gate structure 204, in a similar manner as discussed with respect to the dielectric gate structure 1902. Figure 21 As further shown in FIG. 10B, portions of the spacer layer 2102, the semiconductor layer 108, the sacrificial layer 110, and the dielectric gate structure 1902 can be removed (sometimes referred to as stack recessing) to define a gate patterned trench 2104 that exposes a surface of the buried oxide layer 106. The patterning can be achieved using, for example, wet etching, dry etching, or a combination of wet and / or dry etching. In some embodiments of the application, the semiconductor structure 1200 is patterned using RIE.

[0100] Figure 22 A cross-sectional view of the semiconductor structure 1200 along lines X and Yl of FIG. 10A after processing operations in accordance with one or more embodiments of the application is shown. In some embodiments of the application, the sacrificial layer 110 can be removed to form a cavity 2202 that releases the semiconductor layer 108 (once released, the semiconductor layer 108 is often referred to as a nanosheet). The sacrificial layer 110 can be selectively removed with respect to the semiconductor layer 108. For example, when the semiconductor layer 108 is formed of silicon and the sacrificial liner 202 and the sacrificial layer 110 are formed of SiGe, SiGe can be selectively removed with respect to silicon using, for example, carboxylic acid / nitric acid / HF chemistry, citric acid / nitric acid / HF, and vapor phase HCl. In another example, when the semiconductor layer 108 is formed of SiGe and the sacrificial liner 202 and the sacrificial layer 110 are formed of silicon, silicon can be selectively removed with respect to SiGe using, for example, hydroxide aqueous solution chemistry including ammonium hydroxide and potassium hydroxide.

[0101] Figure 23 A cross-sectional view of the semiconductor structure 1200 along lines X and Yl of FIG. 10A after processing operations in accordance with one or more embodiments of the application is shown. In some embodiments of the application, the gate dielectric 2302, the gate 112, the inner spacer 2304, the source and drain regions 2306, the source / drain contacts 2308, and the gate contacts 2310 can be formed and arranged in a similar manner as discussed with respect to the gate dielectric 702, the gate 112, the inner spacer 902, the source and drain regions 904, the source / drain contacts 1002, and the gate contacts 1004 of the semiconductor structure 100 (as shown in FIG. 10B). Figures 7-10

[0102] Figure 24 ​A flowchart 2400 illustrating a method for forming a semiconductor device in accordance with one or more embodiments of the present application is shown. As represented by block 2402, a nanosheet stack is formed on a substrate. The nanosheet stack can include alternating semiconductor layers and sacrificial layers.

[0103] At block 2404, a sacrificial liner is formed over the nanosheet stack. At block 2406, a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. In some embodiments of the application, the dielectric gate structure is between the nanosheet stack and a gate contact.

[0104] At block 2408, a first inner spacer is formed on sidewalls of the sacrificial layers. In some embodiments of the application, forming the first inner spacer includes recessing the sacrificial layers.

[0105] At block 2410, a gate is formed over a channel region of the nanosheet stack. In some embodiments of the application, the gate includes a conductive bridge extending over the substrate in a direction orthogonal to the nanosheet stack. In some embodiments of the application, forming the gate includes removing a portion of the nanosheet stack and the dielectric gate structure to expose the sidewalls of the sacrificial layers. In some embodiments of the application, forming the gate further includes removing the sacrificial liner and the sacrificial layers.

[0106] In some embodiments of the application, forming the gate includes forming a gate dielectric, forming a conductive region over the gate dielectric, and removing an exposed portion of the gate dielectric. In some embodiments of the application, the gate dielectric extends between the first inner spacer and the gate but not between the second inner spacer and the gate. In other words, the gate dielectric is asymmetric. At block 2412, a second inner spacer is formed on sidewalls of the gate.

[0107] The method can further include forming a first source or drain region on sidewalls of the first inner spacer and a second source or drain region on sidewalls of the second inner spacer. In some embodiments of the application, a gate contact is formed on a surface of the conductive bridge.

[0108] Figure 25 A flowchart 2500 illustrating a method for forming a semiconductor device in accordance with one or more embodiments of the present application is shown. As represented by block 2502, a nanosheet stack is formed on a substrate. The nanosheet stack can include alternating semiconductor layers and sacrificial layers.

[0109] At block 2504, a spacer layer is formed on sidewalls of the nanosheet stack. At block 2506, a first dielectric gate structure is formed on the substrate and on sidewalls of the spacer layer. At block 2508, a sacrificial liner is formed on the first dielectric gate structure. At block 2510, a second dielectric gate structure is formed on the sacrificial liner.

[0110] At block 2512, the sacrificial layer, the spacer layer, and the sacrificial liner are replaced with a gate. In some embodiments of the invention, the gate includes a conductive bridge between the first dielectric gate structure and the second dielectric gate structure. In some embodiments of the invention, the conductive bridge is formed directly on a surface of the first dielectric gate structure. In some embodiments of the invention, the second dielectric gate structure is formed directly on the conductive bridge.

[0111] In some embodiments of the invention, the gate includes a gate dielectric that extends along the top surface, the bottom surface, and the first sidewall of the semiconductor layer, but does not extend along the second sidewall of the semiconductor layer. In other words, the gate dielectric asymmetrically covers the semiconductor layer (nanoplatelet), leaving one sidewall (surface) of the semiconductor layer uncovered.

[0112] The method can include forming a first inner spacer on a sidewall of the sacrificial layer and a second inner spacer on a sidewall of the gate. In some embodiments of the invention, a first source or drain region is formed on a sidewall of the first inner spacer and a second source or drain region is formed on a sidewall of the second inner spacer. In some embodiments of the invention, a gate contact is formed on a surface of the conductive bridge. In some embodiments of the invention, the gate contact extends through a portion of the second dielectric gate structure.

[0113] In some embodiments of the invention, the semiconductor device includes a second nanoplatelet stack positioned adjacent to the first nanoplatelet stack. In some embodiments of the invention, the gate is a shared gate having a first portion and a second portion. In some embodiments of the invention, the first portion is over a channel region of the first nanoplatelet stack and the second portion is over a channel region of the second nanoplatelet stack. In some embodiments of the invention, the gate includes a conductive bridge between the first portion and the second portion. In some embodiments of the invention, the conductive bridge is on a surface of the first dielectric gate structure. In some embodiments of the invention, the second dielectric gate structure is on the conductive bridge.

[0114] The methods described herein and the resulting structures can be used in the fabrication of IC chips. The fabricator can release the resulting IC chips in original wafer form (i.e., as a single wafer having many unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in single chip packages (e.g., with leads that are affixed to a motherboard or other higher level carrier) or in multi-chip packages (e.g., with a ceramic substrate with one or more layers of conductive material interposed between the substrate and the chips). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes IC chips, ranging from toys and other low-end applications to advanced computer

[0115] Various embodiments of the application are described herein with reference to the related drawings. Alternative embodiments of the application can be devised without departing from the scope of the application. Although various connections and positional relationships between elements are set forth in the following description and / or shown in the drawings, persons having ordinary skill in the art will realize that many modifications in these connections and positional relationships can be made without departing from the scope of the application. Accordingly, while the specific embodiments set forth in the description above and illustrated in the drawings are merely exemplary and not intended to be limiting, the scope of the application is commensurate with the claims. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the application pertains. The terminology used in the description is for describing particular embodiments only and is not intended to be limiting. As used in this application, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having," as used in this application, are intended to be inclusive (i.e., to mean either an "includes" or "including" or "has" or "having") and thus specify the presence of stated features, elements, components, or steps, but do not preclude the presence or addition of one or more other features, elements, components, steps, acts, objects, or parts. The terms "coupled" and "coupling," as used in this application, are intended to mean either an indirect or direct connection between elements in

[0116] The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains" or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, a process, a method, an article, or an apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0117] In addition, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e. one, two, three, four, etc. The term "a plurality" is understood to include any integer greater than or equal to two, i.e. two, three, four, five, etc. The term "connection" can include an indirect "connection" and a direct "connection."

[0118] Reference throughout this specification to "one embodiment," "an embodiment," "exemplary embodiment," etc. means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described or claimed.

[0119] For purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figure(s) in which the drawing figure(s) is / are assumed to be oriented upwards. The terms "over", "to over", "positioned over" or "positioned to over" mean that the first element, such as a first structure, is present on top of the second element, such as a second structure, wherein there can be intervening elements, such as an interface structure, present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intervening conductive, insulating, or semiconductive layer at the interface of the two elements.

[0120] For purposes of the description hereinafter, spatially relative terms, such as "below", "above", "upper", "lower", and the like, can be used for describing an element's relationship to another element as illustrated in the drawing figures. It is to be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawing figures. For example, if a device is inverted, then an element described as "below" or "beneath" another element would be oriented "above" or "over" the other element. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0121] The terms "about", "substantially", "approximately", and variations thereof, are intended to include the degree of error associated with measurements that naturally occur as part of using a particular device. For example, "about" can include a range of ± 8% or 5%, or 2% of a given value.

[0122] The phrase "selective to" such as "a first element is selective to a second element" means that the first element can be etched while the second element can act as an etch stop.

[0123] The term "conformal" (e.g., conformal layer or conformal deposition) means that the thickness of the layer is substantially the same across all surfaces, or the thickness varies by less than 15% of the nominal thickness of the layer.

[0124] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), where the grown semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material (seed material) of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by source gases can be controlled and system parameters can be set so that the depositing atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move across the surface so that the depositing atoms orient themselves to the crystalline arrangement of the atoms of the deposition surface. The epitaxially grown semiconductor material can have substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a <100> oriented crystalline surface can exhibit a <100> orientation. In some embodiments of the present application, the epitaxial growth and / or deposition process can be selective to form on a semiconductor surface and can or can not deposit material on other exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0125] As used herein, "p-type" refers to the addition of an impurity to an intrinsic semiconductor, which results in a lack of valence electrons. Examples of p-type dopants, i.e., impurities, in silicon-containing substrates include, but are not limited to: boron, aluminum, gallium, and indium.

[0126] As used herein, "n-type" refers to the addition of an impurity to an intrinsic semiconductor that contributes a free electron. Examples of n-type dopants, i.e., impurities, in silicon-containing substrates include, but are not limited to: antimony, arsenic, and phosphorus.

[0127] As previously described herein, for the sake of brevity, conventional techniques related to semiconductor devices and integrated circuit (IC) fabrication can or can not be described in detail herein. However, as background, a more general description of semiconductor device fabrication processes that can be used to implement one or more embodiments of the present application will now be provided. Although the specific fabrication operations used in implementing one or more embodiments of the present application can be individually known, the combination and / or the resulting structures of the described operations are unique. Thus, the unique combination of operations described in connection with the fabrication of semiconductor devices in accordance with the present application utilizes various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.

[0128] Generally, the various processes used to form the microchips that will be packaged into ICs are divided into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), and the like. For example, reactive ion etching (RIE) is a dry etching that uses a chemically reactive plasma to remove material, such as a masked pattern of semiconductor material, by exposing the material to ion bombardment that removes portions of the material from the exposed surface. The plasma is typically generated by an electromagnetic field under low pressure (vacuum). Semiconductor doping is the process of changing electrical properties by doping, such as transistor source and drain, typically by diffusion and / or by ion implantation. These doping processes are followed by furnace anneal or rapid thermal anneal (RTA). Annealing is used to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to change with the application of voltage. By forming structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate in order to subsequently transfer the pattern to the substrate. In semiconductor lithography, the pattern is formed from a light-sensitive polymer called photoresist. To construct the complex structures that make up the transistors and the many wiring of the millions of transistors that make up the circuit, the lithography and etch pattern transfer steps are repeated many times. Each pattern printed on the wafer is aligned with the previously formed pattern, and slowly the conductors, insulators, and selectively doped regions are built up to form the final device.

[0129] The flow diagrams and block diagrams in the drawings are illustrations of the possible implementations of the methods of manufacturing and / or operating in accordance with various embodiments of the present application. Various functions / operations in the methods are represented by blocks in the flow diagrams. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks noted in succession can, in some instances, actually be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved.

[0130] The description of the embodiments of the application herein is given for illustrative purposes only and is not intended to be exhaustive or to limit the embodiments described to the precise forms disclosed. Many modifications and variations will be apparent to those skilled in the art, without departing from the scope of the embodiments described. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments described herein.

[0131] In preferred embodiments of the application described herein, a method for forming a semiconductor device is provided, the method comprising: forming a nanosheet stack on a substrate, the nanosheet stack comprising alternating semiconductor layers and sacrificial layers; forming a spacer layer on sidewalls of the nanosheet stack; forming a first dielectric gate structure on the substrate and on sidewalls of the spacer layer; forming a sacrificial liner on the first dielectric gate structure; forming a second dielectric gate structure on the sacrificial liner; and replacing the sacrificial layers, the spacer layer, and the sacrificial liner with a gate comprising a conductive bridge between the first dielectric gate structure and the second dielectric gate structure. The method can further comprise forming a first inner spacer on sidewalls of the sacrificial layers. The method can also comprise forming a second inner spacer on sidewalls of the gate. The method can also comprise forming a first source or drain region on sidewalls of the first inner spacer and a second source or drain region on sidewalls of the second inner spacer. The method can also comprise forming a gate contact on a surface of the conductive bridge.

[0132] In preferred embodiments of the application described herein, a semiconductor device is provided, comprising: a nanosheet stack on a substrate, the nanosheet stack comprising semiconductor layers; a first dielectric gate structure on the substrate; a gate over a channel region of the nanosheet stack, the gate comprising a conductive bridge extending on the substrate in a direction orthogonal to the nanosheet stack, the conductive bridge on a surface of the first dielectric gate structure; and a second dielectric gate structure on the conductive bridge. The gate dielectric can extend along a top surface, a bottom surface, and a first sidewall of the semiconductor layers, but not along a second sidewall of the semiconductor layers. The device can also comprise a gate contact on a surface of the conductive bridge. The gate contact can extend through a portion of the second dielectric gate structure.

[0133] In a preferred embodiment of the invention described herein, a semiconductor device is provided, comprising: a first nanosheet stack on a substrate; a second nanosheet stack on the substrate; a first dielectric gate structure on the substrate, the first dielectric gate structure between the first nanosheet stack and the second nanosheet stack; a gate having a first portion on a channel region of the first nanosheet stack and a second portion on a channel region of the second nanosheet stack, the gate comprising a conductive bridge between the first portion and the second portion, the conductive bridge on a surface of the first dielectric gate structure; and a second dielectric gate structure on the conductive bridge. The gate dielectric can extend along a top surface, a bottom surface, and a first sidewall of a nanosheet of the first nanosheet stack, but not along a second sidewall of the nanosheet. The device can further comprise a gate contact on a surface of the conductive bridge. The gate contact can extend through a portion of the second dielectric gate structure.

Claims

1. A method for forming a semiconductor device, the method comprising: A nanosheet stack is formed on a substrate, the nanosheet stack comprising alternating semiconductor layers and sacrificial layers; A sacrificial liner is formed on the nanosheet stack; A dielectric gate structure is formed on the nanosheet stack and the sacrificial liner; A first inner spacer is formed on the sidewall of the sacrificial layer; A gate is formed on the channel region of the nanosheet stack, the gate including a conductive bridge extending on the substrate in a direction orthogonal to the nanosheet stack; as well as A second inner spacer is formed on the sidewall of the gate. The formation of the gate further includes forming a gate dielectric. The gate dielectric extends between the first inner spacer and the gate, but not between the second inner spacer and the gate.

2. The method according to claim 1, wherein, Forming the gate further includes removing a portion of the nanosheet stack and the dielectric gate structure to expose the sidewalls of the sacrificial layer.

3. The method of claim 2, wherein forming the gate further comprises: Remove the sacrificial liner and the sacrificial layer.

4. The method of claim 1, wherein forming the first inner spacer comprises: This causes the sacrificial layer to become concave.

5. The method of claim 1, wherein forming the gate further comprises: A conductive region is formed on the gate dielectric; as well as Remove the exposed portion of the gate dielectric.

6. The method according to claim 1, further comprising: A first source or drain region is formed on the sidewall of the first inner spacer, and a second source or drain region is formed on the sidewall of the second inner spacer.

7. The method of claim 1, further comprising: A gate contact is formed on the surface of the conductive bridge.

8. A semiconductor device, comprising: Nanosheet stacks on a substrate; A gate on the channel region of a nanosheet stack, the gate comprising a conductive bridge extending on the substrate in a direction orthogonal to the nanosheet stack; A dielectric gate structure on the nanosheet stack and the gate; The first inner spacer at the first end of the nanosheet stack; as well as The second inner spacer at the second end of the nanosheet stack; The gate dielectric extends between the first inner spacer and the gate, but not between the second inner spacer and the gate.

9. The semiconductor device according to claim 8, further comprising: The first source or drain region on the sidewall of the first inner spacer.

10. The semiconductor device according to claim 9, further comprising: The second source or drain region on the sidewall of the second inner spacer.

11. The semiconductor device according to claim 8, further comprising: Gate contacts on the surface of the conductive bridge.

12. The semiconductor device according to claim 11, wherein, The dielectric gate structure is located between the nanosheet stack and the gate contact.

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