Zero-crossing detection circuit, voltage conversion circuit and terminal equipment

Abstract

The present invention discloses a zero-crossing detection circuit, a voltage conversion circuit, and a terminal device. The zero-crossing detection circuit includes: a comparator module, a first input terminal of the comparator module is connected to a voltage to be detected, a second input terminal of the comparator module is connected to a reference voltage, an output terminal of the comparator module outputs a detection signal, the comparator module generates a control current according to the voltage difference between the voltage to be detected and the reference voltage, and flips the potential of the detection signal when the control current reaches a preset threshold; a negative feedback module is used to reduce the control current when the voltage to be detected is lower than the reference voltage, so that the comparator module flips the potential of the detection signal when the voltage difference is a threshold voltage, and when the voltage difference is the threshold voltage, the control current is the preset threshold. The technical solution of the present invention can avoid the occurrence of current backflow.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a zero-crossing detection circuit, a voltage conversion circuit and a terminal device. Background Art

[0002] A buck direct current-direct current (Buck DC-DC) converter is a universal voltage conversion device that can convert a DC power supply of one voltage level to a DC power supply of another voltage level. When the buck converter operates in discontinuous conduction mode (DCM), a zero-crossing detection circuit determines whether the synchronous transistor drain voltage is greater than zero to shut down the synchronous transistor.

[0003] However, due to the delay in the zero-crossing detection circuit outputting the detection signal and the delay in the synchronous tube turning off, current backflow may occur, resulting in reduced power conversion efficiency and even damage to the circuit. Summary of the Invention

[0004] The technical problem solved by the present invention is how to design a zero-crossing detection circuit structure to prevent the occurrence of current backflow.

[0005] To solve the above technical problems, an embodiment of the present invention provides a zero-crossing detection circuit. The zero-crossing detection circuit includes: a comparator module, wherein a first input terminal of the comparator module is connected to a voltage to be detected, a second input terminal of the comparator module is connected to a reference voltage, an output terminal of the comparator module outputs a detection signal, the comparator module generates a control current according to the voltage difference between the voltage to be detected and the reference voltage, and flips the potential of the detection signal when the control current reaches a preset threshold, wherein the control current is positively correlated with the voltage difference; and a negative feedback module, which is used to reduce the control current when the voltage to be detected is lower than the reference voltage, so that the comparator module flips the potential of the detection signal when the voltage difference is a threshold voltage, and when the voltage difference is the threshold voltage, the control current is the preset threshold, wherein the voltage difference changes from the threshold voltage to the reference voltage in a time sequence.

[0006] Optionally, the negative feedback module includes: a switch subunit, which is turned on when the voltage to be detected is less than the reference voltage, and the first end of the switch subunit is grounded; an impedance subunit, the first end of the impedance subunit is coupled to the second end of the switch subunit, and the second end of the impedance subunit is connected to the control current.

[0007] Optionally, the switch subunit includes: a first NMOS tube, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is coupled to the first end of the impedance subunit, and the gate of the first NMOS tube is connected to the inverted signal of the detection signal.

[0008] Optionally, the impedance sub-unit includes: a second NMOS transistor, a source of the second NMOS transistor is coupled to the switch sub-unit, and a gate of the second NMOS transistor is connected to the control current.

[0009] Optionally, the impedance sub-unit includes: a third NMOS tube, the source of the third NMOS tube is coupled to the drain of the second NMOS tube, the drain of the third NMOS tube is connected to the control current, and the gate of the third NMOS tube is coupled to the drain of the third NMOS tube and the gate of the second NMOS tube.

[0010] Optionally, the zero-crossing detection circuit further includes: a sampling signal switch module, wherein a control end of the sampling signal switch module is connected to a power switch signal, an output end of the sampling signal switch module is coupled to a first input end of the comparator module, the power switch signal is used to selectively control an external power supply to charge an external inductor, and the sampling signal switch module outputs the reference voltage when the power switch signal controls the external power supply to charge the external inductor.

[0011] Optionally, the input end of the sampling signal switch module is connected to the voltage to be detected, and the sampling signal switch module outputs the voltage to be detected when the power switch signal controls the external power supply to stop charging the external inductor.

[0012] Optionally, the sampling signal switch module includes: a first control unit, a first end of the first control unit is connected to the reference voltage, a second end of the first control unit is coupled to the first input end of the comparator module, and the first control unit is configured to be turned on when the power switch signal controls the external power supply to charge the external inductor; and a second control unit, a first end of the second control unit is connected to the voltage to be detected, a second end of the second control unit is coupled to the first input end of the comparator module, and the second control unit is configured to be turned on when the power switch signal controls the external power supply to stop charging the external inductor.

[0013] Optionally, the sampling signal switch module further includes: an inverting unit, wherein an input end of the inverting unit is connected to the power switching signal, a first output end of the inverting unit is coupled to the control end of the first control unit, a second output end of the inverting unit is coupled to the control end of the second control unit, and an output voltage of the first output end of the inverting unit is in opposite phase to an output voltage of the second output end of the inverting unit.

[0014] Optionally, the inverting unit includes: a first inverter, a first end of the first inverter is connected to the power switch signal, and a second end of the first inverter is the first output end; a second inverter, a first end of the second inverter is coupled to the second end of the first inverter, and a second end of the second inverter is the second output end.

[0015] Optionally, the first control unit includes: a fourth NMOS tube, the gate of the fourth NMOS tube is coupled to the first output end of the inverting unit, the source of the fourth NMOS tube is grounded, and the drain of the fourth NMOS tube is coupled to the first input end of the comparator module.

[0016] Optionally, the second control unit includes: a fifth NMOS tube, the gate of the fifth NMOS tube is coupled to the second output end of the inverting unit, the source of the fifth NMOS tube is coupled to the first input end of the comparator module, and the drain of the fifth NMOS tube is connected to the voltage to be detected; a first PMOS tube, the gate of the first PMOS tube is coupled to the first output end of the inverting unit, the source of the first PMOS tube is connected to the voltage to be detected, and the drain of the first PMOS tube is coupled to the first input end of the comparator module.

[0017] Optionally, the comparator module includes: an input unit, a first input end of the input unit is connected to the voltage to be detected, a second input end of the input unit is connected to the reference voltage, a first output end of the input unit outputs the control current, and a second output end of the input unit outputs the reference current, and the input unit is used to generate a control current according to the voltage difference between the voltage to be detected and the reference voltage; a current mirror unit, a first end of the current mirror unit is connected to the control current, and a second end of the current mirror unit is connected to the reference current; a supplement unit, a first end of the supplement unit is coupled to the first end of the current mirror unit, and is used to increase the control current when the control current is less than the reference current so that the control current reaches a preset threshold; a flip unit, a first end of the flip unit is coupled to the second end of the supplement unit, and the second end of the flip unit outputs the detection signal, and the flip unit is used to flip the potential of the detection signal when the control current reaches the preset threshold.

[0018] An embodiment of the present invention further discloses a voltage conversion circuit, which includes a synchronous tube and an inductor, wherein the synchronous tube is used to selectively control a power supply to discharge the inductor; the voltage conversion circuit also includes: a zero-crossing detection circuit, wherein the detection signal is used to control the conduction state of the synchronous tube.

[0019] Optionally, the voltage conversion circuit further includes a power tube, which is used to selectively control the power supply to charge the inductor, and the conduction state of the power tube is controlled by a power switch signal.

[0020] An embodiment of the present invention further discloses a terminal device, comprising the zero-crossing detection circuit or the voltage conversion circuit.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0022] The present invention proposes a zero-crossing detection circuit, which generates a control current according to the voltage difference between the voltage to be detected and the reference voltage through a comparator module, and flips the potential of the detection signal when the control current reaches a preset threshold value. In addition, a negative feedback module is used to reduce the control current when the voltage to be detected is lower than the reference voltage, so that the comparator module flips the potential of the detection signal when the voltage difference is a threshold voltage. By adding a negative feedback module, the technical solution of the present application can reduce the control current when the voltage to be detected is lower than the reference voltage, so that the control current reaches the preset threshold when the voltage difference is the threshold voltage, thereby achieving the effect of flipping the potential of the detection signal in advance. By flipping the potential of the detection signal before the voltage to be detected changes to the reference voltage, the synchronous tube can be turned off before the current backflow phenomenon occurs, directly avoiding the occurrence of the current backflow phenomenon.

[0023] Furthermore, by coupling the sampling signal switch module to the first input terminal of the comparator module, the power switch signal can be used to control the input signal of the first input terminal. When the power switch signal controls the external power supply to charge the external inductor, the sampling signal switch module outputs a reference voltage to the first input terminal, and when the power switch signal controls the external power supply to stop charging the external inductor, it outputs the first input terminal of the voltage to be detected. The technical solution of the present application reduces the voltage of the first input terminal of the comparator module when the external power supply charges the external inductor, so as to discharge the first input terminal in advance, thereby shortening the discharge time of the first input terminal when the external power supply stops charging the external inductor. The voltage of the first input terminal can reach the threshold voltage for triggering the flip more quickly, so that the detection signal can flip more quickly.

[0024] Furthermore, the negative feedback module and the sampling signal switch module are both deployed inside the zero-crossing detection circuit and have a simple structure. They can avoid the current backflow problem without increasing the circuit area, further reducing the difficulty of circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 1 is a schematic structural diagram of a zero-crossing detection circuit provided by an embodiment of the present invention;

[0026] Figure 2 1 is a schematic diagram of a specific structure of a zero-crossing detection circuit provided by an embodiment of the present invention;

[0027] Figure 3 This is a timing diagram of a zero-crossing detection circuit provided by an embodiment of the present invention;

[0028] Figure 4 1 is a structural diagram of another zero-crossing detection circuit provided by an embodiment of the present invention;

[0029] Figure 5 1 is a schematic diagram of the specific structure of another zero-crossing detection circuit provided by an embodiment of the present invention;

[0030] Figure 6 This is a timing diagram of another zero-crossing detection circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, in a step-down voltage converter, due to the delay in the zero-crossing detection circuit outputting the detection signal and the delay in the synchronous tube turning off, current backflow may occur in the circuit, resulting in reduced power conversion efficiency and even damage to the circuit. The prior art reduces the delay in the zero-crossing detection circuit outputting the detection signal as quickly as possible, causing the synchronous tube in the circuit that controls the discharge of the inductor to turn off earlier to reduce the current backflow. However, when the prior art causes the zero-crossing detection circuit to output the detection signal faster, there is still a certain delay, causing some current to backflow.

[0032] In an embodiment of the present invention, a comparator module generates a control current based on the voltage difference between the voltage to be detected and the reference voltage, and flips the potential of the detection signal when the control current reaches a preset threshold value. In addition, a negative feedback module is used to reduce the control current when the voltage to be detected is lower than the reference voltage, so that the comparator module flips the potential of the detection signal when the voltage difference is a threshold voltage. By adding a negative feedback module, the technical solution of the present application can reduce the control current when the voltage to be detected is lower than the reference voltage, so that the control current reaches the preset threshold value when the voltage difference is the threshold voltage, thereby achieving the effect of flipping the potential of the detection signal in advance. By flipping the potential of the detection signal before the voltage to be detected changes to the reference voltage, the synchronous tube can be turned off before the current backflow phenomenon occurs, directly avoiding the occurrence of the current backflow phenomenon.

[0033] Furthermore, by coupling the sampling signal switch module to the first input terminal of the comparator module, the power switch signal can be used to control the input signal of the first input terminal. When the power switch signal controls the external power supply to charge the external inductor, the sampling signal switch module outputs a reference voltage to the first input terminal, and when the power switch signal controls the external power supply to stop charging the external inductor, it outputs the first input terminal of the voltage to be detected. The technical solution of the present application reduces the voltage of the first input terminal of the comparator module when the external power supply charges the external inductor, so as to discharge the first input terminal in advance, thereby shortening the discharge time of the first input terminal when the external power supply stops charging the external inductor. The voltage of the first input terminal can reach the threshold voltage for triggering the flip more quickly, so that the detection signal can flip more quickly.

[0034] Furthermore, the negative feedback module and the sampling signal switch module are both deployed inside the zero-crossing detection circuit and have a simple structure. They can avoid the current backflow problem without increasing the circuit area, further reducing the difficulty of circuit design.

[0035] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is apparent that the described embodiments are only some of the embodiments of the present invention, and not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are also within the scope of protection of the present invention.

[0036] The embodiment of the present invention provides a zero-crossing detection circuit, referring to Figure 1 , the zero-crossing detection circuit provided by an embodiment of the present invention is described below.

[0037] Figure 1 1 is a schematic diagram of the structure of a zero-crossing detection circuit. The zero-crossing detection circuit 1 includes a comparator module 10 and a negative feedback module 11. Figure 1The zero-crossing detection circuit 1 shown includes:

[0038] A comparator module 10, wherein a first input terminal of the comparator module 10 is connected to a voltage to be detected, a second input terminal of the comparator module 10 is connected to a reference voltage, and an output terminal of the comparator module 10 outputs a detection signal. The comparator module 10 is configured to generate a control current based on the voltage difference between the voltage to be detected and the reference voltage, and to flip the potential of the detection signal when the control current reaches a preset threshold;

[0039] The negative feedback module 11 is used to reduce the control current when the voltage to be detected is lower than the reference voltage, so that the comparator module 10 can flip the potential of the detection signal when the voltage difference is a threshold voltage.

[0040] In a specific implementation, the control current is positively correlated with the voltage difference between the voltage to be detected and the reference voltage. When the voltage difference between the voltage to be detected and the reference voltage is larger, the control current is larger; when the voltage difference between the voltage to be detected and the reference voltage is smaller, the control current is smaller.

[0041] In a specific implementation, when the voltage difference between the voltage to be detected and the reference voltage is a threshold voltage, the control current is a preset threshold value, and the voltage difference changes from the threshold voltage to the reference voltage in a time sequence.

[0042] It is understandable that the reference voltage can be a ground voltage or any achievable voltage. The reference voltage can be selected according to actual conditions, and this application does not impose any restrictions on this.

[0043] In a specific application scenario, the zero-crossing detection circuit is used in a voltage conversion circuit, which includes a synchronous transistor that selectively controls a power supply to discharge an inductor. The voltage to be detected can be the drain voltage of the synchronous transistor.

[0044] It should be noted that the power supply can be an internal power supply in the voltage conversion circuit or an external power supply, and this application does not impose any restrictions on this.

[0045] In a specific implementation, the negative feedback module 11 includes a switch subunit 110 and an impedance subunit 111. The switch subunit 110 is turned on when the voltage to be detected is less than the reference voltage, and the impedance subunit 111 reduces the control current, so that when the voltage difference between the voltage to be detected and the reference voltage reaches a threshold voltage, the control current of the comparator module 10 reaches a preset threshold, thereby reversing the potential of the detection signal.

[0046] Specifically, flipping the potential of the detection signal refers to adjusting the potential of the detection signal, for example, flipping the detection signal from a low potential to a high potential; or flipping the detection signal from a high potential to a low potential.

[0047] Now combined Figure 2The working principle of the negative feedback module 11 is described in detail. Figure 2 A schematic diagram of the specific structure of a zero-crossing detection circuit provided by an embodiment of the present invention.

[0048] In a specific implementation, the first terminal of the switch subunit 110 is grounded; the first terminal of the impedance subunit 111 is coupled to the second terminal of the switch subunit 110, and the second terminal of the impedance subunit 111 is connected to the control current. When the voltage to be detected is less than the reference voltage, the switch subunit 110 is turned on, and the impedance subunit 111 shunts the control current, reducing its magnitude.

[0049] In a specific implementation, the switch subunit 110 includes a first NMOS transistor NM1, the source of the first NMOS transistor NM1 is grounded, the drain of the first NMOS transistor NM1 is coupled to the first end of the impedance subunit 111, and the gate of the first NMOS transistor NM1 is connected to the detection signal V out When V1 is high, the first NMOS transistor NM1 is turned on; when V1 is low, the first NMOS transistor NM1 is turned off. Using V1 as the gate voltage of the first NMOS transistor NM1, the first NMOS transistor NM1 can be turned on when the voltage to be detected is less than the reference voltage, so that the impedance subunit 111 is at the voltage to be detected V LX When the voltage is lower than the reference voltage, the control current is reduced.

[0050] Those skilled in the art will appreciate that the switch subunit may be any implementable component with a switch function, such as a single-pole single-throw switch, and the embodiment of the present invention does not impose any limitation on this.

[0051] In one specific embodiment, the impedance subunit 111 includes a second NMOS transistor NM2. The source of the second NMOS transistor NM2 is connected to the drain of the first NMOS transistor NM1. The gate of the second NMOS transistor NM2 is connected to a first voltage, which is positively correlated with the control current. The drain of the second NMOS transistor NM2 is coupled to the gate of the second NMOS transistor NM2. Connecting the second NMOS transistor NM2 using a MOS diode connection prevents backflow of current flowing through the second NMOS transistor NM2 and enables the second NMOS transistor NM2 to function as a resistor.

[0052] In another specific embodiment, the impedance subunit 111 includes a second NMOS transistor NM2 and a third NMOS transistor NM3.

[0053] The source of the second NMOS transistor NM2 is coupled to the drain of the first NMOS transistor NM1, and the gate of the second NMOS transistor NM2 is connected to the first voltage;

[0054] The source of the third NMOS transistor NM3 is coupled to the drain of the second NMOS transistor NM2. The drain of the third NMOS transistor NM3 receives the control current, and the gate of the third NMOS transistor NM3 is coupled to the drain of the third NMOS transistor NM3 and the gate of the second NMOS transistor NM2. Connecting the second NMOS transistor NM2 and the third NMOS transistor NM3 using a MOS diode connection can increase the resistance of the impedance sub-unit 111, allowing the impedance sub-unit 111 to reduce more of the control current, thereby allowing the control current to reach the preset threshold more quickly.

[0055] Those skilled in the art will appreciate that the impedance sub-unit may include multiple MOS tubes, the number of which may be determined based on actual conditions, and the impedance sub-unit may also be any implementable component with impedance, such as a resistor, which is not limited in this embodiment of the present invention.

[0056] In a specific implementation, the comparator module 10 includes an input unit 101, a current mirror unit 102, a supplement unit 103, a flip unit 104 and a bias unit 105.

[0057] The first input terminal of the input unit 101 is connected to the voltage to be detected V LX The second input terminal of the input unit 101 is connected to the reference voltage, the first output terminal of the input unit 101 outputs the control current, and the second output terminal of the input unit 101 outputs the reference current. The input unit 101 is used to detect the voltage V according to the reference voltage. LX The voltage difference with the reference voltage generates the control current, and the reference voltage can be the ground voltage;

[0058] A first terminal of the current mirror unit 102 is connected to the control current, and a second terminal of the current mirror unit 102 is connected to the reference current;

[0059] The first terminal of the supplement unit 103 is coupled to the first terminal of the current mirror unit 102, and is configured to increase the control current when the control current is less than the reference current, so that the control current reaches a preset threshold;

[0060] The first end of the flip unit 104 is coupled to the second end of the supplement unit 103 , and the second end of the flip unit 104 outputs a detection signal. The flip unit 104 is configured to flip the potential of the detection signal when the control current reaches a preset threshold.

[0061] A first terminal of the bias unit 105 is connected to the power supply voltage VDD, a second terminal of the bias unit 105 is coupled to the input terminal of the input unit 101 , and the bias unit 105 is configured to provide a bias current for the comparator module 10 according to the power supply voltage VDD.

[0062] Furthermore, the input unit 101 is based on the input voltage to be detected V LXThe control current and the reference current are outputted respectively by the input unit 101 according to the voltage to be detected V LX The voltage difference with the reference voltage is generated. LX When the voltage to be detected is less than the reference voltage, the flip unit 104 outputs a low potential detection signal. The first terminal of the current mirror unit 102 is connected to the control current, and the second terminal of the current mirror unit 102 is connected to the reference current to copy the reference current. LX The voltage to be detected V LX The voltage difference between the control current and the reference voltage decreases, causing the control current to decrease. When the control current is less than the reference current, the supplementing unit 103 increases the control current to bring the control current to a preset threshold. When the supplementing unit 103 increases the control current to the preset threshold, the flipping unit flips the potential of the output detection signal, causing the detection signal to change from a low potential to a high potential.

[0063] In a specific implementation, the input unit 101 includes a second PMOS transistor PM2 and a third PMOS transistor PM3. The gate of the second PMOS transistor PM2 is connected to the voltage to be detected V LX , the drain of the second PMOS transistor PM2 outputs a control current; the gate of the third PMOS transistor PM3 is connected to the reference voltage, and the drain of the third PMOS transistor PM3 outputs a reference current.

[0064] In a specific implementation, a PMOS tube is used as the input terminal of the comparator module 10, which can detect non-negative voltage and negative voltage at the same time, expands the voltage range of the input voltage, and can adapt to the voltage to be detected V LX All ranges of variation.

[0065] Furthermore, the current mirror unit 102 includes a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7. The source of the sixth NMOS transistor NM6 is grounded, and the drain of the sixth NMOS transistor NM6 is coupled to the drain of the second PMOS transistor PM2. The source of the seventh NMOS transistor NM7 is grounded, and the drain of the seventh NMOS transistor NM7 is coupled to the drain of the third PMOS transistor PM3. The gate of the seventh NMOS transistor NM7 is coupled to the gate of the sixth NMOS transistor NM6 and the drain of the seventh NMOS transistor NM7.

[0066] Furthermore, the supplementary unit includes an eighth NMOS transistor NM8 , a gate of which is coupled to the drain of the second PMOS transistor PM2 , and a source of which is grounded.

[0067] Furthermore, the flip unit includes a ninth NMOS transistor NM9 , a tenth NMOS transistor NM10 , a fourth PMOS transistor PM4 , and a fifth PMOS transistor PM5 . Among them, the gate of the ninth NMOS transistor NM9 is coupled to the drain of the eighth NMOS transistor NM8, and the source of the ninth NMOS transistor NM9 is grounded; the gate of the fourth PMOS transistor PM4 is coupled to the drain of the eighth NMOS transistor NM8, the source of the fourth PMOS transistor PM4 is connected to the power supply voltage VDD, and the drain of the fourth PMOS transistor PM4 is coupled to the drain of the ninth NMOS transistor NM9; the gate of the tenth NMOS transistor NM10 is coupled to the drain of the ninth NMOS transistor NM9 and the drain of the fourth PMOS transistor PM4, the source of the tenth NMOS transistor NM10 is grounded, and the drain of the tenth NMOS transistor NM10 outputs a detection signal; the gate of the fifth PMOS transistor PM5 is coupled to the drain of the ninth NMOS transistor NM9 and the drain of the fourth PMOS transistor PM4, the source of the fifth PMOS transistor PM5 is connected to the power supply voltage VDD, and the drain of the fifth PMOS transistor PM5 outputs a detection signal.

[0068] Furthermore, the bias unit includes a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, and an eighth PMOS transistor PM8. The drain of the sixth PMOS transistor PM6 is coupled to the drain of the eighth NMOS transistor NM8, and the source of the sixth PMOS transistor PM6 is connected to the power supply voltage VDD. The drain of the seventh PMOS transistor PM7 is coupled to the source of the second PMOS transistor PM2 and the source of the third PMOS transistor PM3, and the source of the seventh PMOS transistor PM7 is connected to the power supply voltage VDD. The drain of the eighth PMOS transistor PM8 is grounded, the source of the eighth PMOS transistor PM8 is connected to the power supply voltage VDD, and the gate of the eighth PMOS transistor PM8 is coupled to the gate of the seventh PMOS transistor PM7 and the gate of the sixth PMOS transistor PM6.

[0069] Now combined Figure 3 The timing diagram shown in FIG. 1 illustrates the process of the comparator module outputting the detection signal. Curve A represents the voltage to be detected V LX Curve B represents the timing diagram of the reference voltage, curve b represents the timing diagram of the detection signal in the prior art, and curve a represents the timing diagram of the detection signal of the present application.

[0070] In a specific implementation, the gate of the second PMOS transistor PM2 in the comparator module 10 is connected to the voltage to be detected V LX During the period from time t0 to time t1, the voltage to be detected V LXWhen the voltage is lower than the reference voltage, the second PMOS transistor PM2 is turned on. Due to the voltage difference between the gate and source of the second PMOS transistor PM2, a control current is generated at the drain of the second PMOS transistor PM2, which flows into the drain of the sixth NMOS transistor NM6. The gate of the third PMOS transistor PM3 is connected to the reference voltage, and the third PMOS transistor PM3 is turned on. Due to the voltage difference between the gate and source of the third PMOS transistor PM3, a reference current is generated at the drain of the third PMOS transistor PM3, which flows into the drain and gate of the seventh NMOS transistor NM7, turning on the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7. The gate of the eighth NMOS transistor NM8 is coupled to the drain of the sixth NMOS transistor NM6, and the gate voltage of the eighth NMOS transistor NM8 is greater than the first turn-on voltage of the eighth NMOS transistor NM8, turning on the eighth NMOS transistor NM8. The drain of the eighth NMOS transistor NM8 is coupled to the gate of the ninth NMOS transistor NM9 and the gate of the fourth PMOS transistor PM4. The gate voltage of the ninth NMOS transistor NM9 is less than the second turn-on voltage of the ninth NMOS transistor NM9, turning off the ninth NMOS transistor NM9. The gate voltage of the fourth PMOS transistor PM4 is less than the third turn-on voltage of the fourth PMOS transistor PM4, turning on the fourth PMOS transistor PM4. The drain voltage V1 of the fourth PMOS transistor PM4 is at a high voltage. The drain of the fourth PMOS transistor PM4 is coupled to the gate of the tenth NMOS transistor NM10 and the gate of the fifth PMOS transistor PM5. The gate voltage of the fifth PMOS transistor PM5 is greater than the fourth turn-on voltage of the fifth PMOS transistor PM5, turning off the fifth PMOS transistor PM5. The gate voltage of the tenth NMOS transistor NM10 is greater than the fifth turn-on voltage of the tenth NMOS transistor NM10, turning on the tenth NMOS transistor NM10. The drain of the tenth NMOS transistor NM10 outputs a low-voltage detection signal Vout.

[0071] During the period from time t1 to time t2, as the voltage to be detected V LXAs the voltage of the gate of the eighth NMOS transistor NM8 decreases, the voltage difference between the gate and source of the second PMOS transistor PM2 decreases, and the control current flowing through the sixth NMOS transistor NM6 decreases accordingly, causing the gate voltage of the eighth NMOS transistor NM8 to decrease. Since the negative feedback module 11 reduces the control current, the gate voltage of the eighth NMOS transistor NM8 will decrease below the first turn-on voltage of the eighth NMOS transistor NM8 in advance, causing the eighth NMOS transistor NM8 to be turned off in advance. Only the drain of the sixth PMOS transistor PM6 provides a power supply voltage to the gate of the fourth PMOS transistor PM4 and the gate of the ninth NMOS transistor NM9, thereby increasing the gate voltage of the fourth PMOS transistor PM4 and the gate voltage of the ninth NMOS transistor NM9. The gate voltage of the ninth NMOS transistor NM9 is greater than the second turn-on voltage of the ninth NMOS transistor NM9, turning on the ninth NMOS transistor NM9. The gate voltage of the fourth PMOS transistor PM4 is greater than the third turn-on voltage of the fourth PMOS transistor PM4, turning off the fourth PMOS transistor PM4, and the drain voltage V1 of the ninth NMOS transistor NM9 is low. The gate voltage of the fifth PMOS transistor PM5 is less than the fourth turn-on voltage of the fifth PMOS transistor PM5, turning on the fifth PMOS transistor PM5. The gate voltage of the tenth NMOS transistor NM10 is less than the fifth turn-on voltage of the tenth NMOS transistor NM10, turning off the tenth NMOS transistor NM10, and the drain of the fifth PMOS transistor PM5 outputs a high-potential detection signal Vout.

[0072] In a specific implementation, since the negative feedback module 11 is set, when the detection signal V out When the inverting signal V1 is high, the switch subunit 110 is turned on, and the impedance subunit 111 in the negative feedback module 11 acts as a shunt to reduce the control current. Therefore, the supplementary unit 103 will output more current to make the control current reach the preset threshold, causing the control current to reach the preset threshold in advance, and the flip unit 104 flips the detection signal V when the control current reaches the preset threshold. out The potential of the detection signal V out Flip from low potential to high potential in advance.

[0073] Furthermore, since the drain of the second PMOS transistor PM2 is coupled to the drain of the third NMOS transistor NM3, the second NMOS transistor NM2 and the third NMOS transistor NM3 shunt the control current, further reducing the magnitude of the control current. The gate capacitance of the eighth NMOS transistor NM8 will release more current to make the control current reach the preset threshold, causing the gate voltage of the eighth NMOS transistor NM8 to drop to the threshold voltage faster, thereby causing the eighth NMOS transistor NM8 to be turned off early, resulting in the output detection signal V out Flip from low potential to high potential in advance.

[0074] Furthermore, when the voltage to be detected V LXWhen the voltage is lower than the reference voltage, the drain voltage V1 of the fourth PMOS transistor PM4 is the power supply voltage, which turns on the first NMOS transistor NM1, and the second NMOS transistor NM2 and the third NMOS transistor NM3 shunt the control current. LX When the voltage difference with the reference voltage is the threshold voltage, the potential of the detection signal is reversed, so that the voltage to be detected V LX When the voltage is lower than the reference voltage, a high-potential detection signal can be output to turn off the synchronous tube, thereby achieving the purpose of turning off the synchronous tube in advance.

[0075] The timing diagram of the zero-crossing detection circuit is as follows Figure 3 As shown in curves a and b, compared with the prior art, the present application sets a negative feedback module so that the detection signal starts to flip when the voltage to be detected is less than the reference voltage, so that the detection signal flips from a low potential to a high potential earlier, and the synchronous tube can be turned off more quickly.

[0076] In a specific implementation, the time required to flip the detection signal can be determined through the simulation waveform of the zero-crossing detection circuit, and then the reference voltage corresponding to the time can be determined as the threshold voltage.

[0077] Alternatively, the threshold voltage can be determined by the maximum reverse current. The specific calculation formula for the threshold voltage is as follows:

[0078]

[0079]

[0080]

[0081] Among them, I L is the maximum reverse current, K=V out / L is the inductor current drop slope of the inductor in the voltage conversion circuit in DCM mode, V out is the output voltage of the voltage conversion circuit, V in is the input voltage of the voltage conversion circuit, L is the inductance of the inductor, τ is the turn-off delay time of the synchronous tube and the output delay time of the comparator, and D is the duty cycle. The current value of the maximum reverse current can be calculated. on is the on-resistance of the synchronous tube in the voltage conversion circuit. When the maximum backflow current flows through the on-resistance of the synchronous tube, the drain voltage of the synchronous tube is V LX , V LX The voltage difference from the reference voltage is △V LX Therefore, a negative feedback module 11 can be set to avoid the occurrence of current backflow phenomenon, and V LX The voltage difference from the reference voltage △V LXAs the threshold voltage. After the negative feedback module 11 is set, the calculation formula of the control current I3 is as follows:

[0082]

[0083] Among them, C ox is the capacitance of the gate capacitor of the second PMOS tube PM2, μ p is the electron mobility of the second PMOS transistor PM2, (W / L) p2 is the width-to-length ratio of the gate of the second PMOS transistor PM2, V th1 is the turn-on voltage of the second PMOS transistor PM2. The current I3 flowing through the third NMOS transistor NM3 is proportional to the gate width-to-length ratio of the first NMOS transistor NM1, the gate width-to-length ratio of the second NMOS transistor NM2, and the gate width-to-length ratio of the third NMOS transistor NM3. The threshold voltage ΔV can be adjusted by setting the gate width-to-length ratio of the first NMOS transistor NM1, the gate width-to-length ratio of the second NMOS transistor NM2, and the gate width-to-length ratio of the third NMOS transistor NM3. LX The size of the detection signal causes the potential to be reversed in advance.

[0084] It should be noted that the threshold voltage △V LX The size can be determined according to actual conditions and is not limited in this application.

[0085] In the embodiment of the present invention, a negative feedback module is provided to reduce the magnitude of the control current when the voltage to be detected is less than the reference voltage. This allows the control current to reach a preset threshold value when the voltage difference between the voltage to be detected and the reference voltage reaches a threshold voltage, thereby inverting the detection signal. This achieves the effect of prematurely inverting the potential of the detection signal. This allows the synchronous transistor to be turned off before current backflow occurs, directly preventing the occurrence of current backflow.

[0086] Now combined Figure 4 The working principle of the sampling signal switch module is explained in detail. Figure 4 It is a structural diagram of another zero-crossing detection circuit provided by an embodiment of the present invention.

[0087] In the embodiment of the present invention, the zero-crossing detection circuit 2 includes a sampling signal switch module 12 .

[0088] In a specific implementation, the control terminal of the sampling signal switch module 12 receives a power switch signal, which controls the conduction state of the power transistor. The power switch signal is used to selectively control the external power supply to charge the external inductor. The output terminal of the sampling signal switch module 12 is coupled to the first input terminal of the comparator module 10. When the power switch signal controls the external power supply to charge the external inductor, the module outputs a ground voltage to the first input terminal of the comparator module 10. The input terminal of the sampling signal switch module 12 receives a voltage to be detected. When the power switch signal controls the external power supply to stop charging the external inductor, the module outputs the voltage to be detected to the first input terminal of the comparator module 10.

[0089] In a specific implementation, the sampling signal switch module 12 includes a first control unit 121, a second control unit 122 and an inverting unit 120.

[0090] A first terminal of the first control unit 121 is connected to the ground voltage, a second terminal of the first control unit 121 is coupled to the first input terminal of the comparator module 10, and the first control unit 121 is configured to be turned on when the power switch signal controls the external power supply to charge the external inductor;

[0091] A first terminal of the second control unit 122 is connected to the voltage to be detected, a second terminal of the second control unit 122 is coupled to the first input terminal of the comparator module 10, and the second control unit 122 is configured to be turned on when the power switch signal controls the external power supply to stop charging the external inductor;

[0092] The input end of the inverting unit 120 is connected to the power switch signal, the first output end of the inverting unit 120 is coupled to the control end of the first control unit 121, the second output end of the inverting unit 120 is coupled to the control end of the second control unit, and the output voltage of the first output end of the inverting unit 120 is in opposite phase to the output voltage of the second output end of the inverting unit 120.

[0093] In a specific implementation, when the power switch signal controls the external power supply to stop charging the external inductor, the first control unit 121 is turned off, the second control unit 122 is turned on, and the sampling signal switch module 12 outputs the voltage to be detected to the first input terminal of the comparator module 10; when the power switch signal controls the external power supply to charge the external inductor, the first control unit 121 is turned on, the second control unit 122 is turned off, and the sampling signal switch module 12 outputs the ground voltage to the first input terminal of the comparator module 10.

[0094] Specifically, when the power switch signal is at a high potential, the power switch signal controls the external power supply to charge the external inductor, and when the power switch signal is at a low potential, the power switch signal controls the external power supply to stop charging the external inductor; it is also possible that when the power switch signal is at a high potential, the power switch signal controls the external power supply to stop charging the external inductor, and when the power switch signal is at a low potential, the power switch signal controls the external power supply to charge the external inductor.

[0095] Now combined Figure 5 The working principle of the sampling signal switch module 12 is described in detail. Figure 5 A schematic diagram of the specific structure of another zero-crossing detection circuit provided by an embodiment of the present invention.

[0096] In a specific implementation, the inverting unit 120 includes a first inverter PI1 and a second inverter PI2. The first terminal of the first inverter PI1 is connected to the power switch signal V Pgate , the second end of the first inverter PI1 is the first output end; the first end of the second inverter PI2 is coupled to the second end of the first inverter PI1, and the second end of the second inverter PI2 is the second output end.

[0097] Furthermore, the first control unit 121 includes a fourth NMOS transistor NM4 , a gate of which is coupled to the second terminal of the first inverter PI1 , a source of which is grounded, and a drain of which is coupled to the first input terminal of the comparator module 10 .

[0098] Furthermore, the second control unit 122 includes a fifth NMOS transistor NM5 and a first PMOS transistor PM1. The gate of the fifth NMOS transistor NM5 is coupled to the second end of the second inverter PI2, and the drain of the fifth NMOS transistor NM5 is connected to the voltage to be detected V LX The source of the fifth NMOS transistor NM5 is coupled to the first input terminal of the comparator module 10; the source of the first PMOS transistor PM1 is connected to the voltage to be detected V LX A gate of the first PMOS transistor PM1 is coupled to the second end of the first inverter PI1 , and a drain of the first PMOS transistor PM1 is coupled to the first input end of the comparator module 10 .

[0099] Now combined Figure 6 The timing diagram shown in FIG. 1 illustrates the process of the comparator module 10 outputting the detection signal. Curve C represents the power switch signal V Pgate The timing diagram of the curve A represents the voltage to be detected V LX Curve D represents the timing diagram of the gate voltage of the second PMOS tube, curve d represents the timing diagram of the detection signal in the prior art, and curve c represents the timing diagram of the detection signal in the present invention.

[0100] In a specific implementation, during the period from time t3 to time t4, the power switch signal V Pgate is high, the power switch signal V Pgate The external power supply is controlled to stop charging the external inductor. The first inverter PI1 and the second inverter PI2 are connected to the power switch signal V Pgate Perform phase shifting so that the gate of the fourth NMOS transistor NM4 and the gate of the first PMOS transistor PM1 are connected to a low potential voltage, the fourth NMOS transistor NM4 is turned off, and the first PMOS transistor PM1 is turned on. The gate of the fifth NMOS transistor NM5 is connected to a high potential voltage, and the fifth NMOS transistor NM5 is turned on. At this time, the voltage to be detected V LX is a high potential, and the gate voltage of the second PMOS transistor PM2 in the comparator module 10 is the voltage to be detected V LX , the comparator module 10 outputs a high-voltage detection signal.

[0101] In a specific implementation, during the period from time t4 to time t5, the power switch signal V Pgate Control the external power supply to charge the external inductor, the power switch signal V Pgate The first inverter PI1 and the second inverter PI2 respond to the power switch signal V Pgate Perform phase conversion, so that the gate of the fourth NMOS transistor NM4 and the gate of the first PMOS transistor PM1 are connected to a high potential voltage, the fourth NMOS transistor NM4 is turned on, the first PMOS transistor PM1 is turned off, the gate of the fifth NMOS transistor NM5 is connected to a low potential voltage, and the fifth NMOS transistor NM5 is turned off. At this time, the voltage to be detected V LX = is high, the gate voltage of the second PMOS transistor PM2 in the comparator module 10 is ground voltage, and the comparator module 10 outputs a high-potential detection signal. LX By lowering the gate voltage of the second PMOS transistor PM2 before lowering the potential to a low level, the gate capacitance of the second PMOS transistor PM2 can be discharged in advance, thereby shortening the time for discharging the gate capacitance of the second PMOS transistor PM2. As a result, the gate voltage of the second PMOS transistor PM2 can more quickly reach the voltage that triggers the potential reversal of the detection signal. That is, the second PMOS transistor PM2 can be turned on more quickly, thereby causing the detection signal to be reversed from a high potential to a low potential more quickly.

[0102] It should be noted that it can be the power switch signal V Pgate When the voltage is low, the external power supply charges the external inductor; it can also be the power switch signal V Pgate When the potential is high, the external power supply charges the external inductor, which is not limited in this application.

[0103] Another timing diagram of the zero-crossing detection circuit is as follows Figure 6 As shown in curves c and d, compared with the prior art, the present application sets a sampling signal switch module, which enables the detection signal to flip from a high potential to a low potential earlier when the voltage to be detected drops to a low potential, thereby reducing the delay when the zero-crossing detection circuit outputs the detection signal.

[0104] An embodiment of the present invention further discloses a voltage conversion circuit, comprising a zero-crossing detection circuit, a synchronous transistor, a power transistor, and an inductor. Specifically, the synchronous transistor selectively controls the power supply to discharge the inductor, while the power transistor selectively controls the power supply to charge the inductor. The detection signal controls the conduction state of the synchronous transistor, which is controlled by a power switch signal.

[0105] The embodiment of the present invention further discloses a terminal device, which includes a zero-crossing detection circuit or a voltage conversion circuit. The terminal device can be a mobile phone, a computer, a tablet computer, or a household appliance.

[0106] The term "plurality" used in the embodiments of the present application refers to two or more.

[0107] The first, second, etc. descriptions appearing in the embodiments of this application are only for illustration and distinction of the description objects. There is no order, nor does it indicate any special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0108] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0109] In addition, the functional units in various embodiments of the present invention may be integrated into a single processing unit, each unit may be physically included separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or hardware plus software functional units.

[0110] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit stored in a storage medium includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to perform some steps of the method described in various embodiments of the present invention.

[0111] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A zero-crossing detection circuit, characterized in that: include: a comparator module, wherein a first input terminal of the comparator module is connected to a voltage to be detected, a second input terminal of the comparator module is connected to a reference voltage, an output terminal of the comparator module outputs a detection signal, the comparator module generates a control current according to a voltage difference between the voltage to be detected and the reference voltage, and flips the potential of the detection signal when the control current reaches a preset threshold, and the control current is positively correlated with the voltage difference; a negative feedback module, configured to reduce the control current when the voltage to be detected is lower than the reference voltage, so that the comparator module flips the potential of the detection signal when the voltage difference is a threshold voltage, and the control current is the preset threshold when the voltage difference is the threshold voltage, wherein the voltage difference changes from the threshold voltage to the reference voltage in a time sequence; a sampling signal switch module, wherein a control end of the sampling signal switch module is connected to a power switch signal, an output end of the sampling signal switch module is coupled to a first input end of the comparator module, the power switch signal is used to selectively control an external power supply to charge an external inductor, and the sampling signal switch module outputs the reference voltage when the power switch signal controls the external power supply to charge the external inductor.

2. The zero-crossing detection circuit according to claim 1, characterized in that The negative feedback module includes: a switch subunit, wherein the switch subunit is turned on when the voltage to be detected is less than the reference voltage, and a first end of the switch subunit is grounded; An impedance subunit, wherein a first end of the impedance subunit is coupled to a second end of the switch subunit, and a second end of the impedance subunit is connected to the control current.

3. The zero-crossing detection circuit according to claim 2, characterized in that: The switch subunit includes: a first NMOS tube, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is coupled to the first end of the impedance subunit, and the gate of the first NMOS tube is connected to the inverted signal of the detection signal.

4. The zero-crossing detection circuit according to claim 2, characterized in that: The impedance subunit includes: A second NMOS transistor, wherein a source of the second NMOS transistor is coupled to the switch sub-unit, and a gate of the second NMOS transistor is connected to the control current.

5. The zero-crossing detection circuit according to claim 4, characterized in that: The impedance subunit includes: a third NMOS transistor, wherein the source of the third NMOS transistor is coupled to the drain of the second NMOS transistor, the drain of the third NMOS transistor is connected to the control current, and the gate of the third NMOS transistor is coupled to the drain of the third NMOS transistor and the gate of the second NMOS transistor.

6. The zero-crossing detection circuit according to claim 1, characterized in that: The input end of the sampling signal switch module is connected to the voltage to be detected. When the power switch signal controls the external power supply to stop charging the external inductor, the sampling signal switch module outputs the voltage to be detected.

7. The zero-crossing detection circuit according to claim 1, characterized in that: The sampling signal switch module includes: a first control unit, wherein a first terminal of the first control unit is connected to the reference voltage, a second terminal of the first control unit is coupled to the first input terminal of the comparator module, and the first control unit is configured to be turned on when the power switch signal controls the external power supply to charge the external inductor; A second control unit, wherein a first end of the second control unit is connected to the voltage to be detected, a second end of the second control unit is coupled to the first input end of the comparator module, and the second control unit is configured to be turned on when the power switch signal controls the external power supply to stop charging the external inductor.

8. The zero-crossing detection circuit according to claim 7, characterized in that: The sampling signal switch module also includes: an inverting unit, wherein an input end of the inverting unit is connected to the power switch signal, a first output end of the inverting unit is coupled to the control end of the first control unit, a second output end of the inverting unit is coupled to the control end of the second control unit, and an output voltage of the first output end of the inverting unit is in opposite phase to an output voltage of the second output end of the inverting unit.

9. The zero-crossing detection circuit according to claim 8, characterized in that: The inverting unit comprises: a first inverter, wherein a first terminal of the first inverter is connected to the power switch signal, and a second terminal of the first inverter is the first output terminal; A second inverter, wherein a first terminal of the second inverter is coupled to the second terminal of the first inverter, and a second terminal of the second inverter is the second output terminal.

10. The zero-crossing detection circuit according to claim 8, characterized in that: The first control unit includes: A fourth NMOS transistor, wherein a gate of the fourth NMOS transistor is coupled to the first output terminal of the inverting unit, a source of the fourth NMOS transistor is grounded, and a drain of the fourth NMOS transistor is coupled to the first input terminal of the comparator module.

11. The zero-crossing detection circuit according to claim 8, characterized in that: The second control unit includes: a fifth NMOS transistor, wherein a gate of the fifth NMOS transistor is coupled to the second output terminal of the inverting unit, a source of the fifth NMOS transistor is coupled to the first input terminal of the comparator module, and a drain of the fifth NMOS transistor is connected to the voltage to be detected; a first PMOS transistor, wherein the gate of the first PMOS transistor is coupled to the first output terminal of the inverting unit, the source of the first PMOS transistor is connected to the voltage to be detected, and the drain of the first PMOS transistor is coupled to the first input terminal of the comparator module.

12. The zero-crossing detection circuit according to claim 1, characterized in that: The comparator module includes: an input unit, wherein a first input terminal of the input unit is connected to the voltage to be detected, a second input terminal of the input unit is connected to the reference voltage, a first output terminal of the input unit outputs the control current, and a second output terminal of the input unit outputs the reference current, and the input unit is configured to generate a control current according to a voltage difference between the voltage to be detected and the reference voltage; a current mirror unit, wherein a first end of the current mirror unit is connected to the control current, and a second end of the current mirror unit is connected to the reference current; a supplementing unit, a first terminal of the supplementing unit being coupled to the first terminal of the current mirror unit, and configured to increase the control current when the control current is less than the reference current, so that the control current reaches a preset threshold; A flip unit, wherein the first end of the flip unit is coupled to the second end of the supplement unit, the second end of the flip unit outputs the detection signal, and the flip unit is used to flip the potential of the detection signal when the control current reaches a preset threshold.

13. A voltage conversion circuit, characterized in that: The circuit comprises a synchronous tube and an inductor, wherein the synchronous tube is used to selectively control the power supply to discharge the inductor; the voltage conversion circuit further comprises: The zero-crossing detection circuit according to any one of claims 1 to 12, wherein the detection signal is used to control the conduction state of the synchronous tube.

14. The voltage conversion circuit according to claim 13, wherein: It also includes a power tube, which is used to selectively control the power supply to charge the inductor, and the conduction state of the power tube is controlled by a power switch signal.

15. A terminal device, characterized in that: The invention comprises the zero-crossing detection circuit according to any one of claims 1 to 12, or the voltage conversion circuit according to claim 13 or 14.

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