A sample-hold and knee-point detection circuit with adaptive pre-charging capability

Abstract

The present invention belongs to the technical field of power management, and particularly relates to a sample and hold and knee point detection circuit with adaptive pre-charging ability. The present invention mainly designs and implements a sample and hold and knee point detection circuit with adaptive pre-charging ability. In order to prevent the problem that the sampling capacitor does not have enough charging time within a short turn-off time, the circuit adds a transient enhancement circuit to pre-charge the sampling capacitor, and through a buffer and C delay and R delay The voltage difference formed between the delayed voltage signal and the original signal causes the second comparator to flip, so as to pre-charge the sampling capacitor C delay during the leading edge blanking stage, thereby reducing the charging time requirement for the sampling capacitor C delay . Compared with the traditional sample and hold and knee point detection circuit, a more accurate knee point voltage can be obtained.

Description

Technical Field

[0001] The invention belongs to the technical field of power management, and in particular relates to a sampling, holding and knee point detection circuit with adaptive pre-charging capability. Background Art

[0002] In recent years, with the development of electronic devices, traditional linear regulated power supplies have gradually failed to meet the demand for power management chips in electronic products, and switching power supplies have gradually become the mainstream of the market. Among them, flyback converters have been widely used in low-power devices due to their small size, low power consumption, and good input-output isolation characteristics. Flyback converters can be divided into primary-side feedback type and secondary-side feedback type according to the feedback regulation method. The output sampling of the secondary-side feedback flyback converter is relatively accurate, but due to components such as optocouplers, it has the disadvantage of poor anti-interference ability. Therefore, the primary-side feedback flyback converter with a simpler structure has become the current hot spot.

[0003] In the primary side feedback mode, the output voltage information is obtained through the primary side of the flyback converter. Since the sampling accuracy determines the accuracy of the output voltage, one of the key points in the design of the primary side feedback flyback converter is the design of the sampling and holding and knee detection circuits. When the secondary side inductor current is zero, that is, at the knee point, the voltage drop caused by the parasitic impedance of the secondary side is not equal to V SW Therefore, V SW Can describe the output voltage information more accurately. Figure 1 As shown in the figure, this is a schematic diagram of a traditional sampling and holding and knee point detection circuit. This scheme uses the characteristic that the voltage waveform will drop sharply when the feedback voltage reaches the knee point, and compares the buffer delay with the original signal to obtain the knee point. However, under the traditional scheme, when the secondary side conduction time is small, the sampling circuit cannot establish a steady-state operating point, resulting in the sampled voltage being less than the actual knee point voltage, thereby affecting the accuracy of the output voltage. Summary of the invention

[0004] The present invention mainly designs and implements an adaptive pre-charging circuit that can be used to optimize the sampling and holding and knee detection circuits. In order to prevent the problem that the sampling capacitor has insufficient charging time during a short off time, the circuit adds a transient enhancement circuit to pre-charge the sampling capacitor. delay and R delay The voltage difference between the delayed voltage signal and the original signal causes the second comparator to flip, thereby causing the sampling capacitor C to be delay Precharge to reduce the sampling capacitor C delay The need for charging time.

[0005] To achieve the above object, the technical solution of the present invention is:

[0006] A sampling and holding and knee point detection circuit with an adaptive pre-charging scheme is used to detect the knee point voltage of a primary-side feedback flyback converter when the secondary-side inductor current is zero, comprising a buffer, a first comparator, a second comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a first resistor, a first capacitor, a second capacitor, a first voltage source, a second voltage source and a current source;

[0007] The in-phase input terminal of the buffer A1 is connected to the feedback voltage, and the inverting input terminal thereof is connected to its output terminal. The output terminal of the buffer is connected to the ground after passing through the first resistor and the first capacitor in sequence. The enable signal of the buffer is defined as the first enable signal. The buffer output voltage V buf Defined as the buffer voltage, the voltage at the other end of the first resistor V delay Defined as the delayed voltage;

[0008] The non-inverting input terminal of the first comparator A2 is connected to the buffer voltage, and the inverting input terminal thereof is connected to the first voltage source V OS1 The positive terminal of the voltage source is connected to the feedback voltage, the negative terminal of the voltage source is connected to the feedback voltage, the enable signal of the first comparator is defined as the second enable signal, the output voltage COMP_knee is defined as the judgment voltage, and the first voltage source generates a fixed offset voltage;

[0009] The non-inverting input terminal of the second comparator A3 is connected to the delay voltage, and the inverting input terminal thereof is connected to the second voltage source V OS2 The positive terminal of the voltage source is connected to the feedback voltage, the negative terminal of the voltage source is connected to the feedback voltage, the enable signal of the second comparator is the second enable signal, the output voltage precharge is defined as the precharge voltage, and the second voltage source generates a fixed offset voltage;

[0010] The drain of the first NMOS tube is connected to the delay voltage, and the gate thereof is connected to the third enable signal;

[0011] The source and drain of the second NMOS tube are connected to the source of the first NMOS tube, the gate of the second NMOS tube is connected to the reverse signal of the third enable signal, the connection point between the source of the first NMOS tube and the source and drain of the second NMOS tube is grounded after passing through the second capacitor, and the output voltage of the connection point between the source of the first NMOS tube, the source and drain of the second NMOS tube, and the second capacitor is defined as a knee voltage holding voltage;

[0012] The drain of the third NMOS tube is connected to the connection point of the first resistor, the first capacitor and the drain of the first NMOS tube, the gate of the third NMOS tube is connected to the PWM pulse signal, and the source of the third NMOS tube is grounded; when the primary side is turned on, the pulse signal is high level, and the third NMOS tube is turned on; when the secondary side is turned on, the pulse signal is low level, and the third NMOS tube is turned off;

[0013] The drain of the first PMOS tube is connected to the connection point of the first resistor, the first capacitor and the drain of the first NMOS tube, the gate of the first PMOS tube is connected to the pre-charge voltage, the source of the first PMOS tube is connected to the positive end of the current source, and the negative end of the current source is connected to the power rail.

[0014] When the secondary side is turned on and the feedback voltage rises, the first enable signal controls the buffer to turn on, and the second enable signal controls the first and second comparators to turn off, so that the buffer voltage always follows the feedback voltage, thereby updating the voltage value of the first capacitor; when the feedback voltage enters the plateau period, the second enable signal controls the first and second comparators to turn on, and during the leading edge blanking time, if the delay voltage is less than the feedback voltage, the second comparator flips, the first PMOS tube turns on to charge the first capacitor, if the delay voltage is charged to the feedback voltage, the second comparator flips again, controls the first PMOS to turn off, and the current source no longer charges the first capacitor. When the knee point is reached, the first comparator flips, and the judgment voltage flips from a low potential to a high potential, the third enable signal turns high accordingly, the first NMOS tube turns on for sampling, the charge of the first capacitor is shared with the second capacitor, and the first enable signal controls the buffer to turn off so that the delay voltage maintains the knee point voltage; after a narrow pulse time, the third enable signal turns low, the first NMOS tube turns off and the second NMOS tube turns on, and the second enable signal controls the first comparator to turn off, and the first enable signal controls the buffer to turn on.

[0015] Further, the buffer includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a twelfth NMOS tube, a second resistor, a third resistor, and a fourth resistor; the first comparator includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, an eleventh NMOS tube, a second resistor, a third resistor, and a fourth resistor;

[0016] Wherein, the sources of the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, and the seventh PMOS tube are all connected to the power supply; the gate and drain of the second PMOS tube are interconnected, and the drain thereof is connected to the current source; the gates of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, and the seventh PMOS tube are all connected to the drain of the second PMOS tube;

[0017] The source of the eighth PMOS tube is connected to the drain of the third PMOS tube, the gate of the eighth PMOS tube is connected to the feedback voltage through the fourth resistor, and the drain of the eighth PMOS tube is grounded through the second resistor;

[0018] The source of the ninth PMOS tube is connected to the drain of the third PMOS tube, the gate of the ninth PMOS tube is connected to the drain of the fourth NMOS tube, and the drain of the ninth PMOS tube is grounded after passing through the third resistor;

[0019] The drain of the ninth NMOS tube is connected to the feedback voltage through the fourth resistor, the gate and source of the ninth NMOS tube are interconnected, and the source of the ninth NMOS tube is grounded;

[0020] The gate and drain of the eighth NMOS tube are connected to the drain of the fourth PMOS tube, and the source of the eighth NMOS tube is grounded after passing through the second resistor; the drain of the seventh NMOS tube is connected to the drain of the fifth PMOS tube, the gate of the seventh NMOS tube is connected to the drain of the eighth NMOS tube, and the source of the seventh NMOS tube is grounded after passing through the third resistor;

[0021] The drain of the sixth NMOS tube is connected to the drain of the sixth PMOS tube, the gate of the sixth NMOS tube is connected to the drain of the seventh NMOS tube, and the source of the sixth NMOS tube is grounded;

[0022] The drain of the eleventh NMOS tube is connected to the drain of the seventh PMOS tube, the gate of the eleventh NMOS tube is connected to the second enable signal, and the source of the eleventh NMOS tube is grounded;

[0023] The connection point of the drain of the sixth PMOS tube, the drain of the sixth NMOS tube and the drain of the eleventh NMOS tube is the output end of the first comparator;

[0024] The drain of the fifth NMOS tube is connected to the power supply, and the gate of the fifth NMOS tube is connected to the drain of the seventh NMOS tube; the gate and drain of the tenth NMOS tube are connected to the drain of the seventh PMOS tube, and the source of the tenth NMOS tube is grounded; the drain of the fourth NMOS tube is connected to the source of the fifth NMOS tube, the gate of the fourth NMOS tube is connected to the drain of the tenth NMOS tube, and the source of the fourth NMOS tube is grounded;

[0025] The drain of the twelfth NMOS tube is connected to the drain of the seventh PMOS tube, the gate of the twelfth NMOS tube is connected to the first enable signal, and the source of the twelfth NMOS tube is grounded;

[0026] The connection point between the source of the fifth NMOS tube, the gate of the ninth PMOS tube and the drain of the fourth NMOS tube is the output end of the buffer;

[0027] The beneficial effect of the present invention is that a more accurate knee point voltage can be obtained compared with a conventional sampling and holding and knee point detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Block diagram of a sample-and-hold and knee detection scheme.

[0029] Figure 2 The present invention provides a block diagram of a sampling and holding and knee point detection circuit with adaptive pre-charging capability.

[0030] Figure 3 A control timing diagram of the sample-and-hold and knee-point detection scheme with an adaptive pre-charging scheme proposed in the present invention.

[0031] Figure 4 The present invention provides a sampling and holding and knee point detection circuit with adaptive pre-charging capability. DETAILED DESCRIPTION

[0032] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings:

[0033] The schematic diagram of the sampling and holding and knee point detection using the optimization scheme of the present invention is as follows: Figure 1 As shown. During the secondary side conduction period, the enable signal V hold With V LEB The process of controlling the knee point detection is to first enable the signal V when the secondary side is just turned on. hold Control buffer A1 to open, enable signal V LEB Control comparator shutdown, V RREF The signal passes through the buffer to get V buf signal; when the ringing of the feedback voltage disappears and enters the platform area, the enable signal V LEB The control comparator is turned on to complete the leading edge blanking. When the knee point is reached, the comparator output flips, the control sampling switch is turned on, and the capacitor C delay The charge on the MOSFET is shared with Chold, and the control buffer is turned off to maintain the knee voltage. After a narrow pulse time, the sampling switch is turned off, the enable signal controls the buffer to work, and the control comparator is turned off. This is how the knee voltage is sampled.

[0034] In this scheme, C delay The capacitor is connected to the VDD power rail through the buffer source and resistor R delay For charging, if the secondary side conduction time is very short and C delay If the capacitance is large, V may be insufficient due to insufficient charging time. delay Voltage below V RREF Voltage, appears as Figure 2 The V delay The sampling and holding circuit with adaptive pre-charging capability and the knee point detection circuit proposed by the present invention are as follows: Figure 2The solution mainly includes the sampling and holding and knee detection part and the adaptive pre-charge part. The sampling and holding and knee detection part mainly includes: buffer A1, comparator A2, first-order low-pass filter resistor R delay and capacitor C delay , holding capacitor C hold , sampling switch MN1, virtual switch MN2 and reset switch MN3; the adaptive pre-charging part includes: comparator A3, pre-charging switch MP1, and current source.

[0035] The control timing of the sampling and holding and knee point detection scheme with adaptive pre-charging scheme proposed by the present invention is as follows: Figure 3 When the secondary side is turned on, the MN3 tube is turned off, and the feedback reference voltage V RREF Rapidly rising, V buffer and V delay Will follow V RREF The voltage starts to rise. 0 -t 1 When the secondary side is just turned on, the parasitic capacitance of the power tube and the primary inductance will form a resonance. In order to avoid the false triggering of comparator A2 during this period, V LEB If it is not enabled, A2 will not work. Figure 3 V appears in delay ', use A3 to control MP1 to make the pre-charge current I charge C delay Charging, when V delay Voltage distance V RREF When the precharge output of comparator A3 is larger, it turns low; when V delay Charged to near V REFF When V is on, comparator A3 flips, precharge turns high, MP1 turns off, and the precharge current is cut off. The introduction of comparator A3 can make the on-time of the precharge current change with V REFF The voltage automatic regulation can be used not only in the application of fixed leading edge blanking time, but also in the application of variable leading edge blanking time. 1 -t 2 , V RREF Enter the platform area, V LEB The signal controls comparator A2 to turn on, and A1 continues to work to update C delay Voltage value. At t 2 At this moment, the secondary inductor current drops to 0, the knee point is reached, V RREF Rapidly falling, due to the pull-down conversion rate and buffer delay, V buffer Unable to follow in time, V buffer With V RREFThere is a voltage difference between them, comparator A2 flips, and the COMP_knee signal flips from low potential to high potential, V SES Flip to high potential, enable signal V hold Flipping to high, buffer A1 turns off, V buffer Keep the knee voltage, the sampling switch is open, C delay and C hold Charge sharing begins. After a narrow pulse reaches t 3 Moment, V SES Turn low, the sampling switch MN1 is disconnected, the virtual switch MN2 is turned on, and the clock feedthrough is compensated. hold Turns low, buffer A1 starts to work normally. 4 At this moment, when the primary side is conducting, the MN3 tube is turned on, and C delay The voltage on resets.

[0036] The sample-hold and knee-point detection circuit with adaptive precharge capability is shown in the figure. Figure 4 As shown. The buffer and comparator of this circuit reuse a folded common source and common gate structure, eliminating additional circuits and reducing the power consumption and cost of the circuit. MP2, MP3, MP4, MP5, MP6, and MP7 form a current mirror to provide bias current for the circuit. MP8 and MP9 are input pair tubes, R1 and R2 are load resistors, R3 is a current limiting resistor, MN9 is a GGNMOS tube for electrostatic discharge, MN7, MN8, MP8, and MP9 together form a folded common source and common gate structure; MP6, MN6, enable tube MN11, and the folded common source and common gate structure together form a comparator; MN10 and MN4 form a current mirror, MN5 is used as a source follower tube, and together with the enable tube MN12 and the folded common source and common gate structure, it forms a buffer; R delay and C delay A first-order low-pass filter is formed, keeping the capacitor C hold , sampling switch MN1, virtual switch MN2, and reset switch MN3 constitute a sample-and-hold circuit. In the circuit of this structure, the input common-mode range is guaranteed while the structure has a large gain. The large gain of the buffer can ensure the output accuracy of the buffer, thereby ensuring the accuracy of the sampled voltage. Knee point detection requires V RREF When falling quickly, V buffer Won't follow V RREF When the knee point is reached, C delay and C hold To share the charge, according to the law of charge conservation, when C delay The bigger the C hold The smaller the time, the sam The error with the knee point voltage is small, so the capacitance ratio of the two capacitors needs to be ten times or more.

[0037] I charge The gate of MP1 is connected to the signal enable signal precharge, which is used to control MP1 to open during the leading edge blanking period, so that C delay Precharge is performed. When V delay Close to V RREF When the precharge signal flips, charging ends, and the offset comparator A3 ensures that V delay If the battery has not reached the platform voltage within the LEB time, the charging is terminated.

[0038] The following is a detailed description of the adaptive pre-charge circuit that can be used to optimize the sample-hold and knee detection circuits. Figure 2 In the circuit, V RREF When in the platform area, C delay The charging current can be expressed as

[0039]

[0040] When the secondary side is just turned on, V buf With V RREF rises rapidly, while V delay The initial potential is zero and the charging current is large. buf With V delay The voltage difference becomes smaller, and the charging current is also smaller. delay The design is also limited by stability and delay compensation, so it cannot be reduced by reducing R delay To increase the charging current. Therefore, when the secondary side conduction time is short, the V delay The sampled voltage is lower than the actual knee voltage. Figure 4 An adaptive pre-charging circuit is added to the circuit.

[0041] Assuming that the charging time from the start of the secondary side conduction is t, when V delay can be charged to V within the leading edge blanking time RREF k times, then C delay The charge stored in

[0042] Q C =kC delay V RREF (t)

[0043] During the charging process, the pre-charge current is given to C delay The charge provided is

[0044] Q C_pre =i charge t

[0045] Therefore, the precharge current for C delay The charging speed does not vary with V buf V delay Get closer to V RREF .

Claims

1. A sampling and holding and knee detection circuit with adaptive pre-charging capability, used to detect the knee voltage of a primary-side feedback flyback converter when the secondary-side inductor current is zero, characterized in that: It includes a buffer, a first comparator, a second comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a first resistor, a first capacitor, a second capacitor, a first voltage source, a second voltage source and a current source; The buffer's in-phase input terminal is connected to the feedback voltage, its inverting input terminal is connected to its output terminal, the buffer's output terminal is connected to the ground after passing through the first resistor and the first capacitor in sequence, the buffer's enable signal is defined as the first enable signal, and the buffer output voltage V buf Defined as the buffer voltage, the voltage V at the connection point between the first resistor and the first capacitor delay Defined as the delayed voltage; The non-inverting input terminal of the first comparator is connected to the buffer voltage, the inverting input terminal thereof is connected to the positive terminal of the first voltage source, the negative terminal of the voltage source is connected to the feedback voltage, the enable signal of the first comparator is defined as the second enable signal, the output voltage COMP_knee is defined as the judgment voltage, and the first voltage source generates a fixed offset voltage; The non-inverting input terminal of the second comparator is connected to the delay voltage, the inverting input terminal thereof is connected to the positive terminal of the second voltage source, the negative terminal of the voltage source is connected to the feedback voltage, the enable signal of the second comparator is the second enable signal, the output voltage precharge is defined as the pre-charge voltage, and the second voltage source generates a fixed offset voltage; The drain of the first NMOS tube is connected to the delay voltage, and the gate thereof is connected to the third enable signal; The source and drain of the second NMOS tube are connected to the source of the first NMOS tube, the gate of the second NMOS tube is connected to the reverse signal of the third enable signal, the connection point between the source of the first NMOS tube and the source and drain of the second NMOS tube is grounded after passing through the second capacitor, and the output voltage of the connection point between the source of the first NMOS tube, the source and drain of the second NMOS tube, and the second capacitor is defined as a knee voltage holding voltage; The drain of the third NMOS tube is connected to the connection point of the first resistor, the first capacitor and the drain of the first NMOS tube, the gate of the third NMOS tube is connected to the PWM pulse signal, and the source of the third NMOS tube is grounded; when the primary side is turned on, the pulse signal is high level, and the third NMOS tube is turned on; when the secondary side is turned on, the pulse signal is low level, and the third NMOS tube is turned off; The drain of the first PMOS tube is connected to the connection point of the first resistor, the first capacitor and the drain of the first NMOS tube, the gate of the first PMOS tube is connected to the pre-charge voltage, the source of the first PMOS tube is connected to the positive end of the current source, and the negative end of the current source is connected to the power rail; When the secondary side is turned on and the feedback voltage rises, the first enable signal controls the buffer to turn on, and the second enable signal controls the first and second comparators to turn off, so that the buffer voltage always follows the feedback voltage, thereby updating the voltage value of the first capacitor; When the feedback voltage enters the plateau period, the second enable signal controls the first and second comparators to turn on. If the delay voltage is less than the feedback voltage during the leading edge blanking time, the second comparator flips, and the first PMOS tube turns on to charge the first capacitor. If the delay voltage is charged to the feedback voltage, the second comparator flips again to control the first PMOS tube to turn off, and the current source no longer charges the first capacitor. When the knee point is reached, the first comparator flips, and the judgment voltage flips from a low potential to a high potential. The third enable signal turns high accordingly, and the first NMOS tube turns on for sampling. The charge of the first capacitor is shared with the second capacitor, and the first enable signal controls the buffer to turn off so that the delay voltage maintains the knee point voltage. After a narrow pulse time, the third enable signal turns low, the first NMOS tube turns off and the second NMOS tube turns on, and the second enable signal controls the first comparator to turn off, and the first enable signal controls the buffer to turn on.

2. A sample-hold and knee-detection circuit with adaptive pre-charging capability according to claim 1, characterized in that: The buffer includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a twelfth NMOS tube, a second resistor, a third resistor, and a fourth resistor; the first comparator includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, an eleventh NMOS tube, a second resistor, a third resistor, and a fourth resistor; Wherein, the sources of the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, and the seventh PMOS tube are all connected to the power supply; the gate and drain of the second PMOS tube are interconnected, and the drain thereof is connected to the current source; the gates of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, and the seventh PMOS tube are all connected to the drain of the second PMOS tube; The source of the eighth PMOS tube is connected to the drain of the third PMOS tube, the gate of the eighth PMOS tube is connected to the feedback voltage through the fourth resistor, and the drain of the eighth PMOS tube is grounded through the second resistor; The source of the ninth PMOS tube is connected to the drain of the third PMOS tube, the gate of the ninth PMOS tube is connected to the drain of the fourth NMOS tube, and the drain of the ninth PMOS tube is grounded after passing through the third resistor; The drain of the ninth NMOS tube is connected to the feedback voltage through the fourth resistor, the gate and source of the ninth NMOS tube are interconnected, and the source of the ninth NMOS tube is grounded; The gate and drain of the eighth NMOS tube are connected to the drain of the fourth PMOS tube, and the source of the eighth NMOS tube is grounded after passing through the second resistor; the drain of the seventh NMOS tube is connected to the drain of the fifth PMOS tube, the gate of the seventh NMOS tube is connected to the drain of the eighth NMOS tube, and the source of the seventh NMOS tube is grounded after passing through the third resistor; The drain of the sixth NMOS tube is connected to the drain of the sixth PMOS tube, the gate of the sixth NMOS tube is connected to the drain of the seventh NMOS tube, and the source of the sixth NMOS tube is grounded; The drain of the eleventh NMOS tube is connected to the drain of the seventh PMOS tube, the gate of the eleventh NMOS tube is connected to the second enable signal, and the source of the eleventh NMOS tube is grounded; The connection point of the drain of the sixth PMOS tube, the drain of the sixth NMOS tube and the drain of the eleventh NMOS tube is the output end of the first comparator; The drain of the fifth NMOS tube is connected to the power supply, and the gate of the fifth NMOS tube is connected to the drain of the seventh NMOS tube; the gate and drain of the tenth NMOS tube are connected to the drain of the seventh PMOS tube, and the source of the tenth NMOS tube is grounded; the drain of the fourth NMOS tube is connected to the source of the fifth NMOS tube, the gate of the fourth NMOS tube is connected to the drain of the tenth NMOS tube, and the source of the fourth NMOS tube is grounded; The drain of the twelfth NMOS tube is connected to the drain of the seventh PMOS tube, the gate of the twelfth NMOS tube is connected to the first enable signal, and the source of the twelfth NMOS tube is grounded; The connection point of the fifth NMOS tube source, the ninth PMOS tube gate and the fourth NMOS tube drain is the output end of the buffer.

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