A method for preparing a split-gate flash memory

Abstract

The present invention provides a method for preparing a split-gate flash memory, comprising: providing a substrate, forming two symmetrically arranged floating gate layers and a source line layer located between the two floating gate layers on the substrate; sequentially forming a first oxide layer and a word line material layer on the substrate outside the floating gate layer, wherein the word line material layer covers the first oxide layer; removing a portion of the word line material layer, so that the remaining word line material layer constitutes a word line layer, a portion of the first oxide layer not covered by the word line layer constitutes a barrier layer, and a portion of the first oxide layer covered by the word line layer constitutes a tunneling oxide layer; and thinning at least a portion of the barrier layer using a wet etching process to reduce a gap formed in the barrier layer by lateral erosion, thereby effectively reducing the adverse effects of the gap in the barrier layer on a dielectric layer and a plug, avoiding poor filling or even loss of the plug caused by the gap, and improving the yield of the split-gate flash memory.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a split-gate flash memory. Background Art

[0002] Flash memory, with its advantages of convenience, high storage density, and excellent reliability, has become a hot topic in non-volatile memory research. Since the advent of the first flash memory in the 1980s, with the development of technology and the demand for storage in various electronic products, flash memory has been widely used in mobile communication devices such as mobile phones, laptops, and USB flash drives.

[0003] Flash memory, a non-volatile memory, operates by controlling the switching of gate channels by changing the threshold voltage of transistors or memory cells to store data. Generally speaking, flash memory is categorized into split-gate, stacked, and hybrid structures. Split-gate flash memory, due to its unique structure, offers unique performance advantages over stacked flash memory during programming and erasing. Split-gate flash memory is also widely used due to its high programming efficiency and wordline structure that prevents over-erasure.

[0004] Figure 1 Schematic diagram of the structure of a split-gate flash memory. Figure 2 for Figure 1 The schematic diagram of the partial structure of the split gate flash memory is shown in FIG. Figure 1 and Figure 2 As shown, the existing split-gate flash memory has a substrate 20, a floating gate layer 21, a sidewall structure 22, a source line layer 23, a word line layer 25 and a dielectric layer 29. The two floating gate layers 21 are symmetrically arranged on the substrate 20, the two sidewall structures 22 completely cover the floating gate layer 21, the source line layer 23 is located between the two sidewall structures 22, and the two word line layers 25 are located on the outside of the two sidewall structures 22; a tunneling oxide layer 24 is further provided below the word line layer 25, and a first sidewall 26 is further formed on the side of the word line layer 25 away from the source line layer 23, and the first sidewall 26 is located on the tunneling oxide layer 24; the dielectric layer 29 covers the word line layer 25, the source line layer 23 and the sidewall structure 22. Figure 2As shown, during the process of preparing the first sidewall 26, lateral erosion will be caused to the tunnel oxide layer 24, resulting in a gap 28 in the tunnel oxide layer 24 below the first sidewall 26. Due to process limitations, a gap will be generated in the dielectric layer 29 near the gap 28. When the plug 27 is formed in the dielectric layer 29, the gap will cause the morphology of the plug 27 to be poor, resulting in the inability to form an effective electrical connection between the plug 27 and the substrate 20, affecting the yield of the split-gate flash memory. Summary of the Invention

[0005] The present invention aims to provide a method for preparing a split-gate flash memory to solve the problem of poor plug morphology caused by a gap between a word line sidewall and a substrate in the existing split-gate flash memory.

[0006] In order to achieve the above object, the present invention provides a method for preparing a split-gate flash memory, comprising:

[0007] Providing a substrate, forming two symmetrically arranged floating gate layers and a source line layer located between the two floating gate layers on the substrate;

[0008] forming a first oxide layer and a word line material layer in sequence on the substrate outside the floating gate layer, wherein the word line material layer covers the first oxide layer;

[0009] removing a portion of the word line material layer, so that the remaining word line material layer constitutes a word line layer, a portion of the first oxide layer not covered by the word line layer constitutes a blocking layer, and a portion of the first oxide layer covered by the word line layer constitutes a tunneling oxide layer;

[0010] thinning at least a portion of the barrier layer using a wet etching process;

[0011] A first spacer is formed, where the first spacer covers the sidewalls of the word line layer and the tunnel oxide layer.

[0012] Optionally, also include:

[0013] forming first source / drain regions in the substrate outside the first sidewalls respectively by a first ion implantation process;

[0014] forming a dielectric layer, wherein the dielectric layer entirely covers the word line layer, the source line layer, the floating gate layer, and the first spacer;

[0015] Plugs electrically connected to the source line layer and the first source / drain region are formed in the dielectric layer.

[0016] Optionally, when forming the first oxide layer, the thickness of the first oxide layer is

[0017] Optionally, when part of the word line material layer is removed to form the word line layer, part of the thickness of the first oxide layer outside the word line layer is removed simultaneously, so that the thickness of the barrier layer is smaller than the thickness of the tunnel oxide layer.

[0018] Optionally, after removing a portion of the thickness of the first oxide layer outside the word line layer, the thickness of the barrier layer is

[0019] Optionally, the thickness of the barrier layer thinned by the wet etching process is greater than

[0020] Optionally, the substrate includes a device area and a logic area, the floating gate layer and the source line layer are located on the device area, and the first oxide layer and the word line material layer cover the device area and the logic area of ​​the substrate.

[0021] Optionally, after forming the word line layer and the barrier layer, and before thinning the barrier layer using a wet etching process, the method further includes:

[0022] A logic gate is formed on the logic region, and the first oxide layer under the logic gate constitutes a logic gate dielectric layer.

[0023] Optionally, the first sidewall spacer includes a third oxide layer and a nitride layer covering the third oxide layer. After the first sidewall spacer is formed, the method further includes:

[0024] A fourth oxide layer is formed, wherein the fourth oxide layer conformally covers the first sidewall spacer.

[0025] Optionally, after forming the first sidewall spacer and before forming the fourth oxide layer, the method further includes:

[0026] The remaining thickness of the barrier layer outside the first sidewall is removed until the substrate is exposed.

[0027] In the method for preparing a split-gate flash memory provided by the present invention, a wet etching process is used to reduce the thickness of the barrier layer before forming the first sidewall, that is, to reduce the thickness of the barrier layer below the first sidewall. Since the barrier layer is easily eroded laterally during the formation of the first sidewall, the thinner the barrier layer, the smaller the gap formed in the barrier layer by the lateral erosion. This effectively reduces the effect of the gap in the barrier layer on the morphology of the plug, avoids poor morphology of the plug caused by the gap, ensures electrical connection between the plug and the substrate, and thus ensures the yield of the split-gate flash memory.

[0028] In addition, when forming the logic gate, the logic gate dielectric layer and the second source / drain region on the logic region, the barrier layer can protect the substrate of the device region from being damaged, thereby further ensuring the performance of the split-gate flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the structure of a split-gate flash memory;

[0030] Figure 2 for Figure 1 A schematic diagram of a partial structure of a split-gate flash memory is shown;

[0031] Figure 3 A flow chart of a method for preparing a split-gate flash memory is provided for an embodiment of the present invention;

[0032] Figures 4 to 18 A schematic structural diagram corresponding to the corresponding steps of the method for preparing a split-gate flash memory provided by an embodiment of the present invention;

[0033] Wherein, the accompanying drawings are marked as follows:

[0034] A-device area; B-logic area;

[0035] 20. 100 - substrate; 101 - second oxide layer; 102 - floating gate material layer; 103 - hard mask layer; 104 - opening; 105 - second spacer; 106 - third spacer; 23. 107 - source line layer; 108 - fourth spacer; 109 - first oxide layer; 110 - word line material layer; 25. 111 - word line layer; 112 - logic gate; 113 - logic gate spacer; 114 - second source / drain region; 26. 115 - first spacer; 116 - first source / drain region; 29. ​​117 - dielectric layer; 27. 118 - plug; 119 - logic gate dielectric layer; 120 - barrier layer; 21. 121 - floating gate layer; 24. 122 - tunneling oxide layer; 123 - fourth oxide layer; 28 - notch; 22 - spacer structure; 124 - logic gate material layer. DETAILED DESCRIPTION

[0036] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0037] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms, when used in this manner, are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the steps presented herein are not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0038] This embodiment provides a method for preparing a split-gate flash memory. Figure 3 FIG. 1 is a flow chart of a method for preparing the split-gate flash memory. Figure 3 As shown, the preparation method of the split-gate flash memory includes:

[0039] Step S1: providing a substrate, and forming two symmetrically arranged floating gate layers and a source line layer located between the two floating gate layers on the substrate;

[0040] Step S2: forming a first oxide layer and a word line material layer in sequence on the substrate outside the floating gate layer, wherein the word line material layer covers the first oxide layer;

[0041] Step S3: removing a portion of the word line material layer, so that the remaining word line material layer constitutes a word line layer, a portion of the first oxide layer not covered by the word line layer constitutes a blocking layer, and a portion of the first oxide layer covered by the word line layer constitutes a tunneling oxide layer;

[0042] Step S4: using a wet etching process to reduce at least a portion of the thickness of the barrier layer;

[0043] Step S5: forming a first spacer, wherein the first spacer covers the sidewalls of the word line layer and the tunnel oxide layer.

[0044] Figures 4 to 18 The schematic diagram of the structure of the corresponding steps of the method for preparing the split gate flash memory provided in this embodiment. Figures 4 to 18 The preparation method of the split-gate flash memory is described in detail.

[0045] like Figure 4 As shown, a substrate 100 is provided, wherein the substrate 100 has a device area A and a logic area B, and a second oxide layer 101, a floating gate material layer 102 and a hard mask layer 103 are stacked in sequence on the substrate 100, wherein the second oxide layer 101 covers the substrate 100, the floating gate material layer 102 covers the second oxide layer 101, and the hard mask layer 103 covers the second oxide layer 102.

[0046] like Figure 5As shown, the hard mask layer 103 on the device region A is etched to form an opening 104 in the hard mask layer 103 to expose the floating gate material layer 102 .

[0047] like Figure 6 As shown, an isotropic etching process is used to remove a portion of the thickness of the floating gate material layer 102 in the opening 104. Due to the use of the isotropic etching process, the upper surface of the floating gate material layer 102 in the opening 104 is in an arc shape.

[0048] like Figure 7 As shown, a second spacer 105 is formed in the opening 104 . The second spacer 105 covers a portion of the upper surface of the floating gate material layer 102 and extends to cover the sidewall of the hard mask layer 103 .

[0049] like Figure 8 As shown, the floating gate material layer 102 and the second oxide layer 101 are further etched using the second side wall 105 as a mask until the substrate 100 is exposed to further deepen the opening 104; then a third side wall 106 is formed in the opening 104, and the third side wall 106 covers the side walls of the floating gate material layer 102, the second oxide layer 101 and part of the second side wall 105.

[0050] like Figure 9 As shown, the second side wall 105 and the third side wall 106 are used as masks to perform a third ion implantation process on the substrate 100 in the opening 104 to form a first source / drain region 116 in the substrate 100; then a source line material layer is formed, and the source line material layer fills part of the opening 104 to form a source line layer 107.

[0051] like Figures 9-10 As shown, the hard mask layer 103 on the device area A and the floating gate material layer 102 and the second oxide layer 101 below the hard mask layer 103 are removed, and the remaining floating gate material layer 102 respectively constitutes two floating gate layers 121. Since the floating gate material layer 102 has an arc-shaped upper surface, the floating gate layers 121 all have floating gate tips pointing away from the source line layer 107. The floating gate tips can enhance the control ability of the floating gate layer 121 over electrons to obtain better device performance.

[0052] Furthermore, a fourth spacer 108 is formed on the substrate 100 , and the fourth spacer 108 covers the sidewalls of the floating gate layer 121 , the second oxide layer 101 and the second spacer 105 .

[0053] In addition, while etching the hard mask layer 103, the floating gate material layer 102 and the second oxide layer 101 on the device area A, the hard mask layer 103, the floating gate material layer 102 and the second oxide layer 101 on the logic area B are removed to expose the substrate 100 of the logic area B.

[0054] like Figure 11 As shown, a first oxide layer 109 and a word line material layer 110 are sequentially formed on the substrate 100 . The first oxide layer 109 covers the substrate 100 in the device area A and the logic area B, and the word line material layer 110 covers the first oxide layer 109 .

[0055] like Figures 12-13 As shown, the word line material layer 110 on the logic region B is removed, and then a logic gate material layer 124 is formed on the first oxide layer 109 in the logic region B. The logic gate material layer 124 covers the first oxide layer 109 .

[0056] like Figure 14 As shown, the logic gate material layer 124 is etched, and the remaining logic gate material layer 124 covers a portion of the first oxide layer 109 to form a logic gate 112. The first oxide layer covered by the logic gate 112 constitutes the logic gate dielectric layer 119. During the process of forming the logic gate 112, the thickness of the first oxide layer 109 outside the logic gate 112 is also reduced.

[0057] like Figure 15 As shown, the word line material layer 110 on the device area A is etched, and the remaining word line material layer 110 covers the fourth sidewall 108 to form two word line layers 111. The portion of the first oxide layer 109 not covered by the word line layer 111 constitutes a blocking layer 120, and the portion of the first oxide layer 109 covered by the word line layer 111 constitutes a tunneling oxide layer 122.

[0058] It should be noted that, in this embodiment, the blocking layer 120 also serves as an etching stop layer when etching the word line material layer 110. Therefore, when etching the word line material layer 110, the thickness of part of the first oxide layer 109 outside the word line layer 111 is also thinned. The thinned first oxide layer 109 constitutes the blocking layer 120, and the thickness of the blocking layer 120 is less than the thickness of the tunneling oxide layer 122.

[0059] In this embodiment, when the first oxide layer 109 is formed, the thickness of the first oxide layer 109 is In order to ensure the protection effect of the barrier layer 120 on the substrate 100, the thickness of the barrier layer 120 formed by the thinned first oxide layer 109 is In other optional embodiments, the first oxide layer 109 outside the word line layer 111 may not be thinned.

[0060] like Figure 16 As shown, the first oxide layer 109 outside the logic gate 112 on the logic area B and the blocking oxide layer on the storage area A are removed simultaneously. In this embodiment, a wet etching process is used to etch the blocking layer 120, wherein the etchant used in the wet etching process is hydrofluoric acid, and the thickness of the blocking layer 120 thinned by the wet etching process is greater than

[0061] In this embodiment, the barrier layer 120 and the first oxide layer 109 are completely removed by the wet etching process. In other optional embodiments, only a portion of the thickness of the barrier layer 120 and the first oxide layer 109 may be thinned.

[0062] like Figure 17 As shown, a third oxide layer and a nitride layer are sequentially formed on the substrate 100, and the third oxide layer conformally covers the word line layer 111, the source line layer 107 and the logic gate 112; the nitride layer and the third oxide layer are sequentially etched, and the remaining third oxide layer and the nitride layer on the storage area A cover the sidewalls of the word line layer 111 and the tunneling oxide layer 122 to form the first spacer 115, and the third oxide layer and the nitride layer on the logic area B cover the logic gate 112 and the logic gate dielectric layer 119 to form the logic gate spacer 113; a fourth oxide layer 123 is formed, and the fourth oxide layer 123 conformally covers the first spacer 115 and the logic gate spacer 113, and the first spacer 115 and the fourth oxide layer 123 constitute an ONO layer.

[0063] It should be noted that, in this embodiment, the entire thickness of the barrier layer 120 is removed through the wet etching process, so there is no need to etch the barrier layer 120 when forming the first sidewall 115, thereby avoiding lateral etching of the barrier layer 120; the same applies to the logic gate 112 and the first oxide layer 109 on the outside.

[0064] In other optional embodiments, when forming the third oxide layer and the nitride layer, the barrier layer 120 and the first oxide layer 109 are still present on the substrate 100. After etching the third oxide layer and the nitride layer, it is necessary to further remove the barrier layer 120 outside the first spacer 115 and the first oxide layer 109 outside the logic gate 112. The barrier layer 120 is made of silicon oxide, and the nitride layer is made of silicon nitride. Because the etching rate of silicon oxide is greater than that of silicon nitride, the barrier layer 120 below the first spacer 115 is lateral etched during the formation of the first spacer 115, forming a gap in the barrier layer 120. The thicker the barrier layer 120, the larger the gap. However, the present invention thins the barrier layer 120 through the wet etching process, thereby reducing the size of the gap caused by lateral erosion.

[0065] like Figures 16-17 As shown, a first ion implantation process is used to form two first source / drain regions 116 in the substrate 100 outside the first sidewall 115 respectively; a second ion implantation process is performed on the substrate 100 outside the logic gate 112 to form second source / drain regions 114 in the substrate 100 outside the logic gate 112 respectively; then a dielectric layer is formed on the substrate 100, and the dielectric layer covers the entire surface of the device area A and all structures on the logic area B; finally, a plug 118 is formed in the dielectric layer to be electrically connected to the source line layer 107, the first source / drain region 116 outside the first sidewall 115, the logic gate and the second source / drain region 114 respectively. Since the gap in the barrier layer 120 is small or even absent, no gap is formed at the interface between the dielectric layer and the substrate 100 during formation, thereby effectively preventing the gap from affecting the morphology of the plug 118, ensuring electrical connection between the plug 118 and the first source / drain region 116, and thus ensuring the yield of the split-gate flash memory.

[0066] In summary, in the method for preparing a split-gate flash memory provided in an embodiment of the present invention, a wet etching process is used to thin the thickness of the barrier layer 120 before forming the first sidewall 115, that is, the thickness of the barrier layer 120 below the first sidewall 115 is thinned. Since the barrier layer 120 is easily eroded laterally during the formation of the first sidewall 115, the smaller the thickness of the barrier layer 120, the smaller the gap formed in the barrier layer 120 by the lateral erosion. This effectively reduces the effect of the gap in the barrier layer 120 on the morphology of the plug 118, ensures the electrical connection between the plug 118 and the substrate 100, and further ensures the yield of the split-gate flash memory.

[0067] In addition, when forming the logic gate, the logic upper gate dielectric layer and the second source / drain region 114 on the logic region B, the barrier layer 120 can protect the substrate 100 of the device region A from damage, further ensuring the performance of the split-gate flash memory.

[0068] These are merely preferred embodiments of the present invention and do not limit the present invention in any way. Any equivalent replacement, modification, or other variation of the technical solution and technical contents disclosed herein made by any person skilled in the art without departing from the scope of the technical solution of the present invention shall be deemed to fall within the scope of the technical solution of the present invention and remain within the scope of protection of the present invention.

Claims

1. A method for preparing a split-gate flash memory, characterized in that: include: Providing a substrate, forming two symmetrically arranged floating gate layers and a source line layer located between the two floating gate layers on the substrate; forming a first oxide layer and a word line material layer in sequence on the substrate outside the floating gate layer, wherein the word line material layer covers the first oxide layer; The substrate includes a device area and a logic area, the floating gate layer and the source line layer are located on the device area, and the first oxide layer and the word line material layer cover the device area and the logic area of ​​the substrate; A portion of the word line material layer is removed, and the remaining word line material layer constitutes a word line layer, a portion of the first oxide layer not covered by the word line layer constitutes a barrier layer, and a portion of the first oxide layer covered by the word line layer constitutes a tunneling oxide layer; wherein, when the portion of the word line material layer is removed to form the word line layer, a portion of the first oxide layer outside the word line layer is simultaneously removed, so that the thickness of the barrier layer is less than the thickness of the tunneling oxide layer, and the material of the barrier layer is silicon oxide; thinning at least a portion of the barrier layer using a wet etching process; A first spacer is formed, where the first spacer covers the sidewalls of the word line layer and the tunnel oxide layer.

2. The method for preparing a split-gate flash memory according to claim 1, wherein: Also includes: forming first source / drain regions in the substrate outside the first sidewalls respectively by a first ion implantation process; forming a dielectric layer, wherein the dielectric layer entirely covers the word line layer, the source line layer, the floating gate layer, and the first spacer; Plugs electrically connected to the source line layer and the first source / drain region are formed in the dielectric layer.

3. The method for preparing a split-gate flash memory according to claim 1, wherein: When the first oxide layer is formed, the thickness of the first oxide layer is 4. The method for preparing a split-gate flash memory according to claim 1, wherein: After removing part of the thickness of the first oxide layer outside the word line layer, the thickness of the barrier layer is 5. The method for preparing a split-gate flash memory according to claim 3 or 4, wherein: The thickness of the barrier layer thinned by the wet etching process is greater than 6. The method for preparing a split-gate flash memory according to claim 5, wherein: After forming the word line layer and the barrier layer, and before thinning the barrier layer using a wet etching process, the method further includes: A logic gate is formed on the logic region, and the first oxide layer under the logic gate constitutes a logic gate dielectric layer.

7. The method for preparing a split-gate flash memory according to claim 1, wherein: The first sidewall spacer includes a third oxide layer and a nitride layer covering the third oxide layer. After the first sidewall spacer is formed, the method further includes: A fourth oxide layer is formed, wherein the fourth oxide layer conformally covers the first sidewall spacer.

8. The method for preparing a split-gate flash memory according to claim 7, wherein: After forming the first sidewall spacer and before forming the fourth oxide layer, the method further includes: The remaining thickness of the barrier layer outside the first sidewall is removed until the substrate is exposed.

Images