Thin film transistor, preparation method thereof, and array substrate

Abstract

A thin film transistor, an array substrate, and a method for manufacturing a thin film transistor. The thin film transistor includes: a substrate; a first active layer, a first insulating layer, and a second active layer sequentially stacked on the substrate; wherein the first active layer is in contact with the second active layer through a first via structure located in the first insulating layer, and the non-contact portions of the first active layer and the second active layer are spaced apart by the first insulating layer. The thin film transistor has multiple active layer structures, such that charges are respectively accumulated on two surfaces of each active layer, thereby doubling the number of charges accumulated on the surfaces of the active layer, and further doubling the on-state current of the thin film transistor.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a thin film transistor, an array substrate, and a method for manufacturing a thin film transistor. Background Art

[0002] According to the relative positions of the gate electrode and the active layer of the thin film transistor, the thin film transistor can be divided into a top-gate structure and a bottom-gate structure. According to the position of the source-drain electrode layer relative to the active layer, the thin film transistor can be divided into a top-contact structure and a bottom-contact structure, that is, the thin film transistor includes four structures: bottom-gate top-contact, bottom-gate bottom-contact, top-gate top-contact, and top-gate bottom-contact.

[0003] The thin film transistor includes a silicon-based thin film transistor, a metal oxide thin film transistor, an organic thin film transistor, etc. The silicon-based thin film transistor is widely used in display panels because of its good performance and the ability to be prepared on a large scale. With the development of display technology, the inherent disadvantages of the silicon-based thin film transistor, such as the low mobility and poor stability of the amorphous silicon thin film transistor, and the poor uniformity and high cost of the polycrystalline silicon thin film transistor, make it difficult for the silicon-based thin film transistor to meet the development needs. Although the organic thin film transistor can effectively reduce the cost, its performance far from meets the needs of display technology. Compared with the silicon-based thin film transistor, the metal oxide thin film transistor has obvious technical advantages. It has a higher mobility, a steeper subthreshold swing, a smaller off-state leakage current, better device performance consistency, a simple process for preparing the metal oxide semiconductor, a low process temperature, good stability, and a high transmittance of the formed metal oxide thin film transistor to visible light. The characteristics of the metal oxide thin film transistor device do not significantly degenerate under a bending state. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a thin film transistor, which includes: a substrate; a first active layer, a first insulating layer, and a second active layer sequentially stacked on the substrate; wherein, the first active layer is in contact with the second active layer through a first via structure located in the first insulating layer, and the non-contact part of the first active layer and the second active layer is separated by the first insulating layer.

[0005] For example, the thin film transistor provided by at least one embodiment of the present disclosure further includes a source-drain electrode layer, wherein the source-drain electrode layer is electrically connected to the first active layer and the second active layer.

[0006] For example, in the thin film transistor provided by at least one embodiment of the present disclosure, the source-drain electrode layer is electrically connected to the second active layer through a second via structure, a positive projection of the first via structure on the substrate and a positive projection of the second via structure on the substrate at least partially overlap, and at least a part of the source-drain electrode layer extends into the first via structure.

[0007] For example, the thin film transistor provided by at least one embodiment of the present disclosure further includes a first gate and a second gate. Among them, the first gate is on a side of the first active layer close to the substrate, and a first gate insulating layer is provided between the first gate and the first active layer; the second gate is on a side of the second active layer away from the substrate, and a second gate insulating layer is provided between the second gate and the second active layer.

[0008] For example, in the thin film transistor provided by at least one embodiment of the present disclosure, an interlayer insulating layer is provided on a side of the second gate away from the substrate, the source-drain electrode layer is provided on a side of the interlayer insulating layer away from the substrate, and the second via structure sequentially penetrates through the interlayer insulating layer, the second gate insulating layer and a part of the first insulating layer.

[0009] For example, the thin film transistor provided by at least one embodiment of the present disclosure further includes a third active layer. Among them, the third active layer is provided on a side of the second gate away from the substrate, the interlayer insulating layer is provided between the third active layer and the second gate, and the third active layer is electrically connected to the source-drain electrode layer.

[0010] For example, the thin film transistor provided by at least one embodiment of the present disclosure further includes a gate. Among them, the gate is between the first active layer and the second active layer.

[0011] For example, in the thin film transistor provided by at least one embodiment of the present disclosure, a gate insulating layer is provided on a side of the gate away from the first insulating layer, and the first via structure simultaneously penetrates through the first insulating layer and the gate insulating layer.

[0012] For example, in the thin film transistor provided by at least one embodiment of the present disclosure, a second insulating layer is provided between the second active layer and the source-drain electrode layer, and the second via structure penetrates through the second insulating layer.

[0013] For example, in the thin film transistor provided by at least one embodiment of the present disclosure, the source-drain electrode layer and the second gate are provided on the same layer, an interlayer insulating layer is provided on a side of the second gate close to the substrate, and the second via structure sequentially penetrates through the interlayer insulating layer, the second gate insulating layer and a part of the first insulating layer.

[0014] For example, in the thin film transistor provided in at least one embodiment of the present disclosure, the first active layer includes a first sub-active layer and a second sub-active layer arranged in a stacked manner, and / or the second active layer includes a third sub-active layer and a fourth sub-active layer arranged in a stacked manner.

[0015] At least one embodiment of the present disclosure further provides an array substrate, and the array substrate includes the thin film transistor described in any one of the above.

[0016] At least one embodiment of the present disclosure further provides a method for manufacturing a thin film transistor, and the manufacturing method includes: providing a substrate; forming a first active layer on the substrate; applying a first insulating layer film on a side of the first active layer away from the substrate; patterning the first insulating layer film to form a first insulating layer having a first via structure; forming a second active layer on a side of the first insulating layer away from the substrate, wherein the second active layer is in contact with the first active layer through the first via structure, and a non-contact portion between the first active layer and the second active layer is spaced apart by the first insulating layer.

[0017] For example, the manufacturing method provided in at least one embodiment of the present disclosure further includes forming a source-drain electrode layer, wherein the source-drain electrode layer is electrically connected to the first active layer and the second active layer.

[0018] For example, in the manufacturing method provided in at least one embodiment of the present disclosure, the source-drain electrode layer is electrically connected to the second active layer through a second via structure, a positive projection of the first via structure on the substrate and a positive projection of the second via structure on the substrate at least partially overlap, and at least part of the source-drain electrode layer extends into the first via structure.

[0019] For example, the manufacturing method provided in at least one embodiment of the present disclosure further includes: forming a first gate on a side of the first active layer close to the substrate; forming a first gate insulating layer between the first gate and the first active layer; forming a second gate on a side of the second active layer away from the substrate; forming a second gate insulating layer between the second gate and the second active layer. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention and do not limit the present invention.

[0021] Figure 1 It is a schematic cross-sectional structure diagram of a thin film transistor;

[0022] Figure 2Schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure;

[0023] Figure 3 Schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure;

[0024] Figure 4 Schematic cross-sectional structure diagram of yet another thin film transistor provided by an embodiment of the present disclosure;

[0025] Figure 5 Schematic cross-sectional structure diagram of yet another thin film transistor provided by an embodiment of the present disclosure;

[0026] Figure 6 Schematic cross-sectional structure diagram of yet another thin film transistor provided by an embodiment of the present disclosure;

[0027] Figure 7 Schematic cross-sectional structure diagram of yet another thin film transistor provided by an embodiment of the present disclosure;

[0028] Figure 8 Block diagram of an array substrate provided by an embodiment of the present disclosure;

[0029] Figure 9 Flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0030] Figures 10A - 10E Process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure;

[0031] Figure 11 Flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure; and

[0032] Figures 12A - 12K Process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure. Detailed embodiments

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0034] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this invention pertains. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] As display panels tend to develop in the direction of high resolution and large size, thin film transistors in display panels require high on-state currents. For example, Figure 1 is a schematic cross-sectional structure diagram of a thin film transistor, as Figure 1 shown, a buffer layer 02, a bottom gate 03, a bottom gate insulating layer 04, an active layer 05, a top gate insulating layer 06, a top gate 07, an insulating layer 08, and a source 09a / drain 09b are sequentially stacked on a substrate 01, that is, Figure 1 the shown structure is a double-gate single-active-layer structure, Figure 1 in the shown structure, the bottom gate 03 and the top gate 07 act on one active layer 05 simultaneously, so as to improve the on-state current of the thin film transistor.

[0036] However, Figure 1 the shown structure also has the following defects: Since there are only the bottom gate insulating layer 04, the top gate insulating layer 06, and the active layer 05 between the top gate 07 and the bottom gate 03 for isolation, on the one hand, when the distance between the top gate 07 and the bottom gate 03 is relatively close, it is easy to cause crosstalk between the electric fields of the top gate 07 and the bottom gate 03, resulting in poor stability of carriers in the active layer 05 and difficult control of the characteristics of the thin film transistor. For example, Figure 1 the voltage of the structure of the shown thin film transistor is prone to positive and negative offsets due to the change of the voltage of the top gate 07, thus deteriorating the characteristics of the thin film transistor; on the other hand, Figure 1 the shown thin film transistor cannot achieve a multiple increase in the on-state current. Currently, Figure 1 the increase in the on-state current of the shown structure can only reach about 50%, Figure 1 the increase in the on-state current of the shown thin film transistor is very small. When it is used in a display panel, it cannot meet the requirements of the display panel for the on-state current and resolution.

[0037] The inventors of the present disclosure have noticed that thin film transistors with multiple active layers can be designed such that charges accumulate on two surfaces of each active layer respectively, thereby doubling the number of charges accumulated on the surfaces of the active layer, and further doubling the on-state current of the thin film transistor.

[0038] For example, Figure 2 FIG. is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure. As Figure 2 shown, the thin film transistor 100 includes: a substrate 101, a first active layer 104, a first insulating layer 105, and a second active layer 106 that are sequentially stacked on the substrate 101. The first active layer 104 is in contact with the second active layer 106 through a first via structure 116 located in the first insulating layer 105. The non-contact portions of the first active layer 104 and the second active layer 106 are spaced apart by the first insulating layer 105. For example, the contact between the first active layer 104 and the second active layer 106 through the first via structure 116 can achieve electrical connection between the first active layer 104 and the second active layer 106; the non-contact portions of the first active layer 104 and the second active layer 106 being spaced apart by the first insulating layer 105 can enable charges to accumulate on both the surface of the first active layer 104 close to the substrate 101 and the surface of the first active layer 104 close to the second active layer, and charges to accumulate on both the surface of the second active layer 106 close to the substrate 101 and the surface of the second active layer 106 far from the substrate 101, so that the number of charges accumulated on the surfaces of the active layer (including the first active layer 104 and the second active layer 106) can be doubled, and thus the on-state current can be doubled.

[0039] For example, as Figure 2 shown, the first active layer 104 is in contact with the second active layer 106 through the first via structure 116 located in the first insulating layer 105 and electrical connection is achieved.

[0040] For example, the number of the first via structures 116 can be one or more. In the Figure 2 schematic cross-sectional structure of the thin film transistor shown, the number of the first via structures 116 is two. The two first via structures 116 are spaced apart from each other. The sum of the widths of the two first via structures 116 on the side close to the substrate 101 is less than the maximum horizontal width of the first active layer 104 and less than the maximum horizontal width of the second active layer 106.

[0041] For example, the second active layer 106 covers both the side of each first via structure 116 close to the substrate 101 and the sidewalls defining the first via structure 116, and each first via structure 116 is not filled with the second active layer 106.

[0042] For example, as Figure 2 shown, the orthographic projection of each first via structure 116 on the substrate 101 is smaller than the orthographic projection of the first active layer 104 on the substrate 101 and smaller than the orthographic projection of the second active layer 106 on the substrate 101. The sum of the orthographic projections of the multiple first via structures 116 on the substrate 101 is smaller than the orthographic projection of the first active layer 104 on the substrate 101 and smaller than the orthographic projection of the second active layer 106 on the substrate 101. Of course, the embodiments of the present disclosure are not limited thereto, and the orthographic projection of each first via structure 116 on the substrate 101 may also be greater than or equal to the orthographic projection of the first active layer 104 on the substrate 101. [[ID=*]] [[ID=*]]

[0043] For example, the materials of the first active layer 104 and the second active layer 106 may be the same or different. The materials of the first active layer 104 and the second active layer 106 may both be silicon-based materials, or both be metal oxide semiconductor materials, or both be organic semiconductor materials. The material of the first active layer 104 is one of silicon-based materials, metal oxide semiconductor materials, and organic semiconductor materials, and the material of the second active layer 106 is one of the other two materials different from the material of the first active layer 104. [[ID=*]] [[ID=*]]

[0044] For example, when the materials of the first active layer 104 and the second active layer 106 are both metal oxide semiconductor materials, the metal oxide semiconductor materials include n-type semiconductor materials such as zinc oxide (ZnO), indium oxide (In2O3), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), boron-doped zinc oxide (BZO), magnesium-doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), and tin oxide (SnO2), and p-type semiconductor materials such as stannous oxide (SnO) and cuprous oxide (Cu2O). For example, methods such as magnetron sputtering, reactive sputtering, anodic oxidation, or spin coating can be used to form the first active layer 104 and the second active layer 106 of the metal oxide semiconductor material. [[ID=*]] [[ID=*]]

[0045] For example, the materials of the first active layer 104 and the second active layer 106 may also be silicon, germanium, silicon-germanium hybrid materials, etc. Methods such as magnetron sputtering or spin coating can be used to form the first active layer 104 and the second active layer 106 of the above semiconductor materials. [[ID=*]] [[ID=*]]

[0046] For example, the materials of the first active layer 104 and the second active layer 106 may also be organic semiconductor materials, and the organic semiconductor materials include pentacene, triphenylamine, fullerene, phthalocyanine, polythiophene, polyaniline, polypyrrole, etc. The above organic semiconductor materials can be formed by spin coating. [[ID=*]]

[0047] For example, the thicknesses of the first active layer 104 and the second active layer 106 are respectively 5 nm to 200 nm. For example, the thickness of the first active layer 104 can be 50 nm, 100 nm, 150 nm, or 200 nm, etc.; the thickness of the second active layer 106 can be 50 nm, 100 nm, 150 nm, or 200 nm, etc.

[0048] For example, the substrate 101 is formed of a rigid material or a flexible material. For example, the rigid material includes one of rigid glass and silicon wafers. The flexible material includes one of polyethylene naphthalate, polyethylene terephthalate, polyimide, and flexible glass.

[0049] For example, the material of the first insulating layer 105 includes one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide.

[0050] For example, the thickness of the first insulating layer 105 is 5 nm to 400 nm, for example, 50 nm, 100 nm, 200 nm, 300 nm, or 400 nm.

[0051] For example, as Figure 2 shown, the thin film transistor 100 further includes a source-drain electrode layer 110, and the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106. The source-drain electrode layer 110 includes a source electrode 110a and a drain electrode 110b, and both the source electrode 110a and the drain electrode 110b are electrically connected to the first active layer 104 and the second active layer 106.

[0052] For example, the forms in which the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 include: the source-drain electrode layer 110 overlaps with the first active layer 104 so that the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106; the source-drain electrode layer 110 overlaps with the second active layer so that the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106; the source-drain electrode layer 110 is electrically connected to the first active layer 104 through a second via structure 113 so that the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 simultaneously; the source-drain electrode layer 110 is electrically connected to the second active layer 106 through the second via structure 113 so that the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 simultaneously.

[0053] For example, in Figure 2In the structure shown, the source-drain electrode layer 110 and the second active layer 106 are electrically connected through the second via structure 113 so that the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 simultaneously. The orthographic projection of the first via structure 116 on the substrate 101 and the orthographic projection of the second via structure 113 on the substrate 101 at least partially overlap, and at least part of the source-drain electrode layer 110 extends into the first via structure 116.

[0054] For example, the width of the first via structure 116 on the side close to the substrate 101 is greater than the width of the second via structure 113 on the side close to the substrate 101, and the second via structure 113 on the side close to the substrate 101 is sleeved in the first via structure 116, so that the source-drain electrode layer 110 can be more stably electrically connected to the second active layer 106.

[0055] For example, the material of the source-drain electrode layer 110 may include one or a combination of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy, and copper (Cu).

[0056] For example, in one example, the material of the source-drain electrode layer 110 is a copper-based metal. Copper metal has the characteristics of low resistivity and good conductivity, so it can improve the signal transmission rate of the source-drain electrode layer 110 (source electrode 110a, drain electrode 110b) and improve the display quality.

[0057] For example, the copper-based metal is a copper-based metal alloy with stable properties such as copper (Cu), copper-zinc alloy (CuZn), copper-nickel alloy (CuNi), or copper-zinc-nickel alloy (CuZnNi).

[0058] For example, the thickness of the source-drain electrode layer 110 can be 200 - 400 nm. For example, it can be 200 nm, 230 nm, 250 nm, 300 nm, 350 nm, 380 nm, and 400 nm.

[0059] For example, the source-drain electrode layer 110 is not limited to being formed on the side of the second active layer 106 away from the substrate 101. It can also be formed on the side of the first active layer 104 close to the substrate, or other positions, as long as the source-drain electrode layer 110 can be electrically connected to the first active layer 104 and the second active layer 106 simultaneously.

[0060] For example, when the first active layer 104 and the second active layer 106 are connected, the resistance is relatively large. When forming the source-drain electrode layer 110, a dry etching process is used. When performing the dry etching process, a reducing gas is required. When the materials of the first active layer 104 and the second active layer 106 are metal oxide semiconductor materials, the reducing gas can be used first to reduce the part of the second active layer 106 exposed to the second via structure 113 into elemental metal, so that the resistivity of the second active layer 106 becomes smaller, and then the overall resistance after the first active layer 104 and the second active layer 106 are electrically connected becomes smaller. That is, new equipment and materials do not need to be added to reduce the resistance when the first active layer 104 and the second active layer 106 are connected.

[0061] For example, as Figure 2 shown, the thin film transistor 100 further includes a first gate 102 and a second gate 108. The first gate 102 is on the side of the first active layer 104 close to the substrate 101, and a first gate insulating layer 103 is provided between the first gate 102 and the first active layer 104. The second gate 108 is on the side of the second active layer 106 away from the substrate 101, and a second gate insulating layer 107 is provided between the second gate 108 and the second active layer 106.

[0062] For example, the materials of the first gate 102 and the second gate 108 may respectively include one or a combination of multiple metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy, and copper (Cu). The materials of the first gate 102 and the second gate 108 may also include one or a combination of multiple transparent conductive materials such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and boron-doped zinc oxide (BZO). The first gate 102 and the second gate 108 may be single-layer structures respectively, or may be double-layer structures respectively. The double-layer first gate 102 and second gate 108 may be composite conductive layers composed of metal and transparent conductive materials respectively.

[0063] For example, the thicknesses of the first gate 102 and the second gate 108 may be 50 nm to 300 nm respectively. For example, the thickness of the first gate 102 may be 50 nm, 100 nm, 200 nm, or 300 nm; the thickness of the second gate 108 may be 50 nm, 100 nm, 200 nm, or 300 nm.

[0064] For example, a first gate of a metal material can be formed by methods such as magnetron sputtering, electron beam evaporation, or thermal evaporation, and a first gate of a transparent conductive material can also be formed by methods such as magnetron sputtering or optical coating.

[0065] For example, the materials of the first gate insulating layer 103 and the second gate insulating layer 107 can be, respectively, one or a combination of more than one of silicon oxide (SiO2), silicon nitride (SiN x ), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2).

[0066] For example, the thicknesses of the first gate insulating layer 103 and the second gate insulating layer 107 can be, respectively, 5 nm to 400 nm. For example, the thickness of the first gate insulating layer 103 can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm, and the thickness of the second gate insulating layer 107 can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm.

[0067] For example, methods such as plasma enhanced chemical vapor deposition (PECVD) can be used to deposit oxide insulating materials such as silicon oxide (SiO2) or silicon nitride (SiN x ) to form the first gate insulating layer 103 and the second gate insulating layer 107. Alternatively, the first gate insulating layer 103 and the second gate insulating layer 107 can also be formed by methods such as spin coating organic insulating materials.

[0068] For example, as Figure 2 shown, an interlayer insulating layer 109 is provided on a side of the second gate 108 away from the substrate 101, a source-drain electrode layer 110 is provided on a side of the interlayer insulating layer 109 away from the substrate 101, and a second via structure 113 sequentially penetrates through the interlayer insulating layer 109, the second gate insulating layer 107, and a part of the first insulating layer 105.

[0069] For example, between the first gate 102 and the second gate 108, there are the first gate insulating layer 103, the first active layer 104, the first insulating layer 105, the second active layer 106, and the second gate insulating layer 107, so that the distance between the first gate 102 and the second gate 108 is relatively large, and the number of insulating film layers in the interval is relatively large, so that crosstalk between the electric fields of the first gate 102 and the second gate 108 is not likely to occur.

[0070] For example, Figure 2The structure of the double gate and double active layer increases the on-state current of the thin film transistor exponentially, and compared with forming two complete thin film transistors, the process step of forming the source and drain electrode layer is reduced once, thereby significantly reducing the number of masks used, thereby reducing production costs, and there is a second gate insulating layer 107 and an interlayer insulating layer 109 between the second active layer 106 and the source and drain electrode layer 110, so that when forming the source and drain electrode layer, no etching damage is caused to the second active layer 106 and the first active layer 104, so that the stability of the thin film transistor 100 is significantly improved. At the same time, since the first gate 102 and the second gate 108 control the first active layer 104 and the second active layer 106 respectively, the control ability of the first gate 102 and the second gate 108 is improved, so that the characteristics of the thin film transistor 101 can be guaranteed while the on-state current is doubled. Figure 1 The structure in Figure 2 The on-state current of the thin film transistor is Figure 1 Twice the on-state current of the thin film transistor.

[0071] For example, Figure 2 As shown, a passivation layer 111 is provided on the side of the source / drain electrode layer 110 away from the base substrate 101 . The passivation layer 111 can prevent external impurities or water vapor from entering the thin film transistor 100 , thereby affecting the performance of the thin film transistor.

[0072] For example, Figure 3 A schematic diagram of a cross-sectional structure of another thin film transistor provided in one embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the second via structure 113 penetrates the interlayer insulating layer 109 and a portion of the second gate insulating layer 107 , and the source-drain electrode layer 110 directly contacts the surface of the second active layer 106 away from the substrate 101 through the second via structure 113 . Figure 3 The structure in can make the second active layer 106 completely fill the first via structure 116 to ensure that the second active layer 106 is not easily broken in the first via structure 116, and can also make the depth of the formed second via structure 113 shallower, making the second via structure 113 easier to form.

[0073] For example, a dry etching process is used to form the source-drain electrode layer 110, and a reducing gas is required to perform the dry etching process. When the materials of the first active layer 104 and the second active layer 106 are metal oxide semiconductor materials, a reducing gas can be used first to reduce the portion of the second active layer 106 away from the base substrate 101 into a metal element, thereby reducing the resistivity of the second active layer 106, and further reducing the overall resistance after the first active layer 104 and the second active layer 106 are electrically connected. That is, there is no need to add new equipment and materials to reduce the resistance when the first active layer 104 and the second active layer 106 are connected.

[0074] For example, in Figure 3 , the orthographic projection of the surface of the source-drain electrode layer 110 contacting the second active layer 106 on the substrate 101 at least partially overlaps with the orthographic projection of the first via structure 116 on the substrate 101, which can make the electrode structure more compact and is more conducive to increasing the on-state current. If the source electrode 110a is offset to the left and the drain electrode 110b is offset to the right, it is difficult to exhibit the characteristics of the thin film transistor 100. Figure 3 The structure in

[0075] can increase the contact area between the source-drain electrode layer 110 and the second active layer 106 to electrically connect the source-drain electrode layer 110 with the first active layer 104 and the second active layer 106. Figure 2 For example, the material and thickness of the source-drain electrode layer 110 can refer to the relevant description of

[0076] above and will not be elaborated here. Figure 4 FIG. Figure 4 shows a cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure. As shown in Figure 4 , the thin film transistor 100 further includes a third active layer 112, which is disposed on a side of the second gate 108 away from the substrate 101, and the third active layer 112 is electrically connected to the source-drain electrode layer 110, and an interlayer insulating layer 109 is disposed between the third active layer 112 and the second gate 108. For example, in Figure 1 , the source-drain electrode layer 110 overlaps both sides of the third active layer 112, that is, the source electrode 110a overlaps on the left side of the third active layer 112, the drain electrode 110b overlaps on the right side of the third active layer 112, and the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 through the second via structure 113. The addition of the third active layer 112 further increases the on-state current of the thin film transistor. Compared with the structure in Figure 4 , the on-state current of the thin film transistor in Figure 1 is 3 times that of the thin film transistor in

[0077] For example, Figure 5 FIG. Figure 5As shown, the first active layer 104 includes a first sub-active layer 104a and a second sub-active layer 104b which are stacked, and the second active layer 106 includes a third sub-active layer 106a and a fourth sub-active layer 106b which are stacked. In one example, it may also be that the first active layer 104 includes a first sub-active layer 104a and a second sub-active layer 104b which are stacked, and the second active layer 106 is a single-layer structure. In yet another example, the second active layer 106 includes a third sub-active layer 106a and a fourth sub-active layer 106b which are stacked, and the first active layer 104 is a single-layer structure.

[0078] For example, the materials of the first sub-active layer 104a and the second sub-active layer 104b are the same or different. The material of the first sub-active layer 104a is one of zinc oxide (ZnO), indium oxide (In2O3), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), boron-doped zinc oxide (BZO), magnesium-doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), tin oxide (SnO2), stannous oxide (SnO), and cuprous oxide (Cu2O). The material of the second sub-active layer 104b is one of the above metal oxides or another material different from the material of the first sub-active layer 104a among the above materials.

[0079] For example, the first sub-active layer 104a is used to prevent the diffusion of elements. For example, it prevents the elements in the first gate 102 from diffusing into the second sub-active layer 104b. The carrier concentration of the second sub-active layer 104b is greater than that of the first sub-active layer 104a, and the bandgap of the second sub-active layer 104b is smaller than that of the first sub-active layer 104a. The second sub-active layer 104b is mainly used to transport carriers.

[0080] For example, the materials of the third sub-active layer 106a and the fourth sub-active layer 106b are the same or different. The material of the third sub-active layer 106a is one of zinc oxide (ZnO), indium oxide (In²O₃), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), boron-doped zinc oxide (BZO), magnesium-doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), tin oxide (SnO₂), stannous oxide (SnO), and cuprous oxide (Cu₂O). The material of the fourth sub-active layer 106b is one of the above metal oxides or another material different from the material of the third sub-active layer 106a among the above materials.

[0081] For example, the fourth sub-active layer 106b is used to prevent the diffusion of elements. For example, it prevents the elements in the second gate 108 from diffusing into the third sub-active layer 106a. The carrier concentration of the third sub-active layer 106a is greater than that of the fourth sub-active layer 106b, and the bandgap of the third sub-active layer 106a is smaller than that of the fourth sub-active layer 106b. The third sub-active layer 106a is mainly used for transporting carriers.

[0082] For example, according to Figure 5 , it should be noted that in the Figure 4 shown structure, the third active layer 112 may also include a fifth sub-active layer and a sixth sub-active layer arranged in a stacked manner. The materials of the fifth sub-active layer and the sixth sub-active layer may be the same or different. For the materials of the fifth sub-active layer and the sixth sub-active layer, reference can be made to the relevant descriptions of the first sub-active layer 104a and the second sub-active layer 104b above, and details will not be elaborated here.

[0083] It should be noted that the materials of the first sub-active layer 104a, the second sub-active layer 104b, the third sub-active layer 106a, the fourth sub-active layer 106b, the fifth sub-active layer and the sixth sub-active layer may also be silicon-based materials or organic semiconductor materials. For the silicon-based materials or organic semiconductor materials, reference can be made to the relevant descriptions above, and details will not be elaborated here.

[0084] For example, Figure 6 is a schematic cross-sectional structure diagram of another thin-film transistor provided by an embodiment of the present disclosure. As Figure 6 shown, the thin-film transistor 100 includes a gate 114. The gate 114 is between the first active layer 104 and the second active layer 106, that is, the gate 114 is between the layer where the first active layer 104 is located and the layer where the second active layer 106 is located. The gate 114 is configured to control both the first active layer 104 and the second active layer 106 simultaneously, so that the structure of the thin-film transistor 100 becomes simple, and at the same time, the on-state current of the thin-film transistor 100 can be doubled.

[0085] It should be noted that the layer where the second active layer 106 is located does not include the part of the second active layer 106 located in the second via structure.

[0086] For example, as Figure 6 shown, a gate insulating layer 115 is provided on the side of the gate 114 away from the first insulating layer 105. The first via structure 116 penetrates through the first insulating layer 105 and the gate insulating layer 115 at the same time. The second active layer 106 is electrically connected to the first active layer 104 through the first via structure 116.

[0087] For example, as Figure 6As shown, a second insulating layer 118 is provided between the second active layer 106 and the source-drain electrode layer 110. The second via structure 113 penetrates through the second insulating layer 118, and the source-drain electrode layer 110 is electrically connected to the second active layer 106 through the second via structure 113. In Figure 6 the second active layer 106 completely fills the first via structure 116, and the source-drain electrode layer 110 does not extend into the first via structure 116. However, the embodiments of the present disclosure are not limited thereto, and the source-drain electrode layer 110 may extend into the first via structure 116 according to the structure in Figure 2 .

[0088] For example, Figure 7 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure. As Figure 7 shown, the source-drain electrode layer 110 and the second gate 108 are provided on the same layer. An interlayer insulating layer 109 is provided on the side of the second gate 108 close to the substrate 101. The second via structure 113 sequentially penetrates through the interlayer insulating layer 109, the second gate insulating layer 107, and a part of the first insulating layer 105.

[0089] For example, as Figure 7 shown, a passivation layer 111 is provided on the side of the source-drain electrode layer 100 and the interlayer insulating layer 109 away from the substrate 101. The passivation layer 111 can prevent external impurities or moisture from entering the thin film transistor 100, thereby affecting the performance of the thin film transistor.

[0090] At least one embodiment of the present disclosure further provides an array substrate, which includes the thin film transistor in any of the above embodiments. For example, Figure 8 is a block diagram of an array substrate provided by an embodiment of the present disclosure. The array substrate 200 includes the thin film transistor 100. The array substrate can be used in a display device, and the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0091] At least one embodiment of the present disclosure further provides a method for manufacturing a thin film transistor. The manufacturing method includes: providing a substrate; sequentially forming a first active layer, a first insulating layer, and a second active layer on the substrate. Among them, the first active layer is in contact with the second active layer through a first via structure located in the first insulating layer, and the non-contact part between the first active layer and the second active layer is separated by the first insulating layer.

[0092] For example, Figure 9 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure. As Figure 9 shown, the manufacturing method includes the following steps.

[0093] S11: Provide a substrate.

[0094] S12: Form a first active layer on the substrate.

[0095] S13: Apply a first insulating layer film on a side of the first active layer away from the substrate.

[0096] S14: Pattern the first insulating layer film to form a first insulating layer having a first via structure.

[0097] S15: Form a second active layer on a side of the first insulating layer away from the substrate, wherein the second active layer contacts the first active layer through the first via structure, and a non - contacting portion between the first active layer and the second active layer is spaced apart by the first insulating layer.

[0098] For example, Figures 10A - 10E is a process diagram of a method for manufacturing a thin - film transistor provided by an embodiment of the present disclosure.

[0099] As Figure 10A shown, provide a substrate 101, and the substrate 101 is made of a rigid material or a flexible material. For example, the rigid material includes one of rigid glass and silicon wafers. The flexible material includes one of polyethylene naphthalate, polyethylene terephthalate, polyimide, and flexible glass.

[0100] As Figure 10B shown, form a first active layer 104 on the substrate 101. For example, the material of the first active layer 104 can be a silicon - based material, or a metal - oxide semiconductor material, or an organic semiconductor material.

[0101] For example, when the material of the first active layer 104 is a metal - oxide semiconductor material, the metal - oxide semiconductor material includes n - type semiconductor materials such as zinc oxide (ZnO), indium oxide (In2O3), indium zinc oxide (IZO), aluminum - doped zinc oxide (AZO), boron - doped zinc oxide (BZO), magnesium - doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), and tin oxide (SnO2), as well as p - type semiconductor materials such as stannous oxide (SnO) and cuprous oxide (Cu2O). For example, methods such as magnetron sputtering, reactive sputtering, anodic oxidation, or spin - coating can be used to form the first active layer 104 of the metal - oxide semiconductor material.

[0102] For example, the material of the first active layer 104 can also be silicon, germanium, a silicon - germanium hybrid material, etc. Methods such as magnetron sputtering or spin - coating can be used to form the first active layer 104 of the above - mentioned semiconductor materials.

[0103] For example, the material of the first active layer 104 can also be an organic semiconductor material, which includes pentacene, triphenylamine, fullerene, phthalocyanine, polythiophene, polyaniline, polypyrrole, etc. The above organic semiconductor material can be formed by spin coating.

[0104] For example, the thickness of the first active layer 104 is 5 nm to 200 nm. For example, the thickness of the first active layer 104 is 50 nm, 100 nm, 150 nm, or 200 nm, etc.

[0105] As Figure 10C shown, a first insulating layer film 105' is applied on the side of the first active layer 104 away from the substrate 101.

[0106] As Figure 10D shown, the first insulating layer film 105' is patterned to form a first insulating layer 105 having a first via structure 116.

[0107] For example, patterning the first insulating layer film 105' includes coating a photoresist on the first insulating layer film 105', and processing the first insulating layer film 105' by processes such as exposure, development, etching, and stripping of the photoresist to form a first insulating layer 105 having a first via structure 116.

[0108] For example, the material of the first insulating layer 105 includes one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide.

[0109] For example, the thickness of the first insulating layer 105 is 5 nm to 400 nm, such as 50 nm, 100 nm, 200 nm, 300 nm, or 400 nm.

[0110] As Figure 10E shown, a second active layer 106 is formed on the side of the first insulating layer 105 away from the substrate 101. The selection range of the material of the second active layer 106 is the same as that of the material of the first active layer 104, and the thickness of the second active layer 106 is 5 nm to 200 nm. For example, the thickness of the second active layer 106 is 50 nm, 100 nm, 150 nm, or 200 nm, etc.

[0111] As Figure 10E shown, the second active layer 106 contacts the first active layer 104 through the first via structure 116 in the first insulating layer 105, and the non-contact part between the first active layer 104 and the second active layer 106 is separated by the first insulating layer 105.

[0112] For example, the first active layer 104 is in contact with the second active layer 106 through a first via structure 116 located in the first insulating layer 105 to achieve electrical connection.

[0113] For example, the number of the first via structures 116 can be one or more. In Figure 10D the cross-sectional structure of the thin film transistor shown, the number of the first via structures 116 is two. The two first via structures 116 are spaced apart from each other. The sum of the widths of the two first via structures 116 on the side close to the substrate 101 is less than the maximum width of the first active layer 104 in the horizontal direction and less than the maximum width of the second active layer 106 in the horizontal direction.

[0114] For example, on the side of each first via structure 116 close to the substrate 101 and on the sidewalls defining the first via structure 116, the second active layer 106 is covered, and each first via structure 116 is not filled with the second active layer 106.

[0115] For example, as Figure 10E shown, the orthographic projection of each first via structure 116 on the substrate 101 is smaller than the orthographic projection of the first active layer 104 on the substrate 101 and smaller than the orthographic projection of the second active layer 106 on the substrate 101. The sum of the orthographic projections of each first via structure 116 on the substrate 101 is smaller than the orthographic projection of the first active layer 104 on the substrate 101 and smaller than the orthographic projection of the second active layer 106 on the substrate 101. Of course, the embodiments of the present disclosure are not limited thereto. The orthographic projection of each first via structure 116 on the substrate 101 can also be greater than or equal to the orthographic projection of the first active layer 104 on the substrate 101.

[0116] For example, the materials of the first active layer 104 and the second active layer 106 can be the same or different. The materials of the first active layer 104 and the second active layer 106 can both be silicon-based materials, or both be metal oxide semiconductor materials, or both be organic semiconductor materials. The material of the first active layer 104 is one of silicon-based materials, metal oxide semiconductor materials, and organic semiconductor materials, and the material of the second active layer 106 is one of the other two materials different from the material of the first active layer 104.

[0117] For example, Figure 11 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure. As Figure 11 shown, the manufacturing method includes:

[0118] S21: Provide a substrate.

[0119] S22: Form a first gate on the substrate.

[0120] For example, a first gate thin film is applied on a substrate, a photoresist is coated on the first gate thin film, and processes such as exposure, development, etching, and stripping of the photoresist are used to pattern the first gate thin film to form a first gate.

[0121] For example, the photoresist can be coated by spin coating, blade coating, or roll coating.

[0122] For example, the material of the first gate includes one or a combination of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy, and copper (Cu). The material of the first gate can also include one or a combination of transparent conductive materials such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and boron-doped zinc oxide (BZO). The first gate can be a single-layer structure or a double-layer structure. The first gate with a double-layer structure can be a composite conductive layer composed of a metal and a transparent conductive material.

[0123] For example, in one example, the material of the first gate can be a combination of copper and other metals, such as copper / molybdenum (Cu / Mo), copper / titanium (Cu / Ti), copper / molybdenum-titanium alloy (Cu / MoTi), copper / molybdenum-tungsten alloy (Cu / MoW), copper / molybdenum-niobium alloy (Cu / MoNb), etc.; the material of the first gate can also be a chromium-based metal or a combination of chromium and other metals, such as chromium / molybdenum (Cr / Mo), chromium / titanium (Cr / Ti), chromium / molybdenum-titanium alloy (Cr / MoTi), etc.

[0124] For example, the thickness of the first gate can be 50 nm to 300 nm respectively, and the thickness of the first gate 102 is 50 nm, 100 nm, 200 nm, or 300 nm, etc.

[0125] For example, methods such as magnetron sputtering, electron beam evaporation, or thermal evaporation can be used to form the first gate thin film, and methods such as magnetron sputtering or optical coating can also be used to form the first gate thin film.

[0126] S23: Form a first gate insulating layer on the first gate.

[0127] For example, a first gate insulating layer thin film is deposited on the first gate, and the first gate insulating layer thin film is patterned to form a first gate insulating layer.

[0128] For example, the first gate insulating layer can be formed by at least one of insulating materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al2O3), aluminum nitride (AlN), etc., and is formed by the method of plasma-enhanced chemical vapor deposition (PECVD), or an organic insulating material can also be formed by spin coating to form the first gate insulating layer.

[0129] S24: Form a first active layer on the first gate insulating layer.

[0130] For example, a first active layer thin film is applied on the first gate insulating layer by magnetron sputtering, a photoresist is formed on the first active layer thin film, and processes such as exposure, development, etching, and photoresist stripping are used to pattern the first active layer thin film to form the first active layer.

[0131] For example, the material of the first active layer can refer to the relevant description in the above embodiments of thin film transistors, which will not be elaborated here.

[0132] S25: Form a first insulating layer on the first active layer.

[0133] For example, a first insulating layer thin film is applied on the side of the first active layer away from the substrate, and the first insulating layer thin film is patterned to form a first insulating layer with a first via structure.

[0134] For example, patterning the first insulating layer thin film includes coating a photoresist on the first insulating layer thin film, and processes such as exposure, development, etching, and photoresist stripping are used to process the first insulating layer thin film to form a first insulating layer with a first via structure.

[0135] S26: Form a second active layer on the first insulating layer.

[0136] For example, a second active layer thin film is applied on the first insulating layer by magnetron sputtering, a photoresist is formed on the second active layer thin film, and processes such as exposure, development, etching, and photoresist stripping are used to pattern the second active layer thin film to form the second active layer.

[0137] For example, the second active layer fills a part of the first via structure, that is, the second active layer does not completely fill the first via structure.

[0138] For example, the material of the second active layer can refer to the relevant description in the above embodiments of thin film transistors, which will not be elaborated here.

[0139] S27: Form a second gate insulating layer on the second active layer.

[0140] For example, a second gate insulating layer thin film is applied on the side of the second active layer away from the substrate, and the second gate insulating layer thin film is patterned to form the second gate insulating layer.

[0141] For example, the second gate insulating layer can be silicon oxide (SiO x ), silicon nitride (SiN x) It can be formed from at least one of insulating materials such as aluminum oxide (Al2O3) and aluminum nitride (AlN), and can be formed by plasma-enhanced chemical vapor deposition (PECVD), or an organic insulating material can be spin-coated to form the second gate insulating layer.

[0142] S28: Form a second gate on the second gate insulating layer.

[0143] For example, a second gate thin film is applied to the side of the second gate insulating layer away from the substrate, a photoresist is formed on the second gate thin film, and processes such as exposure, development, etching, and photoresist stripping are used to pattern the second gate thin film to form the second gate.

[0144] For example, the photoresist can be coated by spin coating, blade coating, or roll coating.

[0145] For example, the material of the second gate includes one or a combination of multiple metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy, and copper (Cu). The material of the second gate can also include one or a combination of multiple transparent conductive materials such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and boron-doped zinc oxide (BZO). The second gate can be a single-layer structure or a double-layer structure. The second gate with a double-layer structure can be a composite conductive layer composed of a metal and a transparent conductive material.

[0146] For example, in one example, the material of the second gate can be a combination of copper and other metals, such as copper / molybdenum (Cu / Mo), copper / titanium (Cu / Ti), copper / molybdenum-titanium alloy (Cu / MoTi), copper / molybdenum-tungsten alloy (Cu / MoW), copper / molybdenum-niobium alloy (Cu / MoNb), etc.; the material of the second gate can also be a chromium-based metal or a combination of chromium and other metals, such as chromium / molybdenum (Cr / Mo), chromium / titanium (Cr / Ti), chromium / molybdenum-titanium alloy (Cr / MoTi), etc.

[0147] For example, the thickness of the second gate can be 50nm - 300nm respectively, and the thickness of the second gate can be 50nm, 100nm, 200nm, or 300nm, etc.

[0148] For example, methods such as magnetron sputtering, electron beam evaporation, or thermal evaporation can be used to form the second gate thin film, or methods such as magnetron sputtering or optical coating can also be used to form the second gate thin film.

[0149] S29: Form an interlayer insulating layer on the second gate.

[0150] For example, an interlayer insulating layer film is applied on the side of the second gate away from the substrate, a photoresist is coated on the interlayer insulating layer film, and the interlayer insulating layer film and the second gate insulating layer are patterned by processes such as exposure, development, etching and stripping of the photoresist to form an interlayer insulating layer and a second via structure that penetrates the interlayer insulating layer, the second gate insulating layer and part of the first insulating layer.

[0151] For example, the material of the interlayer insulating layer includes silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al2O3), aluminum nitride (AlN) and other insulating materials, and an interlayer insulating layer is formed by a plasma enhanced chemical vapor deposition (PECVD) method, or an organic insulating material is formed by a spin coating method to form an interlayer insulating layer.

[0152] S30: forming a source-drain electrode layer on the interlayer insulating layer.

[0153] For example, a source-drain electrode layer film is applied to the side of the interlayer insulating layer away from the substrate by magnetron sputtering, a photoresist is formed on the source-drain electrode layer film, and the source-drain electrode layer film is patterned by exposure, development, etching and stripping of the photoresist to form a source-drain electrode layer. The material and thickness of the source-drain electrode layer can be found in the relevant description above and will not be repeated here.

[0154] For example, the resistance when the first active layer and the second active layer are connected is relatively large, and a dry etching process is used to form the source-drain electrode layer. A reducing gas is required when performing the dry etching process. When the materials of the first active layer and the second active layer are metal oxide semiconductor materials, a reducing gas can be used first to reduce the portion of the second active layer exposed to the second via structure to a metal element, thereby reducing the resistivity of the second active layer, and further reducing the overall resistance after the first active layer and the second active layer are electrically connected. That is, the resistance when the first active layer and the second active layer are connected can be reduced without adding new equipment and materials.

[0155] S31: forming a passivation layer on a side of the source / drain electrode layer away from the substrate.

[0156] For example, the passivation layer can be formed by plasma chemical vapor deposition, and the material of the passivation layer is silicon nitride (SiN x ), silicon oxide (SiO x ), acrylic resin, etc. The passivation layer can prevent external impurities or water vapor from entering the thin film transistor, thereby affecting the performance of the thin film transistor.

[0157] For example, a passivation layer film may also be deposited on a side of the source-drain electrode layer away from the substrate, a photoresist may be coated on the passivation layer film, and processes such as exposure, development, etching, and stripping of the photoresist may be used to process the passivation layer film to form a passivation layer.

[0158] For example, Figures 12A - 12K is a process diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure. The manufacturing method includes:

[0159] As Figure 12A shown, a substrate 101 is provided. The material of the substrate 101 may refer to the relevant description above and will not be elaborated here.

[0160] As Figure 12B shown, a first gate 102 is formed on the substrate 101. The specific process of forming the first gate 102 is as follows: a first gate material layer is formed on the substrate 101, and the first gate material layer is patterned to form the first gate 102.

[0161] For example, the material and formation method of the first gate 102 may refer to the relevant description above and will not be elaborated here.

[0162] As Figure 12C shown, a first gate insulating layer 103 is formed on the first gate 102. The material and thickness of the first gate insulating layer 103 may refer to the relevant description above and will not be elaborated here.

[0163] For example, silicon oxide (SiO2) or silicon nitride (SiN x ) may be deposited by plasma-enhanced chemical vapor deposition (PECVD) to form the first gate insulating layer 103, or the first gate insulating layer 103 may also be formed by spin-coating an organic insulating material or the like.

[0164] As Figure 12D shown, a first active layer 104 is formed on the first gate insulating layer 103.

[0165] For example, a first active layer material is deposited on the first gate insulating layer 103 and patterned to form the first active layer 104. The material, formation method, and thickness of the first active layer 104 may refer to the relevant description above and will not be elaborated here.

[0166] As Figure 12E shown, a first insulating layer 105 is formed on the first active layer 104, and a first via structure 116 is formed in the first insulating layer 105. The material of the first insulating layer 105 and the formation method of the first via structure 116 may refer to the relevant description above and will not be elaborated here.

[0167] AsFigure 12F As shown, a second active layer 106 is formed on the first insulating layer 105. The first active layer 104 is in contact with the second active layer 106 through a first via structure 116 located in the first insulating layer 105, and the non-contact portions of the first active layer 104 and the second active layer 106 are separated by the first insulating layer 105.

[0168] For example, a second active layer material is deposited on the patterned first insulating layer 105 and patterned to form the second active layer 106. For example, the number of the first via structures 116 is multiple, for example, two. The bottom and side walls of each first via structure 116 in the first insulating layer 105 are covered with the second active layer 106, and each first via structure 116 is not filled with the second active layer 106.

[0169] For example, the material and structure of the second active layer 106 can refer to the relevant descriptions above, which will not be elaborated here.

[0170] As Figure 12G shown, a second gate insulating layer 107 is formed on the second active layer 106.

[0171] For example, the formation method and material of the second gate insulating layer 107 can refer to the relevant descriptions about the first gate insulating layer 103 above, which will not be elaborated here.

[0172] As Figure 12H shown, a second gate 108 is formed on the second gate insulating layer 107.

[0173] For example, the material and formation method of the second gate 108 can refer to the relevant descriptions above, which will not be elaborated here.

[0174] As Figure 12I shown, an interlayer insulating layer 109 is formed on the second gate 108.

[0175] For example, a second via structure 113 is formed in the interlayer insulating layer 109 and the second gate insulating layer 107. The material of the interlayer insulating layer 109 can refer to the relevant descriptions above, which will not be elaborated here.

[0176] As Figure 12J shown, a source-drain electrode layer 110 is formed on the interlayer insulating layer 109.

[0177] For example, a conductive material is deposited on the interlayer insulating layer 109 and in the second via structure 113 and patterned to form the source-drain electrode layer 110 (including a source electrode 110a and a drain electrode 110b), and the source electrode 110a and the drain electrode 110b are electrically connected to the first active layer 104 and the second active layer 106 simultaneously.

[0178] For example, the source-drain electrode layer 110 is electrically connected to the second active layer 106 through the second via structure 113. In one example, the orthographic projection of the first via structure 116 on the substrate 101 and the orthographic projection of the second via structure 113 on the substrate 101 at least partially overlap, and at least a part of the source-drain electrode layer 110 extends into the first via structure 116.

[0179] For example, in one example, a part of the second via structure 113 is formed in the first via structure 116, and the orthographic projection of the second via structure 113 on the substrate 101 is located within the orthographic projection of the first via structure 116 on the substrate 101.

[0180] For example, the material of the source-drain electrode layer 110 may respectively include one or a combination of multiple metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy, and copper (Cu).

[0181] For example, the material of the source-drain electrode layer 110 is a copper-based metal. Copper metal has the characteristics of low resistivity and good conductivity, so it can improve the signal transmission rate of the source and drain and improve the display quality.

[0182] For example, the copper-based metal is a copper-based metal alloy with stable properties such as copper (Cu), copper-zinc alloy (CuZn), copper-nickel alloy (CuNi), or copper-zinc-nickel alloy (CuZnNi).

[0183] For example, the thickness of the source-drain electrode layer 110 can be 200 - 400 nm. For example, it can be 200 nm, 230 nm, 250 nm, 300 nm, 350 nm, 380 nm, and 400 nm.

[0184] For example, deposit the source-drain electrode layer material on the interlayer insulating layer 109, coat photoresist on the source-drain electrode layer material, and pattern the source-drain electrode layer material through processes such as exposure, development, etching, and photoresist stripping to form the source-drain electrode layer. For example, a reducing gas can also be used to form the source-drain electrode layer by dry etching.

[0185] As Figure 12K shown, a passivation layer 111 is formed on the side of the source-drain electrode layer away from the substrate 101.

[0186] For example, the passivation layer 111 can be formed by plasma chemical vapor deposition.

[0187] For example, compared with the process diagram of forming Figure 2 the thin-film transistor in Figure 3When referring to the structure of the thin film transistor shown, each first via structure 116 is filled with the second active layer 106 so that the second active layer 106 completely fills the first via structure 116, ensuring that the second active layer 106 is not easily broken in the first via structure 116. It can also make the depth of the formed second via structure 113 shallower, making the second via structure 113 easier to form. The formed second via structure 113 penetrates the interlayer insulating layer 109 and part of the second gate insulating layer 107, and the source-drain electrode layer 110 is in direct contact with the surface of the second active layer 106 away from the substrate 101 through the second via structure 113.

[0188] For example, compared with the process diagram of forming Figure 2 the thin film transistor in Figure 4 When referring to the structure of the thin film transistor shown, the manufacturing method further includes: after forming the interlayer insulating layer 109, before or after forming the source-drain electrode layer 110, forming a third active layer 112 on the side of the interlayer insulating layer 109 away from the substrate 101. The third active layer 112 and the source-drain electrode layer 110 are electrically connected, and the interlayer insulating layer 109 is disposed between the third active layer 112 and the second gate 108. For example, in combination with Figure 4 the source-drain electrode layer 110 overlaps both sides of the third active layer 112, that is, the source electrode 110a overlaps the left side of the third active layer 112, the drain electrode 110b overlaps the right side of the third active layer 112, and the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 through the second via structure 113. The addition of the third active layer 112 further increases the on-state current of the thin film transistor. Compared with the structure in Figure 1 the on-state current of the thin film transistor in Figure 4 is Figure 1 3 times that of the thin film transistor in

[0189] For example, compared with the process diagram of forming Figure 2 the thin film transistor in Figure 5 When referring to the structure of the thin film transistor shown, the formed first active layer 104 in the manufacturing method includes a first sub-active layer 104a and a second sub-active layer 104b arranged in a stacked manner, and the second active layer 106 includes a third sub-active layer 106a and a fourth sub-active layer 106b arranged in a stacked manner. The materials and manufacturing methods of the first sub-active layer 104a, the second sub-active layer 104b, the third sub-active layer 106a, and the fourth sub-active layer 106b can refer to the relevant descriptions above and will not be elaborated here.

[0190] For example, compared with the process diagram of forming Figure 2 the thin film transistor in Figure 6When forming the structure of the thin-film transistor shown, only one gate 114 is formed in this manufacturing method. The gate 114 is formed between the layer where the first active layer 104 is located and the layer where the second active layer 106 is located. The gate 114 is configured to control both the first active layer 104 and the second active layer 106 simultaneously, thereby simplifying the structure of the thin-film transistor 100 and doubling the on-state current of the thin-film transistor 100 at the same time.

[0191] For example, when forming Figure 6 the thin-film transistor shown, a gate insulating layer 115 is formed on the side of the gate 114 away from the first insulating layer 105. The first via structure 116 penetrates through both the first insulating layer 105 and the gate insulating layer 115 at the same time. The second active layer 106 is electrically connected to the first active layer 104 through the first via structure 116. A second insulating layer 118 is formed between the second active layer 106 and the source-drain electrode layer 110. The second via structure 113 penetrates through the second insulating layer 118, and the source-drain electrode layer 110 is electrically connected to the second active layer 106 through the second via structure 113.

[0192] For example, when forming Figure 7 the structure of the thin-film transistor shown, the difference between this manufacturing method and Figures 12A - 12K the process shown is that after forming the second gate insulating layer 107, the second gate 108 is not directly formed, but the interlayer insulating layer 109 is directly formed. After forming the interlayer insulating layer 109, the source-drain electrode layer 110 and the second gate 108 are formed in the same process step, and the second via structure 113 penetrates through the interlayer insulating layer 109 and the second gate insulating layer 107.

[0193] For example, the thin-film transistor, the array substrate, and the manufacturing method of the thin-film transistor provided by the embodiments of the present disclosure have at least one of the following beneficial technical effects:

[0194] (1) The thin-film transistor provided by at least one embodiment of the present disclosure has a dual active layer structure, enabling charges to accumulate on the two surfaces of the two active layers respectively, thereby doubling the number of charges accumulated on the surfaces of the active layers, and doubling the on-state current of the thin-film transistor.

[0195] (2) The thin-film transistor provided by at least one embodiment of the present disclosure further includes a third active layer, which further increases the on-state current of the thin-film transistor.

[0196] (3) The thin film transistor provided by at least one embodiment of the present disclosure, when the materials of the first active layer and the second active layer are metal oxide semiconductor materials, can first use a reducing gas to reduce the part of the second active layer exposed to the second via structure into elemental metal, so that the resistivity of the second active layer becomes smaller, and then the overall resistance after the first active layer and the second active layer are electrically connected becomes smaller. That is, it is possible to reduce the resistance when the first active layer and the second active layer are connected without adding new equipment and materials.

[0197] The following points need to be explained:

[0198] (1) The drawings of the embodiments of the present invention only relate to the structures involved in the embodiments of the present invention, and other structures can refer to the general design.

[0199] (2) For clarity, in the drawings used to describe the embodiments of the present invention, the thickness of the layer or region is enlarged or reduced, that is, these drawings are not drawn according to the actual scale. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there can be an intermediate element.

[0200] (3) Without conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to obtain new embodiments.

[0201] As described above, this is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A thin film transistor, comprising: substrate; A first active layer, a first insulating layer and a second active layer are sequentially stacked on the base substrate; wherein, The first active layer contacts the second active layer through a first via structure in the first insulating layer, and portions of the first active layer and the second active layer that are not in contact are separated by the first insulating layer; The thin film transistor further includes a source-drain electrode layer, the source-drain electrode layer being electrically connected to the second active layer via a second via structure, the width of the first via structure close to the base substrate being greater than the width of the second via structure close to the base substrate, a portion of the second via structure close to the base substrate being nested in the first via structure, and the second via structure exposing the second active layer; The thin film transistor further includes a first gate and a second gate, wherein the first gate is located on a side of the first active layer close to the base substrate, and a first gate insulating layer is provided between the first gate and the first active layer; the second gate is located on a side of the second active layer away from the base substrate, and a second gate insulating layer is provided between the second gate and the second active layer; An interlayer insulating layer is provided on a side of the second gate away from the base substrate, the source-drain electrode layer is provided on a side of the interlayer insulating layer away from the base substrate, and the second via structure sequentially penetrates the interlayer insulating layer, the second gate insulating layer and a portion of the first insulating layer; The thin film transistor further includes a third active layer, wherein the third active layer is arranged on a side of the second gate away from the base substrate, the interlayer insulating layer is arranged between the third active layer and the second gate, and the third active layer is electrically connected to the source-drain electrode layer; In a first direction, the first active layer and the second active layer are arranged between the first gate and the second gate, and in a second direction, the second gate is arranged between the source and the drain, and the first direction and the second direction intersect; The first active layer includes a first sub-active layer and a second sub-active layer arranged in a stacked manner, the second active layer includes a third sub-active layer and a fourth sub-active layer arranged in a stacked manner, the first sub-active layer is configured to prevent elements in the first gate from diffusing into the second sub-active layer, the carrier concentration of the second sub-active layer is greater than the carrier concentration of the first sub-active layer, and the band gap of the second sub-active layer is smaller than the band gap of the first sub-active layer, the fourth sub-active layer is configured to prevent elements in the second gate from diffusing into the third sub-active layer, the carrier concentration of the third sub-active layer is greater than the carrier concentration of the fourth sub-active layer, and the band gap of the third sub-active layer is smaller than the band gap of the fourth sub-active layer, and only the third sub-active layer is arranged in the first via structure, and the fourth sub-active layer is not arranged in the first via structure.

2. The thin film transistor according to claim 1, wherein An orthographic projection of the first via structure on the base substrate and an orthographic projection of the second via structure on the base substrate at least partially overlap, and at least a portion of the source-drain electrode layer extends into the first via structure.

3. An array substrate comprising the thin film transistor according to claim 1 or 2.

4. A method for preparing a thin film transistor, comprising: providing a substrate; forming a first active layer on the base substrate; Applying a first insulating layer thin film on a side of the first active layer away from the substrate; patterning the first insulating layer film to form a first insulating layer having a first via structure; forming a second active layer on a side of the first insulating layer away from the base substrate; The second active layer contacts the first active layer through the first via structure, and the first active layer and the second active layer are separated by the first insulating layer. The preparation method further includes forming a source-drain electrode layer, wherein the source-drain electrode layer is electrically connected to the second active layer through a second via structure, the width of the first via structure on a side close to the base substrate is greater than the width of the second via structure on a side close to the base substrate, a portion of the second via structure close to the base substrate is nested in the first via structure, and the second via structure exposes the second active layer; The preparation method further includes: forming a first gate on a side of the first active layer close to the base substrate; forming a first gate insulating layer between the first gate and the first active layer; forming a second gate on a side of the second active layer away from the base substrate; and forming a second gate insulating layer between the second gate and the second active layer. An interlayer insulating layer is provided on a side of the second gate away from the base substrate, the source-drain electrode layer is provided on a side of the interlayer insulating layer away from the base substrate, and the second via structure sequentially penetrates the interlayer insulating layer, the second gate insulating layer and a portion of the first insulating layer; The preparation method further includes forming a third active layer, wherein the third active layer is arranged on a side of the second gate away from the base substrate, the interlayer insulating layer is arranged between the third active layer and the second gate, and the third active layer is electrically connected to the source-drain electrode layer, wherein in a first direction, the first active layer and the second active layer are arranged between the first gate and the second gate, and in a second direction, the second gate is arranged between the source electrode and the drain electrode, and the first direction and the second direction intersect; The first active layer includes a first sub-active layer and a second sub-active layer arranged in a stacked manner, the second active layer includes a third sub-active layer and a fourth sub-active layer arranged in a stacked manner, the first sub-active layer is configured to prevent elements in the first gate from diffusing into the second sub-active layer, the carrier concentration of the second sub-active layer is greater than the carrier concentration of the first sub-active layer, and the band gap of the second sub-active layer is smaller than the band gap of the first sub-active layer, the fourth sub-active layer is configured to prevent elements in the second gate from diffusing into the third sub-active layer, the carrier concentration of the third sub-active layer is greater than the carrier concentration of the fourth sub-active layer, and the band gap of the third sub-active layer is smaller than the band gap of the fourth sub-active layer, and only the third sub-active layer is arranged in the first via structure, and the fourth sub-active layer is not arranged in the first via structure.

5. The preparation method according to claim 4, wherein An orthographic projection of the first via structure on the base substrate and an orthographic projection of the second via structure on the base substrate at least partially overlap, and at least a portion of the source-drain electrode layer extends into the first via structure.

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