A method and device for constructing a dual-band low noise amplifier

Abstract

The present application discloses a construction method and device of a dual-band low-noise amplifier, the method comprising: constructing a low-noise amplifier and calculating the gate width of a first transistor for reducing a noise coefficient, determining the sizes of the first transistor and the second transistor according to the gate width of the first transistor and a preset gate length, determining the sizes of the third transistor and the fourth transistor to be a target gate width smaller than the gate width of the first transistor, and adjusting the sizes of the first transistor, the second transistor, the third transistor, and the fourth transistor to obtain a dual-band low-noise amplifier. It can be seen that by adjusting the sizes of the first transistor, the second transistor, the third transistor, and the fourth transistor, the output impedance matching network in the dual-band low-noise amplifier obtained after adjusting the sizes of each transistor can suppress the interference signal between the two preset signal frequency bands to the maximum extent, and the noise coefficient of the dual-band low-noise amplifier is better and the power gain is higher.

Description

Technical Field

[0001] The present application relates to the field of circuits, and more specifically, to a construction method and device for a dual-band low-noise amplifier. Background Art

[0002] With the continuous development of communication technology, more and more researchers are committed to optimizing the system parameters of communication systems, such as the signal-to-noise ratio of communication systems. The signal-to-noise ratio (SNR) of a communication system depends largely on the noise figure (NF) and gain of a low-noise amplifier. As shown in the Friis formula:

[0003]

[0004] Where F is the total noise factor, F i and G i They refer to the noise factor and useful power gain of the i-th stage circuit respectively. The Friis formula shows that most of the total circuit noise comes from the first stage amplifier. The influence of the noise generated by each stage circuit on the total noise of the communication system will decrease as the gain of its previous stage circuit increases. Therefore, as the first stage active amplifier circuit of the RF receiver in the communication system, the low noise amplifier has a vital impact on the overall performance of the communication system.

[0005] At present, there are many methods to realize multi-band low noise amplifiers, such as switch parallel low noise amplifiers and broadband low noise amplifiers. However, the switch parallel low noise amplifier is controlled by the RF switch and can only work in one frequency band at a time. The insertion loss of the switch will worsen the circuit noise. The broadband low noise amplifier covers a certain bandwidth with a single low noise amplifier. All frequency points of the low noise amplifier can work within the bandwidth. However, since the broadband low noise amplifier covers a continuous frequency band, when only multiple separated frequency points need to be amplified, it will amplify the interference signals of other frequency bands, resulting in poor performance of the low noise amplifier.

[0006] How to build a high-performance dual-band low-noise amplifier with low noise and high efficiency in suppressing interference signals between the dual frequency bands is an issue that needs attention. Summary of the invention

[0007] In view of the above problems, the present application is proposed to provide a method and device for constructing a dual-band low-noise amplifier to efficiently suppress interference signals between the dual-bands and improve the performance of the low-noise amplifier.

[0008] In order to achieve the above objectives, the specific plan is proposed as follows:

[0009] A method for constructing a dual-band low noise amplifier, comprising:

[0010] Constructing a low-noise amplifier, the low-noise amplifier comprising a signal source, an input-stage amplification system, an input impedance matching network, an output-stage amplification system, an inter-stage impedance matching network, and an output impedance matching network, the input-stage amplification system comprising a first transistor with an adjustable size and a second transistor with an adjustable size, the output-stage amplification system comprising a third transistor with an adjustable size and a fourth transistor with an adjustable size, the input-stage amplification system being connected to the input impedance matching network, and the inter-stage impedance matching network being connected to the output impedance matching network through the output-stage amplification system;

[0011] During the operation of the low noise amplifier, the gate width of the first transistor for reducing the noise coefficient of the low noise amplifier is calculated according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low noise amplifier, and a preset quality factor;

[0012] Determine the size of the first transistor according to the gate width of the first transistor and the preset gate length, and determine the size of the second transistor to be the same as the size of the first transistor, so that the low-noise amplifier can continuously cover two preset signal frequency bands when the input stage amplification system cooperates with the input impedance matching network to reduce the noise coefficient of the low-noise amplifier based on the size of the first transistor and the size of the second transistor;

[0013] The gate widths of the third transistor and the fourth transistor are both determined to be smaller than the target gate width within the preset range of the gate width of the first transistor, and the gate lengths of the third transistor and the fourth transistor are both determined to be the preset gate length, so as to obtain the size of the third transistor and the size of the fourth transistor, so that the output impedance matching network can suppress the signal between the two preset signal frequency bands when the output stage amplification system cooperates with the inter-stage impedance matching network to reduce the power consumption of the low noise amplifier based on the size of the third transistor and the size of the fourth transistor;

[0014] According to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, the first transistor, the second transistor, the third transistor and the fourth transistor are adjusted respectively in the low-noise amplifier to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands.

[0015] Optionally, calculating the gate width of the first transistor for reducing the noise coefficient of the low-noise amplifier according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low-noise amplifier, and a preset quality factor includes:

[0016] The gate width of the first transistor for reducing the noise figure of the low noise amplifier is calculated using the following formula:

[0017]

[0018] Wherein, ω is the operating frequency of the low noise amplifier, L is the preset gate length, C ox is the unit area oxide capacitance of the first transistor, R s is the built-in impedance of the signal source, Q sp is the preset quality factor.

[0019] Optionally, the target gate width is half of the gate width of the first transistor.

[0020] Optionally, the input stage amplification system in the low-noise amplifier also includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth transistor of adjustable size, a first inductor, a second inductor, a third inductor, a fourth inductor, a first capacitor, a second capacitor and a third capacitor, the first inductor and the first capacitor are connected in series between the drain of the first transistor and the gate of the second transistor, a parallel LC network is connected in series between the drain of the first transistor and the source of the second transistor, the parallel LC network is composed of the second inductor and the second capacitor in parallel, the source of the second transistor is connected to the third capacitor for bypass, the source of the first transistor is connected to the third inductor, the first transistor, the fifth transistor, the first resistor and the second resistor form a current mirror structure, the gate of the second transistor is connected to the third resistor, the fourth inductor connected to the drain of the second transistor is connected in series with the fourth resistor, and the source of the fifth transistor, the third inductor and the third capacitor are all grounded.

[0021] Optionally, the input impedance matching network in the low noise amplifier includes a fourth capacitor, a fifth inductor and a sixth inductor, the fourth capacitor, the fifth inductor and the sixth inductor form a T-type LCL network, and the fourth capacitor is grounded.

[0022] Optionally, the output stage amplification system in the low-noise amplifier also includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a sixth transistor of adjustable size, a seventh inductor, an eighth inductor, a ninth inductor, a tenth inductor, a fifth capacitor, a sixth capacitor and a seventh capacitor. The circuit topology structure formed by the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the third transistor, the fourth transistor, the sixth transistor, the seventh inductor, the eighth inductor, the ninth inductor, the tenth inductor, the fifth capacitor, the sixth capacitor and the seventh capacitor is the same as the circuit topology structure of the input stage amplification system.

[0023] Optionally, the inter-stage impedance matching network in the low noise amplifier consists of an eighth capacitor, a ninth capacitor and an eleventh inductor, and the eighth capacitor and the eleventh inductor are both grounded.

[0024] Optionally, the output impedance matching network includes a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a twelfth inductor and a thirteenth inductor, the eleventh capacitor and the twelfth inductor constitute a bypass series resonant network, the twelfth capacitor and the thirteenth inductor constitute a parallel resonant network, the twelfth inductor is grounded, and the tenth capacitor is connected to the parallel resonant network via the bypass series resonant network.

[0025] Optionally, the signal source is connected to the input impedance matching network via a first DC blocking capacitor, and the inter-stage matching network is connected to the output stage amplification system via a second DC blocking capacitor.

[0026] A construction device for a dual-band low-noise amplifier, comprising:

[0027] A low noise amplifier construction unit, used to construct a low noise amplifier, the low noise amplifier comprising a signal source, an input stage amplification system, an input impedance matching network, an output stage amplification system, an inter-stage impedance matching network and an output impedance matching network, the input stage amplification system comprising a first transistor with an adjustable size and a second transistor with an adjustable size, the output stage amplification system comprising a third transistor with an adjustable size and a fourth transistor with an adjustable size, the input stage amplification system being connected to the input impedance matching network, and the inter-stage impedance matching network being connected to the output impedance matching network through the output stage amplification system;

[0028] a gate width calculation unit, configured to calculate, during the operation of the low-noise amplifier, a gate width of the first transistor for reducing a noise coefficient of the low-noise amplifier according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low-noise amplifier, and a preset quality factor;

[0029] a first dual-transistor size determination unit, configured to determine the size of the first transistor according to the gate width of the first transistor and the preset gate length, and to determine the size of the second transistor to be the same as the size of the first transistor, so that the low-noise amplifier can continuously cover two preset signal frequency bands when the input stage amplification system cooperates with the input impedance matching network to reduce the noise coefficient of the low-noise amplifier based on the size of the first transistor and the size of the second transistor;

[0030] a second dual-transistor size determination unit, configured to determine the gate widths of both the third transistor and the fourth transistor to be smaller than the target gate width within a preset range of the gate width of the first transistor, and to determine the gate lengths of both the third transistor and the fourth transistor to be the preset gate lengths, to obtain the size of the third transistor and the size of the fourth transistor, so that the output impedance matching network, when the output stage amplification system cooperates with the inter-stage impedance matching network to reduce the power consumption of the low-noise amplifier based on the size of the third transistor and the size of the fourth transistor, suppresses the signal between the two preset signal frequency bands;

[0031] A transistor size adjustment unit is used to adjust the first transistor, the second transistor, the third transistor and the fourth transistor in the low-noise amplifier according to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, respectively, to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands.

[0032] By means of the above technical solution, the present application constructs a low-noise amplifier and during the operation of the low-noise amplifier, calculates the gate width of the first transistor for reducing the noise coefficient of the low-noise amplifier according to a preset gate length, the oxide layer capacitance per unit area of ​​the first transistor, the built-in impedance of the signal source, the operating frequency of the low-noise amplifier and a preset quality factor, determines the size of the first transistor according to the gate width of the first transistor and the preset gate length, determines the size of the second transistor to be the same as the size of the first transistor, determines the gate widths of both the third transistor and the fourth transistor to be a target gate width within a preset range smaller than the gate width of the first transistor, and determines the gate lengths of both the third transistor and the fourth transistor to be the preset gate length, obtains the size of the third transistor and the size of the fourth transistor, and adjusts the first transistor, the second transistor, the third transistor and the fourth transistor in the low-noise amplifier according to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, respectively, to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands. It can be seen that by adjusting the size of the first transistor and the second transistor in the input stage amplification system to a size that reduces the noise coefficient of the low noise amplifier, and adjusting the gate width of the third transistor and the fourth transistor in the output stage amplification system to be smaller than the gate width of the first transistor, the output impedance matching network in the dual-band low noise amplifier obtained after adjusting the size of each transistor can maximize the suppression of interference signals between two preset signal frequency bands. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0034] Figure 1 A schematic diagram of a process for implementing a dual-band low noise amplifier provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of simulation results of the noise coefficient of a dual-band low noise amplifier provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of simulation results of a power gain of a dual-band low noise amplifier provided in an embodiment of the present application;

[0037] Figure 4A schematic diagram of a circuit topology of an input stage amplification system provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of a circuit topology of an input impedance matching network provided in an embodiment of the present application;

[0039] Figure 6 A circuit topology diagram of an output stage amplification system provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a circuit topology of an inter-stage impedance matching network provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of a circuit topology of an output impedance matching network provided in an embodiment of the present application;

[0042] Fig. 9 A schematic diagram of a circuit topology of a dual-band low noise amplifier provided in an embodiment of the present application;

[0043] Fig.10 A schematic diagram of a dual-band low noise amplifier structure provided in an embodiment of the present application;

[0044] Fig.11 A schematic diagram of the structure of a dual-band low noise amplifier construction device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] The present application solution can be implemented based on a terminal with data processing capabilities, which can be a computer, server, etc.

[0047] Next, combine Figure 1 The method for constructing the dual-band low noise amplifier of the present application may include the following steps:

[0048] Step S110, constructing a low noise amplifier, wherein the low noise amplifier includes a signal source, an input stage amplification system, an input impedance matching network, an output stage amplification system, an inter-stage impedance matching network, and an output impedance matching network.

[0049] Specifically, the signal source can provide various input signals to the low noise amplifier, and the input stage amplification system can include an input stage amplification circuit and a DC bias circuit of the input stage amplification circuit. The input stage amplification circuit can adopt a two-stage cascade common source (CS-CS cascade) current multiplexing structure, and the current multiplexing structure can provide a sufficiently high gain without increasing the DC current and overall power consumption of the circuit by sharing a DC path.

[0050] The input stage amplification system may include a first transistor with adjustable size and a second transistor with adjustable size, the output stage amplification system may include a third transistor with adjustable size and a fourth transistor with adjustable size, the input stage amplification system may be connected to an input impedance matching network, and the inter-stage impedance matching network may be connected to the output impedance matching network through the output stage amplification system. The sizes of the first transistor and the second transistor may be adjusted within a predetermined size range.

[0051] With the cooperation of the input stage amplification system and the input impedance matching network, the low noise amplifier can continuously cover two preset signal frequency bands, such as signal frequency band F1: 1176MHz ~ 1268MHz and signal frequency band F2: 1561MHz ~ 1603MHz.

[0052] The output stage amplification system may include an output stage amplification circuit and a DC bias circuit of the output stage amplification circuit, which may cooperate with an inter-stage impedance matching network to increase the band edge attenuation of the input stage broadband amplification circuit, and match the input impedance of the output stage amplification circuit to the conjugate value of the output impedance of the input stage amplification circuit to achieve maximum power transmission.

[0053] The output impedance matching network may include a capacitor for adjusting the imaginary part of the output impedance, a bypass series resonant network, and a parallel resonant network. The parallel resonant network may suppress the passage of interference signals between F1 and F2 to filter out the interference signals.

[0054] Step S120: During the operation of the low-noise amplifier, the gate width of the first transistor for reducing the noise coefficient of the low-noise amplifier is calculated according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low-noise amplifier, and a preset quality factor.

[0055] It can be understood that the noise in the low noise amplifier can be reduced by optimizing the noise factor of the low noise amplifier, and thus the effect of reducing the noise factor in the low noise amplifier can be achieved by determining a transistor with an optimal size.

[0056] Specifically, the gate width of the first transistor used to reduce the noise figure of the low-noise amplifier can be calculated using a transistor gate width formula for optimal noise under power consumption constraints.

[0057] Step S130: Determine the size of the first transistor according to the gate width of the first transistor and the preset gate length, and determine that the size of the second transistor is the same as that of the first transistor.

[0058] Specifically, the preset gate length can be customized, such as 0.13um.

[0059] It can be understood that after determining the sizes of the first transistor and the second transistor, the low-noise amplifier can continuously cover two preset signal frequency bands (F1 and F2) when the input stage amplification system cooperates with the input impedance matching network to reduce the noise coefficient of the low-noise amplifier based on the size of the first transistor and the size of the second transistor.

[0060] Step S140, determine the gate widths of both the third transistor and the fourth transistor to be a target gate width within a preset range that is smaller than the gate width of the first transistor, and determine the gate lengths of both the third transistor and the fourth transistor to be the preset gate lengths, to obtain the size of the third transistor and the size of the fourth transistor.

[0061] Specifically, the target gate width may be half of the gate width of the first transistor.

[0062] It can be understood that after determining the sizes of the third transistor and the fourth transistor, the output impedance matching network can suppress the signal between the two preset signal frequency bands when the output stage amplification system cooperates with the inter-stage impedance matching network to reduce the power consumption of the low-noise amplifier based on the size of the third transistor and the size of the fourth transistor.

[0063] Step S150: According to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, the first transistor, the second transistor, the third transistor and the fourth transistor are respectively adjusted in the low-noise amplifier to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands.

[0064] Specifically, the noise coefficient of the constructed dual-band low noise amplifier is simulated, such as Figure 2 As shown, the simulation results of the noise figure NF are that the NF is less than 1.32dB in the F1 signal frequency band, and the NF is less than 1.36dB in the F2 signal frequency band.

[0065] Furthermore, the power gain of the constructed dual-band low noise amplifier is simulated, such as Figure 3 As shown, the simulation results of the power gain of the dual-band low noise amplifier are that the gains in the two signal bands F1 and F2 are both above 31dB, and the in-band flatness is less than 1dB.

[0066] The method for constructing a dual-band low noise amplifier provided in the present embodiment constructs a low noise amplifier and during the operation of the low noise amplifier, calculates the gate width of the first transistor for reducing the noise coefficient of the low noise amplifier according to a preset gate length, the oxide layer capacitance per unit area of ​​the first transistor, the built-in impedance of the signal source, the operating frequency of the low noise amplifier, and a preset quality factor; determines the size of the first transistor according to the gate width of the first transistor and the preset gate length, and determines the size of the second transistor to be the same as the size of the first transistor; determines the gate widths of both the third transistor and the fourth transistor to be a target gate width within a preset range smaller than the gate width of the first transistor, and determines the gate lengths of both the third transistor and the fourth transistor to be the preset gate length, obtains the size of the third transistor and the size of the fourth transistor; and adjusts the first transistor, the second transistor, the third transistor, and the fourth transistor in the low noise amplifier according to the size of the first transistor, the size of the second transistor, the size of the third transistor, and the size of the fourth transistor, respectively, to obtain a dual-band low noise amplifier for suppressing signals between the two preset signal frequency bands. It can be seen that by adjusting the sizes of the first transistor and the second transistor in the input stage amplification system to a size that reduces the noise coefficient of the low noise amplifier, and adjusting the gate widths of the third transistor and the fourth transistor in the output stage amplification system to be smaller than the gate width of the first transistor, the output impedance matching network in the dual-band low noise amplifier obtained after adjusting the sizes of each transistor can maximally suppress the interference signal between the two preset signal frequency bands, and the obtained dual-band low noise amplifier has the advantages of low noise coefficient and high gain.

[0067] In some embodiments of the present application, the process of calculating the gate width of the first transistor for reducing the noise coefficient of the low-noise amplifier according to the preset gate length, the unit area oxide layer capacitance of the first transistor, the built-in impedance of the signal source, the operating frequency of the low-noise amplifier and the preset quality factor mentioned in the above embodiment is introduced, and the process may include:

[0068] The gate width of the first transistor for reducing the noise figure of the low noise amplifier is calculated using the following formula:

[0069]

[0070] Wherein, ω is the operating frequency of the low noise amplifier, L is the preset gate length, C ox is the unit area oxide capacitance of the first transistor, R s is the built-in impedance of the signal source, Q sp For the preset quality factor, the built-in impedance of the signal source can be measured in real time or a preset value. For example, if a source impedance value of 50Ω is adopted, the value range of the preset quality factor can be between 3.5 and 5.5, such as taking the preset quality factor as 4.5.

[0071] In some embodiments of the present application, the input stage amplification system in the low noise amplifier mentioned in the above embodiment is described in detail. Figure 4 The input stage amplification system includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor M1 with adjustable size, a second transistor M2 with adjustable size, a fifth transistor M5 with adjustable size, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0072] Specifically, the first inductor L1 and the first capacitor C1 are connected in series between the drain of the first transistor M1 and the gate of the second transistor M2, a parallel LC network is connected in series between the drain of the first transistor M1 and the source of the second transistor M2, the parallel LC network is formed by the second inductor L2 and the second capacitor C2 being connected in parallel, the source of the second transistor M2 is connected to the third capacitor C3 for bypass, the source of the first transistor M1 is connected to the third inductor L3, the first transistor M1, the third transistor M5, the first resistor R1 and the second resistor R2 form a current mirror structure, the gate of the second transistor M2 is connected to the third resistor R3, the fourth inductor L4 connected to the drain of the second transistor M2 is connected in series with the fourth resistor R4, and the source of the fifth transistor M5, the third inductor L3 and the third capacitor C3 are all grounded.

[0073] It can be understood that the inductor L1 and the coupling capacitor C1 are connected in series between the drain of M1 and the gate of M2 to generate resonance at the high end of the operating frequency band, providing a low impedance path for the drain of M1, so that the signal is output from the drain of M1 and coupled to the gate of M2 through C1, achieving two signal amplifications, thereby improving the gain of the amplifier. A parallel LC network composed of L2 and C2 is added between the drain of M1 and the source of M2 to generate an AC high impedance, thereby preventing the RF signal from leaking from the drain of M1 to the source of M2. At the same time, C3 provides AC grounding for M2, so the introduction of L1, C1, L2, C2, and C3 constitutes a current multiplexing structure, so that the common source and common gate connection of M1 and M2 becomes a two-stage common source amplifier structure. Connect an L3 to the source of M1, so that by adjusting the transconductance g of M1 m and gate-source capacitance C gs , which can provide low noise while achieving 50Ω input impedance. M1, M5, R1 and R2 form a current mirror structure to provide a stable bias voltage for M1. R3 provides a bias voltage for M2 while preventing the AC signal from short-circuiting to the ground. A series circuit of R4 and L4 is connected to the gate of M2, so that M2, R4 and L4 form a parallel peaking common source amplifier, which can expand the working bandwidth of the circuit.

[0074] In some embodiments of the present application, the input impedance matching network in the low noise amplifier mentioned in the above embodiment is described in detail. Figure 5 , the input impedance matching network may include a fourth capacitor C4, a fifth inductor L5 and a sixth inductor L6.

[0075] Specifically, the fourth capacitor C7, the fifth inductor L9 and the sixth inductor L10 form a T-type LCL network, and the fourth capacitor is grounded.

[0076] It can be understood that by using passive components L9, L10 and C7 to form a T-type matching network with a low quality factor, a broadband low noise amplifier can be realized so that the low noise amplifier continuously covers the F1 and F2 signal frequency bands.

[0077] In some embodiments of the present application, the output stage amplification system in the low noise amplifier mentioned in the above embodiment is described in detail. Figure 6 The output stage amplification system may include a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fourth transistor M4 with an adjustable size, a third transistor M3 with an adjustable size, a sixth transistor M6 with an adjustable size, a seventh inductor L5, an eighth inductor L6, a ninth inductor L7, a tenth inductor L8, a fifth capacitor C5, a sixth capacitor C6 and a seventh capacitor C4.

[0078] Specifically, the circuit topology structure formed by the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the fourth transistor M4 with adjustable size, the third transistor M3 with adjustable size, the sixth transistor M6 with adjustable size, the seventh inductor L5, the eighth inductor L6, the ninth inductor L7, the tenth inductor L8, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C4 can be the same as the circuit topology structure of the input stage amplification system.

[0079] It is understandable that in order to reduce the power consumption of the low noise amplifier circuit, M3 and M4 can be selected to be smaller than M1 and M2. Therefore, it can be determined that the gate width of M3 and M4 is half of the gate width of M1 and M2, and their gate length is the same as the gate length of M1 and M2, such as M1, M2, M3 and M4 are all determined to have a gate length of 0.13um.

[0080] In some embodiments of the present application, the inter-stage impedance matching network in the low noise amplifier mentioned in the above embodiment is described in detail. Figure 7 , the inter-stage impedance matching network can be composed of an eighth capacitor C9, a ninth capacitor C8 and an eleventh inductor L11.

[0081] Wherein, the eighth capacitor C9 and the eleventh inductor L11 are both grounded.

[0082] It can be understood that by using passive components L11, C8 and C9 to form an inter-stage impedance matching network with a slightly higher quality factor than the input impedance matching network, the band edge attenuation of the input stage broadband amplifier circuit is increased. At the same time, C8 also plays a role in DC isolation. The inter-stage impedance matching network can match the input impedance of the output stage amplifier circuit to the conjugate value of the output impedance of the input stage amplifier circuit to achieve maximum power transmission.

[0083] In some embodiments of the present application, the output impedance matching network in the low noise amplifier mentioned in the above embodiment is described in detail. Figure 8 , the output impedance matching network may include a tenth capacitor C11, an eleventh capacitor C12, a twelfth capacitor C13, a twelfth inductor L12 and a thirteenth inductor L13.

[0084] Specifically, the eleventh capacitor C12 and the twelfth inductor L12 form a bypass series resonant network, the twelfth capacitor C13 and the thirteenth inductor L13 form a parallel resonant network, the twelfth inductor L12 is grounded, and the tenth capacitor C11 can be connected to the parallel resonant network through the bypass series resonant network.

[0085] It can be understood that L12 and C12 constitute a bypass-type series resonant network, so that the resonant frequency of the bypass-type series resonant network can be set to the middle frequency of the interference signal frequency band (such as 1415MHz), so that the impedance of the LC series resonant circuit to the interference frequency is extremely small, and the interference signal can be bypassed to the ground through the LC series resonant circuit. The L13, C13 parallel resonant network is connected in series to the output channel of the low-noise amplifier, and its resonant frequency is also set to the middle frequency of the interference signal frequency band (such as 1415MHz), so that the impedance of the LC parallel resonant circuit to the interference frequency is extremely large, suppressing the interference signal components that are not bypassed to the ground from the series resonant circuit composed of L12 and C12, so as to filter out the interference signal output. C11 can adjust the imaginary part of the output impedance. When working in the F1 frequency band (one of the two preset signal frequency bands), the parallel resonant network composed of L13 and C13 can be equivalent to an inductor. When working in the F2 frequency band (one of the two preset signal frequency bands), the parallel resonant network composed of L13 and C13 can be equivalent to a capacitor, so that both the F1 and F2 frequency bands can be equivalent to a T-type impedance matching network, realizing output impedance matching of the two frequency bands.

[0086] In some embodiments of the present application, the low noise amplifier mentioned in the above embodiments is described in detail. Fig. 9 In the low noise amplifier, the signal source can be connected to the input impedance matching network through a first DC blocking capacitor C14, the inter-stage matching network can be connected to the output stage amplification system through a second DC blocking capacitor C10, and the output impedance matching network can be connected to the output end of the low noise amplifier through a third DC blocking capacitor C15.

[0087] The following is a description of a construction device for implementing a low-noise amplifier provided in an embodiment of the present application. The construction device for implementing a low-noise amplifier described below and the construction method for implementing a low-noise amplifier described above can refer to each other.

[0088] See also Fig.10 , Fig.10 A schematic diagram of the structure of a construction device for realizing a low noise amplifier disclosed in an embodiment of the present application.

[0089] like Fig.10 As shown, the device may include:

[0090] A low noise amplifier construction unit 11 is used to construct a low noise amplifier, the low noise amplifier comprising a signal source, an input stage amplification system, an input impedance matching network, an output stage amplification system, an inter-stage impedance matching network and an output impedance matching network, the input stage amplification system comprising a first transistor with an adjustable size and a second transistor with an adjustable size, the output stage amplification system comprising a third transistor with an adjustable size and a fourth transistor with an adjustable size, the input stage amplification system being connected to the input impedance matching network, and the inter-stage impedance matching network being connected to the output impedance matching network through the output stage amplification system;

[0091] A gate width calculation unit 12, used to calculate the gate width of the first transistor for reducing the noise coefficient of the low noise amplifier according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low noise amplifier and a preset quality factor during the operation of the low noise amplifier;

[0092] A first dual-transistor size determination unit 13 is used to determine the size of the first transistor according to the gate width of the first transistor and the preset gate length, and to determine the size of the second transistor to be the same as the first transistor, so that the low-noise amplifier can continuously cover two preset signal frequency bands when the input stage amplification system cooperates with the input impedance matching network to reduce the noise coefficient of the low-noise amplifier based on the size of the first transistor and the size of the second transistor;

[0093] A second dual-transistor size determination unit 14 is used to determine the gate widths of both the third transistor and the fourth transistor to be smaller than the target gate width within a preset range of the gate width of the first transistor, and to determine the gate lengths of both the third transistor and the fourth transistor to be the preset gate lengths, to obtain the size of the third transistor and the size of the fourth transistor, so that the output impedance matching network, when the output stage amplification system cooperates with the inter-stage impedance matching network to reduce the power consumption of the low-noise amplifier based on the size of the third transistor and the size of the fourth transistor, suppresses the signal between the two preset signal frequency bands;

[0094] The transistor size adjustment unit 15 is used to adjust the first transistor, the second transistor, the third transistor and the fourth transistor in the low-noise amplifier according to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, respectively, to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands.

[0095] The dual-band low noise amplifier construction device provided in the embodiment of the present application can be applied to a dual-band low noise amplifier construction device, such as a terminal: a mobile phone, a computer, etc. Optionally, Fig.11 The hardware structure diagram of the dual-band low noise amplifier construction device is shown in FIG. Fig.11 , the hardware structure of the construction device of the dual-band low noise amplifier may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4;

[0096] In the embodiment of the present application, the number of the processor 1, the communication interface 2, the memory 3, and the communication bus 4 is at least one, and the processor 1, the communication interface 2, and the memory 3 communicate with each other through the communication bus 4;

[0097] The processor 1 may be a central processing unit CPU, or an application-specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention, etc.;

[0098] The memory 3 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory;

[0099] The memory stores a program, and the processor can call the program stored in the memory, wherein the program is used to:

[0100] Constructing a low-noise amplifier, the low-noise amplifier comprising a signal source, an input-stage amplification system, an input impedance matching network, an output-stage amplification system, an inter-stage impedance matching network, and an output impedance matching network, the input-stage amplification system comprising a first transistor with an adjustable size and a second transistor with an adjustable size, the output-stage amplification system comprising a third transistor with an adjustable size and a fourth transistor with an adjustable size, the input-stage amplification system being connected to the input impedance matching network, and the inter-stage impedance matching network being connected to the output impedance matching network through the output-stage amplification system;

[0101] During the operation of the low noise amplifier, the gate width of the first transistor for reducing the noise coefficient of the low noise amplifier is calculated according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low noise amplifier, and a preset quality factor;

[0102] Determine the size of the first transistor according to the gate width of the first transistor and the preset gate length, and determine the size of the second transistor to be the same as the size of the first transistor, so that the low-noise amplifier can continuously cover two preset signal frequency bands when the input stage amplification system cooperates with the input impedance matching network to reduce the noise coefficient of the low-noise amplifier based on the size of the first transistor and the size of the second transistor;

[0103] The gate widths of the third transistor and the fourth transistor are both determined to be smaller than the target gate width within the preset range of the gate width of the first transistor, and the gate lengths of the third transistor and the fourth transistor are both determined to be the preset gate length, so as to obtain the size of the third transistor and the size of the fourth transistor, so that the output impedance matching network can suppress the signal between the two preset signal frequency bands when the output stage amplification system cooperates with the inter-stage impedance matching network to reduce the power consumption of the low noise amplifier based on the size of the third transistor and the size of the fourth transistor;

[0104] According to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, the first transistor, the second transistor, the third transistor and the fourth transistor are adjusted respectively in the low-noise amplifier to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands.

[0105] Optionally, the detailed functions and extended functions of the program may refer to the above description.

[0106] The embodiment of the present application further provides a storage medium, which may store a program suitable for execution by a processor, wherein the program is used to:

[0107] Constructing a low-noise amplifier, the low-noise amplifier comprising a signal source, an input-stage amplification system, an input impedance matching network, an output-stage amplification system, an inter-stage impedance matching network, and an output impedance matching network, the input-stage amplification system comprising a first transistor with an adjustable size and a second transistor with an adjustable size, the output-stage amplification system comprising a third transistor with an adjustable size and a fourth transistor with an adjustable size, the input-stage amplification system being connected to the input impedance matching network, and the inter-stage impedance matching network being connected to the output impedance matching network through the output-stage amplification system;

[0108] During the operation of the low noise amplifier, the gate width of the first transistor for reducing the noise coefficient of the low noise amplifier is calculated according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low noise amplifier, and a preset quality factor;

[0109] Determine the size of the first transistor according to the gate width of the first transistor and the preset gate length, and determine the size of the second transistor to be the same as the size of the first transistor, so that the low-noise amplifier can continuously cover two preset signal frequency bands when the input stage amplification system cooperates with the input impedance matching network to reduce the noise coefficient of the low-noise amplifier based on the size of the first transistor and the size of the second transistor;

[0110] The gate widths of the third transistor and the fourth transistor are both determined to be smaller than the target gate width within the preset range of the gate width of the first transistor, and the gate lengths of the third transistor and the fourth transistor are both determined to be the preset gate length, so as to obtain the size of the third transistor and the size of the fourth transistor, so that the output impedance matching network can suppress the signal between the two preset signal frequency bands when the output stage amplification system cooperates with the inter-stage impedance matching network to reduce the power consumption of the low noise amplifier based on the size of the third transistor and the size of the fourth transistor;

[0111] According to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, the first transistor, the second transistor, the third transistor and the fourth transistor are adjusted respectively in the low-noise amplifier to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands.

[0112] Optionally, the detailed functions and extended functions of the program may refer to the above description.

[0113] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0114] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can refer to each other.

[0115] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for constructing a dual-band low noise amplifier, characterized in that: include: Constructing a low-noise amplifier, the low-noise amplifier comprising a signal source, an input-stage amplification system, an input impedance matching network, an output-stage amplification system, an inter-stage impedance matching network, and an output impedance matching network, the input-stage amplification system comprising a first transistor with an adjustable size and a second transistor with an adjustable size, the output-stage amplification system comprising a third transistor with an adjustable size and a fourth transistor with an adjustable size, the input-stage amplification system being connected to the input impedance matching network, and the inter-stage impedance matching network being connected to the output impedance matching network through the output-stage amplification system; During the operation of the low noise amplifier, the gate width of the first transistor for reducing the noise coefficient of the low noise amplifier is calculated according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low noise amplifier, and a preset quality factor; Determine the size of the first transistor according to the gate width of the first transistor and the preset gate length, and determine the size of the second transistor to be the same as the size of the first transistor, so that the low-noise amplifier can continuously cover two preset signal frequency bands when the input stage amplification system cooperates with the input impedance matching network to reduce the noise coefficient of the low-noise amplifier based on the size of the first transistor and the size of the second transistor; The gate widths of the third transistor and the fourth transistor are both determined to be smaller than the target gate width within the preset range of the gate width of the first transistor, and the gate lengths of the third transistor and the fourth transistor are both determined to be the preset gate length, so as to obtain the size of the third transistor and the size of the fourth transistor, so that the output impedance matching network can suppress the signal between the two preset signal frequency bands when the output stage amplification system cooperates with the inter-stage impedance matching network to reduce the power consumption of the low noise amplifier based on the size of the third transistor and the size of the fourth transistor; According to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, the first transistor, the second transistor, the third transistor and the fourth transistor are adjusted respectively in the low-noise amplifier to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands.

2. The method according to claim 1, characterized in that Calculating the gate width of the first transistor for reducing the noise coefficient of the low noise amplifier according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low noise amplifier, and a preset quality factor, comprising: The gate width of the first transistor for reducing the noise figure of the low noise amplifier is calculated using the following formula: Wherein, ω is the operating frequency of the low noise amplifier, L is the preset gate length, C ox is the unit area oxide capacitance of the first transistor, R s is the built-in impedance of the signal source, Q sp is the preset quality factor.

3. The method according to claim 1, characterized in that The target gate width is half of the gate width of the first transistor.

4. The method according to claim 1, characterized in that: The input stage amplification system in the low noise amplifier also includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth transistor with adjustable size, a first inductor, a second inductor, a third inductor, a fourth inductor, a first capacitor, a second capacitor and a third capacitor. The first inductor and the first capacitor are connected in series between the drain of the first transistor and the gate of the second transistor. A parallel LC network is connected in series between the drain of the first transistor and the source of the second transistor. The parallel LC network is formed by the second inductor and the second capacitor in parallel. The source of the second transistor is connected to the third capacitor for bypass. The source of the first transistor is connected to the third inductor. The first transistor, the fifth transistor, the first resistor and the second resistor form a current mirror structure. The gate of the second transistor is connected to the third resistor. The fourth inductor connected to the drain of the second transistor is connected in series with the fourth resistor. The source of the fifth transistor, the third inductor and the third capacitor are all grounded.

5. The method according to claim 1, characterized in that The input impedance matching network in the low noise amplifier includes a fourth capacitor, a fifth inductor and a sixth inductor. The fourth capacitor, the fifth inductor and the sixth inductor form a T-type LCL network. The fourth capacitor is grounded.

6. The method according to claim 4, characterized in that The output stage amplification system in the low noise amplifier also includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a sixth transistor of adjustable size, a seventh inductor, an eighth inductor, a ninth inductor, a tenth inductor, a fifth capacitor, a sixth capacitor and a seventh capacitor. The circuit topology structure formed by the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the third transistor, the fourth transistor, the sixth transistor, the seventh inductor, the eighth inductor, the ninth inductor, the tenth inductor, the fifth capacitor, the sixth capacitor and the seventh capacitor is the same as the circuit topology structure of the input stage amplification system.

7. The method according to claim 1, characterized in that The inter-stage impedance matching network in the low noise amplifier is composed of an eighth capacitor, a ninth capacitor and an eleventh inductor, and the eighth capacitor and the eleventh inductor are both grounded.

8. The method according to claim 1, characterized in that The output impedance matching network includes a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a twelfth inductor and a thirteenth inductor, the eleventh capacitor and the twelfth inductor form a bypass series resonant network, the twelfth capacitor and the thirteenth inductor form a parallel resonant network, the twelfth inductor is grounded, and the tenth capacitor is connected to the parallel resonant network via the bypass series resonant network.

9. The method according to any one of claims 1 to 8, characterized in that: The signal source is connected to the input impedance matching network via a first DC blocking capacitor, and the inter-stage impedance matching network is connected to the output stage amplification system via a second DC blocking capacitor.

10. A device for constructing a dual-band low noise amplifier, characterized in that: include: A low noise amplifier construction unit, used to construct a low noise amplifier, the low noise amplifier comprising a signal source, an input stage amplification system, an input impedance matching network, an output stage amplification system, an inter-stage impedance matching network and an output impedance matching network, the input stage amplification system comprising a first transistor with an adjustable size and a second transistor with an adjustable size, the output stage amplification system comprising a third transistor with an adjustable size and a fourth transistor with an adjustable size, the input stage amplification system being connected to the input impedance matching network, and the inter-stage impedance matching network being connected to the output impedance matching network through the output stage amplification system; a gate width calculation unit, configured to calculate, during the operation of the low-noise amplifier, a gate width of the first transistor for reducing a noise coefficient of the low-noise amplifier according to a preset gate length, a unit area oxide layer capacitance of the first transistor, a built-in impedance of the signal source, an operating frequency of the low-noise amplifier, and a preset quality factor; a first dual-transistor size determination unit, configured to determine the size of the first transistor according to the gate width of the first transistor and the preset gate length, and to determine the size of the second transistor to be the same as the size of the first transistor, so that the low-noise amplifier can continuously cover two preset signal frequency bands when the input stage amplification system cooperates with the input impedance matching network to reduce the noise coefficient of the low-noise amplifier based on the size of the first transistor and the size of the second transistor; a second dual-transistor size determination unit, configured to determine the gate widths of both the third transistor and the fourth transistor to be smaller than the target gate width within a preset range of the gate width of the first transistor, and to determine the gate lengths of both the third transistor and the fourth transistor to be the preset gate lengths, to obtain the size of the third transistor and the size of the fourth transistor, so that the output impedance matching network, when the output stage amplification system cooperates with the inter-stage impedance matching network to reduce the power consumption of the low-noise amplifier based on the size of the third transistor and the size of the fourth transistor, suppresses the signal between the two preset signal frequency bands; A transistor size adjustment unit is used to adjust the first transistor, the second transistor, the third transistor and the fourth transistor in the low-noise amplifier according to the size of the first transistor, the size of the second transistor, the size of the third transistor and the size of the fourth transistor, respectively, to obtain a dual-band low-noise amplifier for suppressing signals between the two preset signal frequency bands.

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