LTCC duplexer for 5G

Abstract

A kind of LTCC duplexer for 5G, including base body, terminal head being arranged in the four around of base body and circuit layer being arranged in the inside of base body, the circuit layer of the inside of the base body is in laminated structure, the special structure of the duplexer is designed by lumped parameter, it is combined by low-pass filter and band-pass filter, low-pass filter mainly separates out low frequency band signal, band-pass filter mainly separates out high frequency band signal, the frequency division function of low frequency signal and high frequency signal is effectively realized in the application, with low loss, high suppression, high isolation, high reliability, low cost, consistency is good and is suitable for large-scale production etc.Advantages, in addition, it also adapts to the development trend of new electronic component integration, miniaturization.

Description

Technical Field

[0001] The present invention relates to a new LTCC duplexer for 5G, which is used for wireless connection of 5G mobile communication equipment, tablet computers and various other communication devices. Background Art

[0002] Low-Temperature Co-fired Ceramic (LTCC) technology involves sintering ceramic powder at low temperatures into a dense, precisely thickened green tape, which serves as a circuit substrate. The tape is then used to create the required circuit pattern using processes such as laser drilling, micropore grouting, and precision conductor paste printing. Multiple passive components are then embedded within the tape, laminated together, and sintered at approximately 900°C to create independent, individual passive devices.

[0003] With the widespread adoption of 5G technology, mobile communications are placing urgent demands on electronic components for diverse performance, miniaturized packaging, and high reliability. RF microwave components designed and manufactured using LTCC technology, including filters, duplexers, antennas, couplers, baluns, receiver front-end modules, and antenna switch modules, are widely used in various communications equipment due to their excellent high-frequency characteristics, high-speed transmission, high integration, and high reliability. Summary of the Invention

[0004] The present invention provides a 5G LTCC low-insertion-loss, high-suppression duplexer. The duplexer adopts a special structure of lumped parameter design and is composed of a low-pass filter and a band-pass filter. The low-pass filter mainly separates low-frequency signals, and the band-pass filter mainly separates high-frequency signals. This duplexer has the advantages of low loss, high suppression, and high isolation.

[0005] The technical solution adopted by the present invention to solve the technical problem is: a new LTCC low insertion loss, high suppression duplexer, including a substrate, connection terminals arranged around the outside of the substrate and a circuit layer arranged inside the substrate, wherein the circuit layer inside the substrate has a laminated structure.

[0006] The application provides a 5G LTCC duplexer, wherein signals enter from a first port and output from a second port, the link is a second low-pass filter, and low-frequency signals are separated; signals enter from the first port and output from a third port, the link is a band-pass filter, and high-frequency signals are separated.

[0007] The first port ① is a common port of the duplexer, the second port ② is a low-frequency input / output port, and the third port ③ is a high-frequency input / output port.

[0008] The duplexer comprises a base body, and the base body is externally provided with a first grounding port (P1), a second grounding port (P3), a third grounding port (P5), a common port (P2), a low-frequency band-pass input / output port (P4) and a high-frequency input / output port (P6), the base body is internally provided with a first band-pass filter for separating high-frequency signals between the common port (P2) and the high-frequency input / output port (P6), and the base body is internally provided with a second low-pass filter for separating low-frequency signals between the common port (P2) and the low-frequency band-pass input / output port (P4), Mark is a direction mark, and the base body is internally provided with twelve circuit layers in a laminated structure.

[0009] The application provides a 5G LTCC duplexer, wherein signals enter from a first port and output from a second port, the link is a second low-pass filter, and low-frequency signals are separated; signals enter from the first port and output from a third port, the link is a band-pass filter, and high-frequency signals are separated.

[0010] The first layer (1) is formed by printing three mutually independent first-layer first metal conductor capacitor substrates (1-1), first-layer second metal conductor capacitor substrates (1-2a & 1-2b), and first-layer third metal conductor capacitor substrates (1-3) on a ceramic dielectric substrate. The first-layer first connection terminal (1a), first-layer second connection terminal (1b), first-layer third connection terminal (1c), first-layer fourth connection terminal (1d), first-layer fifth connection terminal (1e), and first-layer sixth connection terminal (1f) provided in the layer are respectively connected to the high-frequency input / output port (P6), the third ground port (P5), the low-frequency band-pass input / output port (P4), the second ground port (P3), the common port (P2), and the first ground port (P1);

[0011] The second layer (2) has five mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are respectively the second layer first capacitor substrate (2-1), the second layer second capacitor substrate (2-2), the second layer third capacitor substrate (2-3), the second layer fourth capacitor substrate (2-4) and the second layer first dummy connection terminal (2b), wherein the second layer first capacitor substrate (2-1) is connected to the high frequency band input / output port (P6) through the second layer first connection terminal (2a), and the second layer second dummy connection terminal (2b) is connected to the first ground port (P1);

[0012] The third layer (3) has six mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are respectively the third layer first capacitor substrate (3-1), the third layer second capacitor substrate (3-2), the third layer third capacitor substrate (3-3), the third layer fourth capacitor substrate (3-4), the third layer fifth capacitor substrate (3-5) and the third layer first dummy connection terminal (3c). The third layer first capacitor substrate (3-1) is connected to the fourth metal via (16), the third layer first connection terminal (3a), the third layer second connection terminal (3b), the third layer first dummy connection terminal (3c) and the third layer fourth connection terminal (3d) are respectively connected to the third ground port (P5), the low frequency band pass input / output port (P4), the second ground port (P3) and the common port (P2), and the third layer fifth capacitor substrate (3-5a) is connected to the second layer second capacitor substrate (2-2) through the third metal via (15);

[0013] The fourth layer (4) is provided with four mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are respectively the fourth layer first capacitor substrate (4-1), the fourth layer second capacitor substrate (4-2a & 4-2b), the fourth layer third capacitor substrate (4-3) and the fourth layer fourth capacitor substrate (4-4). The layer also has a fourth metal via (16) and a fifth metal via (17). The fourth layer first connection terminal (4a) on the layer is connected to the high frequency band input / output port (P6), the fourth layer second connection terminal (4b) is connected to the third ground port (P5), the fourth layer third connection terminal (4c) is connected to the first ground port (P1), the fourth layer fourth connection terminal (4d) is connected to the common port (P2), and the fourth layer first capacitor substrate (4-1) is connected to the second layer third capacitor substrate (2-3) through the first metal via (13);

[0014] The fifth layer (5) has two mutually insulated first capacitor substrates (5-1) and second capacitor substrates (5-2) printed on a ceramic dielectric substrate. The first capacitor substrate (5-1) and the fourth metal via (16) are connected via a fifth metal via (17), a sixth metal via (18) and a seventh metal via (19). The first connection terminal (5a) of the fifth layer is connected to a low-frequency bandpass input / output port (P4), and the second connection terminal (5b) of the fifth layer is connected to a low-frequency bandpass input / output port (P4).

[0015] The sixth layer (6) has two mutually insulated metal coils printed on a ceramic dielectric substrate, namely the first inductor coil (6-1 & 6-2) of the sixth layer and the second inductor coil (6-3) of the sixth layer, and is also provided with a fifth metal via (17) and a seventh metal through hole (19), wherein the first connection terminal (6-1a) of the sixth layer, the second connection terminal (6-1b) of the sixth layer, and the third connection terminal (6-2a) of the sixth layer are respectively connected to the eighth metal via (20), the tenth metal via (22), and the ninth metal via (21), wherein the fourth connection terminal (6-3a) of the sixth layer and the fifth connection terminal (6-3b) of the sixth layer are respectively connected to the sixth metal through hole (18) and the eleventh metal through hole (24);

[0016] The seventh layer (7) has two mutually insulated metal coils printed on a ceramic dielectric substrate, namely the first inductor coil (7-1) of the seventh layer and the second inductor coil (7-2) of the seventh layer. The first connection terminal (7-1a), the second connection terminal (7-1b), the third connection terminal (7-2a) and the fourth connection terminal (7-2b) of the seventh layer are respectively connected to the thirteenth connection point column (26), the tenth metal via (22), the fourteenth connection point column (23) and the twelfth connection point column (25). The layer also has a fifth metal via (17), a seventh metal through hole (19) and a ninth metal via (21).

[0017] The eighth layer (8) is printed on a ceramic dielectric substrate with an eighth layer first dummy connection terminal (8a) and two mutually insulated metal coils, namely the eighth layer first inductance coil (8-1) and the eighth layer second inductance coil (8-2), and is also provided with an eighth layer first connection terminal (8-1a), an eighth layer second connection terminal (8-1b), an eighth layer third connection terminal (8-2a), and an eighth layer fourth connection terminal (8b); wherein the eighth layer first connection terminal (8-1a) and the eighth layer second connection terminal (8-1b) are connected to the thirteenth connection point column (26) and the seventh metal through hole 19, the eighth layer first dummy connection terminal (8a) is connected to the low-frequency band pass input / output port (P4), and the eighth layer fourth connection terminal (8b) is connected to the second ground port (P3);

[0018] The ninth layer (9) is printed with a ninth metal via (21), a ninth layer first metal coil (9-1), and a ninth layer second metal coil (9-2) on the ceramic dielectric substrate; the ninth layer first connection terminal (9-1a), the ninth layer second connection terminal (9-1b), the ninth layer third connection terminal (9-2a), and the ninth layer fourth connection terminal (9-2b) are respectively connected to the fifteenth metal via (27), the eleventh metal via (24), the fifth metal via (17), and the sixteenth metal via (28);

[0019] The tenth layer (10) has three mutually insulated metal coils printed on a ceramic dielectric substrate, namely the tenth layer first inductor coil (10-1), the tenth layer second inductor coil (10-2) and the tenth layer third inductor coil (10-3), and the tenth layer first connection terminal (10-1a), the tenth layer second connection terminal (10-1b), the tenth layer third connection terminal (10-2a), the tenth layer fourth connection terminal (10-2b), the tenth layer fifth connection terminal (10-3a) and the tenth layer sixth connection terminal (10-3b) located in the layer are connected to the seventh metal through hole (19), the ninth metal via hole (21), the nineteenth metal via hole (31), the sixteenth metal via hole (28), the eighteenth metal via hole (30) and the fifteenth metal via hole (27) respectively;

[0020] The eleventh layer (11) has three mutually insulated metal coils printed on a ceramic dielectric substrate, namely the first inductor coil (11-1) of the eleventh layer, the second inductor coil (11-2) of the eleventh layer, and the third inductor coil (11-3) of the eleventh layer. The first connection terminal (11-1a) of the eleventh layer, the second connection terminal (11-1b) of the eleventh layer, the third connection terminal (11-2a) of the eleventh layer, the fourth connection terminal (11-2b) of the eleventh layer, the first and fifth connection terminals (11-3a) of the eleventh layer, and the sixth connection terminal (11-3b) of the eleventh layer located on the layer are respectively connected to the twentieth metal via (32), the seventeenth metal via (29), the nineteenth metal via (31), the twenty-second metal via (34), the eighteenth metal via (30), and the twenty-first metal via (33);

[0021] The twelfth layer (12) has three mutually insulated metal coils printed on a ceramic dielectric substrate, namely the twelfth layer first inductor coil (12-1), the twelfth layer second inductor coil (12-2), and the twelfth layer third inductor coil (12-3); the twelfth layer first connection terminal (12-1a), the twelfth layer second connection terminal (12-2a), and the twelfth layer third connection terminal (12-3a) located in the layer are respectively connected to the twentieth metal via (32), the twenty-second metal via (34), and the twenty-first metal via (33); the twelfth layer first connection terminal (12a), the twelfth layer second connection terminal (12b), the twelfth layer third connection terminal (12c), the twelfth layer fourth connection terminal (12d), and the twelfth layer fifth connection terminal (12e) are respectively connected to the high-frequency band input / output port (P6), the third ground port (P5), the second ground port (P3), the common port (P2), and the first ground port (P1).

[0022] The present invention has the following beneficial effects: Based on LTCC (low-temperature co-fired ceramic) technology, the present invention utilizes a lumped parameter model to design a novel 5G LTCC low-insertion-loss, high-rejection duplexer that meets the specific electrical performance requirements. This invention effectively achieves the frequency division function between low-frequency and high-frequency signals, and offers advantages such as low loss, high rejection, high isolation, high reliability, low cost, excellent consistency, and suitability for large-scale production. Furthermore, it adapts to the emerging trend of electronic component integration and miniaturization.

[0023] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of an equivalent circuit of a new LTCC duplexer for 5G use in the present invention;

[0025] Figure 2 A new type of LTCC duplexer appearance structure for 5G;

[0026] Figure 3 A new type of LTCC duplexer internal structure for 5G;

[0027] Figure 4 A new type of LTCC duplexer electrical characteristic curve for 5G;

[0028] Figure 5 A first layer circuit plane structure diagram of the present application;

[0029] Figure 6 A second layer circuit plane structure diagram of the present application;

[0030] Figure 7 A metal via connection plane structure diagram between the second layer and the third layer circuits of the present application;

[0031] Figure 8 A third layer circuit plane structure diagram of the present application;

[0032] Figure 9 A metal via connection plane structure diagram between the third layer and the fourth layer circuits of the present application;

[0033] Figure 10 A fourth layer circuit plane structure diagram of the present application;

[0034] Figure 11 A metal via connection plane structure diagram between the fourth layer and the fifth layer of the present application;

[0035] Figure 12 A fifth layer circuit plane structure diagram of the present application;

[0036] Figure 13 A metal via connection plane structure diagram between the fifth layer and the sixth layer of the present application;

[0037] Figure 14 A sixth layer circuit plane structure diagram of the present application;

[0038] Figure 15 A metal via connection plane structure diagram between the sixth layer and the seventh layer of the present application;

[0039] Figure 16 A seventh layer circuit plane structure diagram of the present application;

[0040] Figure 17 A metal via connection plane structure diagram between the seventh layer and the eighth layer of the present application;

[0041] Figure 18 This is a schematic diagram of the planar structure of the eighth layer circuit of the present invention;

[0042] Figure 19 Schematic diagram of the metal via plane structure between the eighth and ninth layers of the present invention;

[0043] Figure 20 This is a schematic diagram of the planar structure of the ninth layer circuit of the present invention;

[0044] Figure 21 This is a schematic diagram of the planar structure of the metal via connection between the ninth layer and the tenth layer of the present invention;

[0045] Figure 22 This is a schematic diagram of the planar structure of the tenth layer circuit of the present invention;

[0046] Figure 23 This is a schematic diagram of the planar structure of metal via connections between the tenth and eleventh layers of the present invention;

[0047] Figure 24 This is a schematic diagram of the circuit plan structure of the eleventh layer of the present invention;

[0048] Figure 25 Schematic diagram of the planar structure of metal via connections between the eleventh and twelfth layers of the present invention;

[0049] Figure 26 This is a schematic diagram of the planar structure of the twelfth layer circuit of the present invention;

[0050] Numbering in the figure, the first layer circuit plane structure (1), the second layer circuit plane structure (2), the third layer circuit plane structure (3), the fourth layer circuit plane structure (4), the fifth layer circuit plane structure (5), the sixth layer circuit plane structure (6), the seventh layer circuit plane structure (7), the eighth layer circuit plane structure (8), the ninth layer circuit plane structure (9), the tenth layer circuit plane structure (10), the eleventh layer circuit plane structure (11), the twelfth layer circuit plane structure (12), the first metal via (13) - used to connect the second layer third capacitor substrate (2-3) and the fourth layer first capacitor substrate (4-1), the second metal via (14) - used to connect the second layer third capacitor substrate (2-3) and the capacitor substrate 4- 2b, a third metal via (15) for connecting the second capacitor substrate (2-2) of the second layer and the fifth capacitor substrate (3-5a) of the third layer, a fourth metal via (16) for connecting the first capacitor substrate (3-1) of the third layer and the first capacitor substrate (5-1) of the fifth layer, a fifth metal via (17) for connecting the fifth capacitor substrate (3-5) of the third layer and the second metal coil (9-2) of the ninth layer, a sixth metal through hole (18) for connecting the first capacitor substrate (4-1) of the fourth layer and the fifth connection terminal (6-3b) of the second inductor coil (6-3) of the sixth layer, a seventh metal through hole (19) for connecting the capacitor substrate 4-2b and the first inductor coil (8-1) of the eighth layer The second connection terminal (8-1b) of the eighth layer, the eighth metal via (20) - used to connect the first capacitor substrate (5-1) of the fifth layer and the first connection terminal (6-1a) of the sixth layer, the ninth metal via (21) - used to connect the third connection terminal (6-2a) of the sixth layer and the connection terminal of the first inductor coil (10-1) of the tenth layer, the second connection terminal (10-1b) of the tenth layer, the tenth metal via (22) - used to connect the second connection terminal (6-1b) of the sixth layer and the second connection terminal (7-1b) of the seventh layer, the fourteenth connection point column (23) - used to connect the fourth connection terminal (6-3a) of the sixth layer and the third connection terminal (7-2a) of the seventh layer, the eleventh metal via (24) - used to connect the fifth connection terminal (6-1b) of the sixth layer point (6-3b) and the second connection terminal (9-1b) of the ninth layer, the twelfth connection point column (25) - used to connect the fourth connection terminal (7-2b) of the seventh layer and the third connection terminal (8-2a) of the eighth layer, the thirteenth connection point column (26) - used to connect the seventh layer first connection terminal (7-1a) of the first inductor (7-1) of the seventh layer and the eighth layer first connection terminal (8-1a) of the first inductor (8-1) of the eighth layer, the fifteenth metal via (27) - used to connect the ninth layer first connection terminal (9-1a) and the tenth layer sixth connection terminal (10-3b), the sixteenth metal via (28) - used to connect the ninth layer fourth connection terminal (9-2b) and the tenth layer fourth connection terminal (10-2b),The seventeenth metal via (29) is used to connect the first connection terminal (10-1a) of the tenth layer and the second connection terminal (11-1b) of the eleventh layer. The eighteenth metal via (30) is used to connect the fifth connection terminal (10-3a) of the tenth layer and the first fifth connection terminal (11-3a) of the eleventh layer. The nineteenth metal via (31) is used to connect the third connection terminal (10-2a) of the tenth layer and the third connection terminal (11-2a) of the eleventh layer. The twentieth metal via (32) is used to connect the first connection terminal (11-1a) of the eleventh layer and the first connection terminal (12-1a) of the twelfth layer. The twenty-first metal via (33) is used to connect the sixth connection terminal (11-3b) of the eleventh layer and the third connection terminal (12-3a) of the twelfth layer. The twenty-second metal via (34) is used to connect the fourth connection terminal (11-2b) of the eleventh layer and the second connection terminal (12-2a) of the twelfth layer. DETAILED DESCRIPTION

[0051] Figure 1 This is the equivalent circuit diagram of a new LTCC low-insertion-loss, high-rejection duplexer. Taking a signal input from common port ① as an example, the signal enters port ① and exits port ②. This link acts as a second low-pass filter, separating low-frequency signals. The signal enters port ① and exits port ③, forming a bandpass filter, separating high-frequency signals. This high-frequency bandpass filter is composed of a first high-pass filter and a first low-pass filter. The first high-pass filter consists of inductor L1 and capacitors C1, C2, and C3, with C3 acting as a bridge capacitor between C1 and C2, effectively improving the high-frequency bandpass filter's stopband attenuation. The first low-pass filter is composed of inductors L2 and L3 and capacitors C4, C5, C6, and C7. L2 and C4, and L3 and C5, respectively, form parallel resonances, creating two stopband attenuation zeros in the bandpass filter's high frequency range, effectively improving the bandpass filter's stopband attenuation in the high frequency range. The low-frequency signal is separated by the second low-pass filter, which is composed of inductors L4, L5 and capacitors C8, C9, and C10. The inductor L5 and capacitor C8 resonate in parallel to form a transmission zero, which effectively improves the stop-band attenuation of the low-frequency signal at the high end.

[0052] The first port ① constitutes the common port of the duplexer, the second port ② is a low-frequency band input / output port, and the third port ③ is a high-frequency band input / output port.

[0053] Figure 2 This is the appearance structure of the new LTCC low insertion loss, high rejection duplexer. P1, P3, and P5 are ground ports, P2 is the common port of the chip duplexer, P4 is the low-frequency band passband input / output port, P6 is the high-frequency band input / output port, and Mark is its direction indicator.

[0054] Figure 4 This is the electrical characteristic curve of the new LTCC low insertion loss, high rejection duplexer.

[0055] Figure 3 The internal structure of the LTCC low insertion loss, high rejection duplexer of the present invention is shown. The circuit structure is distributed inside the ceramic substrate. The circuit structure has a total of twelve layers.

[0056] First layer (1), please refer to Figure 5 , three mutually independent first-layer first metal conductor capacitor substrates (1-1), first-layer second metal conductor capacitor substrates (1-2a & 1-2b), and first-layer third metal conductor capacitor substrates (1-3) are printed on a ceramic dielectric substrate, wherein the first-layer first connection terminal (1a), the first-layer second connection terminal (1b), the first-layer third connection terminal (1c), the first-layer fourth connection terminal (1d), the first-layer fifth connection terminal (1e), and the first-layer sixth connection terminal (1f) provided in the layer are respectively connected to the high-frequency input / output port (P6), the third ground port (P5), the low-frequency band-pass input / output port (P4), the second ground port (P3), the common port (P2), and the first ground port (P1);

[0057] Second layer (2), please refer to Figure 6 Five mutually insulated metal plane conductors are printed on a ceramic dielectric substrate, which are respectively a second-layer first capacitor substrate (2-1), a second-layer second capacitor substrate (2-2), a second-layer third capacitor substrate (2-3), a second-layer fourth capacitor substrate (2-4) and a second-layer first dummy connection terminal (2b), wherein the second-layer first capacitor substrate (2-1) is connected to a high-frequency band input / output port (P6) via a second-layer first connection terminal (2a), and the second-layer second dummy connection terminal (2b) is connected to a first ground port (P1);

[0058] Figure 7 2 shows a schematic diagram of the planar structure of metal via connections between the second and third layer circuits.

[0059] The third layer (3), please refer to Figure 8Six mutually insulated metal plane conductors are printed on a ceramic dielectric substrate, which are respectively the third layer first capacitor substrate (3-1), the third layer second capacitor substrate (3-2), the third layer third capacitor substrate (3-3), the third layer fourth capacitor substrate (3-4), the third layer fifth capacitor substrate (3-5) and the third layer first dummy connection terminal (3c). A first metal via (13) and a second metal via (14) are also provided, wherein the third layer first capacitor substrate (3-1) is connected to the fourth metal via (16), the third layer first connection terminal (3a), the third layer second connection terminal (3b), the third layer first dummy connection terminal (3c) and the third layer fourth connection terminal (3d) are respectively connected to the third ground port (P5), the low frequency band pass input / output port (P4), the second ground port (P3) and the common port (P2), and the third layer fifth capacitor substrate (3-5a) is connected to the second layer second capacitor substrate (2-2) through a third metal via (15);

[0060] Figure 9 2 shows a schematic diagram of the planar structure of metal via connections between the third and fourth layer circuits.

[0061] The fourth layer (4), please refer to Figure 10 Four mutually insulated metal plane conductors are printed on a ceramic dielectric substrate, namely a fourth-layer first capacitor substrate (4-1), a fourth-layer second capacitor substrate (4-2a & 4-2b), a fourth-layer third capacitor substrate (4-3) and a fourth-layer fourth capacitor substrate (4-4). The layer also has a fourth metal via (16) and a fifth metal via (17). The fourth-layer first connection terminal (4a) on the layer is connected to a high-frequency band input / output port (P6), the fourth-layer second connection terminal (4b) is connected to a third ground port (P5), the fourth-layer third connection terminal (4c) is connected to the first ground port (P1), and the fourth-layer fourth connection terminal (4d) is connected to a common port (P2). The fourth-layer first capacitor substrate (4-1) is connected to the second-layer third capacitor substrate (2-3) through a first metal via (13).

[0062] Figure 11 Shown is a schematic diagram of the plane structure of metal via connections between the fourth and fifth layers.

[0063] Fifth level (5), please refer to Figure 12Two mutually insulated fifth-layer first capacitor substrates (5-1) and fifth-layer second capacitor substrates (5-2) are printed on a ceramic dielectric substrate. The fifth-layer first capacitor substrate (5-1) and the fourth metal via (16) are connected via a fifth metal via (17), a sixth metal via (18), and a seventh metal via (19). The fifth-layer first connection terminal (5a) is connected to a low-frequency band-pass input / output port (P4), and the fifth-layer second connection terminal (5b) is connected to the low-frequency band-pass input / output port (P4).

[0064] Figure 13 Shown is a schematic diagram of the plane structure of the metal via connection between the fifth and sixth layers.

[0065] The sixth layer (6), please refer to Figure 14 Two mutually insulated metal coils are printed on a ceramic dielectric substrate, namely the first inductor coil (6-1 & 6-2) of the sixth layer and the second inductor coil (6-3) of the sixth layer, and a fifth metal via (17) and a seventh metal through hole (19) are also provided, wherein the first connection terminal (6-1a) of the sixth layer, the second connection terminal (6-1b) of the sixth layer, and the third connection terminal (6-2a) of the sixth layer are respectively connected to the eighth metal via (20), the tenth metal via (22), and the ninth metal via (21), wherein the fourth connection terminal (6-3a) of the sixth layer and the fifth connection terminal (6-3b) of the sixth layer are respectively connected to the sixth metal through hole (18) and the eleventh metal through hole (24);

[0066] Figure 15 Shown is a schematic diagram of the metal via connection plan structure between the sixth and seventh layers;

[0067] The seventh floor (7), please refer to Figure 16 Two mutually insulated metal coils are printed on a ceramic dielectric substrate, namely the seventh layer first inductor coil (7-1) and the seventh layer second inductor coil (7-2). The seventh layer first connection terminal (7-1a), the seventh layer second connection terminal (7-1b), the seventh layer third connection terminal (7-2a), and the seventh layer fourth connection terminal (7-2b) of the layer are respectively connected to the thirteenth connection point column (26), the tenth metal via (22), the fourteenth connection point column (23), and the twelfth connection point column (25). The layer also has a fifth metal via (17), a seventh metal through hole (19), and a ninth metal via (21).

[0068] Figure 17 Shown is a schematic diagram of the metal via connection plan structure between the seventh and eighth layers;

[0069] The eighth layer (8), please refer to Figure 18, an eighth-layer first dummy connection terminal (8a) and two mutually insulated metal coils are printed on a ceramic dielectric substrate, namely an eighth-layer first inductance coil (8-1) and an eighth-layer second inductance coil (8-2), and an eighth-layer first connection terminal (8-1a), an eighth-layer second connection terminal (8-1b), an eighth-layer third connection terminal (8-2a), and an eighth-layer fourth connection terminal (8b); wherein the eighth-layer first connection terminal (8-1a) and the eighth-layer second connection terminal (8-1b) are connected to the thirteenth connection point column (26) and the seventh metal through hole 19, the eighth-layer first dummy connection terminal (8a) is connected to the low-frequency bandpass input / output port (P4), and the eighth-layer fourth connection terminal (8b) is connected to the second ground port (P3);

[0070] Figure 19 Shown is a schematic diagram of the metal via planar structure between the eighth and ninth layers.

[0071] Ninth floor (9), please refer to Figure 20 A ninth metal via (21), a ninth layer first metal coil (9-1), and a ninth layer second metal coil (9-2) are printed on the ceramic dielectric substrate; a ninth layer first connection terminal (9-1a), a ninth layer second connection terminal (9-1b), a ninth layer third connection terminal (9-2a), and a ninth layer fourth connection terminal (9-2b) are respectively connected to a fifteenth metal via (27), an eleventh metal via (24), a fifth metal via (17), and a sixteenth metal via (28);

[0072] Figure 21 Shown is a schematic diagram of the metal via connection plan structure between the ninth and tenth layers;

[0073] Tenth floor (10), please refer to Figure 22 Three mutually insulated metal coils are printed on a ceramic dielectric substrate, namely the tenth layer first inductor coil (10-1), the tenth layer second inductor coil (10-2) and the tenth layer third inductor coil (10-3), and the tenth layer first connection terminal (10-1a), the tenth layer second connection terminal (10-1b), the tenth layer third connection terminal (10-2a), the tenth layer fourth connection terminal (10-2b), the tenth layer fifth connection terminal (10-3a) and the tenth layer sixth connection terminal (10-3b) located on the layer are connected to the seventh metal through hole (19), the ninth metal via hole (21), the nineteenth metal via hole (31), the sixteenth metal via hole (28), the eighteenth metal via hole (30) and the fifteenth metal via hole (27) respectively;

[0074] Figure 23 Shown is a schematic diagram of the planar structure of metal via connections between the tenth and eleventh layers;

[0075] Eleventh layer (11), please refer to Figure 24 Printed on the ceramic dielectric substrate are three mutually insulated metal coils, namely the eleventh layer first inductor coil (11-1), the eleventh layer second inductor coil (11-2), and the eleventh layer third inductor coil (11-3). The eleventh layer first connection end point (11-1a), the eleventh layer second connection end point (11-1b), the eleventh layer third connection end point (11-2a), the eleventh layer fourth connection end point (11-2b), the eleventh layer fifth connection end point (11-3a), and the eleventh layer sixth connection end point (11-3b) of this layer are respectively connected to the twentieth metal via (32), the seventeenth metal via (29), the nineteenth metal via (31), the twenty-second metal via (34), the eighteenth metal via (30), and the twenty-first metal via (33).

[0076] Figure 25 The figure shows the schematic diagram of the metal via connection plane structure between the eleventh layer and the twelfth layer.

[0077] Twelfth layer (12), please refer to Figure 26 Printed on the ceramic dielectric substrate are three mutually insulated metal coils, namely the twelfth layer first inductor coil (12-1), the twelfth layer second inductor coil (12-2), and the twelfth layer third inductor coil (12-3). The twelfth layer first connection end point (12-1a), the twelfth layer second connection end point (12-2a), and the twelfth layer third connection end point (12-3a) of this layer are respectively connected to the twentieth metal via (32), the twenty-second metal via (34), and the twenty-first metal via (33). The twelfth layer first connection end point (12a), the twelfth layer second connection end point (12b), the twelfth layer third connection end point (12c), the twelfth layer fourth connection end point (12d), and the twelfth layer fifth connection end point (12e) are respectively connected to the high-frequency input / output port (P6), the third ground port (P5), the second ground port (P3), the common port (P2), and the first ground port (P1).

[0078] The inductor L1 in the circuit is formed by interconnecting a ninth-layer second metal coil (9-2), a tenth-layer second inductor coil (10-2), an eleventh-layer second inductor coil (11-2), and a twelfth-layer second inductor coil (12-2); the inductor L2 in the circuit is formed by interconnecting a portion of a sixth-layer first inductor coil (6-1), a seventh-layer first inductor coil (7-1), and an eighth-layer first inductor coil (8-1); and the inductor L3 in the circuit is formed by interconnecting a portion of a sixth-layer first inductor coil (6-2), a tenth-layer first inductor coil (10-1), an eleventh-layer first inductor coil (11-1), and a twelfth-layer first inductor coil (12-1). The inductor L4 in the circuit is formed by interconnecting the ninth layer of the first metal coil (9-1), the tenth layer of the first inductor coil (10-1) and the eleventh layer of the first inductor coil (11-1); the inductor L5 in the circuit is formed by interconnecting the sixth layer of the second inductor coil (6-3), the seventh layer of the second inductor coil (7-2) and the ninth layer of the first metal coil (9-1), the tenth layer of the third inductor coil (10-3), the eleventh layer of the third inductor coil (11-3) and the twelfth layer of the third inductor coil (12-3); and the capacitor C1 in the circuit is formed by partially connecting the first layer of the second metal conductor capacitor substrate (1-2a), the second layer of the second capacitor substrate (2-2) and the third layer of the second capacitor substrate. The circuit is composed of a fifth capacitor substrate (3-2), a capacitor C2 in the circuit is composed of a third layer of fifth capacitor substrate (3-5), a second layer of third capacitor substrate (2-3) and a portion of a fourth layer of second capacitor substrate (4-2b), a capacitor C3 in the circuit is composed of a portion of a first layer of second metal conductor capacitor substrate (1-2b) and a second layer of third capacitor substrate (2-3), a capacitor C4 in the circuit is composed of a third layer of first capacitor substrate (3-1) and a fifth layer of first capacitor substrate (5-1), a capacitor C5 in the circuit is composed of a third layer of first capacitor substrate (3-1) and a fourth layer of third capacitor substrate (4-3), a capacitor C6 in the circuit is composed of a third layer of first capacitor substrate (3-1) and a second layer of first capacitor substrate (4-3), and a capacitor C7 in the circuit is composed of a third layer of first capacitor substrate (3-1) and a second layer of first capacitor substrate (4-2b). The invention relates to a circuit comprising a first layer of a first metal conductor capacitor substrate (1-1) and a second layer of the first capacitor substrate (2-1), a capacitor C7 in the circuit comprising a first layer of a first metal conductor capacitor substrate (1-1) and a second layer of the first capacitor substrate (2-1), a capacitor C8 in the circuit comprising a second layer of a fourth capacitor substrate (2-4) and a third layer of a fourth capacitor substrate (3-4), a capacitor C9 in the circuit comprising a first layer of a third metal conductor capacitor substrate (1-3), a second layer of a fourth capacitor substrate (2-4), a third layer of a third capacitor substrate (3-3) and a fourth layer of the first capacitor substrate (4-1), and a capacitor C10 in the circuit comprising a third layer of a fourth capacitor substrate (3-4), a fourth layer of a fourth capacitor substrate (4-4) and a fifth layer of the second capacitor substrate (5-2).

Claims

1. A 5G LTCC duplexer, characterized in that: The duplexer includes a substrate, wherein a first ground port (P1), a second ground port (P3), a third ground port (P5), a common port (P2), a low-frequency bandpass input / output port (P4), and a high-frequency band input / output port (P6) are provided on the outside of the substrate, a first bandpass filter for separating high-frequency band signals is provided between the common port (P2) and the high-frequency band input / output port (P6) inside the substrate, a second low-pass filter for separating low-frequency band signals is provided between the common port (P2) and the low-frequency bandpass input / output port (P4) inside the substrate, and twelve circuit layers with a stacked structure are provided inside the substrate; wherein, The first layer (1) is formed by printing three mutually independent first-layer first metal conductor capacitor substrates (1-1), first-layer second metal conductor capacitor substrates (1-2a & 1-2b), and first-layer third metal conductor capacitor substrates (1-3) on a ceramic dielectric substrate. The first-layer first connection terminal (1a), first-layer second connection terminal (1b), first-layer third connection terminal (1c), first-layer fourth connection terminal (1d), first-layer fifth connection terminal (1e), and first-layer sixth connection terminal (1f) provided in the layer are respectively connected to the high-frequency input / output port (P6), the third ground port (P5), the low-frequency band-pass input / output port (P4), the second ground port (P3), the common port (P2), and the first ground port (P1); The second layer (2) has five mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are respectively the second layer first capacitor substrate (2-1), the second layer second capacitor substrate (2-2), the second layer third capacitor substrate (2-3), the second layer fourth capacitor substrate (2-4) and the second layer first dummy connection terminal (2b), wherein the second layer first capacitor substrate (2-1) is connected to the high frequency band input / output port (P6) through the second layer first connection terminal (2a), and the second layer second dummy connection terminal (2b) is connected to the first ground port (P1); The third layer (3) has six mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are respectively the third layer first capacitor substrate (3-1), the third layer second capacitor substrate (3-2), the third layer third capacitor substrate (3-3), the third layer fourth capacitor substrate (3-4), the third layer fifth capacitor substrate (3-5) and the third layer first dummy connection terminal (3c). The third layer first capacitor substrate (3-1) is connected to the fourth metal via (16), the third layer first connection terminal (3a), the third layer second connection terminal (3b), the third layer first dummy connection terminal (3c) and the third layer fourth connection terminal (3d) are respectively connected to the third ground port (P5), the low frequency band pass input / output port (P4), the second ground port (P3) and the common port (P2), and the third layer fifth capacitor substrate (3-5a) is connected to the second layer second capacitor substrate (2-2) through the third metal via (15); The fourth layer (4) is provided with four mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are respectively the fourth layer first capacitor substrate (4-1), the fourth layer second capacitor substrate (4-2a & 4-2b), the fourth layer third capacitor substrate (4-3) and the fourth layer fourth capacitor substrate (4-4). The layer also has a fourth metal via (16) and a fifth metal via (17). The fourth layer first connection terminal (4a) on the layer is connected to the high frequency band input / output port (P6), the fourth layer second connection terminal (4b) is connected to the third ground port (P5), the fourth layer third connection terminal (4c) is connected to the first ground port (P1), the fourth layer fourth connection terminal (4d) is connected to the common port (P2), and the fourth layer first capacitor substrate (4-1) is connected to the second layer third capacitor substrate (2-3) through the first metal via (13); The fifth layer (5) has two mutually insulated first capacitor substrates (5-1) and second capacitor substrates (5-2) printed on a ceramic dielectric substrate. The first capacitor substrate (5-1) and the fourth metal via (16) are connected via a fifth metal via (17), a sixth metal via (18) and a seventh metal via (19). The first connection terminal (5a) of the fifth layer is connected to a low-frequency bandpass input / output port (P4), and the second connection terminal (5b) of the fifth layer is connected to a low-frequency bandpass input / output port (P4). The sixth layer (6) has two mutually insulated metal coils printed on a ceramic dielectric substrate, namely the first inductor coil (6-1 & 6-2) of the sixth layer and the second inductor coil (6-3) of the sixth layer, and is also provided with a fifth metal via (17) and a seventh metal through hole (19), wherein the first connection terminal (6-1a) of the sixth layer, the second connection terminal (6-1b) of the sixth layer, and the third connection terminal (6-2a) of the sixth layer are respectively connected to the eighth metal via (20), the tenth metal via (22), and the ninth metal via (21), wherein the fourth connection terminal (6-3a) of the sixth layer and the fifth connection terminal (6-3b) of the sixth layer are respectively connected to the sixth metal through hole (18) and the eleventh metal through hole (24); The seventh layer (7) has two mutually insulated metal coils printed on a ceramic dielectric substrate, namely the first inductor coil (7-1) of the seventh layer and the second inductor coil (7-2) of the seventh layer. The first connection terminal (7-1a), the second connection terminal (7-1b), the third connection terminal (7-2a) and the fourth connection terminal (7-2b) of the seventh layer are respectively connected to the thirteenth connection point column (26), the tenth metal via (22), the fourteenth connection point column (23) and the twelfth connection point column (25). The layer also has a fifth metal via (17), a seventh metal through hole (19) and a ninth metal via (21). The eighth layer (8) is printed on a ceramic dielectric substrate with an eighth layer first dummy connection terminal (8a) and two mutually insulated metal coils, namely the eighth layer first inductance coil (8-1) and the eighth layer second inductance coil (8-2), and is also provided with an eighth layer first connection terminal (8-1a), an eighth layer second connection terminal (8-1b), an eighth layer third connection terminal (8-2a), and an eighth layer fourth connection terminal (8b); wherein the eighth layer first connection terminal (8-1a) and the eighth layer second connection terminal (8-1b) are connected to the thirteenth connection point column (26) and the seventh metal through hole 19, the eighth layer first dummy connection terminal (8a) is connected to the low-frequency band pass input / output port (P4), and the eighth layer fourth connection terminal (8b) is connected to the second ground port (P3); The ninth layer (9) is printed with a ninth metal via (21), a ninth layer first metal coil (9-1), and a ninth layer second metal coil (9-2) on the ceramic dielectric substrate; the ninth layer first connection terminal (9-1a), the ninth layer second connection terminal (9-1b), the ninth layer third connection terminal (9-2a), and the ninth layer fourth connection terminal (9-2b) are respectively connected to the fifteenth metal via (27), the eleventh metal via (24), the fifth metal via (17), and the sixteenth metal via (28); The tenth layer (10) has three mutually insulated metal coils printed on a ceramic dielectric substrate, namely the tenth layer first inductor coil (10-1), the tenth layer second inductor coil (10-2) and the tenth layer third inductor coil (10-3), and the tenth layer first connection terminal (10-1a), the tenth layer second connection terminal (10-1b), the tenth layer third connection terminal (10-2a), the tenth layer fourth connection terminal (10-2b), the tenth layer fifth connection terminal (10-3a) and the tenth layer sixth connection terminal (10-3b) located in the layer are connected to the seventh metal through hole (19), the ninth metal via hole (21), the nineteenth metal via hole (31), the sixteenth metal via hole (28), the eighteenth metal via hole (30) and the fifteenth metal via hole (27) respectively; The eleventh layer (11) has three mutually insulated metal coils printed on a ceramic dielectric substrate, namely the first inductor coil (11-1) of the eleventh layer, the second inductor coil (11-2) of the eleventh layer, and the third inductor coil (11-3) of the eleventh layer. The first connection terminal (11-1a) of the eleventh layer, the second connection terminal (11-1b) of the eleventh layer, the third connection terminal (11-2a) of the eleventh layer, the fourth connection terminal (11-2b) of the eleventh layer, the first and fifth connection terminals (11-3a) of the eleventh layer, and the sixth connection terminal (11-3b) of the eleventh layer located on the layer are respectively connected to the twentieth metal via (32), the seventeenth metal via (29), the nineteenth metal via (31), the twenty-second metal via (34), the eighteenth metal via (30), and the twenty-first metal via (33); The twelfth layer (12) has three mutually insulated metal coils printed on a ceramic dielectric substrate, namely the twelfth layer first inductor coil (12-1), the twelfth layer second inductor coil (12-2), and the twelfth layer third inductor coil (12-3); the twelfth layer first connection terminal (12-1a), the twelfth layer second connection terminal (12-2a), and the twelfth layer third connection terminal (12-3a) located in the layer are respectively connected to the twentieth metal via (32), the twenty-second metal via (34), and the twenty-first metal via (33); the twelfth layer first connection terminal (12a), the twelfth layer second connection terminal (12b), the twelfth layer third connection terminal (12c), the twelfth layer fourth connection terminal (12d), and the twelfth layer fifth connection terminal (12e) are respectively connected to the high-frequency band input / output port (P6), the third ground port (P5), the second ground port (P3), the common port (P2), and the first ground port (P1).

Images