Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit. The comparator comprises: a first-stage circuit, which comprises a main circuit, an auxiliary circuit and a common circuit, the main circuit and the auxiliary circuit are connected to a power supply end or a ground end, the common circuit is connected to the ground end or the power supply end, the main circuit is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage, the auxiliary circuit is used for generating a second differential signal according to a second input signal and a second reference signal in the sampling stage, a first positive feedback circuit is used for accelerating the difference between the first differential signal, a second positive feedback circuit is used for accelerating the difference between the second differential signal, and a second-stage circuit is connected to the power supply end and the ground end and is used for amplifying and latching the first differential signal and the second differential signal and then outputting a comparison result in a regeneration stage. The comparator provided by the scheme can eliminate inter-symbol interference, has high response speed, low working voltage and low power consumption.

Description

Technical Field

[0001] This application relates to integrated circuits, and more particularly to a comparator and a decision feedback equalization circuit. Background Technology

[0002] Today, people's demand for mobile devices such as smartphones, tablets, and various wearable accessories has increased significantly, greatly enriching our daily lives and work.

[0003] However, due to limited battery life, higher demands are placed on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, therefore, DRAM also urgently needs to achieve lower operating voltage and lower power consumption. Among them, the comparator is a crucial device for realizing DRAM data read and write, and existing comparators can no longer meet current usage requirements. Summary of the Invention

[0004] This application provides a comparator and a decision feedback equalization circuit, which aims to eliminate inter-symbol interference of the comparator, reduce the operating voltage and power consumption of the comparator, and improve the response rate of the comparator.

[0005] In a first aspect, this application provides a comparator, comprising:

[0006] The first-level circuit includes a main circuit, an auxiliary circuit, and a common circuit. The main circuit and the auxiliary circuit are both connected to the power supply terminal or the ground terminal, and the common circuit is connected to the ground terminal or the power supply terminal. The main circuit is used to generate a first differential signal based on the first input signal and the first reference signal during the sampling stage. The auxiliary circuit is used to generate a second differential signal based on the second input signal and the second reference signal during the sampling stage.

[0007] A first positive feedback circuit, which is connected to the main circuit, is used to accelerate the difference between the first differential signals;

[0008] A second positive feedback circuit, which is connected to the auxiliary circuit, is used to accelerate the difference between the second differential signals;

[0009] The second-stage circuit, which connects the power supply terminal and the ground terminal, is connected to the output terminal of the first-stage circuit. It is used to amplify and latch the first differential signal and the second differential signal during the regeneration stage to output the comparison result.

[0010] In a second aspect, this application provides a decision feedback equalization circuit, including four comparators involved in the first aspect and optional schemes, which are sequentially labeled as a first comparator, a second comparator, a third comparator and a fourth comparator;

[0011] The first comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator.

[0012] The second comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the first comparator, and a fourth input terminal connected to the second output terminal of the first comparator.

[0013] The third comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the second comparator, and a fourth input terminal connected to the second output terminal of the second comparator.

[0014] The fourth comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the third comparator, and a fourth input terminal connected to the second output terminal of the third comparator.

[0015] This application provides a comparator and a decision feedback equalization circuit. The comparator includes a first-stage circuit, a second-stage circuit, a first positive feedback circuit, and a second positive feedback circuit. The first-stage circuit includes a main circuit, an auxiliary circuit, and a common circuit. The main circuit generates a first differential signal based on a first input signal and a first reference signal during the sampling stage. The auxiliary circuit generates a second differential signal based on a second input signal and a second reference signal during the sampling stage. The second-stage circuit amplifies and latches the first and second differential signals during the regeneration stage to output a comparison result. When inter-symbol interference (ISI) prevents the main circuit from accurately sensing and outputting the differential signal, the second differential signal output by the auxiliary circuit can adjust the first differential signal, thereby eliminating ISI and improving the comparator's accuracy. By using a two-stage circuit setup—that is, the first-stage circuit generates the differential signal, and the second-stage circuit generates the comparison result based on the differential signal—the number of transistors in the same circuit path can be reduced, thereby reducing the comparator's operating voltage. When either or both of the first and second reference signals are not properly selected, it takes a relatively long time to generate a differential signal with a large difference in the corresponding input circuit. The positive feedback circuit in the corresponding input circuit accelerates the difference through a positive feedback mechanism after there is a slight difference between the two outputs of the input circuit, shortening the sampling stage time, thereby improving the comparator's response rate and reducing the comparator's power consumption. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] Figure 1 A specific circuit diagram of a comparator provided in this application;

[0018] Figure 2 The timing diagram of the comparator provided in this application;

[0019] Figure 3 A structural block diagram of a comparator provided in this application;

[0020] Figure 4 For based on Figure 3 A specific circuit diagram of the provided comparator;

[0021] Figure 5 For based on Figure 3 Another specific circuit diagram of the provided comparator;

[0022] Figure 6 A structural block diagram of another comparator provided in this application;

[0023] Figure 7 For based on Figure 6 A specific circuit diagram of one type of comparator is provided;

[0024] Figure 8 for Figure 7 The specific circuit diagram of the controllable feedback module in the provided comparator;

[0025] Figure 9 For based on Figure 6 A specific circuit diagram of one type of comparator is provided;

[0026] Figure 10 for Figure 9 The specific circuit diagram of the controllable feedback module in the provided comparator;

[0027] Figure 11 A block diagram of a decision feedback equalization circuit provided in this application;

[0028] Figure 12 A schematic diagram illustrating the effect of the decision feedback equalization circuit provided in this application;

[0029] Figure 13 The timing diagram of the decision feedback equalization circuit provided in this application.

[0030] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0032] like Figure 1 As shown, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

[0033] The input circuit 101 includes transistors N1, N2, and N3. Transistors N1 and N2 form a differential transistor pair. The gates of transistors N1 and N2 form the first input terminal IN and the second input terminal IN of the input circuit. The drains of transistors N1 and N2 form the two output terminals of the input circuit.

[0034] The output circuit 102 includes transistors P1, P2, N4, and N5, which form a cross-coupled transistor pair. The drains of transistors P1 and N4 form the first output terminal ON of the output circuit 102, and the drains of transistors P2 and N5 form the second output terminal OP of the output circuit 102. The reset circuit 103 includes transistors P3 and P4.

[0035] The comparator's operation consists of four stages: reset, sampling, regeneration, and decision. The following section will discuss these stages in conjunction with... Figure 2 describe Figure 1 The working process of the comparator shown is as follows:

[0036] During the reset phase, from time t0 to time t1, the clock signal is low, transistor N3 is open, the input and output circuits stop working, transistors P3 and P4 are closed, the reset circuit works, and pulls the drain voltage of transistor N4 and the drain voltage of transistor N5 to high level.

[0037] During the sampling phase, from time t1 to t2, the clock signal is high, transistors P3 and P4 are open, and the reset circuit stops working. Transistor N3 is closed, and the input circuit acquires the input signal through the first input terminal IN and the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of transistor N1, and the reference signal pulls down the drain voltage of transistor N2. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Because the input signal is higher than the reference signal, the rate at which the input signal pulls down the drain voltage of transistor N1 is faster, resulting in the drain voltage of transistor N4 being lower than that of transistor N5.

[0038] During the regeneration phase, from time t2 to t3, the drain voltages of transistor N4 and N5 reach the flip voltage, transistors P2 and N4 are turned on, while transistors P1 and N5 are gradually turned off. Transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

[0039] During the decision-making phase, from time t3 to t4, transistors P2 and N4 are turned on, while transistors P1 and N5 are turned off. The drain voltage of transistor N5 continues to be pulled up, and the drain voltage of transistor N4 continues to be pulled down. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0040] When the next working cycle arrives, the clock signal goes low, and the drain voltages of transistors N4 and N5 are reset to high by transistors P1 and P2.

[0041] like Figure 3 As shown, this application discloses a comparator, which includes a first-stage circuit 201, a second-stage circuit 202, a first positive feedback circuit 203, and a second positive feedback circuit 204. The first-stage circuit 201 includes a main circuit 2011, an auxiliary circuit 2012, and a common circuit 2013.

[0042] The main circuit 2011, auxiliary circuit 2012, and common circuit 2013 each have two output terminals, labeled as the first output terminal and the second output terminal. The first output terminals of the main circuit 2011, auxiliary circuit 2012, and common circuit 2013 are interconnected to form the first output terminal of the first-stage circuit 201. The second output terminals of the main circuit 2011, auxiliary circuit 2012, and common circuit 2013 are interconnected to form the second output terminal of the second-stage circuit 202.

[0043] When the main circuit 2011 and auxiliary circuit 2012 are connected to the power supply, the common circuit 2013 is connected to the ground. When the main circuit 2011 and auxiliary circuit 2012 are connected to the ground, the common circuit 2013 is connected to the power supply. This arrangement creates a single current path for the transistors in the first-stage circuit 201. The second-stage circuit 203 connects to both the power supply and ground, creating another current path for the transistors in the second-stage circuit 203. Compared to a comparator structure containing only one stage of circuitry, this arrangement reduces the number of transistors in each current path, thereby lowering the comparator's operating voltage.

[0044] The second-stage circuit 202 has two input terminals, labeled as the first input terminal and the second input terminal. The first input terminal of the second-stage circuit 202 is connected to the first output terminal O1 of the first-stage circuit, and the second input terminal of the second-stage circuit 202 is connected to the second output terminal O2 of the first-stage circuit. The main circuit generates a first differential signal based on the first input signal and the first reference signal during the sampling phase, and the auxiliary circuit generates a second differential signal based on the second input signal and the second reference signal during the sampling phase. The second-stage circuit amplifies and latches the first and second differential signals during the regeneration phase to output the comparison result.

[0045] By setting up a main circuit and an auxiliary circuit, and having the main circuit and the auxiliary circuit generate a first differential signal and a second differential signal respectively, when inter-symbol interference occurs and the main circuit cannot accurately sense and output the differential signal, the second differential signal output by the auxiliary circuit can adjust the first differential signal, so that the second-stage circuit can generate a comparison result based on the adjusted first differential signal, thereby eliminating inter-symbol interference and improving the accuracy of the comparator.

[0046] In one embodiment, the first-stage circuit 201 and the second-stage circuit 202 have the same number of transistors in their respective current paths, so that the first-stage circuit 201 and the second-stage circuit 202 operate at the same voltage, reducing the number of power supply terminals required by the comparator and simplifying the comparator circuit.

[0047] In the above technical solution, by setting up a main circuit and an auxiliary circuit in the first-stage circuit, when the main circuit is unable to accurately output the first differential signal due to inter-symbol interference, the auxiliary circuit adjusts the first differential signal so that the second-stage circuit can accurately generate the comparison result based on the adjusted first differential signal, thereby improving the accuracy of the comparator. Furthermore, using a two-stage structure can reduce the operating voltage of the comparator.

[0048] When the first reference signal is not properly selected, the response time of the main circuit 2011 becomes longer, meaning that the main circuit 2011 needs a longer time to present a first differential signal with a relatively large difference at the output. The first positive feedback circuit 203 accelerates the difference between the first differential signals through a positive feedback mechanism, thereby reducing the time that the main circuit 2011 presents a first differential signal with a relatively large difference at the output, which shortens the time that the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing its power consumption.

[0049] Similarly, when the second reference signal is not properly selected, the response time of the auxiliary circuit 2012 becomes longer, meaning that the auxiliary circuit 2012 needs a longer time to present a second differential signal with a relatively large difference at the output. The second positive feedback circuit 204 accelerates the difference between the second differential signals through a positive feedback mechanism, thereby reducing the time that the auxiliary circuit 2012 presents a second differential signal with a relatively large difference at the output, which shortens the time the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing its power consumption.

[0050] In one embodiment, the first positive feedback circuit 203 includes a first feedback unit 2031 and a second feedback unit 2032, both of which are provided with a control terminal and a first terminal.

[0051] The control terminal of the first feedback unit 2031 is connected to the first output terminal of the main circuit 2011, and the first end of the first feedback unit 2031 is connected to the second output terminal of the main circuit 2011. The control terminal of the second feedback unit 2032 is connected to the second output terminal of the main circuit 2011, and the first end of the second feedback unit 2032 is connected to the first output terminal of the main circuit 2011.

[0052] The first feedback unit 2031 is used to pull the voltage of the second output terminal of the main circuit 2011 according to the voltage of the first output terminal of the main circuit 2011 during the sampling phase, and the second feedback unit 2032 is used to pull the voltage of the first output terminal of the main circuit 2011 according to the voltage of the second output terminal of the main circuit 2011 during the sampling phase.

[0053] The first feedback unit 2031 pulls the voltage at the second output terminal of the main circuit 2011 in the same direction as the second feedback unit 2032 pulls the voltage at the first output terminal of the main circuit 2011. When the first feedback unit 2031 pulls the voltage at the second output terminal of the main circuit 2011 upwards, the second feedback unit 2032 also pulls the voltage at the first output terminal of the main circuit 2011 upwards. When the first feedback unit 2031 pulls the voltage at the second output terminal of the main circuit 2011 downwards, the second feedback unit 2032 also pulls the voltage at the first output terminal of the main circuit 2011 downwards.

[0054] In one embodiment, the second positive feedback circuit 204 includes a third feedback unit 2041 and a fourth feedback unit 2042, both of which have a control terminal and a first terminal.

[0055] The control terminal of the third feedback unit 2041 is connected to the first output terminal of the auxiliary circuit 2012, and the first terminal of the third feedback unit 2041 is connected to the second output terminal of the auxiliary circuit 2012. The control terminal of the fourth feedback unit 2042 is connected to the second output terminal of the auxiliary circuit 2012, and the first terminal of the fourth feedback unit 2042 is connected to the first output terminal of the auxiliary circuit 2012.

[0056] The third feedback unit 2041 is used to pull the voltage of the second output terminal of the auxiliary circuit 2012 according to the voltage of the first output terminal of the auxiliary circuit 2012 during the sampling phase, and the fourth feedback unit 2042 is used to pull the voltage of the first output terminal of the auxiliary circuit 2012 according to the voltage of the second output terminal of the auxiliary circuit 2012 during the sampling phase.

[0057] The direction in which the third feedback unit 2041 pulls the voltage at the second output terminal of the auxiliary circuit 2012 is the same as the direction in which the fourth feedback unit 2042 pulls the voltage at the first output terminal of the auxiliary circuit 2012. When the third feedback unit 2041 pulls the voltage at the second output terminal of the auxiliary circuit 2012 upwards, the fourth feedback unit 2042 also pulls the voltage at the first output terminal of the auxiliary circuit 2012 upwards. When the third feedback unit 2041 pulls the voltage at the second output terminal of the auxiliary circuit 2012 downwards, the fourth feedback unit 2042 also pulls the voltage at the first output terminal of the auxiliary circuit 2012 downwards.

[0058] The following example illustrates the effect of pulling down the voltage of the two output terminals of the main circuit 2011: When the voltage of the first output terminal of the main circuit 2011 is higher than the voltage of the second output terminal of the main circuit 2011, the first feedback unit 2031 has a stronger ability to pull down the voltage of the second output terminal of the main circuit 2011, while the second feedback unit 2032 has a weaker ability to pull down the voltage of the first output terminal of the main circuit 2011. In other words, the voltage drop rate of the first output terminal is lower than that of the second output terminal, which in turn makes the voltage difference between the first and second output terminals larger and larger, thus achieving positive feedback.

[0059] When the voltage at the first output terminal of the main circuit 2011 is lower than the voltage at the second output terminal of the main circuit 2011, the first feedback unit 2031 has a weaker ability to pull down the voltage at the second output terminal of the main circuit 2011, while the second feedback unit 2032 has a stronger ability to pull down the voltage at the first output terminal of the main circuit 2011. In other words, the voltage drop rate at the first output terminal is higher than the voltage drop rate at the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0060] The following example illustrates the effect of pulling up the voltage of the two output terminals of the main circuit 2011: When the voltage of the first output terminal of the main circuit 2011 is higher than the voltage of the second output terminal of the main circuit 2011, the first feedback unit 2031 has a weaker ability to pull up the voltage of the second output terminal of the main circuit 2011, while the second feedback unit 2032 has a stronger ability to pull up the voltage of the first output terminal of the main circuit 2011. In other words, the voltage rise rate of the first output terminal is higher than that of the second output terminal, which in turn makes the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0061] When the voltage at the first output terminal of the main circuit 2011 is lower than the voltage at the second output terminal of the main circuit 2011, the first feedback unit 2031 has a stronger ability to pull up the voltage at the second output terminal of the main circuit 2011, while the second feedback unit 2032 has a weaker ability to pull up the voltage at the first output terminal of the main circuit 2011. In other words, the voltage rise rate at the first output terminal is lower than the voltage rise rate at the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal increasingly larger, thus achieving positive feedback.

[0062] In the above technical solution, when any one or both of the first reference signal and the second reference signal are not properly selected, it takes a relatively long time to generate a differential signal with a large difference in the corresponding input circuit. The positive feedback circuit in the corresponding input circuit accelerates the difference through the positive feedback mechanism after there is a slight difference between the two output terminals of the input circuit, shortens the sampling stage time, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

[0063] like Figure 4 As shown, one embodiment of this application provides a specific circuit structure for a comparator. The comparator has four input terminals and two output terminals. The comparator includes a first-stage circuit 201, a second-stage circuit 202, a first positive feedback circuit 203, and a second positive feedback circuit 204. The first-stage circuit 201 includes a main circuit 2011, an auxiliary circuit, and a common circuit 2013.

[0064] The main circuit includes a first input transistor N1, a second input transistor N2, and a third input transistor N3. The control terminal of the first input transistor N1 serves as the first input terminal of the comparator, used to receive the first input signal In1. The first terminal of the first input transistor N1 serves as the first output terminal of the main circuit. The control terminal of the second input transistor N2 serves as the second input terminal of the comparator, used to receive the first reference signal Vr1. The first terminal of the second input transistor N2 serves as the second output terminal of the main circuit. The control terminal of the third input transistor N3 receives a clock signal. The first terminal of the third input transistor N3 is connected to the second terminals of the first input transistor N1 and the second terminals of the second input transistor N2, and the second terminal of the third input transistor N3 is connected to ground.

[0065] The third input transistor N3 is used to control the operating state of the main circuit. During the reset phase, the third input transistor N3 is off, and the main circuit stops working. During the sampling phase, regeneration phase, and decision phase, the third input transistor N3 is on, and the main circuit operates. During the sampling phase, the first input transistor N1 and the second input transistor N2 generate a first differential signal under the control of the first input signal and the first reference signal.

[0066] The auxiliary circuit includes at least one parallel equalization module 2014. Each equalization module 2014 has a first output terminal and a second output terminal. The first output terminals of each equalization module 2014 are connected to each other to form the first output terminal of the auxiliary circuit. The second output terminals of each equalization module 2014 are connected to each other to form the second output terminal of the auxiliary circuit 2012.

[0067] Each equalizer module includes a fourth input transistor N4, a fifth input transistor N5, and a sixth input transistor N6. The control terminals of the fourth input transistors N4 of each equalizer module are connected to form the third input terminal of the comparator. The control terminals of the fifth input transistors N5 of each equalizer module are connected to form the fourth input terminal of the comparator.

[0068] The control terminal of the fourth input transistor N4 receives the second input signal In2, and the first terminal of the fourth input transistor N4 serves as the first output terminal of the equalization module. The control terminal of the fifth input transistor N5 receives the second reference signal Vr2, and the first terminal of the fifth input transistor N5 serves as the second output terminal of the equalization module. The control terminal of the sixth input transistor N6 receives the clock signal, and the first terminal of the sixth input transistor N6 is connected to the second terminals of the fourth input transistor N4 and the fifth input transistor N5. The second terminal of the sixth input transistor N6 is used to connect to the ground terminal.

[0069] The sixth input transistor N6 controls the operating state of the equalization module. During the reset phase, the sixth input transistor N6 is off, and the equalization module stops working. During the sampling, regeneration, and decision phases, the sixth input transistor N6 is on, and the equalization module operates. During the sampling phase, the fourth input transistor N4 and the fifth input transistor N5 generate a second differential numerator signal under the control of the second input signal and the second reference signal. The second differential numerator signals output by each equalization module are superimposed to form the second differential signal.

[0070] The common circuit 2013 includes a seventh input transistor P1 and an eighth input transistor P2. The control terminal of the seventh input transistor P1 is used to receive a clock signal, the first terminal of the seventh input transistor P1 is connected to the power supply terminal, and the second terminal of the seventh input transistor P1 is connected to the first terminal of the first input transistor N1 and the first terminal of the fourth input transistor N4.

[0071] The control terminal of the eighth input transistor P2 is used to receive the clock signal. The first terminal of the eighth input transistor P2 is connected to the power supply terminal. The second terminal of the eighth input transistor P2 is connected to the first terminal of the second input transistor N2 and the first terminal of the fifth input transistor N5.

[0072] The seventh input transistor P1 and the eighth input transistor P2 are turned on during the reset phase to reset the voltages at the two output terminals of the first stage circuit to a high level.

[0073] The second-stage circuit includes a first output transistor N7, a second output transistor N8, a third output transistor N9, a fourth output transistor N10, a fifth output transistor P3, a sixth output transistor P4, and a seventh output transistor P5.

[0074] The control terminal of the first output transistor N7 is the first input terminal of the second-stage circuit, and its control terminal is connected to the first terminal of the first input transistor N1 in the first-stage circuit. The first terminal of the first output transistor N7 is the first output terminal of the comparator. The second terminal of the first output transistor N7 is connected to the ground terminal.

[0075] The control terminal of the second output transistor N8 is the second input terminal of the second-stage circuit, and its control terminal is connected to the first terminal of the second input transistor N2 in the first-stage circuit. The first terminal of the second output transistor N8 is the second output terminal of the comparator. The second terminal of the second output transistor N8 is connected to the ground terminal.

[0076] The first terminal of the third output transistor N9 is connected to the first terminal of the first output transistor N7, and the second terminal of the third output transistor N9 is connected to the second terminal of the first output transistor N7.

[0077] The first terminal of the fourth output transistor N10 is connected to the first terminal of the second output transistor N8, and the second terminal of the fourth output transistor N10 is connected to the second terminal of the second output transistor N8.

[0078] The second terminal of the fifth output transistor P3 is connected to the first terminal of the third output transistor N9. After the control terminal of the fifth output transistor P3 is connected to the control terminal of the third output transistor N9, it is connected to the first terminal of the fourth output transistor N10.

[0079] The second terminal of the sixth output transistor P4 is connected to the first terminal of the fourth output transistor N10. After the control terminal of the sixth output transistor P4 is connected to the control terminal of the fourth output transistor N10, it is connected to the first terminal of the third output transistor N9.

[0080] The control terminal of the seventh output transistor P5 is used to receive the clock signal. The first terminal of the seventh output transistor P5 is connected to the power supply terminal. The second terminal of the seventh output transistor P5 is connected to the first terminal of the fifth output transistor P3 and the first terminal of the sixth output transistor P4.

[0081] The seventh output transistor P5 is used to control the operating state of the second-stage circuit. During the reset phase, the seventh output transistor P5 is turned off, and the second-stage circuit stops working. During the sampling phase, regeneration phase, and decision phase, the seventh output transistor P5 is turned on, and the second-stage circuit starts working.

[0082] During the regeneration and decision-making phases, the first output transistor N7 and the second output transistor N8 are used to amplify the differential signal of the first-stage circuit. The third output transistor N9, the fourth output transistor N10, the fifth output transistor P3, and the sixth output transistor P4 form a latch, which is used to amplify and latch the signal at the first terminal of the first output transistor N7 and the second output transistor N8 to output the comparison result.

[0083] The main circuit is connected to the ground terminal through the third input transistor N3, and to the power supply terminal through the seventh input transistor P1 and the eighth input transistor P2. That is, each current path in the main circuit contains 3 transistors, for example, the current path formed by the first input transistor N1, the third input transistor N3 and the seventh input transistor P1.

[0084] The second-stage circuit connects to the ground terminal via any one of the first output transistors N7 to the fourth output transistor N10, and connects to the power supply terminal via the seventh output transistor P5. That is, each current path in the second-stage circuit contains 3 transistors, for example, the current path formed by the first output transistor N7, the fifth input transistor P3, and the seventh input transistor P5.

[0085] With the above setup, using a first-stage circuit and a second-stage circuit structure, the comparator operates at a lower voltage and has a wider range of applications compared to a comparator using a single-stage structure.

[0086] In one embodiment, the first feedback unit 2031 includes a first feedback transistor N11. The control terminal of the first feedback transistor N11 is connected to the first terminal of the first input transistor N1, and the first terminal of the first feedback transistor N11 is connected to the first terminal of the second input transistor N2. The second terminal of the first feedback transistor N11 is connected to the second terminal of the second input transistor N2.

[0087] The second feedback unit 2032 includes a second feedback transistor N12. The control terminal of the second feedback transistor N12 is connected to the first terminal of the second input transistor N2. The first terminal of the second feedback transistor N12 is connected to the first terminal of the first input transistor N1. The second terminal of the second feedback transistor N12 is connected to the second terminal of the first input transistor N1.

[0088] In one embodiment, the first feedback transistor N11, the second feedback transistor N12, the first input transistor N1, and the second input transistor N2 are of the same type, ensuring that the direction of the voltage at the second output terminal of the main circuit 2011 pulled by the first feedback transistor N11 is the same as the direction of the voltage at the first output terminal of the main circuit 2011 pulled by the second feedback transistor N12. It is also ensured that the direction of the voltage at the output terminal of the main circuit 2011 pulled by the feedback transistor is the same as the direction of the voltage at the output terminal of the main circuit 2011 pulled by the input transistor, thereby achieving positive feedback.

[0089] The greater the voltage at the first terminal of the first input transistor N1, the greater the ability of the first feedback transistor N11 to pull down the voltage at the first terminal of the second input transistor N2, and the faster the voltage at the first terminal of the second input transistor N2 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the first input transistor N1 and the second input transistor N2.

[0090] In one embodiment, the third feedback unit 2041 includes a third feedback transistor N13. The control terminal of the third feedback transistor N13 is connected to the first terminal of the fourth input transistor N4, and the first terminal of the third feedback transistor N13 is connected to the first terminal of the fifth input transistor N5. The second terminal of the third feedback transistor N13 is connected to the second terminal of the fourth input transistor N4.

[0091] The fourth feedback unit 2042 includes a fourth feedback transistor N14. The control terminal of the fourth feedback transistor N14 is connected to the first terminal of the fifth input transistor N5. The first terminal of the fourth feedback transistor N14 is connected to the first terminal of the fourth input transistor N4. The second terminal of the fourth feedback transistor N14 is connected to the second terminal of the fifth input transistor N5.

[0092] In one embodiment, the third feedback transistor N13, the fourth feedback transistor N14, the fourth input transistor N4, and the fifth input transistor N5 are of the same type, ensuring that the direction of the voltage at the second output terminal of the auxiliary circuit 2012 pulled by the third feedback transistor N13 is the same as the direction of the voltage at the first output terminal of the auxiliary circuit 2012 pulled by the fourth feedback transistor N14. It also ensures that the voltage at the output terminal of the auxiliary circuit 2012 pulled by the feedback transistor is in the same direction as the voltage at the output terminal of the auxiliary circuit 2012 pulled by the input transistor, thereby achieving positive feedback.

[0093] The greater the voltage at the first terminal of the fourth input transistor N4, the greater the ability of the third feedback transistor N13 to pull down the voltage at the first terminal of the fifth input transistor N5, and the faster the voltage at the first terminal of the fifth input transistor N5 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the fourth input transistor N4 and the fifth input transistor N5.

[0094] In one embodiment, the first feedback transistors N11 to N14, the first input transistors N1 to N6 are of the same type, and the seventh input transistor P1 and the eighth input transistor P2 are of the same type.

[0095] If the first feedback transistor N11 to the fourth feedback transistor N14, and the first input transistor N1 to the sixth input transistor N6 are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. If the seventh input transistor P1 and the eighth input transistor P2 are P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0096] In one embodiment, the first input transistor N1 and the second input transistor N2 are the same size, the fourth input transistor N4 and the fifth input transistor N5 are the same size, and the size of the fourth input transistor N4 is less than half the size of the first input transistor N1.

[0097] With the above settings, the influence of the auxiliary circuit can be avoided from being too great, which would cause the first differential signal to be reversed. For example, the first input signal and the first reference signal make the first terminal voltage of the first input transistor N1 greater than the first terminal voltage of the second input transistor N2. Due to the intervention of the second differential signal, the first differential signal is reversed, which means that the first terminal voltage of the first input transistor N1 is less than the first terminal voltage of the second input transistor N2.

[0098] In one embodiment, the first feedback transistor N11 and the second feedback transistor N12 are of the same size, and the third feedback transistor N13 and the fourth feedback transistor N14 are of the same size. The size of the first feedback transistor N11 is less than half the size of the first input transistor N1. The size of the third feedback transistor N13 is less than half the size of the fourth input transistor N4.

[0099] By using the above settings, we can avoid the feedback transistor from having too much influence on the voltage, which would affect the input transistor's accurate sensing of the input and reference signals. This ensures both the improved response rate of the comparator and the accuracy of the comparator's output.

[0100] In one embodiment, the first output transistor N7 to the fourth output transistor N10 are of the same type, and the fifth output transistor P3 to the seventh output transistor P5 are of the same type.

[0101] If the first output transistor N7 to the fourth output transistor N10 are all N-type transistors, with the drain of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal. If the fifth output transistor P3 to the seventh output transistor P5 are all P-type transistors, with the source of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal.

[0102] The principle of the comparator in eliminating inter-symbol interference is described below with reference to Table 1. The values ​​of the second input signal and the second reference signal at time t1 are determined based on the magnitudes of the first input signal and the first reference signal at time t0. If the first input signal at time t0 is greater than the first reference signal at time t0, the second input signal at time t1 is less than the value of the second reference signal, and vice versa.

[0103] Table 1. Inter-symbol interference situation

[0104]

[0105] As shown in Table 1, in the first case, inter-symbol interference makes the voltage of the first input transistor N1 equal to the voltage of the second input transistor N2, but the voltage of the fourth input transistor N4 is less than the voltage of the fifth input transistor N5, which makes the voltage of the first output terminal O1 of the first stage circuit less than the voltage of the second output terminal O2. This is the same result as when there is no inter-symbol interference, and the inter-symbol interference is eliminated. It should be noted here that, since the size of each transistor in the auxiliary circuit is less than half the size of each transistor in the main circuit, even in the second case, VN1 < VN2, VN4 > VN5, where VN1, VN2, VN4, and VN5 represent the drain voltages of the first input transistor N1, the second input transistor N2, the third input transistor N3, and the fourth input transistor N4, respectively, the voltage pull capability of the fourth input transistor N4 and the fifth input transistor N5 is less than that of the first input transistor N1 and the second input transistor N2. This results in the voltage VO1 at the first output terminal of the first stage circuit still being less than the voltage VO2 at the second output terminal of the first stage circuit. This is the same result as the absence of inter-symbol interference, and the inter-symbol interference is eliminated.

[0106] like Figure 5 As shown, one embodiment of this application provides a specific circuit structure for a comparator. The comparator has four input terminals and two output terminals. The comparator includes a first-stage circuit 201, a second-stage circuit 202, a first positive feedback circuit 203, and a second positive feedback circuit 204. The first-stage circuit 201 includes a main circuit 2011, an auxiliary circuit, and a common circuit 2013.

[0107] The main circuit includes a first input transistor P1, a second input transistor P2, and a third input transistor P3. The control terminal of the first input transistor P1 serves as the first input terminal of the comparator, used to receive the first input signal In1. The first terminal of the first input transistor P1 serves as the first output terminal of the main circuit. The control terminal of the second input transistor P2 serves as the second input terminal of the comparator, used to receive the first reference signal Vr1. The first terminal of the second input transistor P2 serves as the second output terminal of the main circuit. The control terminal of the third input transistor P3 receives the clock signal. The first terminal of the third input transistor P3 is connected to the second terminals of the first input transistor P1 and the second terminals of the second input transistor P2, and the second terminal of the third input transistor P3 is connected to the power supply terminal.

[0108] The third input transistor P3 is used to control the operating state of the main circuit. During the reset phase, the third input transistor P3 is turned off, and the main circuit stops working. During the sampling phase, regeneration phase, and decision phase, the third input transistor P3 is turned on, and the main circuit works. During the sampling phase, the first input transistor P1 and the second input transistor P2 generate the first differential signal under the control of the first input signal and the first reference signal.

[0109] The auxiliary circuit includes at least one equalization module 2014 connected in parallel. Each equalization module 2014 has a first output terminal and a second output terminal. The first output terminals of each equalization module 2014 are connected to each other to form the first output terminal of the auxiliary circuit. The second output terminals of each equalization module 2014 are connected to each other to form the second output terminal of the auxiliary circuit.

[0110] By controlling the number of equalization modules, the ability of the auxiliary circuit to pull the voltage at the output of the main circuit can be adjusted, avoiding the auxiliary circuit's excessive pulling ability from affecting the polarity of the differential signal at the output of the main circuit. Furthermore, by setting the second input signal and the second reference signal at the current moment based on the first input signal and the first reference signal received by the main circuit at the previous moment, the inter-symbol interference at the first input of the main circuit can be effectively eliminated, thereby improving the accuracy of the comparator.

[0111] Each equalizer module includes a fourth input transistor P4, a fifth input transistor P5, and a sixth input transistor P6. The control terminals of the fourth input transistors P4 of each equalizer module are connected to form the third input terminal of the comparator. The control terminals of the fifth input transistors P5 of each equalizer module are connected to form the fourth input terminal of the comparator.

[0112] The control terminal of the fourth input transistor P4 receives the second input signal In2, and the first terminal of the fourth input transistor P4 serves as the first output terminal of the equalization module. The control terminal of the fifth input transistor P5 receives the second reference signal Vr2, and the first terminal of the fifth input transistor P5 serves as the second output terminal of the equalization module. The control terminal of the sixth input transistor P6 receives the clock signal, and the first terminal of the sixth input transistor P6 is connected to the second terminals of the fourth input transistor P4 and the fifth input transistor P5. The second terminal of the sixth input transistor P6 is connected to the power supply terminal.

[0113] The sixth input transistor P6 controls the operating state of the equalization module. During the reset phase, the sixth input transistor P6 is off, and the equalization module stops working. During the sampling, regeneration, and decision phases, the sixth input transistor P6 is on, and the equalization module operates. During the sampling phase, the fourth input transistor P4 and the fifth input transistor P5 generate a second differential numerator signal under the control of the second input signal and the second reference signal. The second differential numerator signals output by each equalization module are superimposed to form the second differential signal.

[0114] The common circuit 2013 includes a seventh input transistor N1 and an eighth input transistor N2. The control terminal of the seventh input transistor N1 is used to receive a clock signal. The first terminal of the seventh input transistor N1 is connected to the ground terminal, and the second terminal of the seventh input transistor N1 is connected to the first terminal of the first input transistor P1 and the first terminal of the fourth input transistor P4.

[0115] The control terminal of the eighth input transistor N2 is used to receive the clock signal. The first terminal of the eighth input transistor N2 is connected to the ground terminal. The second terminal of the eighth input transistor N2 is connected to the first terminal of the second input transistor P2 and the first terminal of the fifth input transistor P5.

[0116] The seventh input transistor N1 and the eighth input transistor N2 are turned on during the reset phase to reset the voltages at the two output terminals of the first stage circuit to a high level.

[0117] The second-stage circuit includes a first output transistor P7, a second output transistor P8, a third output transistor P9, a fourth output transistor P10, a fifth output transistor N3, a sixth output transistor N4, and a seventh output transistor N5.

[0118] The control terminal of the first output transistor P7 is the first input terminal of the second-stage circuit, and its control terminal is connected to the first terminal of the first input transistor P1 in the first-stage circuit. The first terminal of the first output transistor P7 is the first output terminal of the comparator. The second terminal of the first output transistor P7 is connected to the power supply terminal.

[0119] The control terminal of the second output transistor P8 is the second input terminal of the second-stage circuit, and its control terminal is connected to the first terminal of the second input transistor P2 in the first-stage circuit. The first terminal of the second output transistor P8 is the second output terminal of the comparator. The second terminal of the second output transistor P8 is connected to the power supply terminal.

[0120] The first terminal of the third output transistor P9 is connected to the first terminal of the first output transistor P7, and the second terminal of the third output transistor P9 is connected to the second terminal of the first output transistor P7.

[0121] The first terminal of the fourth output transistor P10 is connected to the first terminal of the second output transistor P8, and the second terminal of the fourth output transistor P10 is connected to the second terminal of the second output transistor P8.

[0122] The second terminal of the fifth output transistor N3 is connected to the first terminal of the third output transistor P9. After the control terminal of the fifth output transistor N3 is connected to the control terminal of the third output transistor P9, it is connected to the first terminal of the fourth output transistor P10.

[0123] The second terminal of the sixth output transistor N4 is connected to the first terminal of the fourth output transistor P10. After the control terminal of the sixth output transistor N4 is connected to the control terminal of the fourth output transistor P10, it is connected to the first terminal of the third output transistor P9.

[0124] The control terminal of the seventh output transistor N5 is used to receive the clock signal. The first terminal of the seventh output transistor N5 is connected to the ground terminal. The second terminal of the seventh output transistor N5 is connected to the first terminal of the fifth output transistor N3 and the first terminal of the sixth output transistor N4.

[0125] The seventh output transistor N5 is used to control the operating state of the second-stage circuit. During the reset phase, the seventh output transistor N5 is turned off, and the second-stage circuit stops working. During the sampling phase, regeneration phase, and decision phase, the seventh output transistor N5 is turned on, and the second-stage circuit starts working.

[0126] During the regeneration and decision-making phases, the first output transistor P7 and the second output transistor P8 are used to amplify the differential signal of the first-stage circuit. The third output transistor P9, the fourth output transistor P10, the fifth output transistor N3, and the sixth output transistor N4 form a latch, which is used to amplify and latch the signal at the first terminal of the first output transistor P7 and the second output transistor P8 to output the comparison result.

[0127] The main circuit is connected to the power supply terminal through the third input transistor P3, and to the ground terminal through the seventh input transistor N1 and the eighth input transistor N2. That is, each current path in the main circuit contains 3 transistors, for example, the current path formed by the first input transistor P1, the third input transistor P3 and the seventh input transistor N1.

[0128] The second-stage circuit connects to the power supply terminal through any one of the first output transistors P7 to the fourth output transistor P10, and connects to the ground terminal through the seventh output transistor N5. That is, each current path in the second-stage circuit contains 3 transistors, for example, the current path formed by the first output transistor P7, the fifth input transistor N3, and the seventh input transistor N5.

[0129] With the above setup, using a first-stage circuit and a second-stage circuit structure, the comparator operates at a lower voltage and has a wider range of applications compared to a comparator using a single-stage structure.

[0130] In one embodiment, the first feedback unit 2031 includes a first feedback transistor P11. The control terminal of the first feedback transistor P11 is connected to the first terminal of the first input transistor P1, and the first terminal of the first feedback transistor P11 is connected to the first terminal of the second input transistor P2. The second terminal of the first feedback transistor P11 is connected to the second terminal of the second input transistor P2.

[0131] The second feedback unit 2032 includes a second feedback transistor P12. The control terminal of the second feedback transistor P12 is connected to the first terminal of the second input transistor P2. The first terminal of the second feedback transistor P12 is connected to the first terminal of the first input transistor P1. The second terminal of the second feedback transistor P12 is connected to the second terminal of the first input transistor P1.

[0132] In one embodiment, the first feedback transistor P11, the second feedback transistor P12, the first input transistor P1, and the second input transistor P2 are of the same type, ensuring that the direction of the voltage at the second output terminal of the main circuit 2011 pulled by the first feedback transistor P11 is the same as the direction of the voltage at the first output terminal of the main circuit 2011 pulled by the second feedback transistor P12. It is also ensured that the direction of the voltage at the output terminal of the main circuit 2011 pulled by the feedback transistor is the same as the direction of the voltage at the output terminal of the main circuit 2011 pulled by the input transistor, thereby achieving positive feedback.

[0133] The greater the voltage at the first terminal of the first input transistor P1, the greater the ability of the first feedback transistor P11 to pull down the voltage at the first terminal of the second input transistor P2, and the faster the voltage at the first terminal of the second input transistor P2 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the first input transistor P1 and the second input transistor P2.

[0134] In one embodiment, the third feedback unit 2041 includes a third feedback transistor P13. The control terminal of the third feedback transistor P13 is connected to the first terminal of the fourth input transistor P4, and the first terminal of the third feedback transistor P13 is connected to the first terminal of the fifth input transistor P5. The second terminal of the third feedback transistor P13 is connected to the second terminal of the fourth input transistor P4.

[0135] The fourth feedback unit 2042 includes a fourth feedback transistor P14. The control terminal of the fourth feedback transistor P14 is connected to the first terminal of the fifth input transistor P5. The first terminal of the fourth feedback transistor P14 is connected to the first terminal of the fourth input transistor P4. The second terminal of the fourth feedback transistor P14 is connected to the second terminal of the fifth input transistor P5.

[0136] In one embodiment, the third feedback transistor P13, the fourth feedback transistor P14, the fourth input transistor P4, and the fifth input transistor P5 are of the same type, ensuring that the direction of the voltage at the second output terminal of the auxiliary circuit 2012 pulled by the third feedback transistor P13 is the same as the direction of the voltage at the first output terminal of the auxiliary circuit 2012 pulled by the fourth feedback transistor P14. It also ensures that the voltage at the output terminal of the auxiliary circuit 2012 pulled by the feedback transistor is in the same direction as the voltage at the output terminal of the auxiliary circuit 2012 pulled by the input transistor, thereby achieving positive feedback.

[0137] The greater the voltage at the first terminal of the fourth input transistor P4, the greater the ability of the third feedback transistor P13 to pull down the voltage at the first terminal of the fifth input transistor P5, and the faster the voltage at the first terminal of the fifth input transistor P5 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the fourth input transistor P4 and the fifth input transistor P5.

[0138] In one embodiment, the first feedback transistors P11 to P14, the first input transistors P1 to P6, are of the same type, and the seventh input transistor N1 and the eighth input transistor N2 are of the same type.

[0139] If the first feedback transistor P11 to the fourth feedback transistor P14, and the first input transistor P1 to the sixth input transistor P6 are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. If the seventh input transistor N1 and the eighth input transistor N2 are N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0140] In one embodiment, the first input transistor P1 and the second input transistor P2 are the same size, the fourth input transistor P4 and the fifth input transistor P5 are the same size, and the size of the fourth input transistor P4 is less than half the size of the first input transistor P1.

[0141] With the above settings, the influence of the auxiliary circuit can be avoided from being too great, which would cause the first differential signal to be reversed. For example, the first input signal and the first reference signal make the first terminal voltage of the first input transistor P1 greater than the first terminal voltage of the second input transistor P2. Due to the intervention of the second differential signal, the first differential signal is reversed, which means that the first terminal voltage of the first input transistor P1 is less than the first terminal voltage of the second input transistor P2.

[0142] In one embodiment, the first feedback transistor P11 and the second feedback transistor P12 are of the same size, and the third feedback transistor P13 and the fourth feedback transistor P14 are of the same size. The size of the first feedback transistor P11 is less than half the size of the first input transistor P1. The size of the third feedback transistor P13 is less than half the size of the fourth input transistor P4.

[0143] By using the above settings, we can avoid the feedback transistor from having too much influence on the voltage, which would affect the input transistor's accurate sensing of the input and reference signals. This ensures both the improved response rate of the comparator and the accuracy of the comparator's output.

[0144] In one embodiment, the first output transistor P7 to the fourth output transistor P10 are of the same type, and the fifth output transistor N3 to the seventh output transistor N5 are of the same type.

[0145] If the first output transistor P7 to the fourth output transistor P10 are all P-type transistors, with the drain of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal. If the fifth output transistor N3 to the seventh output transistor N5 are all N-type transistors, with the source of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal.

[0146] The principle of the comparator in eliminating inter-symbol interference is described below with reference to Table 2. The values ​​of the second input signal and the second reference signal at time t1 are determined based on the magnitudes of the first input signal and the first reference signal at time t0. If the first input signal at time t0 is greater than the first reference signal at time t0, the second input signal at time t1 is less than the value of the second reference signal, and vice versa.

[0147] Table 2 shows the inter-symbol interference situation.

[0148]

[0149] As shown in Table 2, in the first case, inter-symbol interference (ISI) causes the voltages of the first input transistor P1 and the second input transistor P2 to be equal, but the voltage of the fourth input transistor P4 is less than the voltage of the fifth input transistor P5. This results in the voltage at the first output terminal O1 of the first stage circuit being less than the voltage at the second output terminal O2. This is the same result as without ISI, and the ISI is eliminated. It should be noted that, since the size of each transistor in the auxiliary circuit is less than half the size of each transistor in the main circuit, even in the second case, where VP1 < VP2 and VP4 > VP5 (where VP1, VP2, VP4, and VP5 represent the drain voltages of the first input transistor P1, the second input transistor P2, the third input transistor P3, and the fourth input transistor P4, respectively), the voltage pull capability of the fourth input transistor P4 and the fifth input transistor P5 is less than that of the first input transistor P1 and the second input transistor P2. This results in the voltage VO1 at the first output terminal of the first stage circuit still being less than the voltage VO2 at the second output terminal of the first stage circuit. This is the same result as without ISI, and the ISI is eliminated.

[0150] like Figure 6As shown, one embodiment of this application provides a specific circuit structure for a comparator. The comparator has four input terminals and two output terminals. The comparator includes a first-stage circuit 201, a second-stage circuit 202, a first positive feedback circuit 203, and a second positive feedback circuit 204. The first-stage circuit 201 includes a main circuit 2011, an auxiliary circuit 2012, and a common circuit 2013.

[0151] The auxiliary circuit includes at least one controllable input module. Each input module includes a fourth input transistor, a fifth input transistor, and a sixth input transistor. The control terminal of the fourth input transistor is used to receive a second reference signal, and the control terminal of the fifth input transistor is used to receive a second input signal. The first terminal of the sixth input transistor is connected to the second terminals of the fourth and fifth input transistors. The sixth input transistor is used to receive a clock signal, which can control the operating state of the controllable input module, thereby controlling the number of operating controllable input modules.

[0152] The second positive feedback circuit 204 includes at least one controllable feedback module 2040, wherein each controllable feedback module includes a third feedback unit 2041, a fourth feedback unit 2042, a first switch 2043, and a second switch 2044. The third feedback unit 2041 and the fourth feedback unit 2042 are each provided with a control terminal and a first terminal.

[0153] The control terminal of the third feedback unit 2041 is connected to the first output terminal of the auxiliary circuit 202 via the first switch 2043, and the first terminal of the third feedback unit 2041 is connected to the second output terminal of the auxiliary circuit 202. The control terminal of the fourth feedback unit 2042 is connected to the second output terminal of the auxiliary circuit 202 via the second switch 2044, and the first terminal of the fourth feedback unit 2042 is connected to the first output terminal of the auxiliary circuit 202.

[0154] The first switch 2043 controls whether the third feedback unit 2041 generates positive feedback, and the second switch 2044 controls whether the fourth feedback unit 2042 generates positive feedback. By controlling the closing and opening of the first switch 2043 and the second switch 2044, the controllable feedback module 2040 can be controlled to generate positive feedback. When both the first switch 2043 and the second switch 2044 are closed, the controllable feedback module 2040 can accelerate the difference between the second differential signals at the output of the auxiliary circuit through the positive feedback mechanism. When both the first switch 2043 and the second switch 2044 are open, the controllable feedback module 2040 is disconnected from the auxiliary circuit and cannot generate positive feedback at the output of the auxiliary circuit.

[0155] When the comparator is operating, the number of controllable feedback modules generating positive feedback can be controlled, thereby controlling the ability of the second positive feedback circuit to pull the difference between the second differential signals. This controls, on the one hand, the time the comparator spends in the sampling phase, ensuring the comparator's response rate. On the other hand, it balances the ability of the second positive feedback circuit to pull the voltage at the output of the auxiliary circuit and the ability of the second input signal and the second reference signal to pull the voltage at the output of the auxiliary circuit, preventing the second positive feedback circuit from affecting the polarity of the second differential signal generated at the output of the auxiliary circuit. Furthermore, the number of operating controllable input modules can be controlled, and based on this number, the number of controllable feedback modules generating positive feedback can be controlled, ensuring that the polarity of the signal after the first differential signal and the second differential signal are added is the same as the polarity of the first differential signal. The second differential signal only serves to adjust the first differential signal, ensuring that the comparator can accurately output the comparison result based on the first input signal and the first reference signal.

[0156] Figure 7 and Figure 8 For based on Figure 6 The circuit diagram shown represents one specific example of a comparator, in which the main circuit 2011, auxiliary circuit 2012, common circuit 2013, second-stage circuit 202, and first positive feedback circuit 203 have the same structure. Figure 4 The comparators shown are the same, so they will not be described again here.

[0157] The following is combined with Figure 7 and Figure 8 Describe the specific circuit structure of each controllable feedback module 2040 in the second positive feedback circuit 204.

[0158] The third feedback unit 2041 includes a third feedback transistor N13. The control terminal of the third feedback transistor N13 serves as the control terminal of the third feedback unit 2041, and the first terminal of the third feedback transistor N13 serves as the first terminal of the third feedback unit 2041. The control terminal of the third feedback transistor N13 is connected to the first terminal of the fourth input transistor N4 via a first switch 2045. The fourth feedback unit 2042 includes a fourth feedback transistor N14. The control terminal of the fourth feedback transistor N14 serves as the control terminal of the fourth feedback unit 2042, and the first terminal of the fourth feedback transistor N14 serves as the first terminal of the fourth feedback unit 2042. The control terminal of the fourth feedback transistor N14 is connected to the first terminal of the fifth input transistor N5 via a second switch 2044.

[0159] The first switch 2043 includes a first transmission gate G1, and the second switch 2044 includes a second transmission gate G2. The first transmission gate G1 is controlled by a first enable signal EN1, and the second transmission gate G2 is controlled by a second enable signal EN2. The first enable signal EN1 and the second enable signal EN2 are generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and the test mode signal.

[0160] By controlling the switching states of the first transmission gate G1 and the second transmission gate G2 with the enable signal, the third feedback transistor N13 and the fourth feedback transistor N14 can be controlled to provide a positive feedback mechanism, thereby adjusting the number of controllable feedback modules participating in the positive feedback.

[0161] In one embodiment, the second positive feedback circuit 204 further includes a first zero switch K10 and a second zero-zero switch K00. The control terminal of the third feedback unit 2041 is also connected to the ground terminal through the first zero switch K10. The first zero switch K10 is used to conduct when the first transmission gate G1 is closed, so that the transistor in the third feedback unit 2041 is not floating, reducing external interference to the comparator. The control terminal of the fourth feedback unit 2042 is also connected to the ground terminal through the second zero-zero switch K00. The second zero-zero switch K00 is used to conduct when the second transmission gate G2 is closed, so that the transistor in the fourth feedback unit 2042 is not floating, reducing external interference to the comparator.

[0162] In one embodiment, if the third feedback transistor N13, the fourth feedback transistor N14, the first zero switch K10, and the zero-zero switch K00 are N-type transistors, the drain of the N-type transistor is the first terminal, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal. The first terminal of the first zero switch K10 is connected to the control terminal of the third feedback transistor N13, the first terminal of the zero-zero switch K00 is connected to the control terminal of the fourth feedback transistor N14, and the second terminals of the first zero switch K10 and the zero-zero switch K00 are grounded, so as to pull down the third feedback transistor N13 to a low level when the first transmission gate G1 is closed, and pull down the fourth feedback transistor N14 to a low level when the second transmission gate G2 is closed.

[0163] Figure 9 and Figure 10 For based on Figure 6 The circuit diagram of one specific comparator shown has the same structure as the main circuit 2011, auxiliary circuit 2012, common circuit 2013, second-stage circuit 202, and first positive feedback circuit 203. Figure 5 The comparators shown are the same, so they will not be described again here.

[0164] The connection relationships between the third feedback unit 2041, the fourth feedback unit 2042, the first switch 2043, and the second switch 2044 of each controllable feedback module 2040 in the second positive feedback circuit 204 have been described. Figure 8 The structure is described in detail here, and will not be repeated.

[0165] It should be noted here that if the third feedback transistor P13, the fourth feedback transistor P14, the first zero switch K10, and the zero-zero switch K00 are P-type transistors, the drain of the P-type transistor is the first terminal, the source of the P-type transistor is the second terminal, the gate of the P-type transistor is the control terminal, and the second terminals of the first zero switch K10 and the zero-zero switch K00 are connected to the power supply terminal.

[0166] In the above embodiments, the second positive feedback circuit includes multiple controllable feedback modules. By controlling the number of controllable feedback modules that provide the positive feedback mechanism, the ability of the second positive feedback circuit to pull the voltage of the two output terminals of the auxiliary circuit can be adjusted, thereby controlling the time when the comparator is in the sampling stage. It can also balance the pulling ability of the second positive feedback circuit, the second input signal, and the second reference signal on the output terminal of the auxiliary circuit, thereby improving the response rate and accuracy of the comparator.

[0167] like Figure 11 As shown, an embodiment of this application provides a decision feedback equalization circuit, including the four comparators described in the above embodiment, which are sequentially labeled as first comparator 100, second comparator 200, third comparator 300 and fourth comparator 400.

[0168] Specifically, the third input terminal In2 of the first comparator 100 is connected to the first output terminal P270B of the fourth comparator 400, and the fourth input terminal Vr2 of the first comparator 100 is connected to the second output terminal P270 of the fourth comparator 400. The third input terminal In2 of the second comparator 200 is connected to the first output terminal P0B of the first comparator 100, and the fourth input terminal Vr2 of the second comparator 200 is connected to the second output terminal P0 of the first comparator 100. The third input terminal In2 of the third comparator 300 is connected to the first output terminal P90B of the second comparator 200, and the fourth input terminal Vr2 of the third comparator 300 is connected to the second output terminal P90 of the second comparator 200. The third input terminal In2 of the fourth comparator 400 is connected to the first output terminal P270B of the third comparator 300, and the fourth input terminal Vr2 of the fourth comparator 400 is connected to the second output terminal P270 of the third comparator 300.

[0169] The first input terminal In1 of the first comparator 100 to the fourth comparator 400 all receive the first input signal, and the second input terminal Vref1 of the first comparator 100 to the fourth comparator 400 all receive the first reference signal.

[0170] Assuming that at the previous moment, when the first input signal was greater than the first reference signal, the fourth register 400 output the number "1", at the current moment, the third input terminal In2 of the first register 100 receives a low level, and the fourth input terminal Vr2 of the first register 100 receives a high level. That is, the signal at the third input terminal In2 is less than the signal at the fourth input terminal Vr2. Assuming that the first input signal is also greater than the first reference signal at the current moment, inter-symbol interference will still make the first input signal greater than the first reference signal, and the first register 100 will still output the number "1".

[0171] Assuming that at the previous moment, when the first input signal was greater than the first reference signal, the fourth register 400 output the number "1". At the current moment, the signal at the third input terminal In2 of the first register is less than the signal at the fourth input terminal Vr2. Assuming that the first input signal is less than the first reference signal at the current moment, if inter-symbol interference makes the first input signal equal to or slightly greater than the first reference signal, since the signal at the third input terminal In2 is less than the signal at the fourth input terminal Vr2, the first register 100 will still output the number "0".

[0172] Assuming that at the previous moment, when the first input signal was less than the first reference signal, the fourth register 400 output the number "0". At the current moment, the signal at the third input terminal In2 of the first register 100 is greater than the signal at the fourth input terminal Vr2. Assuming that the first input signal is also less than the first reference signal at the current moment, inter-symbol interference will still cause the first input signal to be less than the first reference signal, and the first register 100 will still output the number "0".

[0173] Assuming that at the previous moment, when the first input signal was less than the first reference signal, the fourth register 400 output the number "0". At the current moment, the signal In2 at the third input terminal of the first register 100 is greater than the signal at the fourth input terminal Vr2. Assuming that the first input signal is greater than the first reference signal at the current moment, if inter-symbol interference makes the first input signal equal to or slightly less than the first reference signal, the first register 100 will still output the number "1" because the signal at the third input terminal is greater than the signal at the fourth input terminal.

[0174] The working principle of the second register 200 to the fourth register 400 is the same as that of the first register 100, and will not be repeated here.

[0175] Figure 11 The decision feedback equalization circuit shown is a first-order circuit. To achieve better elimination of inter-symbol interference, multi-order circuits are usually used. Figure 12 This is a schematic diagram of the effect of a fourth-order decision feedback equalizer circuit. Tap1 to tap4 represent the first-order to fourth-order decision feedback equalizer circuits, respectively. Figure 12As shown in Figure 1, the actual waveform of the first input signal under inter-symbol interference (ISI) is relatively flat when the first input signal switches from high to low level, indicating a possibility of misidentification of the first input signal as high. The fourth-order decision feedback equalization circuit effectively eliminates ISI, resulting in the equivalent waveform of the first input signal input to the equalization circuit, as shown in Figure 2, with a steeper falling edge.

[0176] In one embodiment, the phase of the first clock signal of the first comparator 100 is 90° earlier than the phase of the second clock signal of the second comparator 200, the phase of the first clock signal of the first comparator 100 is 180° earlier than the phase of the third clock signal of the third comparator 300, and the phase of the first clock signal of the first comparator 100 is 270° earlier than the phase of the fourth clock signal of the fourth comparator 400.

[0177] In one embodiment, the voltage flip time from the output of the first comparator 100 to the voltage flip time T of the output of the fourth comparator 400 is... FB Both are less than the time interval 1U1 between the first clock signal and the second clock signal, such as Figure 13 As shown, taking the fourth comparator as an example, when the switching time of the output voltage of the fourth comparator 400 is less than 1U1, 1UI represents the time interval between the first clock signal and the second clock signal. This ensures that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has already stably output the comparison result, and the fourth comparator 400 maintains the comparison result, so that the first comparator 100 can eliminate inter-symbol interference based on the comparison result of the fourth comparator 400.

[0178] In one embodiment, the decision feedback equalization circuit further includes four registers, labeled sequentially as first register 500, second register 600, third register 700, and fourth register 800. The input of first register 500 is connected to the two outputs of first comparator 100, the input of second register 600 is connected to the two outputs of second comparator 200, the input of third register 700 is connected to the two outputs of third comparator 300, and the input of fourth register 800 is connected to the two outputs of fourth comparator 400. The four registers are used to store the comparison results of the four corresponding comparators: D0 is the result output by first register 500, D90 is the result output by second register 600, D180 is the result output by third register 700, and D270 is the result output by fourth register 800.

[0179] In the above technical solution, the two output terminals of the fourth register are connected to the two input terminals of the first register, and the two output terminals of the first register are connected to the two input terminals of the second register, and so on, to form a decision feedback equalization circuit. The other two input terminals of the four registers receive the first input signal and the first reference signal. Under the control of the output terminal signals of the four registers, the inter-symbol interference caused by the continuous input of the first input signal in the register can be effectively eliminated.

[0180] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0181] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A decision feedback equalization circuit, characterized in that, It includes four comparators, labeled as the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. Each of the comparators has four inputs and two outputs, including: The first-level circuit includes a main circuit, an auxiliary circuit, and a common circuit. The main circuit and the auxiliary circuit are both connected to a power supply terminal or a ground terminal, and the common circuit is connected to a ground terminal or a power supply terminal. The main circuit has two input terminals and two output terminals. Its output terminal serves as the output terminal of the first stage circuit, and its two input terminals serve as the first input terminal and the second input terminal of the comparator. It is used to receive a first input signal and a first reference signal, and is also used to generate a first differential signal based on the first input signal and the first reference signal during the sampling stage. The auxiliary circuit has two input terminals and two output terminals. Its output terminals are connected to the output terminals of the main circuit. Its two input terminals serve as the third and fourth input terminals of the comparator, used to receive the second input signal and the second reference signal, and also used to generate a second differential signal based on the second input signal and the second reference signal during the sampling stage. A first positive feedback circuit, which is connected to the main circuit, is used to accelerate the difference between the first differential signals; A second positive feedback circuit, which is connected to the auxiliary circuit, is used to accelerate the difference between the second differential signals; The second-stage circuit has two input terminals and two output terminals. The two output terminals are the output terminals of the comparator, which are connected to the power supply terminal and the ground terminal. The two input terminals are connected to the output terminals of the first-stage circuit. It is used to amplify and latch the first differential signal and the second differential signal during the regeneration stage to output the comparison result. The first comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal directly connected to the first output terminal of the fourth comparator for receiving a second input signal, and a fourth input terminal directly connected to the second output terminal of the fourth comparator for receiving a second reference signal. The second comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal directly connected to the first output terminal of the first comparator for receiving a second input signal, and a fourth input terminal directly connected to the second output terminal of the first comparator for receiving a second reference signal. The third comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal directly connected to the first output terminal of the second comparator for receiving a second input signal, and a fourth input terminal directly connected to the second output terminal of the second comparator for receiving a second reference signal. The fourth comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal directly connected to the first output terminal of the third comparator for receiving a second input signal, and a fourth input terminal directly connected to the second output terminal of the third comparator for receiving a second reference signal.

2. The decision feedback equalization circuit according to claim 1, characterized in that, The first-stage circuit and the second-stage circuit have the same number of transistors in their respective current paths.

3. The decision feedback equalization circuit according to claim 1 or 2, characterized in that, The first positive feedback circuit includes: The first feedback unit has its control terminal connected to the first output terminal of the main circuit, and its first terminal connected to the second output terminal of the main circuit. The second feedback unit has its control terminal connected to the second output terminal of the main circuit, and its first terminal connected to the first output terminal of the main circuit.

4. The decision feedback equalization circuit according to claim 3, characterized in that: The first feedback unit includes: a first feedback transistor, whose control terminal is the control terminal of the first feedback unit, and whose first terminal is the first terminal of the first feedback unit; The second feedback unit includes: a second feedback transistor, whose control terminal is the control terminal of the second feedback unit, and whose first terminal is the first terminal of the second feedback unit.

5. The decision feedback equalization circuit according to claim 4, characterized in that, The main circuit includes: The first input transistor has a control terminal for receiving the first input signal, a first terminal for serving as the first output terminal of the main circuit, and a second terminal for being connected to the second terminal of the first feedback transistor. The second input transistor has a control terminal for receiving the first reference signal, a first terminal for serving as the second output terminal of the main circuit, and a second terminal connected to the second terminal of the second feedback transistor. The third input transistor has a control terminal for receiving clock signals. Its first terminal is connected to the second terminal of the first input transistor, the second terminal of the second input transistor, the second terminal of the first feedback transistor, and the second terminal of the second feedback transistor. Its second terminal is connected to the ground terminal or the power supply terminal.

6. The decision feedback equalization circuit according to claim 3, characterized in that, The second positive feedback circuit includes: The third feedback unit has its control terminal connected to the first output terminal of the auxiliary circuit, and its first terminal connected to the second output terminal of the auxiliary circuit. The fourth feedback unit has its control terminal connected to the second output terminal of the auxiliary circuit, and its first terminal connected to the first output terminal of the auxiliary circuit.

7. The decision feedback equalization circuit according to claim 6, characterized in that: The third feedback unit includes: a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, whose control terminal is the control terminal of the fourth feedback unit, and whose first terminal is the first terminal of the fourth feedback unit.

8. The decision feedback equalization circuit according to claim 7, characterized in that, The auxiliary circuit includes: The fourth input transistor has a control terminal for receiving the second input signal, a first terminal for serving as the first output terminal of the auxiliary circuit, and a second terminal for being connected to the second terminal of the third feedback transistor. The fifth input transistor has a control terminal for receiving the second reference signal, a first terminal for serving as the second output terminal of the auxiliary circuit, and a second terminal for being connected to the second terminal of the fourth feedback transistor. The sixth input transistor has a control terminal for receiving clock signals. Its first terminal is connected to the second terminal of the fourth input transistor, the second terminal of the fifth input transistor, the second terminal of the third feedback transistor, and the second terminal of the fourth feedback transistor. Its second terminal is connected to the ground terminal or the power supply terminal.

9. The decision feedback equalization circuit according to claim 8, characterized in that, The common circuit includes: The seventh input transistor has a control terminal for receiving clock signals, a first terminal connected to a power supply terminal or a ground terminal, and a second terminal connected to the first terminal of the first input transistor and the first terminal of the fourth input transistor. The eighth input transistor has a control terminal for receiving clock signals, a first terminal connected to a power supply terminal or a ground terminal, and a second terminal connected to the first terminal of the second input transistor and the first terminal of the fifth input transistor.

10. The decision feedback equalization circuit according to claim 8, characterized in that, The first to fourth feedback transistors and the first to sixth input transistors are all of the same type; the seventh and eighth input transistors are of the same type.

11. The decision feedback equalization circuit according to claim 9, characterized in that: The first feedback transistor and the second feedback transistor have the same size, the first input transistor and the second input transistor have the same size, and the size of the first feedback transistor is less than half the size of the first input transistor. The third feedback transistor and the fourth feedback transistor are the same size, the fourth input transistor and the fifth input transistor are the same size, and the size of the third feedback transistor is less than half the size of the fourth input transistor; The size of the fourth input transistor is less than half the size of the first input transistor.

12. The decision feedback equalization circuit according to claim 9, characterized in that: When the first feedback transistor to the fourth feedback transistor and the first input transistor to the sixth input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal and the gate of the N-type transistor is the control terminal; The seventh input transistor and the eighth input transistor are P-type transistors, with the source of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal. or When the first feedback transistor to the fourth feedback transistor and the first input transistor to the sixth input transistor are all P-type transistors, the drain of the P-type transistor is the first terminal and the gate of the P-type transistor is the control terminal. The seventh input transistor and the eighth input transistor are N-type transistors, with the source of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal.

13. The decision feedback equalization circuit according to claim 1, characterized in that, The second-stage circuit includes: The first output transistor has a control terminal that is the first input terminal of the second stage circuit, a first terminal that is the first output terminal of the second stage circuit, and a second terminal that is connected to ground or power supply. The second output transistor has a control terminal that is the second input terminal of the second stage circuit, a first terminal that is the second output terminal of the second stage circuit, and a second terminal that is connected to ground or power supply. The third output transistor has its first terminal connected to the first terminal of the first output transistor and its second terminal connected to the second terminal of the first output transistor. The fourth output transistor has its first terminal connected to the first terminal of the second output transistor and its second terminal connected to the second terminal of the second output transistor. The fifth output transistor has its second terminal connected to the first terminal of the third output transistor, its control terminal connected to the control terminal of the third output transistor, and its control terminal also connected to the first terminal of the fourth output transistor. The sixth output transistor has its second terminal connected to the first terminal of the fourth output transistor, its control terminal connected to the control terminal of the fourth output transistor, and its control terminal also connected to the first terminal of the third output transistor. The seventh output transistor has a control terminal for receiving clock signals, a first terminal connected to a power supply terminal or a ground terminal, and a second terminal connected to the first terminal of the fifth output transistor and the first terminal of the sixth output transistor.

14. The decision feedback equalization circuit according to claim 13, characterized in that: All of the first to fourth output transistors are N-type transistors, with the drain of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal. The fifth to the seventh output transistors are all P-type transistors, with the source of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal. or All of the first to fourth output transistors are P-type transistors, with the drain of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal. The fifth to the seventh output transistors are all N-type transistors, with the source of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal.

15. The decision feedback equalization circuit according to claim 1, characterized in that, The second positive feedback circuit includes at least one controllable feedback module; wherein each controllable feedback module includes: The third feedback unit has its control terminal connected to the first output terminal of the auxiliary circuit via a first switch, and its first terminal connected to the second output terminal of the auxiliary circuit. The fourth feedback unit has its control terminal connected to the second output terminal of the auxiliary circuit via a second switch, and its first terminal connected to the first output terminal of the auxiliary circuit.

16. The decision feedback equalization circuit according to claim 15, characterized in that: The third feedback unit includes: a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, whose control terminal is the control terminal of the fourth feedback unit, and whose first terminal is the first terminal of the fourth feedback unit.

17. The decision feedback equalization circuit according to claim 15, characterized in that: The first switch includes a first transmission gate, which is controlled by a first enable signal, which is generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and a test mode signal. The second switch includes a second transmission gate, which is controlled by a second enable signal, which is generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and the test mode signal.

18. The decision feedback equalization circuit according to claim 15, characterized in that, The control terminal of the third feedback unit is also connected to the ground terminal or the power supply terminal through the first zero switch; the control terminal of the fourth feedback unit is also connected to the ground terminal or the power supply terminal through the zero zero switch.

19. The decision feedback equalization circuit according to claim 1, characterized in that: The phase of the first clock signal of the first comparator is 90° earlier than the phase of the second clock signal of the second comparator; The phase of the first clock signal of the first comparator is 180° earlier than the phase of the third clock signal of the third comparator; The phase of the first clock signal of the first comparator is 270° earlier than the phase of the fourth clock signal of the fourth comparator.

20. The decision feedback equalization circuit according to claim 19, characterized in that: The voltage flip time of the first comparator and the voltage flip time of the output terminal of the fourth comparator are both less than the time interval between the first clock signal and the second clock signal.

21. The decision feedback equalization circuit according to any one of claims 1 to 20, characterized in that, The circuit also includes four registers, which are labeled as register 1, register 2, register 3 and register 4 in sequence; The input terminal of the first register is connected to the two output terminals of the first comparator; The input of the second register is connected to the two outputs of the second comparator; The input of the third register is connected to the two outputs of the third comparator; The input of the fourth register is connected to the two outputs of the fourth comparator.

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