Circuit board manufacturing method and circuit board

Abstract

The application relates to the technical field of circuit board manufacturing, and provides a circuit board manufacturing method and a circuit board. The circuit board manufacturing method comprises the following steps: providing a substrate; performing one-time exposure and one-time development on the substrate; performing one-time electroplating on the substrate; removing the first photoresist covering the second area; arranging the second photoresist on the substrate; removing the first photoresist and the second photoresist on the substrate; and etching to remove the first copper layer in the first to-be-etched area and the first copper layer in the second to-be-etched area. The circuit board manufacturing method can solve the problem that the fine circuit manufactured by the traditional fine circuit manufacturing method cannot meet the requirements of being thin and thick.

Description

Technical Field

[0001] This application relates to the field of circuit board manufacturing technology, and in particular to a circuit board manufacturing method and a circuit board. Background Technology

[0002] In the process of manufacturing circuit boards, in order to make the circuit boards meet certain functional requirements, in addition to making regular circuits on the circuit boards, it is often necessary to make fine circuits in certain areas of the circuit boards. Some circuit board products also have limitations on the copper thickness of the fine circuits, requiring the fine circuits to be both thin and thick.

[0003] Traditional methods for fabricating fine lines often require multiple pattern electroplating and copper layer thinning processes, followed by etching of the thinned first copper layer to obtain the fine lines. However, the fine lines produced in this way are difficult to meet the requirements of being both fine and thick. Summary of the Invention

[0004] This application provides a method for manufacturing a circuit board and a circuit board to solve the problem that traditional fine line manufacturing methods cannot meet the requirements of being both thin and thick.

[0005] An embodiment of the first aspect of this application provides a method for manufacturing a circuit board, including:

[0006] A substrate is provided, the substrate having a first copper layer, the side of the first copper layer facing away from the substrate having a first region and a second region, the first region including alternating fine line regions and a first region to be etched, the second region including alternating conventional line regions and a second region to be etched, and both the first region and the second region being covered with a first photoresist.

[0007] The substrate is exposed and developed once, so that the first area to be etched and the second area are both covered by the cured first photoresist and the fine line area is exposed.

[0008] The substrate is electroplated once to thicken the first copper layer in the fine line area;

[0009] Remove the first photoresist covering the second region, and retain the first photoresist covering the first area to be etched;

[0010] A second photoresist is applied to the substrate, and the substrate is subjected to a second exposure and a second development, so that the second area to be etched is covered by the cured second photoresist and the conventional circuit area, the first area and the first photoresist are exposed.

[0011] The substrate is subjected to secondary electroplating, which thickens the first copper layer in the fine line area and the first copper layer in the conventional line area.

[0012] Remove the first photoresist and the second photoresist from the substrate;

[0013] Etching removes the first copper layer in the first area to be etched and the first copper layer in the second area to be etched. The first copper layer in the fine line area forms a fine line, and the first copper layer in the conventional line area forms a conventional line.

[0014] In some embodiments, removing the first photoresist covering the second region while retaining the first photoresist covering the first area to be etched includes: first attaching a protective film to the first photoresist in the first area to be etched, and then using a stripping solution to remove the first photoresist covering the second region; removing the protective film before applying the second photoresist to the substrate.

[0015] In some embodiments, the first copper layer further has a plating area adjacent to and spaced apart from the fine line region; during a single electroplating of the substrate, the first copper layer in the fine line region and the first copper layer in the plating area are simultaneously thickened.

[0016] In some embodiments, the first copper layer in the first etchable region and the first copper layer in the second etchable region are simultaneously etched away while the first copper layer in the plating region is being removed.

[0017] In some embodiments, after the substrate is subjected to secondary electroplating and before the first photoresist and the second photoresist on the substrate are removed, a protective layer is provided on the first copper layer in the fine line area and the first copper layer in the conventional line area.

[0018] In some embodiments, the thickness of the first photoresist is greater than the thickness of the second photoresist.

[0019] In some embodiments, a blind via is provided on the substrate, the blind via penetrating the first copper layer, and the side of the first copper layer facing away from the substrate also has a third region, the blind via being located within the third region; when the substrate is electroplated once, the blind via is filled with the first plating layer.

[0020] In some embodiments, the substrate has a through hole, and the side of the substrate opposite to the first copper layer has a second copper layer. The through hole penetrates the first copper layer and the second copper layer. The side of the first copper layer opposite to the substrate also has a fourth region, and the through hole is located in the fourth region. When the substrate is electroplated once, the hole wall of the through hole is covered with a second plating layer.

[0021] An embodiment of the second aspect of this application provides a method for manufacturing a circuit board, including:

[0022] A substrate is provided, the substrate having a first copper layer, the side of the first copper layer facing away from the substrate having a first region and a second region, the first region including alternating fine line regions and a first region to be etched, the second region including alternating conventional line regions and a second region to be etched, and both the first region and the second region being covered with a first photoresist.

[0023] The substrate is exposed and developed once, so that both the first area to be etched and the second area are covered with the cured first photoresist.

[0024] The substrate is electroplated once to thicken the first copper layer in the fine line area;

[0025] Remove the first photoresist covering the second region and the first photoresist covering the first area to be etched;

[0026] A second photoresist is applied to the substrate, and the substrate is subjected to a second exposure and a second development, so that the first area to be etched and the second area to be etched are both covered by the cured second photoresist and the conventional line area and the fine line area are both exposed.

[0027] The substrate is subjected to secondary electroplating, which thickens the first copper layer in the fine line area and the first copper layer in the conventional line area.

[0028] Remove the second photoresist from the substrate;

[0029] Etching removes the first copper layer in the first area to be etched and the first copper layer in the second area to be etched. The first copper layer in the fine line area forms a fine line, and the first copper layer in the conventional line area forms a conventional line.

[0030] An embodiment of the third aspect of this application provides a circuit board manufactured by the circuit board manufacturing method described in the first or second aspect.

[0031] The circuit board manufacturing method provided in this application has the following advantages: by performing electroplating on the substrate once, the first copper layer in the fine line area is thickened. Then, by performing electroplating on the substrate a second time, the first copper layer in the fine line area is thickened, and the first copper layer in the conventional line area is also thickened. Finally, the first copper layer in the first area to be etched and the first copper layer in the second area to be etched are removed by etching. This allows the first copper layer in the fine line area to form a fine line, and the first copper layer in the conventional line area to form a conventional line. Moreover, since the first copper layer in the fine line area has been thickened twice, the fine line formed can also meet the requirement of being both fine and thick.

[0032] The advantages of the circuit board provided in this application compared to the prior art are the same as the advantages of the circuit board manufacturing method provided in this application compared to the prior art, and will not be repeated here. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a flowchart of a circuit board manufacturing method in one embodiment of this application;

[0035] Figure 2 This is a schematic diagram of the substrate structure in one embodiment of this application;

[0036] Figure 3 It is to remove Figure 2 A schematic diagram of the structure of the substrate after the first photoresist covering the second region on the substrate is shown, and the first photoresist covering the first area to be etched is retained.

[0037] Figure 4 Yes Figure 3 A schematic diagram of the substrate after secondary electroplating is shown.

[0038] Figure 5 Is Figure 4 A schematic diagram of the substrate structure after protective layers are applied to the first copper layer in the fine line area and the first copper layer in the conventional line area.

[0039] Figure 6 It is to remove Figure 5 The diagram shows the structure of the substrate after etching away the first copper layer in the first area to be etched and the first copper layer in the first area to be etched.

[0040] Figure 7 This is a top view of the substrate in one embodiment of this application.

[0041] The markings in the diagram mean:

[0042] 10. Substrate; 11. First copper layer; 11a. First region; 11b. Plating area; 11c. Third region; 11d. Fourth region; 111. Fine line region; 111a. Fine line; 112. First area to be etched; 12. Dielectric layer; 13. Second copper layer; 14. First photoresist; 15. Protective layer; 16. Blind via; 17. First plating layer; 18. Through hole; 19. Second plating layer. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0046] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0047] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.

[0048] Please refer to Figure 1 , Figure 2 and Figure 3 The embodiments of this application provide a method for manufacturing a circuit board, including:

[0049] S101: A substrate 10 is provided. The substrate 10 has a first copper layer 11. The side of the first copper layer 11 facing away from the substrate 10 has a first region 11a and a second region. The first region 11a includes alternating fine line regions 111 and a first region to be etched 112. The second region includes alternating conventional line regions and a second region to be etched. Both the first region 11a and the second region are covered with a first photoresist 14.

[0050] Specifically, the substrate 10 can be a substrate 10 after undergoing blanking, inner layer circuitry, AOI and lamination processes. The number of layers in the substrate 10 can be greater than or equal to 4. The substrate 10 has a dielectric layer 12. A first copper layer 11 is disposed on one side of the dielectric layer 12. A fine line region 111 is used to form fine lines 111a. The area between any two adjacent fine lines 111a is the first area to be etched 112. A conventional line region is used to form conventional lines. The first photoresist 14 is a dry film or a wet film, etc. The first region 11a and the second region can be adjacent or not adjacent. The first region 11a is a local area on the side of the first copper layer 11 facing away from the substrate 10. The second region is most of the area on the side of the first copper layer 11 facing away from the substrate 10.

[0051] It is understandable that a standard line is a line with standard requirements for both width and thickness, while a fine line 111a is a line with a width smaller than that of a standard line and a thickness larger than that of a standard line.

[0052] S102: The substrate 10 is exposed and developed once, so that the first area to be etched 112 and the second area are both covered by the cured first photoresist 14 and the fine line area 111 is exposed.

[0053] Specifically, when the substrate 10 is exposed once, the first photoresist 14 corresponding to the first area to be etched 112 and the second area is exposed to cure all the first photoresist 14 corresponding to the first area to be etched 112 and the second area. Then, a developing solution, usually a weakly alkaline solution, is used to remove the first photoresist 14 corresponding to the fine line area 111, so that the fine line area 111 is not covered by the first photoresist 14.

[0054] S103: Perform electroplating on the substrate 10 to thicken the first copper layer 11 in the fine line region 111.

[0055] Specifically, please refer to the following: Figure 3The substrate 10 is electroplated with copper, which thickens the first copper layer 11 in the fine line region 111 for the first time.

[0056] Optionally, to ensure the uniformity of the copper thickness of the first copper layer 11 in the fine line area 111, electroplating can be performed using a small current for a long time, such as electroplating parameters of 15ASF*90min.

[0057] S104: Remove the first photoresist 14 covering the second region, and retain the first photoresist 14 covering the first area to be etched 112.

[0058] Specifically, a stripping solution can be used to remove the cured photoresist covering the second area on the surface of the substrate 10, while retaining the first photoresist 14 covering the first area to be etched 112, in preparation for subsequent secondary electroplating.

[0059] S105: A second photoresist is applied to the substrate 10, and the substrate 10 is subjected to a second exposure and a second development, so that the second area to be etched is covered by the cured second photoresist and the fine line area 111, the conventional line area and the first photoresist 14 are exposed.

[0060] Specifically, when the substrate 10 is subjected to secondary exposure, the second photoresist on the conventional line area and the first photoresist 14 covering the first photoresist to be etched 112 is exposed to cure all the second photoresist corresponding to the second photoresist to be etched. Then, a developing solution, usually a weakly alkaline solution, is used to remove the second photoresist corresponding to the conventional line area, the second photoresist corresponding to the fine line area 111, and the second photoresist on the first photoresist 14. However, at this time, the first photoresist to be etched 112 is still covered with the cured first photoresist 14.

[0061] It is understandable that since the first copper layer 11 in the fine line region 111 has been thickened during the first electroplating, if the cured second photoresist is re-covered on the first area to be etched 112, due to the precision of the equipment itself and the expansion and contraction of the substrate 10, alignment errors will inevitably occur during the second exposure and development of the substrate 10. This will result in poor precision during the second electroplating of the substrate 10, affecting the final precision of the fine line 111a. Furthermore, since the first copper layer 11 in the fine line region 111 has been thickened during the first electroplating, there is a height difference between the first copper layer 11 and the side of the first copper layer 11 that is away from the substrate 10. If the cured second photoresist is re-covered on the first area to be etched 112, it is also easy for it to not adhere tightly, causing the subsequent etching solution to enter, which will also affect the precision of the fine line 111a.

[0062] S106: Perform secondary electroplating on the substrate 10 to thicken the first copper layer 11 in the fine line region 111 and to thicken the first copper layer 11 in the conventional line region.

[0063] Specifically, please refer to the following: Figure 5 The substrate 10 is electroplated with copper, which thickens the first copper layer 11 in the fine line area 111 for the second time and thickens the first copper layer 11 in the conventional line area for the first time.

[0064] To ensure the uniformity of the copper thickness of the first copper layer 11 in the fine line area 111 and the uniformity of the copper thickness of the first copper layer 11 in the conventional line area, electroplating can be performed using a small current for a long time, such as electroplating parameters of 10ASF*90min.

[0065] S107: Remove the first photoresist 14 and the second photoresist from the substrate 10.

[0066] Specifically, please refer to the following: Figure 6 All the first photoresist 14 and all the second photoresist on the substrate 10 can be removed using a photoresist removal solution.

[0067] S108: Etching removes the first copper layer 11 in the first area to be etched 112 and the first copper layer 11 in the second area to be etched. The first copper layer 11 in the fine line area 111 forms a fine line 111a, and the first copper layer 11 in the conventional line area forms a conventional line.

[0068] Specifically, since the thickness of the first copper layer 11 is generally thin, such as less than 8 micrometers, the substrate 10 can be directly etched (flash etched). After etching, the first copper layer 11 in the first area to be etched 112 and the first copper layer 11 in the second area to be etched are both removed. The first copper layer 11 in the remaining fine line area 111 forms fine line 111a, and the first copper layer 11 in the remaining conventional line area forms conventional line.

[0069] It is understandable that since the first area to be etched 112 has not undergone multiple electroplating thickening and copper reduction, it maintains good uniformity. Therefore, the etching time and etching amount are relatively easy to control, thus avoiding the abnormal problem of uneven etching caused by the thickness difference of the first copper layer 11. Furthermore, the thickness of the first copper layer in the first area to be etched 112 will not change significantly, and the uniformity is good.

[0070] The circuit board manufacturing method provided in this application involves first electroplating the substrate 10 to thicken the first copper layer 11 in the fine line region 111, then performing a second electroplating on the substrate 10 to thicken the first copper layer 11 in the fine line region 111 and the first copper layer 11 in the conventional line region, and finally etching to remove the first copper layer 11 in the first etchable region 112 and the first copper layer 11 in the second etchable region. This allows the first copper layer 11 in the fine line region 111 to form a fine line 111a, and the first copper layer 11 in the conventional line region to form a conventional line. Since the first copper layer 11 in the fine line region 111 is thickened twice, the resulting fine line 111a can also meet the requirement of being both fine and thick.

[0071] Optionally, after etching away the first copper layer 11 in the first area to be etched 112 and the first copper layer 11 in the second area to be etched, the protective layer 15 is removed, and the substrate 10 is then subjected to processes such as solder resist, nickel-palladium-gold plating, molding, testing, and FQC.

[0072] In another embodiment of this application, when removing the first photoresist 14 covering the second region, the first photoresist 14 covering the first etchable region 112 is also removed. Then, a second photoresist is applied to the substrate 10, and the substrate 10 undergoes a second exposure and a second development, so that both the first etchable region and the etchable region are covered by the cured second photoresist, exposing both the conventional line region and the fine line region. After a second electroplating of the substrate 10, only the second photoresist on the substrate 10 is removed. In this way, the first copper layer 11 in the fine line region 111 can form a fine line 111a, and the first copper layer 11 in the conventional line region can form a conventional line. Furthermore, because the first copper layer 11 in the fine line region 111 is thickened twice, the resulting fine line 111a can also meet the requirement of being both fine and thick.

[0073] Please refer to Figure 2 and Figure 3 In some embodiments, removing the first photoresist 14 covering the second region and retaining the first photoresist 14 covering the first area to be etched 112 includes: first attaching a protective film to the first photoresist 14 of the first area to be etched 112, and then using a film removal solution to remove the first photoresist 14 covering the second region; removing the protective film before setting the second photoresist on the substrate 10.

[0074] By adopting the above scheme, a protective film can be used to protect the first photoresist 14 of the first area to be etched 112 from being removed by the stripping solution.

[0075] It is understandable that the protective film can also directly cover the first region 11a, that is, directly and simultaneously cover the fine line region 111 and the first region to be etched 112. In this way, the application of the protective film can be facilitated.

[0076] Optionally, the protective film can be an acid and alkali resistant and removable film, such as PI (Polyimide) film, blue glue film, etc.

[0077] Optionally, after pretreatment of the substrate 10, i.e., after cleaning and roughening the area on the substrate 10 where the second photoresist needs to be applied, the protective film is removed. In this way, the pretreatment process can avoid damaging the first photoresist 14 in the first area to be etched 112.

[0078] Please refer to Figure 5 and Figure 6 In some embodiments, after the substrate 10 is electroplated a second time, and before the first photoresist 14 and the second photoresist on the substrate 10 are removed, a protective layer 15 is provided on the first copper layer 11 in the fine line region 111 and the first copper layer 11 in the conventional line region.

[0079] By adopting the above solution, when the thickness of the first copper layer 11 is large, a protective layer 15 can be used to protect the first copper layer 11 in the fine line area 111 and the first copper layer 11 in the conventional line area from being eroded by the etching solution in the future. The protective layer 15 can be plated tin, etc.

[0080] Please refer to Figure 3 , Figure 6 and Figure 7 In some embodiments, the first copper layer 11 further has a plating area 11b that is adjacent to and spaced apart from the fine line area 111; during a single electroplating of the substrate 10, the first copper layer 11 in the fine line area 111 and the first copper layer 11 in the plating area 11b are simultaneously thickened.

[0081] By adopting the above scheme, the current in the fine line region 111 can be dispersed during the first electroplating of the substrate 10, so that the thickness of the first copper layer 11 in the fine line region 111 is increased more uniformly, and the thickness of the first copper layer 11 is not increased too much, which would make it difficult to remove the first photoresist 14 in the future.

[0082] It can be understood that the plating area 11b is a substrate area on the substrate 10 that does not need to be fabricated with circuits. Its plating area should be comparable to the area of ​​the fine line area 111. Its shape can be flexibly set according to the size of the substrate area. If the substrate area is large, the plating area can also be designed with the same shape as the fine line area 111. If the substrate area is small, it can also be designed as a copper block, a grid or other form. There are no restrictions. The number of plating areas 11b can be one or more.

[0083] It is understandable that after one exposure and one development of the substrate 10, the first photoresist 14 on the plating area 11b should be removed.

[0084] Optionally, while etching away the first copper layer 11 in the first etchable area 112 and the first copper layer 11 in the second etchable area, the first copper layer 11 in the plating area 11b is also etched away simultaneously.

[0085] It is understood that the first copper layer 11 in the plating area 11b is covered with a cured second photoresist to prevent tin from being plated on the first copper layer 11 in the subsequent plating area 11b, which would prevent it from being etched away.

[0086] In some embodiments, the thickness of the first photoresist 14 is greater than the thickness of the second photoresist. This avoids the situation where, after the first copper layer 11 in the fine line region 111 has been thickened twice, the difference between the copper thickness of the first copper layer 11 in the fine line region 111 and the thickness of the first photoresist 14 becomes too large, causing the first photoresist 14 to be trapped in the middle of the first copper layer 11 in the fine line region 111 and unable to be completely removed, resulting in incomplete subsequent etching.

[0087] Please refer to Figure 2 , Figure 3 and Figure 4 In some embodiments, a blind hole 16 is provided on the substrate 10, the blind hole 16 penetrates the first copper layer 11, and the side of the first copper layer 11 facing away from the substrate 10 also has a third region 11c, the blind hole 16 is located in the third region 11c; when the substrate 10 is electroplated once, the blind hole 16 is filled with the first plating layer 17, that is, the blind hole 16 is filled with the first plating layer 17.

[0088] By adopting the above scheme, the hole metallization process of blind via 16 can be completed at the same time as the conventional line and fine line 111a are fabricated on the substrate 10, so that the hole of blind via 16 is filled with the first plating layer 17, thereby improving production efficiency.

[0089] Optionally, if the first plating layer 17 is to be further thickened, the first plating layer 17 inside the blind via 16 is thickened during the secondary electroplating of the substrate 10. When a protective layer 15 is provided on both the first copper layer 11 in the fine line region 111 and the first copper layer 11 in the conventional line region, a protective layer 15 is also provided on the thickened first plating layer 17.

[0090] Optionally, to ensure the conductivity of the blind via 16, the indentation of the blind via 16 after filling must be ≤15um.

[0091] Optionally, a through hole 18 is provided on the substrate 10, and a second copper layer 13 is provided on the side of the substrate 10 away from the first copper layer 11. The through hole 18 penetrates the first copper layer 11 and the second copper layer 13. The side of the first copper layer 11 away from the substrate 10 also has a fourth region 11d, and the through hole 18 is located in the fourth region 11d. When the substrate 10 is electroplated once, a second plating layer 19 is applied to the hole wall of the through hole 18.

[0092] By adopting the above scheme, the hole metallization process of the through hole 18 can be completed simultaneously while fabricating conventional lines and fine lines 111a on the substrate 10, so that the second plating layer 19 on the hole wall of the through hole 18 reaches the preset thickness, thus improving production efficiency. Moreover, it eliminates the need for multiple copper plating processes, maintaining good uniformity of the copper surfaces of the first copper layer 11 and the second copper layer 13.

[0093] Optionally, if the second plating layer 19 is to be further thickened, the second plating layer 19 is thickened during the second electroplating of the substrate 10. When a protective layer 15 is provided on both the first copper layer 11 in the fine line region 111 and the first copper layer 11 in the conventional line region, a protective layer 15 is simultaneously provided on both the thickened second plating layer 19 and the second copper layer 13.

[0094] It is understood that the second copper layer 13 is disposed on the side of the dielectric layer 12 away from the first copper layer 11, and multiple blind vias 16 and through vias 18 can be disposed at intervals. Blind vias 16 can be disposed on both the first copper layer 11 and the second copper layer 13.

[0095] Alternatively, the blind hole 16 and the through hole 18 can be machined by laser ablation, mechanical milling, or a combination of both.

[0096] Optionally, before electroplating the substrate 10, copper plating and plate electroplating are performed on the substrate 10 to deposit a copper layer of a certain thickness in both the blind holes 16 and the through holes 18. This allows the hole walls of the blind holes 16 and the through holes 18 to form an electrical connection with the surface of the substrate 10 (i.e., the first copper layer 11), facilitating subsequent thickening by electroplating. Therefore, the thickness of the first copper layer 11 increased by this second copper plating and electroplating is relatively small, and the impact on the uniformity of the copper thickness of the first copper layer 11 is also relatively small.

[0097] On the other hand, embodiments of this application provide a circuit board, which is manufactured by the circuit board manufacturing method described above.

[0098] The circuit board provided in this application embodiment first performs electroplating on the substrate 10 during manufacturing, which thickens the first copper layer 11 in the fine line region 111. Then, the substrate 10 performs a second electroplating, which thickens the first copper layer 11 in the fine line region 111 and the first copper layer 11 in the conventional line region. Finally, the first copper layer 11 in the first etchable region 112 and the first copper layer 11 in the second etchable region are etched away. This allows the first copper layer 11 in the fine line region 111 to form a fine line 111a, and the first copper layer 11 in the conventional line region to form a conventional line. Since the first copper layer 11 in the fine line region 111 is thickened twice, the formed fine line 111a can also meet the requirement of being both fine and thick.

[0099] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of manufacturing a wiring board, characterized by, include: A substrate is provided, the substrate having a first copper layer, the side of the first copper layer facing away from the substrate having a first region and a second region, the first region including alternating fine line regions and a first region to be etched, the second region including alternating conventional line regions and a second region to be etched, and both the first region and the second region being covered with a first photoresist. The substrate is exposed and developed once, so that the first area to be etched and the second area are both covered by the cured first photoresist and the fine line area is exposed. The substrate is electroplated once to thicken the first copper layer in the fine line area; Remove the first photoresist covering the second region, and retain the first photoresist covering the first area to be etched; A second photoresist is applied to the substrate, and the substrate is subjected to a second exposure and a second development, so that the second area to be etched is covered by the cured second photoresist and the conventional line area, the fine line area and the first photoresist are exposed. The substrate is subjected to secondary electroplating, which thickens the first copper layer in the fine line area and the first copper layer in the conventional line area. Remove the first photoresist and the second photoresist from the substrate; Etching removes the first copper layer in the first area to be etched and the first copper layer in the second area to be etched. The first copper layer in the fine line area forms a fine line, and the first copper layer in the conventional line area forms a conventional line.

2. The circuit board manufacturing method according to claim 1, characterized in that, Removing the first photoresist covering the second region while retaining the first photoresist covering the first area to be etched includes: firstly attaching a protective film to the first photoresist in the first area to be etched, and then using a stripping solution to remove the first photoresist covering the second region; removing the protective film before applying the second photoresist to the substrate.

3. The circuit board manufacturing method according to claim 1, characterized in that, The first copper layer also has a plating area adjacent to and spaced apart from the fine line area; during a single electroplating of the substrate, the first copper layer in the fine line area and the first copper layer in the plating area are simultaneously thickened.

4. The circuit board manufacturing method according to claim 3, characterized in that, While etching away the first copper layer in the first area to be etched and the first copper layer in the second area to be etched, the first copper layer in the plating area is also etched away simultaneously.

5. The circuit board manufacturing method according to claim 1, characterized in that, After the substrate is electroplated a second time, and before the first photoresist and the second photoresist on the substrate are removed, a protective layer is provided on the first copper layer in the fine line area and the first copper layer in the conventional line area.

6. The circuit board manufacturing method according to claim 1, characterized in that, The thickness of the first photoresist is greater than the thickness of the second photoresist.

7. The method for manufacturing a circuit board according to any one of claims 1 to 6, characterized in that, The substrate has a blind hole that penetrates the first copper layer. The side of the first copper layer facing away from the substrate also has a third region, and the blind hole is located in the third region. When the substrate is electroplated once, the blind hole is filled with the first plating layer.

8. The method for manufacturing a circuit board according to any one of claims 1 to 6, characterized in that, The substrate has a through hole, and the side of the substrate opposite to the first copper layer has a second copper layer. The through hole penetrates the first copper layer and the second copper layer. The side of the first copper layer opposite to the substrate also has a fourth region, and the through hole is located in the fourth region. When the substrate is electroplated once, the hole wall of the through hole is covered with a second plating layer.

9. A method for manufacturing a circuit board, characterized in that, include: A substrate is provided, the substrate having a first copper layer, the side of the first copper layer facing away from the substrate having a first region and a second region, the first region including alternating fine line regions and a first region to be etched, the second region including alternating conventional line regions and a second region to be etched, and both the first region and the second region being covered with a first photoresist. The substrate is exposed and developed once, so that both the first area to be etched and the second area are covered with the cured first photoresist. The substrate is electroplated once to thicken the first copper layer in the fine line area; Remove the first photoresist covering the second region and the first photoresist covering the first area to be etched; A second photoresist is applied to the substrate, and the substrate is subjected to a second exposure and a second development, so that the first area to be etched and the second area to be etched are both covered by the cured second photoresist and the conventional line area and the fine line area are both exposed. The substrate is subjected to secondary electroplating, which thickens the first copper layer in the fine line area and the first copper layer in the conventional line area. Remove the second photoresist from the substrate; Etching removes the first copper layer in the first area to be etched and the first copper layer in the second area to be etched. The first copper layer in the fine line area forms a fine line, and the first copper layer in the conventional line area forms a conventional line.

10. A circuit board, characterized in that, The circuit board is manufactured by the circuit board manufacturing method as described in any one of claims 1 to 9.

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