Asymmetric multi-core pipelined parallel processing method based on clock interrupt synchronization

Abstract

The application relates to the technical field of embedded multi-core computer systems, and provides a non-symmetrical multi-core flow parallel processing method based on clock interrupt synchronization, which comprises the following steps: dividing a task to be executed into n sub-tasks according to data correlation and execution sequence, and binding one processor core to each sub-task; using a general counter on the processor to periodically generate an interrupt at a specified time interval; and responding to the interrupt by an interrupt service program of each core, simulating a synchronous clock rising edge through the interrupt and setting an identification bit, so that relatively independent processor cores can simultaneously start executing three stages of the respective sub-tasks at the clock rising edge. According to the method, multi-core resources can be fully utilized, the execution of the whole task can still obtain parallel acceleration when there is data correlation among the sub-tasks, the scalability of multi-core application is enhanced, multi-core scheduling management is simplified, the system design complexity is reduced, and the multi-core management time cost is lowered.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of embedded multi-core computer system, and particularly relates to an asymmetric multi-core pipelined parallel processing method based on clock interrupt synchronization. BACKGROUND

[0002] Generally, multi-core processors work in SMP or AMP mode. In SMP mode, all processor cores are managed by one operating system or one application program, and have a unified memory space. In AMP mode, each processor core has its own independent memory space, and runs an operating system or an application program independently, and only a small amount of information is exchanged between the processor cores.

[0003] In SMP mode, the multi-core processor completes the allocation of multiple sub-tasks on the processor cores by scheduling multiple threads. The task scheduling module in the operating system or program is responsible for organizing and managing the sub-task (i.e. thread) queue, and constantly monitors the running state of each core in the processor. If a processor core meets the condition of allocating a sub-task, such as the processor core being in an idle state, the task scheduling module will allocate the first thread (sub-task) in the queue to the core, and generally will not allocate a new sub-task to the core before the execution of the sub-task is completed. In order to make the best use of multi-core resources in parallel, the sub-tasks are generally designed to have less data correlation and independence between each other when dividing the sub-tasks.

[0004] In AMP mode, the tasks are implemented as programs running on each processor core (whether there is an operating system or not). The application programs running on the processor cores can be the same or different, i.e. the functions of the cores can be the same or different. In order to achieve parallelism as much as possible, the sub-tasks are generally designed to have less data correlation and independence between each other when planning the tasks.

[0005] Taking a four-core processor as an example, in the conventional parallel processing mode, SMP and AMP can be abstracted as the model shown in Figure 1 , i.e. a task is pre-divided into sub-tasks with independence between each other, and then the sub-tasks are dynamically allocated to the processor cores according to the working state of the processor cores, such as whether they can run normally or whether they are in an idle state, such as SMP mode, or the sub-tasks are statically bound to a core, such as AMP mode. Since the sub-tasks are independent of each other, they can be executed in parallel on different processor cores, thereby achieving the purpose of speeding up the processing of the entire task.

[0006] Suppose t schFor the inter-core task scheduling time overhead, the execution time of {subtask 0, subtask 1, subtask 2, subtask 3} is {t0, t1, t2, t3} respectively, and the task execution time t is: t = t sch + max{t0, t1, t2, t3}.

[0007] However, in practical applications, not all tasks can be divided into independent subtasks. When the processing input of a subtask depends on the processing result of another subtask, the two subtasks are serial. If there is data correlation between subtasks, the worst case of 4 subtasks is completely serial, and the task execution time is: The task serial time is

[0008] In the above case, parallel acceleration does not work, on the contrary, due to the overhead of inter-core task scheduling and data transfer, the execution time of 4 cores may be longer than that of serial on a single core. SUMMARY

[0009] To solve the problems in the background art, the application provides a non-symmetric multi-core pipeline parallel processing method based on clock interrupt synchronization, which includes the following steps: dividing the tasks to be executed according to data correlation and execution order into n subtasks, each subtask is bound to a processor core, that is, a subtask can only be executed on a fixed processor core; each subtask is divided into three stages of data input, processing and result output, wherein the data input is to read the result output of the previous subtask saved in the specific position of the shared memory, and the result output of itself is written to the specific position of the shared memory to save as the data input of the subsequent subtask; using a general counter on the processor to generate an interrupt at a specified time interval and periodically, the interrupt service program of each core responds to the interrupt, and the interrupt and the setting of the identification bit are used to simulate the rising edge of the synchronous clock, so that the relatively independent processor cores can start executing the three stages of their subtasks at the same time. The rising edge of the clock; the three stages of the subtasks of each core must be completed before the next "synchronous clock rising edge arrives" and the flag bit is flipped; the result output of the processor core where the last subtask is located is the output of the entire task processing result, which is written to the shared memory for subsequent processing or directly output from the peripheral interface controlled by the core.

[0010] In a preferred scheme, the following steps are taken:

[0011] S1: process the task in a pipeline manner; a plurality of processor cores are coded as core 0, core 1, core 2, core i, …, core n-1; wherein n is the maximum number of cores in the processor;

[0012] S2: divide the task to be processed into subtask 0, subtask 1, subtask 2, subtask i, …, subtask n-1, wherein n is the maximum number of subtasks, and subtask i corresponds to running on core i;

[0013] S3: set the running time of each subtask as t0, t1, t2, t i , …, t n-1 ; take t' as the longest execution time, i.e. t' = Δt + max{t0, t1, t2, …, t n-1}, wherein Δt is a reserved waiting time; set t' as the execution time of each stage;

[0014] S4: set the maximum time value of the general counter as t', after starting the counter to count, the counter does the minus 1 operation under the driving of the internal system clock frequency of the processor, and the value of the counter becomes 0 every interval t', i.e. triggering an interrupt once;

[0015] S5: set a flag c i for each processor core, and set c i as 0 in initialization; set c i as 1 by the interrupt service function when the interrupt is generated, representing the rising edge of the synchronous clock; and set c i back to 0 by the subtask after the result output of the subtask is completed.

[0016] Further, the specific steps of processing the task in the pipeline mode are as follows:

[0017] Q1: after the system is started, core 0 completes the initialization of the general counter: setting the time threshold t'; hanging the counter with interrupt A, and setting the counter to generate interrupt A after counting overflow; setting the time threshold t' to be automatically loaded again after counting overflow;

[0018] Q2: each processor core completes the registration of the interrupt service function and the clearing of the interrupt mask; and initializes the flag c i of each core as 0;

[0019] Q3: the counter loads the time threshold t';

[0020] Q4: the counter counts;

[0021] After interval t', the general counter generates interrupt A, and go to step b; otherwise, execute step Q5;

[0022] The interrupt service function of each core responds to interrupt A, sets the flag c i of each core as 1, and executes step Q5;

[0023] Q5: each core loops to query the flag c ithe value of the flag bit c i is 0, step Q4 is executed; if the flag bit c i is 1, step Q6 is executed;

[0024] Q6: each core sequentially executes the three stages of data input, processing and result output according to the division of the respective subtask i, and completes the subtask i process;

[0025] Q7: each core sets the respective flag bit c i to 0, and returns to step Q3.

[0026] The present application has the following beneficial effects:

[0027] In the present application, when the processor has n cores, the tasks are processed according to the pipeline mode of the present application. In the first (n-1) t', there is no task processing result output; in the nth t', i.e. after the pipeline is full, the processing result of the first task is output. After that, every time interval t', a task processing result is output, i.e. after the pipeline is full, the execution time of the whole task is t=t'=Δt+max{t0,t1,t2,......,t n-1} from the outside, instead of After the pipeline is full, every time interval t', a task is completed, achieving a good parallel effect.

[0028] According to the method of the present application, the multi-core resources can be fully utilized, so that when there is data correlation between the subtasks, the execution of the whole task can still obtain parallel acceleration, enhancing the scalability of multi-core application. Meanwhile, the synchronization clock of the pipeline is simulated by the interruption of the general counter and the flag bit, simplifying the multi-core scheduling management, reducing the system design complexity and lowering the multi-core management time cost. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a conventional parallel processing model;

[0030] Figure 2 is a task parallel processing process diagram under the condition of data irrelevance;

[0031] Figure 3 is a task parallel processing process diagram under the condition of data relevance;

[0032] Figure 4 is the three stages of a subtask

[0033] Figure 5 is a general counter function block diagram

[0034] Figure 6 is a timing diagram for simulating the synchronization clock by interruption and flag bit

[0035] Figure 7 A schematic diagram of a pipeline from empty to full. DETAILED DESCRIPTION

[0036] In order for those skilled in the art to understand the present application, the specific embodiments of the present application are described below in conjunction with the embodiments and drawings.

[0037] With reference to Figures 1-7 , the non-symmetrical multi-core pipeline parallel processing method based on clock interrupt synchronization of the present application comprises the following steps: dividing the task to be executed according to data correlation and execution sequence into n sub-tasks, each sub-task being bound to a processor core, i.e. a sub-task can only be executed on a fixed processor core; each sub-task is divided into three stages of data input, processing and result output, wherein the data input is to read the result output of the previous sub-task saved at a specific location of the shared memory, and the result output of itself is written into a specific location of the shared memory for saving, as the data input of the subsequent sub-task; using the general-purpose counter on the processor to periodically generate an interrupt at a specified time interval, the interrupt service program of each core responding to the interrupt, simulating the rising edge of the synchronous clock through the interrupt and setting the identification bit, so that the relatively independent processor cores can start executing the three stages of their respective sub-tasks at the same time at the rising edge of the clock; the three stages of the sub-tasks of each core must be completed before the arrival of the next "synchronous clock rising edge" and the flag bit is flipped; the result output of the processor core where the last sub-task is located is the output of the entire task processing result, which is written into the shared memory for subsequent processing or directly output from the peripheral interface controlled by the core.

[0038] The specific steps are as follows:

[0039] S1: processing the task in a pipeline manner; a plurality of processor cores are coded as core 0, core 1, core 2, core i,..., and core n-1; wherein n is the maximum number of cores in the processor;

[0040] S2: dividing the task to be processed into sub-task 0, sub-task 1, sub-task 2, sub-task i,..., and sub-task n-1, wherein n is the maximum number of sub-tasks, and sub-task i corresponds to running in core i;

[0041] S3: setting the running time of each sub-task as t0, t1, t2, t i ,..., and t n-1 ; taking t' as the longest execution time, i.e. t' = Δt + max{t0, t1, t2,..., t n-1}, wherein Δt is the reserved waiting time; setting t' as the execution time of each stage;

[0042] S4: Set the maximum time value of the general-purpose counter to t'. After the counter starts counting, it decrements by 1 under the drive of the processor's internal system clock frequency. Every time interval t', the value of the counter becomes 0, which triggers an interrupt.

[0043] S5: Each processor core sets a flag bit c i During initialization, c i Set to 0; when an interrupt occurs, the interrupt service function will set c to 0. i Setting it to 1 represents the rising edge of the synchronization clock; after the subtask's result output is complete, the subtask will output c. i Reset to 0.

[0044] The specific steps for processing tasks using a pipeline approach are as follows:

[0045] Q1: After system startup, core 0 completes the initialization of the general-purpose counter: sets the time threshold t'; attaches interrupt A to the counter, sets the counter to generate interrupt A after the count overflows; sets the time threshold t' to be automatically reloaded after the count overflows.

[0046] Q2: Each processor core completes its own interrupt service routine registration and interrupt mask clearing; initializes its own flag bits c. i =0;

[0047] Q3: Counter loading time threshold t';

[0048] Q4: Counter counting;

[0049] After interval t', the general-purpose counter generates interrupt A, proceeding to step b; otherwise, step Q5 is executed.

[0050] Each core's interrupt service routine responds to interrupt A, setting the flag c of each core. i Set to 1 and proceed to step Q5;

[0051] Q5: Each core cycles through the flag bit c i The value of the flag bit c; i If the value is 0, proceed to step Q4; if the flag bit c i If the value is 1, proceed to step Q6;

[0052] Q6: Each core executes the three stages of data input, processing, and result output sequentially according to its respective subtask i, thus completing the process of subtask i.

[0053] Q7: Each core will set its own flag bit c i Set to 0 and return to step Q3.

[0054] Example 1,

[0055] In the embodiment, the processor is set to 4 cores; the general counter uses interrupt 9, and the clock interrupt synchronization-based asymmetric multi-core flow parallel processing method of the application is described through the embodiment.

[0056] (1) After the system is started, core 0 completes initialization of the general counter: first, set the counter control register to all 0, then set the counter load register to all 0, and set the time threshold t' in the counter load value register, such as 0x00F00000;

[0057] (2) Each processor core completes registration of the respective interrupt service function and clears the interrupt mask; and initializes the respective flag c i =0; core 0 writes 0x0000000F into the counter control register;

[0058] (3) The counter automatically loads the time threshold 0x00F00000;

[0059] (4) The counter counts;

[0060] a) After decrementing to 0, the general counter generates interrupt 9, and goes to step b; otherwise, go to step (4);

[0061] b) The interrupt service function of each core responds to interrupt 9, sets the flag c i of each core to 1, and goes to step (5);

[0062] (5) Each core cyclically queries the value of the flag c i ; if the flag c i is 0, go to step (4); if the flag c i has been changed to 1, which is equivalent to detecting a "synchronous clock rising edge", go to step (6);

[0063] (6) Each core sequentially executes the "data input", "processing", and "result output" three stages according to the division of the respective subtasks, and completes the three stages of the subtasks of each core before the next "synchronous clock rising edge" arrives;

[0064] (7) Each core modifies the respective flag c i to 0, and goes to step (3).

[0065] When the processor has 4 cores, the tasks are processed in the above-described pipeline manner, and in the first 3 times t', there is no task processing result output; after the 4th t' is passed, that is, after the pipeline is full, the processing result of the first task is output; after that, every time t' is passed, a task processing result is output, that is, after the pipeline is full, the execution time of the task from the outside is the time value corresponding to 0x00F00000, and is no longer

[0066] The above embodiments of the present application are not only all optional combinations, but also all modifications, equivalent replacements, improvements and the like made within the spirit and principle of the present application. They should be included in the protection scope of the claims of the present application.

Claims

1. A method for non-symmetrical multi-core pipelined parallel processing based on clock interrupt synchronization, characterized in that, It comprises the following steps: The tasks to be executed are divided into n sub-tasks according to data correlation and execution sequence, each sub-task is bound to a processor core, i.e. a sub-task can only be executed on a fixed processor core; Each sub-task is divided into three stages of data input, processing and result output, wherein the data input is to read the result output saved by the previous sub-task at a specific position of the shared memory, and the result output of itself is written to a specific position of the shared memory for saving, as the data input of the subsequent sub-task; The processor uses a general-purpose counter to periodically generate interrupts at specified time intervals t', where t' = Δt + max{t0, t1, t2, ..., t}. n-1 }, where Δt is the reserved waiting time; t0, t1, t2, ..., t n-1 These are the execution times for each subtask; each core's interrupt service routine responds to the interrupt, simulating the rising edge of the synchronous clock by interrupting and setting flag bits, so that each relatively independent processor core can simultaneously begin executing the three stages of its respective subtask at the rising edge of the clock; the three stages of each core's subtask are completed before the next rising edge of the synchronous clock arrives, and the flag bits are toggled. The result output of the processor core where the last sub-task is located is the output of the entire task processing result, which is written to the shared memory for subsequent processing or directly output from the peripheral interface controlled by the core.

2. The clock interrupt synchronization based asymmetric multi-core pipelined parallel processing method according to claim 1, wherein, It comprises the following steps: S1: processing the task in a pipeline manner; a plurality of processor cores are coded as core 0, core 1, core 2, core i, …, core n-1; wherein n is the maximum number of cores in the processor; S2: divide the task to be processed into subtask 0, subtask 1, subtask 2, subtask i, …, subtask n - 1, wherein, wherein the number of subtasks is equal to the number of processor cores, both are n, and subtask i corresponds to running on core i; S3: set the running time of each subtask as t0, t1, t2, t i , …, t n-1 ; take t' as the longest execution time, i.e. t' = Δt + max{t0, t1, t2, …, t n-1}, wherein Δt is a reserved waiting time; set t' as the execution time of each stage; S4: set the maximum time value of the general counter as t', after starting the counter to count, the counter does the minus 1 operation under the driving of the internal system clock frequency of the processor, and the value of the counter becomes 0 every interval t', i.e. triggering an interrupt once; S5: Each processor core sets a flag bit c i During initialization, c i Set to 0; when an interrupt occurs, the interrupt service function will set c to 0. i Setting it to 1 represents the rising edge of the synchronization clock; after the subtask's result output is complete, the subtask will output c. i Reset to 0.

3. The clock interrupt synchronization based asymmetric multi-core pipelined parallel processing method according to claim 2, wherein: The specific steps of processing the task in a pipeline manner are as follows: Q1: after the system starts, core 0 completes the initialization of the general counter: setting the time threshold t'; hanging the counter with interrupt A, setting the counter to generate interrupt A after counting overflow; setting the time threshold t' to be automatically loaded again after counting overflow; Q2: Each processor core completes its own interrupt service function registration, interrupt mask clearing; initializes its own flag bit c i is 0; Q3: the counter loads the time threshold t'; Q4: the counter counts; After an interval t', the general counter generates an interrupt A; the interrupt service function in each core responds to the interrupt A by setting the flag bit c of each core to 1. i After an interval t', the general counter generates an interrupt A; the interrupt service function in each core responds to the interrupt A by setting the flag bit c of each core to 1. Q5: Query each core loop flag bit c i value; if flag bit c i 0, execute step Q4; if flag bit c i 1, go to step Q6; Q6: each core executes the three stages of data input, processing and result output according to the division of its own sub-task i in sequence, and completes the process of sub-task i. Q7: Each core sets its own flag c to 0, and returns to step Q3. i Q7: Each core sets its own flag c to 0, and returns to step Q3.

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