On-chip integrated adjustable LVDS receiver circuit and adjustment method

Abstract

An on-chip LVDS receiver circuit with adjustable terminating resistors and its adjustment method are disclosed. The circuit includes two identical adjustable resistor arrays Rx1 and Rx2, an amplification and comparator unit, and a finite state machine. It includes multiple parallel resistors, at least some of which are connected in series with a MOSFET switch. Each MOSFET switch controls the conduction state of its corresponding resistor. Rx1 is connected between the power supply voltage and a current source I1, which is grounded. The voltage at the connection point between Rx1 and the current source I1 is Vcal. Rx2 is connected between the two ends of the input differential signal of the LVDS receiver. One input of the amplification and comparator unit is connected to the voltage Vcal, and the other input is connected to a reference voltage Vref. The amplification and comparator unit amplifies and compares the voltages Vcal and Vref, outputting the comparison result. The finite state machine outputs control signals based on the comparison result to control the on / off state of each MOSFET switch to adjust the resistance values ​​of Rx1 and Rx2. Integrating the terminating resistors into the LVDS receiver chip and achieving adjustable values ​​through digital control simplifies the implementation.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an LVDS receiver circuit and adjustment method with an on-chip integrated adjustable terminating resistor. Background Technology

[0002] With the continuous advancement of science and technology, the development of integrated circuit devices exhibits the following three trends: continuously increasing functional density; gradually increasing requirements for digitization, standardization, and generalization; and gradually increasing processing speed and bus speed. These three trends are driving electronic components towards higher integration, miniaturization, lighter weight, and higher speed. LVDS circuits, due to their outstanding performance in low power consumption, low electromagnetic interference, noise immunity, and strong integration capabilities, are highly suitable for high-frequency, high-speed transmission environments and have been widely used in aerospace, aviation, display, and image sampling fields.

[0003] A traditional LVDS data transmission system consists of three parts: a transmitter, a receiver, and a terminal matching resistor. The system block diagram is shown below. Figure 1 As shown, the LVDS transmitter converts the CMOS level signal into a differential current signal with a standard current value of 3.5 mA. This current passes through a 100Ω terminating resistor, generating a voltage difference of 350mV across the resistor. Finally, the LVDS receiver converts the 350mV differential voltage signal back into a CMOS logic level. However, due to signal reflection caused by instantaneous impedance changes during transmission line propagation, and the significant impact of environmental changes on resistor values, this fixed and non-adjustable input resistor structure is unsuitable for applications with specific requirements regarding area and impedance accuracy.

[0004] CN101751902A discloses an LVDS receiver circuit with adjustable input resistors, which integrates an ESD protection module and an adjustable matching resistor module. It can manually or automatically adjust the input impedance of the receiver circuit within a certain range to achieve impedance matching and reduce signal reflection. However, due to its relatively simple structure, the adjustable range and accuracy of the resistor are limited. Furthermore, the resistors integrated on the chip are greatly affected by temperature and the chip's operating environment, and the fixed resistors will deviate significantly from the design and expected values. Summary of the Invention

[0005] To address the shortcomings of the prior art, this application provides an LVDS receiver circuit and adjustment method with an on-chip integrated adjustable terminating resistor. The terminating resistor is integrated into the LVDS receiver chip and its size is adjustable through digital control. Moreover, the implementation method is simple.

[0006] To achieve the above objectives, the present invention employs the following techniques:

[0007] An on-chip integrated adjustable termination resistor LVDS receiver circuit is integrated into an LVDS receiver. The LVDS receiver circuit includes an adjustable resistor array Rx1, an adjustable resistor array Rx2, an amplification and comparison unit, and a finite state machine.

[0008] The adjustable resistor arrays Rx1 and Rx2 have the same structure, both including multiple parallel resistors, of which at least some resistors are connected in series with one MOSFET switch; the specific number of switches can be the same as the number of parallel resistors, or less than the number of resistors; each MOSFET switch controls the conduction state of the corresponding connected resistor.

[0009] An adjustable resistor array Rx1 is connected between the power supply voltage and the current source I2. The current source I2 is grounded. The voltage at the connection point between the adjustable resistor array Rx1 and the current source I2 is Vcal.

[0010] An adjustable resistor array Rx2 is connected between the two ends of the input differential signal of the LVDS receiver;

[0011] One input terminal of the amplification and comparison unit is connected to the voltage Vcal, and a reference voltage Vref is introduced into the other input terminal. This unit amplifies and compares the voltages Vcal and Vref, and outputs the comparison result.

[0012] The finite state machine is connected to the output of the amplification and comparison unit, and is also connected to the adjustable resistor arrays Rx1 and Rx2. It is used to output control signals based on the comparison results to control the on / off state of each MOSFET switch in the adjustable resistor arrays Rx1 and Rx2, so as to adjust the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2 until the difference between voltage Vref and voltage Vcal is adjusted to the minimum that can be adjusted, and then the adjustment ends.

[0013] A method for adjusting an LVDS receiver circuit with an on-chip integrated adjustable terminating resistor, comprising the following steps:

[0014] S100, Select the reference voltage Vref, and select the number of resistors and the resistance value of each resistor in the adjustable resistor array Rx1. The adjustable resistor array Rx2 adopts the same configuration as the adjustable resistor array Rx1. The Rctrl[0:n] control signal is set to the initial value.

[0015] S200: When the voltage Vcal is greater than the voltage Vref, output the comparison result 1 to the finite state machine; when the voltage Vcal is less than the voltage Vref, output the comparison result 0 to the finite state machine.

[0016] S300. When the comparison result received by the finite state machine is 1, the finite state machine outputs a new Rctrl[0:n] control signal to control each MOSFET switch to adjust and decrease the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2; when the comparison result received by the finite state machine is 0, the finite state machine outputs a new Rctrl[0:n] control signal to control each MOSFET switch to adjust and increase the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2.

[0017] The process of executing S200~S300 is repeated until the adjustment is "decrease-increase-decrease" or "increase-decrease-increase" three times in a row. Then, the adjustment ends after the resistance value of the adjustable resistor array Rx2 is adjusted with the latest Rctrl[0:n] control signal, or the adjustment ends after the Rctrl[0:n] control signal is updated again to increase or decrease the resistance value of the adjustable resistor array Rx2 once.

[0018] The beneficial effects of this invention are as follows:

[0019] 1. Two adjustable resistor arrays are introduced into the circuit, and the voltage Vcal is compared with the reference voltage Vref for adjustment. The adjustment is carried out using digital control to make the resistance values ​​of the adjustable resistor arrays accurately match different resistance values. When the requirements are met, the other adjustable resistor array connected between the differential signal input terminals is adjusted according to the control signal. By selecting different resistors, the receiving circuit can operate normally under different input currents, achieving impedance matching at high frequencies and reducing signal reflection.

[0020] 2. In this invention, the adjustable resistor array is adjusted by a standard resistor or reference, and the adjustment is automatically made by digital means so that the resistance value can be close to the ideal value under different temperatures and working environments. It has a wide range of applications and can better adapt to applications in harsh environments.

[0021] 3. The on-chip adjustable terminating resistor module in the LVDS receiver circuit of this invention can be referenced by an externally connected ideal resistor or by an internal reference source. It is compatible with the current 100Ω terminating resistor in most environments, and can also be set to other resistance values. Furthermore, an enable switch can be used to disable the digital adjustment process, allowing the terminating resistor value to be determined manually by directly setting the adjustment input. The entire design offers high flexibility and can meet the needs of various applications. Attached Figure Description

[0022] Figure 1 This is a structural diagram of an existing LVDS data transmission system.

[0023] Figure 2 This is an example of an LVDS receiving circuit according to an embodiment of this application.

[0024] Figure 3 This is a schematic diagram of a circuit structure of an adjustable resistor array Rx1 / Rx2 according to an embodiment of this application.

[0025] Figure 4 This is a schematic diagram of another circuit structure of the adjustable resistor array Rx1 / Rx2 according to an embodiment of this application.

[0026] Figure 5 This is a schematic diagram of a finite state machine according to an embodiment of this application.

[0027] Figure 6 This is a schematic diagram of a specific example circuit structure of the adjustable resistor array Rx1 / Rx2 according to an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the implementation methods of the present invention will be described in detail below with reference to the accompanying drawings. However, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments.

[0029] This application provides an LVDS receiver circuit with an on-chip integrated adjustable termination resistor, integrated within an LVDS receiver. For example... Figures 2-3 As shown, the LVDS receiving circuit in this example includes an adjustable resistor array Rx1, an adjustable resistor array Rx2, an amplification and comparison unit, a finite state machine, etc.

[0030] Adjustable resistor arrays Rx1 and Rx2 have the same structure, both including multiple parallel resistors, with at least some of the resistors connected in series with a MOSFET switch. The specific number of switches can be the same as or less than the number of parallel resistors. Each MOSFET switch controls the conduction state of the corresponding connected resistor.

[0031] The adjustable resistor array Rx1 is connected between the power supply voltage and the current source I2, which is grounded. The voltage at the connection point between the adjustable resistor array Rx1 and the current source I2 is Vcal. The adjustable resistor array Rx2 is connected between the two ends of the input differential signal of the LVDS receiver.

[0032] Optional, such as Figure 3 As shown, the adjustable resistor arrays Rx2 and Rx1 each include n parallel resistors and n MOSFETs, meaning that each resistor is equipped with one MOSFET.

[0033] Another alternative, such as Figure 4 As shown, the adjustable resistor arrays Rx2 and Rx1 include n+1 parallel resistors and n MOSFETs, where one resistor Rn+1 is not connected to a MOSFET, and the remaining n resistors are each equipped with a MOSFET.

[0034] As alternative implementations, there can be more specific configurations of the adjustable resistor array Rx2 and the adjustable resistor array Rx1. The number of resistors and MOSFETs used for parallel connection can be adjusted according to the required adjustment.

[0035] One input of the amplification and comparison unit is connected to voltage Vcal, and the other input is connected to a reference voltage Vref. This amplifies and compares voltages Vcal and Vref, outputting the comparison result. A finite state machine is connected to the output of the amplification and comparison unit and to adjustable resistor arrays Rx1 and Rx2. Based on the comparison result, it outputs control signals to control the on / off state of each MOSFET switch in adjustable resistor arrays Rx1 and Rx2, adjusting their resistance values. Each adjustment is followed by a re-comparison, and this process is repeated until the difference between voltage Vref and voltage Vcal is adjusted to its minimum adjustable value (depending on the selected voltage Vref and the number and resistance values ​​of resistors in adjustable resistor array Rx1).

[0036] The resistance value of the adjustable resistor array Rx2 can be adjusted synchronously with that of the adjustable resistor array Rx1, or it can be adjusted once when the final adjustment value is determined.

[0037] Optionally, the reference voltage Vref can be provided externally or through an internally integrated reference source, such as a reference source circuit within the chip. Alternatively, it can be provided by connecting a reference resistor R0, which can be integrated internally or externally. Figure 2 The connection of the reference resistor R0 is shown, which is connected between the power supply voltage and the current source I1, with the current source I1 grounded. Here, the power supply voltage, the reference resistor R0, the current source I1, and ground form a branch. If the reference resistor R0 is introduced, according to Ohm's law, Vref = VDD - I1 × R0, Vcal = VDD - I2 × Rx1. If I1 = I2, to compare the magnitudes of Rx1 and R0, it is only necessary to compare the magnitudes of Vcal and Vref.

[0038] As an optional method, such as Figure 2 As shown, the amplification and comparison unit includes a preamplifier and a comparator.

[0039] One input of the preamplifier is connected to the voltage Vcal, and the other input is connected to a reference voltage Vref. The input of the comparator is connected to the output of the preamplifier, and the output of the comparator is connected to a finite state machine. The preamplifier is used to amplify the difference between the voltages Vcal and Vref, and the comparator is used to compare the amplified difference and output the comparison result to the finite state machine.

[0040] Specifically, when voltage Vcal is greater than voltage Vref, the comparison result is 1; when voltage Vcal is less than voltage Vref, the comparison result is 0. Alternatively, the output value can be set to other values, as long as the two comparison results are distinguished.

[0041] The finite state machine (FSM) is a digitally controlled automatic adjustment module. Its input ports include Res, Comp, and CLK, and its output ports include Down and Rctrl[0:n]. The Comp port of the FSM is connected to the output of the amplification and comparison unit, used to receive the comparison result of 1 or 0. The Rctrl[0:n] ports of the FSM are connected to adjustable resistor arrays Rx1 and Rx2, specifically connected to each MOSFET switch. The Rctrl[0:n] signal is output to control the conduction and cutoff of each MOSFET switch in adjustable resistor arrays Rx1 and Rx2, thereby adjusting the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2. The CLK port of the FSM is connected to the clock signal; one comparison between voltage Vref and voltage Vcal constitutes one clock cycle. The Res port of the FSM is the reset port. When its value is 1, the system returns to the default state, and Rctrl[0:n] is restored to the system default value; when its value is 0, the system maintains the current state. The Done port of the finite state machine is an adjustment status flag. When its value is 0, it indicates that the Rctrl[0:n] signal value is still being adjusted. When its value is 1, it indicates that the adjustment is over and the Rctrl[0:n] signal value is fixed.

[0042] In practical applications, the desired resistor is selected as R0, and then the value of Rx1 is adjusted by the value of the Rctrl[0:n] signal. The value of the Rctrl[0:n] signal can be initialized directly within the logic, or it can be set as a variable, with the user able to set the initial value of the Rctrl[0:n] signal through external input. Designers can choose either method to create their designs according to their needs.

[0043] This application also provides an adjustment method for the LVDS receiver circuit with an on-chip integrated adjustable termination resistor as described above, including the following steps:

[0044] S100, Select the reference voltage Vref (for the form of introducing a reference resistor R0, the resistance value of the reference resistor R0 can be selected), and select the number of resistors and the resistance value of each resistor in the adjustable resistor array Rx1. The adjustable resistor array Rx2 adopts the same configuration as the adjustable resistor array Rx1. The Rctrl[0:n] control signal sets the initial value.

[0045] S200: When the voltage Vcal is greater than the voltage Vref, output comparison result 1 to the finite state machine; when the voltage Vcal is less than the voltage Vref, output comparison result 0 to the finite state machine.

[0046] S300. When the comparison result received by the finite state machine is 1, the finite state machine outputs a new Rctrl[0:n] control signal to control each MOSFET switch to adjust and decrease the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2; when the comparison result received by the finite state machine is 0, the finite state machine outputs a new Rctrl[0:n] control signal to control each MOSFET switch to adjust and increase the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2.

[0047] The process repeats steps S200 to S300 until three consecutive adjustments satisfy the condition of "decrease-increase-decrease" or "increase-decrease-increase". The adjustment then ends, with the adjustable resistor array Rx2 determining the value after the final adjustment. Since the resistance values ​​of the adjustable resistor array Rx1 obtained in the last adjustment and the previous adjustment are very similar when this condition is met, the previous adjustment's value can also be used as the basis for determining the final stable operating state of the circuit. Therefore, the adjustment ends after further increasing or decreasing the adjustable resistor arrays Rx1 and Rx2.

[0048] Optionally, the adjustment in S300 above can also be performed first only on the adjustable resistor array Rx1, and then the adjustable resistor array Rx2 can be adjusted with the current Rctrl[0:n] control signal when the conditions are met.

[0049] That is, the specific marker to end the adjustment can be determined by the relevant flag, and the cycle is performed under clock control according to the pattern described in this example, with the number of cycles recorded as n, State[0] = Comp n-2 State[1] = Comp n-1 State[2] = Comp n When State[0:2] = 010 or 101, it means that the difference between voltage Vref and voltage Vcal has been minimized. At this time, the value of the control signal will no longer change. Done=1, the entire adjustment process ends, the circuit enters a stable state, and the digital adjustment module is automatically turned off.

[0050] In this example, the Rctrl[0:n] control signal is an n-bit binary number, where n is the same as the number of MOSFETs. Each bit controls one MOSFET. When the current bit is 0, the corresponding MOSFET is off, and when the current bit is 1, the corresponding MOSFET is on.

[0051] The n MOSFETs are switch n, switch n-1, ..., switch 1, which are respectively connected to resistors Rn, Rn-1, ..., R1 in the adjustable resistor array Rx1, with the resistance values ​​of Rn, Rn-1, ..., R1 decreasing from large to small. Meanwhile, in the binary representation of the Rctrl[0:n] control signal, starting from the left, the first bit corresponds to control switch 1, ..., the (n-1)th bit corresponds to control switch n-1, and the nth bit corresponds to control switch n.

[0052] Therefore, the finite state machine adds or subtracts a predetermined number from the previous Rctrl[0:n] control signal based on the comparison result being 1 or 0, in order to generate a new Rctrl[0:n] control signal.

[0053] Generally, the initial value of the Rctrl[0:n] control signal is not set at either of the two "endpoints," meaning it is not at the maximum or minimum value among all current Rctrl[0:n] control signals. Also, during adjustment, it is rare to reach the maximum or minimum value to end the adjustment. If the finite state machine returns a comparison result of 1, and the binary number of the previous Rctrl[0:n] control signal is the maximum value among all Rctrl[0:n] control signals, it cannot continue to increase the predetermined number of Rctrl[0:n] control signals, thus ending the adjustment. The number and value of each resistor in the adjustable resistor array Rx1 need to be reset. If the finite state machine returns a comparison result of 0, and the binary number of the previous Rctrl[0:n] control signal is the minimum value among all Rctrl[0:n] control signals, it cannot continue to decrease the predetermined number of Rctrl[0:n] control signals, thus ending the adjustment. The number and value of each resistor in the adjustable resistor array Rx1 need to be reset.

[0054] In implementation, the resistance values ​​of resistors Rn, Rn-1, ..., R1 in the adjustable resistor array Rx1 change from large to small. Furthermore, in the binary representation of the Rctrl[0:n] control signals, starting from the left, the first bit corresponds to control switch 1, ..., the (n-1)th bit corresponds to control switch n-1, and the nth bit corresponds to control switch n. All n-bit binary numbers of the Rctrl[0:n] control signals can be arranged in ascending order. At this time:

[0055] (1) If the resistance value of the adjustable resistor array Rx1 corresponding to each Rctrl[0:n] control signal shows a monotonically linear decreasing trend, then the predetermined number of increase or decrease for each adjustment is 1. This is a relatively ideal and convenient situation to implement.

[0056] (2) If the resistance value of the adjustable resistor array Rx1 shows a monotonically linear decreasing trend, and there are several changes in the middle where it first increases and then continues to decrease, such is the case in some implementations. For each increment, the binary number corresponding to the resistance value at the peak of the increment is taken as the first jump point, and the binary number corresponding to the resistance value that is greater than the current resistance value and has the smallest difference before the current resistance value is taken as the second jump point. The number of intervals between the first jump point and the second jump point is counted. If the binary number of the current Rctrl[0:n] control signal is not the first jump point or the second jump point, the predetermined number of increase or decrease for each adjustment is 1. If the binary number of the current Rctrl[0:n] control signal is the first jump point, the predetermined number of increase or decrease for each adjustment is 1 or the predetermined number of decrease is 1 + the number of intervals corresponding to the first jump point. If the binary number of the current Rctrl[0:n] control signal is the second jump point, the predetermined number of increase or decrease for each adjustment is 1 + the number of intervals corresponding to the second jump point or the predetermined number of decrease is 1. If the binary number of the current Rctrl[0:n] control signal is between the first jump point and the second jump point, the predetermined number of increase or decrease is the number of intervals, that is, jump out of the region first.

[0057] by Figure 6 An example of an adjustable resistor array Rx1 / adjustable resistor array Rx2 is shown to illustrate this embodiment in detail. Figure 6 As shown, the adjustable resistor array Rx1 / adjustable resistor array Rx2 has a total of 6 resistors, where n=5. Resistor R6 is not connected to a MOSFET switch. Resistors R5, R4, R3, R2, and R1 are each connected to a MOSFET switch. The control signals Rctrl[0:4] are Rctrl[4], Rctrl[3], Rctrl[2], Rctrl[1], and Rctrl[0], which means they are controlled by a 5-bit binary control signal.

[0058] In this example, resistor R1 is 180Ω, resistor R2 is 250Ω, resistor R3 is 500Ω, resistor R4 is 1kΩ, resistor R5 is 2kΩ, and resistor R6 is 70Ω. If the control signal Rctrl[0:4] is 10010, that is, when the values ​​of Rctrl[0], Rctrl[1], Rctrl[2], Rctrl[3], and Rctrl[4] are 1, 0, 0, 1, and 0 respectively, then resistors R1 and R4 are turned on, and resistors R2, R3, and R5 are turned off. The resistor network of the adjustable resistor array Rx1 / adjustable resistor array Rx2 consists of three resistors R1, R4, and R6 connected in parallel, and their total resistance is:

[0059]

[0060] Specifically, in this example, the relationship between the total resistance of the adjustable resistor array Rx1 and the Rctrl[0:4] signal is shown in the table below:

[0061]

[0062] As can be seen from the above encoding, the total resistance of Rx1 can be varied from 36.57Ω to 70Ω by controlling the value of Rctrl[0:4]. Rctrl[0:4] can be used as the resistance value of the external port to manually control the resistor. However, in this case, due to changes in the chip's operating environment, the actual resistance value will be inconsistent with the set value.

[0063] Therefore, the solution in this example can be used for adjustment, employing the circuit described above and adjusting it through a finite state machine. The state flow is as follows: Figure 4 As shown:

[0064] When Res=1, the digital adjustment module enters the initial state. In this state, the state machine assigns an initial value to Rctrl[0:4] and Done = 0. The circuit in this example converts the comparison of resistances into a comparison between voltages Vcal and Vref. When Vcal < Vref, it means Rx1 < R0, Comp = 0, so Rctrl[0:4] - 1 to increase the resistance value of Rx1. When Vcal > Vref, it means Rx1 > R0, Comp = 1, so Rctrl[0:4] + 1 to decrease the resistance value of Rx1.

[0065] The loop continues according to the above pattern under clock control, with the number of loops denoted as n. State[0] = Comp n-2 State[1] = Comp n-1 State[2] = Comp nWhen State[0:2] = 010 or 101, it means that the resistance value Rx1 closest to R0 has been found. At this time, the value of Rctrl[0:4] will no longer change, Done = 1, the whole adjustment process ends, and the circuit enters a stable state.

[0066] Among them, the resistance of Rctrl[0:4] changes non-monotonic linearly between 01011-10000-10011, which corresponds to the situation described above where the resistance first increases and then continues to decrease on the basis of monotonically decreasing. Here, 10000 is the first jump point and 01011 is the second jump point, with an interval of 4. If Rctrl[0:4] is at 01011, to increase it, simply increase it by 1+4=5, then jump to 10000; to decrease it, decrease it by 1. If Rctrl[0:4] is at 10000, to increase it, simply increase it by 1; to decrease it, simply decrease it by 1+4=5, then jump to 01011. If Rctrl[0:4] is at 01111, then regardless of whether it increases or decreases, it will proceed by 4. For example, increasing it by 4 will jump to 10011, and decreasing it by 4 will jump to 01011. If Rctrl[0:4] is at 01110, then regardless of whether it increases or decreases, it will proceed by 4. For example, increasing it by 4 will jump to 10010, and decreasing it by 4 will jump to 01010.

[0067] Set the reference resistor R0 to 50Ω. Taking Rctrl[0:4] with an initial value of 15 (binary 01111) as an example, the initial resistance of Rx1 is 45.9Ω according to the table above. At this time:

[0068] First comparison period: Rx1 = 45.9 <R0,Comp=0,Rctrl[0:4]-1=14(01110);

[0069] Second comparison period: Rx1 = 46.98 <R0,Comp=0,Rctrl[0:4]-1=13(01101),

[0070] Third comparison period: Rx1 = 48.11 <R0,Comp=0,Rctrl[0:4]-1=12(01100);

[0071] Fourth comparison period: Rx1 = 49.30 <R0,comp=0,Rctrl[0:4]-1=11(01011);

[0072] Fifth comparison period: Rx1=50.54>R0, comp=1, Rctrl[0:4]+1=12(01100);

[0073] Sixth comparison period: Rx1 = 49.30 <R0,comp=0,Rctrl[0:4]-1=11(01011)。

[0074] As can be seen, Comp n-2 =0, Comp n-1 =1, Comp n =0, State[0:2] = 010, done=1, Rctrl[0:4]=11(01011), the calibration process is over, and the calibration module is closed.

[0075] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. An on-chip integrated adjustable terminating resistor LVDS receiver circuit, integrated within an LVDS receiver, characterized in that, The LVDS receiver circuit includes an adjustable resistor array Rx1, an adjustable resistor array Rx2, an amplification and comparison unit, and a finite state machine; The adjustable resistor arrays Rx1 and Rx2 have the same structure, both including multiple parallel resistors, wherein at least some of the resistors are connected in series with a MOSFET switch, and each MOSFET switch is used to control the conduction state of the corresponding connected resistor. An adjustable resistor array Rx1 is connected between the power supply voltage and the current source I2. The current source I2 is grounded. The voltage at the connection point between the adjustable resistor array Rx1 and the current source I2 is Vcal. An adjustable resistor array Rx2 is connected between the two ends of the input differential signal of the LVDS receiver; One input of the amplification and comparison unit is connected to the voltage Vcal, and a reference voltage Vref is introduced into the other input. This amplifies the difference between the voltage Vcal and the voltage Vref for comparison and outputs the comparison result. The finite state machine is connected to the output of the amplification and comparison unit, and is also connected to the adjustable resistor arrays Rx1 and Rx2. It is used to output control signals based on the comparison results to control the conduction / cutoff of each MOSFET switch in the adjustable resistor arrays Rx1 and Rx2, so as to adjust the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2.

2. The LVDS receiver circuit with on-chip integrated adjustable termination resistor according to claim 1, characterized in that, The amplification and comparison unit includes a preamplifier and a comparator. One input of the preamplifier is connected to the voltage Vcal, and the other input is connected to a reference voltage Vref. The input of the comparator is connected to the output of the preamplifier, and the output of the comparator is connected to a finite state machine. The preamplifier is used to amplify the difference between the voltage Vcal and the voltage Vref, and the comparator is used to compare the amplified difference and output the comparison result to the finite state machine.

3. The LVDS receiver circuit with on-chip integrated adjustable terminating resistor according to claim 1, characterized in that: The comp port of the finite state machine is connected to the output of the amplification and comparison unit to receive the comparison result; The Rctrl[0:n] port of the finite state machine is connected to the adjustable resistor arrays Rx1 and Rx2. It is used to control the conduction and cutoff of each MOSFET switch of the adjustable resistor arrays Rx1 and Rx2 by outputting the Rctrl[0:n] signal, so as to adjust the resistance value of the adjustable resistor arrays Rx1 and Rx2. The CLK port of the finite state machine is connected to the clock signal, and one comparison between voltage Vref and voltage Vcal is one clock cycle. The Rst port of the finite state machine is the reset port. When its value is 1, the system returns to the default state. Rctrl[0:n] is restored to the system default value. When its value is 0, the system maintains the current state. The Done port of the finite state machine is an adjustment status flag. When its value is 0, it indicates that the Rctrl[0:n] signal value is still being adjusted. When its value is 1, it indicates that the adjustment is over and the Rctrl[0:n] signal value is fixed.

4. A method for adjusting an LVDS receiver circuit with an on-chip integrated adjustable terminating resistor as described in any one of claims 1 to 3, characterized in that, Including the following steps: S100, Select the reference voltage Vref, and select the number of resistors and the resistance value of each resistor in the adjustable resistor array Rx1. The adjustable resistor array Rx2 adopts the same configuration as the adjustable resistor array Rx1. The Rctrl[0:n] control signal is set to the initial value. S200: When the voltage Vcal is greater than the voltage Vref, output the comparison result 1 to the finite state machine; when the voltage Vcal is less than the voltage Vref, output the comparison result 0 to the finite state machine. S300. When the comparison result received by the finite state machine is 1, the finite state machine outputs a new Rctrl[0:n] control signal to control each MOSFET switch to adjust and decrease the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2; when the comparison result received by the finite state machine is 0, the finite state machine outputs a new Rctrl[0:n] control signal to control each MOSFET switch to adjust and increase the resistance values ​​of the adjustable resistor arrays Rx1 and Rx2. The process of executing S200~S300 is repeated until the adjustment is "decrease-increase-decrease" or "increase-decrease-increase" three times in a row. Then, the adjustment ends after the latest Rctrl[0:n] control signal adjusts the resistance value of the adjustable resistor array Rx2, or the adjustment ends after the Rctrl[0:n] control signal is updated again to increase or decrease the resistance value of the adjustable resistor array Rx2 once.

5. The adjustment method of the LVDS receiver circuit with on-chip integrated adjustable termination resistor according to claim 4, characterized in that, The Rctrl[0:n] control signal is an n-bit binary number, where n is the same as the number of MOSFETs. Each bit controls one MOSFET. When the current bit is 0, the corresponding MOSFET is off, and when it is 1, the corresponding MOSFET is on.

6. The adjustment method of the LVDS receiver circuit with on-chip integrated adjustable termination resistor according to claim 5, characterized in that: The n MOSFETs are switch n, switch n-1, ..., switch 1, which are respectively connected to resistors Rn, Rn-1, ..., R1 in the adjustable resistor array Rx1. The resistance values ​​of resistors Rn, Rn-1, ..., R1 decrease from large to small. In a binary number, starting from the left, the first bit corresponds to control switch 1, ..., the (n-1)th bit corresponds to control switch n-1, and the nth bit corresponds to control switch n. The finite state machine adds or subtracts a predetermined number from the previous Rctrl[0:n] control signal based on the comparison result being 1 or 0, in order to generate a new Rctrl[0:n] control signal.

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