A method for identifying trapped atomic configurations in gate oxide layers of MOSFETs

Abstract

A method for identifying trapped atomic configurations in the gate oxide layer of MOSFETs comprises the following steps: constructing an atomic-level model of the near-interface oxide layer of MOSFETs and introducing various single defect configurations, thereby forming several defect models containing single defect configurations; calculating the electronic state density for each defect model, qualitatively characterizing the electronic state density peak introduced by the corresponding defect, i.e., the position of the electrically neutral defect energy level; defining the defect formation energy, fitting and solving the charge transition energy levels between different charge states of each defect model, i.e., the position of the charged defect energy level; measuring the low-frequency 1 / f leakage current noise power spectrum of the MOSFETs device, solving the trap distribution in the gate oxide layer of the MOSFETs device, and analyzing the position of the trap center; comparing the position of the electrically neutral defect energy level, the position of the charged defect energy level, and the position of the trap center, to identify the trapped atomic configuration that causes the leakage current noise of the MOSFETs device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a method for identifying the configuration of trapped atoms in a gate oxide layer of MOSFETs. Background Art

[0002] Traps in the gate oxide of MOSFETs capture emitted carriers, causing charge variations in the oxide. These variations significantly affect the semiconductor's surface potential, leading to fluctuations in the channel current. Furthermore, charge variations in the oxide can modulate channel carrier mobility through Coulomb scattering. Therefore, the level and distribution of traps in the gate oxide of MOSFETs is a key factor affecting their performance and reliability. Clarifying the atomic configuration of these traps is crucial for reliability analysis and process improvement.

[0003] Commonly used atomic configuration characterization techniques include: XPS (X-ray photoelectron spectroscopy) [Kosugi R, Ichimura S, Kurokawa A, et al. Effects of ozone treatment of 4H-SiC(0001) surface [J]. Applied Surface Science, 2000, 159(16): 550-555.], HRTEM (high-resolution transmission electron microscopy), and EELS (electron energy loss spectroscopy) [Hatakeyama T, Matsuhata H, Suzuki T, et al. Microscopic Examination of SiO2 / 4H-SiC Interfaces [J]. Materials Science Forum, 2011, 679-680: 330-333.] 0Etc. Currently, the most widely used XPS (X-ray photoelectron spectroscopy) in experimental testing: its basic principle is the photoelectric effect proposed by A. Einstein in 1905. It uses X-rays to irradiate the sample surface to excite the inner electrons of the atomic orbitals of the elements in the sample being tested. The excited electrons are called photoelectrons, and the energy spectrum of the photoelectrons can be obtained by collecting the kinetic energy distribution of the photoelectrons. XPS uses the measurement of electron binding energy to realize surface structure analysis. Binding energy is a characteristic parameter of the chemical bond of an element. By analyzing the binding energy, the bonding information of the measured element can be determined, and then the composition information of the substance can be obtained. Therefore, after sample preparation and testing, the defect structure existing in the sample can be judged by the obtained sample composition and chemical bond information, and its electronic configuration and carrier capture and emission capabilities can be studied, thereby analyzing its trap effect and the impact on the device's macroscopic parameters (output current, transfer characteristics). In actual testing, the XPS instrument can only collect the kinetic energy of the emitted photoelectrons, and the relationship between the binding energy of the core electron and its emitted kinetic energy can be expressed as:

[0004] E b =hv-E k -φ

[0005] Among them, E b is the binding energy corresponding to the excited orbital, that is, the energy difference between the excited orbital and the Fermi level; hv is the energy of the incident X-ray; E k is the kinetic energy of the excited electron, and its value is referenced to the vacuum energy level; φ is the work function of the photoelectron, that is, the minimum energy required for the excited electron to escape from the Fermi level to the vacuum energy level. For a given instrument, this parameter is known.

[0006] When these microscopic characterization techniques are used to characterize gate oxide traps in MOSFET devices, sample preparation is required. Common sample preparation techniques, such as electron beam etching and ion beam bombardment, destroy the existing device microstructure and make it difficult to distinguish newly introduced defects from existing ones. This not only increases costs and wastes considerable time, but the results are often unreliable and unable to accurately identify and analyze the defect trap configurations that significantly contribute to high leakage current noise. Summary of the Invention

[0007] In order to solve the above problems, the purpose of the present invention is to provide a method for identifying the atomic configuration of traps in the gate oxide layer of MOSFETs. Based on first-principles calculations and 1 / f noise testing, by comparing the defect energy level positions calculated by first-principles calculations with the center positions of the gate oxide traps measured by 1 / f noise testing, the specific atomic configuration of traps in the gate oxide layer of MOSFETs is identified in a rapid and non-destructive manner, providing a new approach for more accurately exploring the origin of noise and the causes of defect properties such as high surface state density in MOSFETs devices.

[0008] In order to achieve the above object, the technical solution adopted by the present invention is:

[0009] A method for identifying trapped atomic configurations in a gate oxide layer of a MOSFET comprises the following steps:

[0010] Step 1: Build an atomic-level model of the oxide layer near the interface of MOSFETs and introduce various single defect configurations to form several defect models containing single defect configurations;

[0011] Step 2: Calculate the electronic state density for each defect model to qualitatively characterize the electronic state density peak introduced by the corresponding defect, that is, the position of the electrically neutral defect energy level;

[0012] Step 3: Using the definition of defect formation energy, fit and solve the charge transition energy level ε(q / q′) between different charge states of each defect model, that is, the position of the charged defect energy level, where q and q′ are the charge states of the defect configuration before and after the transition, respectively;

[0013] Step 4: Measure the low-frequency 1 / f leakage current noise power spectrum S of the MOSFETs device Id -f, based on the theoretical model of low-frequency noise and the device physical model, solves the trap distribution N in the gate oxide layer of MOSFETs devices t (E t ,z), analyze the center position of the trap;

[0014] Step 5: Compare the positions of the electrically neutral defect energy levels, the charged defect energy levels, and the trap center positions to identify the trap atom configuration that causes leakage current noise in the MOSFET device.

[0015] In one embodiment, step 1 includes:

[0016] First, during the first-principles modeling process, atomic-level single-crystal material models of the oxide layer near the interface of MOSFETs were constructed. These models were then sectioned perpendicular to the atomic stacking direction, i.e., the direction of oxide layer growth. The models were then expanded and spliced while maintaining a lattice mismatch ratio of <3%. The exposed upper and lower surfaces of the models were treated with pseudo-H to construct the initial heterojunction interface model of the MOSFET oxide layer.

[0017] The initial heterojunction interface model of the MOSFET oxide layer is then input into the first-principles calculation software VASP. Under the condition that the substrate is fixed, the first-principles molecular dynamics simulation calculation is performed on the crystalline oxide layer to amorphize it, thereby obtaining a MOSFET near-interface oxide layer model that does not contain any coordination defects.

[0018] Finally, various single defect configurations that may exist in real devices are introduced into the MOSFETs near-interface oxide layer model to obtain a defect model containing single defect configurations.

[0019] In one embodiment, the defect model is subjected to a structural optimization to minimize lattice stress.

[0020] In one embodiment, the single defect structure is an O vacancy defect, a Si2-C=O defect structure, or other defects.

[0021] In one embodiment, step 2 includes:

[0022] Add LORBIT and NEDOS parameters to INCAR of the first-principles quantum computing software VASP to perform static calculations, output the projected electronic density of states DOSCAR and .xml files, and process the data using Vaspkit scripts or P4vasp software. The density of states of the defect model and the contribution of various single defect configurations to DOS are obtained. By comparing the two, the electronic density of states peak introduced by specific defects, that is, the position of the electrically neutral defect energy level, can be analyzed.

[0023] In one embodiment, the step 3 uses the defect formation energy formula to change the electron chemical potential E F By fitting the formation energies of various interface defect models constructed in step 1 under different charge states, the charge transition energy levels of the interface defect configuration and their relative positions in the band gap can be solved; the defect formation energy formula is as follows:

[0024]

[0025] Where, is the defect formation energy, that is, the theoretical energy required to form or introduce a defect D with a charge state of q. is the total free energy of the system containing defect D and charge state q, is the total free energy of the system without any defects, n α It represents the number of additional atoms of α-type elements added or reduced to the system due to the introduction of defect D, n α >0 means adding, n α <0 means decrease, μ α is the atomic average chemical potential of the α-type elements obtained from the phase diagram, E V is the maximum value of the valence band of the corresponding material, namely the substrate or oxide, ΔE V is the E of the defect system after band alignment calibration V difference;

[0026] The horizontal coordinate of the intersection point where the defect formation energy is fitted under different charge states is the position of the charged defect energy level of the defect configuration.

[0027] In one embodiment, for the same defect configuration, the defect formation energy formula is rewritten as:

[0028]

[0029] Then, static calculation of the system energy is performed in VASP. By changing the NELECT parameter to change the number of valence electrons in the defect system, that is, the charge state of the defect, the energy of the defect system under different charge states can be obtained. and ΔE relative to the electroneutrality defect configuration V Finally, the data of the defect configuration is brought into the above formula and E is changed F Fitting is performed to obtain the defect formation energy of each defect configuration in the oxide layer near the interface of MOSFETs at different charge states. F The changing relationship.

[0030] In one embodiment, step 4 includes:

[0031] Step 4.1: Transfer characteristics of the MOSFETs to be tested and different gate voltages V gs The drain current noise power spectrum S under Id -f is measured and the transconductance curve g is calculated from the transfer characteristic m -V gs ;

[0032] Step 4.2, at a specific gate voltage V gs (1) below, i.e. at a specific trap level The discrete low-frequency noise analysis model and device physical model are numerically solved to obtain the relationship between the trap density in the device oxide layer and the thickness position.

[0033] Step 4.3, calculate the gate voltage V gs (1) The trap level under location;

[0034] Step 4.4, change multiple gate voltages V gs (j), calculation of multiple trap energy levels The relationship between the trap density at the location and the thickness position It can be further summarized as the trap density varies with the trap energy E t Joint distribution N with thickness position z t (E t ,z), analyze the center position of the trap that causes the leakage current noise of MOSFETs devices.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. While microscopic methods like XPS can analyze defect structures in samples by measuring electronic properties such as structural composition and chemical bonding, they cannot distinguish the contribution of these defect traps to MOSFET device performance. This project, starting with low-frequency noise measurements of MOSFETs, identifies the locations of trap centers in the oxide layer that significantly contribute to this contribution. This is then combined with first-principles calculations of the locations of defect energy levels introduced within the bandgap by various microscopic defect structures. By comparing these two, it is possible to identify the defect structures that degrade MOSFET device performance.

[0037] 2. Microscopic testing methods such as XPS generally require sample preparation before microscopic characterization. Sample preparation techniques such as electron beam etching and ion beam bombardment can damage the device's existing microstructure, making it difficult to distinguish newly introduced defects from existing ones. The experimental technique used in this invention is non-destructive. First-principles theoretical calculations only need to be performed once, and the results are permanently available for query. A database can be created for even easier access. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a flow chart of an embodiment of the present invention.

[0039] Figure 2 It is the interface between the single cell used in this embodiment and the initial 4H-SiC / α-SiO2 heterojunction.

[0040] Figure 3 (a) The model of the near-interface oxide layer (4H-SiC / amorphous SiO2 interface) of the 4H-SiC MOSFETs constructed in this embodiment, as well as (b) the top view and (c) the side view of the interface transition region.

[0041] Figure 4 These are two defect configurations introduced into the near-interface oxide layer model of 4H-SiC MOSFETs constructed in this embodiment, namely: (a) O vacancy defect and (b) Si2-C=O defect.

[0042] Figure 5 These are DOS diagrams of two 4H-SiC MOSFETs near-interface oxide layer defect models constructed in this embodiment.

[0043] Figure 6 This is a diagram showing the relationship between the defect formation energy of two oxide layer interface defect models and the change of electron chemical potential under different charge states.

[0044] Figure 7These are the defect charge transition energy level positions of the two 4H-SiC MOSFETs near-interface oxide layer defect models constructed in this embodiment.

[0045] Figure 8 These are the measurement results of the sample 4H-SiC MOSFETs device: (a) transfer characteristics and (b) low-frequency noise characteristics.

[0046] Figure 9 This is the joint distribution of traps in the oxide layer of the sample 4H-SiC MOSFETs calculated in this embodiment with respect to position and energy.

[0047] Figure 10 3 is a comparison of the O vacancy defect energy level position and the center position of the oxide layer trap near the interface of the 4H-SiC MOSFET in this embodiment. DETAILED DESCRIPTION

[0048] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0049] The present invention provides a method for identifying the atomic configuration of MOSFETs gate oxide layer traps. The method realizes the atomic configuration identification of MOSFETs gate oxide layer traps through first-principles calculation of oxide layer trap energy levels and low-frequency 1 / f noise measurement.

[0050] Taking 4H-SiC MOSFETs as an example, according to Figure 1 As shown in the figure, the defect trap atomic configuration identification method mainly includes the following five steps:

[0051] Step 1: Build an atomic-level model of the near-interface oxide layer of MOSFETs (the corresponding 4H-SiCMOSFETs is the 4H-SiC / amorphous SiO2 interface model), and introduce various single defect configurations to form several defect models containing single defect configurations.

[0052] Specifically, step 1 includes:

[0053] First, in the first-principles modeling process, atomic-level single crystal material models of the oxide layer near the interface of MOSFETs are built respectively. The single crystal material models are cut along the vertical atomic stacking direction, i.e., the direction of oxide layer growth. The lattice mismatch rate is kept <3%, and reasonable expansion and splicing are performed. The upper and lower exposed surfaces of the model are treated with pseudo-H to form the initial heterojunction interface model of the MOSFETs oxide layer. For the 4H-SiCMOSFETs initial interface model studied in this embodiment, Figure 2 shown.

[0054] Then, the constructed MOSFETs oxide layer initial heterojunction interface model is input into the first-principles calculation software VASP. Under the condition that the substrate is fixed, the first-principles molecular dynamics simulation calculation is performed on the crystalline oxide layer part to make it amorphous, and obtain the MOSFETs near-interface oxide layer model without any coordination defects, that is, the perfect interface model. For this embodiment, the 4H-SiC / amorphous SiO2 heterojunction interface model is as follows: Figure 3 shown.

[0055] Finally, various single representative defect configurations that may exist in real devices are introduced into the above-mentioned perfect interface model to obtain defect models containing single defect configurations. These models are then structurally optimized to minimize lattice stress and serve as templates for first-principles defect calculations in subsequent steps. For this embodiment, two main defect configurations existing in the near-interface oxide layer of 4H-SiC MOSFETs are introduced, namely: (a) O vacancy defect (obtained by removing an O from the near-interface amorphous SiO2 part); (b) Si2-C=O defect configuration (obtained by introducing a C into the near-interface amorphous SiO2 part to form C=O). The obtained 4H-SiC MOSFETs near-interface oxide layer defect model is as follows: Figure 4 shown.

[0056] A structural optimization method of the present invention is based on the above-mentioned setting of a 6×6×3 Monkhorst-Pack K-point scattering grid (K points are selected according to the actual lattice length), and setting the accuracy to Accurate and the cutoff energy to 500eV. When the maximum Hellmann-Feynman force when the atoms inside the lattice relax to the equilibrium position is less than Under the condition of , the defect model is structurally optimized.

[0057] Step 2: Perform DOS (electronic density of states) calculation on the defect model obtained in step 1 to qualitatively characterize the electronic density of states peak introduced by the corresponding defect, that is, the position of the electrically neutral defect energy level.

[0058] Specifically, LORBIT and NEDOS parameters are added to INCAR of the first-principles quantum computing software VASP to perform static calculations, output the projected electronic density of states DOSCAR and .xml files (in this embodiment, LORBIT=11 and NEDOS=3000 are set), and the data files are processed using Vaspkit scripts or P4vasp software; the overall density of states of the defect model (TDOS, dark curve) and the contribution of various single defect configurations to DOS (PDOS, light curve) are obtained, as shown in Figure 2. Figure 5As shown, by comparing the two, we can qualitatively analyze the electronic state density peak introduced by a specific defect, as shown by the black dotted line in the figure, that is, the position of the electrically neutral defect energy level. For example, for the O vacancy defect in the embodiment, it is located near the conduction band in the interface band gap, that is, E c A defect energy level is introduced at the -0.42eV position.

[0059] Step 3: Using the definition of defect formation energy, fit and solve the charge transition energy level ε(q / q′) between different charge states of the defect model constructed in step 1, that is, the position of the charged defect energy level.

[0060] Specifically, according to the definition of defect formation energy, the lower the defect formation energy under the same electron chemical potential, the more stable its structure. Under different charged conditions, the chemical potential of the electron when the two lowest energy configurations transform is the charge transition energy level ε(q / q′) of the defect, where q and q′ are the charge states of the defect configuration before and after the transformation, respectively. The position of the charged defect energy level can be quantitatively expressed by the charge transition energy level of the defect. Therefore, the defect formation energy formula is used to express the position of the charged defect energy level. By changing the electron chemical potential E F By fitting the formation energy of the defect model built in step 1 under different charge states, the charge transition energy level of the corresponding defect configuration and its relative position in the band gap can be accurately solved.

[0061] Where, is the defect formation energy, that is, the theoretical energy required to form or introduce a defect D with a charge state of q. is the total free energy of the system containing defect D and charge state q, is the total free energy of the system without any defects, n α It represents the number of additional atoms of α-type elements added or reduced to the system due to the introduction of the defect configuration D (n α >0 means adding, n α <0 means decrease), μ α is the atomic average chemical potential of the α-type element obtained from the phase diagram, E V is the maximum value of the valence band of the material (substrate or oxide), ΔE V is the E of the defect system after band alignment calibration V difference.

[0062] In summary, the horizontal coordinate of the intersection point where the defect formation energy is fitted under different charge states is the position of the charged defect energy level of the defect configuration.

[0063] In subsequent calculations, for the same defect configuration, and The same, so the term can be eliminated in the formula, and for the sake of simplicity, the electron chemical potential E of the defect in the substrate or in the oxide layer is F The E of this part of the material V As a reference, the range of variation is 0eV to the band gap value E of this part of the material. g , E V can be set to 0, so the defect formation energy formula can be rewritten as Then, static calculation of the system energy is performed in VASP. By changing the NELECT parameter to change the number of valence electrons in the defect system (i.e., the charge state of the defect), the energy of the defect system under different charge states can be obtained. and ΔE relative to the electroneutrality defect configuration V Finally, these data of the defect configuration can be brought into the above formula, changing E F Fitting is performed to obtain the defect formation energy of each defect configuration in the oxide layer near the interface of MOSFETs at different charge states. F The defect formation energy of the two defect configurations of 4H-SiC MOSFETs introduced in this embodiment is as follows: Figure 6 As shown, the gray dotted line is the position of the charged defect energy level corresponding to the defect configuration. The defect energy levels of the two configurations are summarized to show their relative positions in the band gap, as shown in Figure 7 shown.

[0064] Step 4: Measure the low-frequency 1 / f leakage current noise power spectrum S of the MOSFETs device Id -f, based on the theoretical model of low-frequency noise and the device physical model, solves the trap distribution N in the gate oxide layer of MOSFETs devices t (E t ,z), analyze the center position of the trap;

[0065] Specifically, step 4 includes:

[0066] 4.1. Transfer characteristics of the MOSFETs under test and different gate voltages V gs The drain current noise power spectrum S under Id -f is measured and the transconductance curve g is calculated from the transfer characteristic m -V gs .

[0067] Select the drain voltage. Under this test condition, the transfer characteristic I d -V gs and different gate voltages V gs The drain current noise power spectrum S under Id-f is measured, where the measured drain current noise power spectrum is a function of the power spectrum amplitude and frequency. To ensure that the MOSFETs sample works in linear mode when performing low-frequency noise measurement, the drain voltage V is selected in the range of 0.05V to 0.1V. D .

[0068] In the linear region, the transfer characteristic curve I d -V gs Using g m =dI d / dV g (g m is the transconductance) to obtain the curve g m -V g The transfer characteristics and low-frequency noise characteristics of the device samples are measured as follows: Figure 8 shown.

[0069] 4.2, at a specific gate voltage V gs (1) below, i.e. at a specific trap level The discrete low-frequency noise analysis model is numerically solved to obtain the relationship between the trap density in the device oxide layer and the thickness position.

[0070] For a specific gate voltage V gs (1) Below, the leakage current noise spectrum data S Id and f are both m-dimensional vectors. S measured in step 4.1 is Id -f noise data is substituted into the discrete low-frequency 1 / f noise analysis model to solve (where τ = τ0exp(γ·z), and the typical value of τ0 is 10 -10 s, f is the frequency, z i is the position of the oxide layer along the thickness direction, Δz i is the thickness of the unit oxide layer, n is the total number of layers, I d is the drain current, k is the Boltzmann constant, T is the absolute temperature, α sc is the Coulomb scattering coefficient), we can get a linear equation system containing n unknowns and m equations. By solving the linear equation system using the non-negative least squares method, we can get

[0071] 4.3, calculate the specific gate voltage V gs (1) The trap level under location.

[0072] Determining trap energy levels The location of The distance ΔE from the material band edge: First, numerically solve the transcendental equation Solve for the surface potential Where β=e / kT, e is the elementary charge, is the ionized dopant concentration, in n-type MOSFETs is the acceptor ionization concentration In p-type MOSFETs is the donor ionization concentration ε s is the semiconductor dielectric constant, R represents the square of the ratio of the substrate equilibrium minority carrier concentration to the majority carrier concentration. In n-type MOSFETs, R is the ratio of the substrate electron concentration to the hole concentration (n p0 / p p0 ) 2 In p-type MOSFETs, R is the ratio of substrate hole concentration to electron concentration (p n0 / n n0 ) 2 . use Calculating trap energy levels The distance ΔE from the band edge can be expressed as Will Substitution Available Among them, E g represents the bandgap width, is the substrate Fermi potential; for p-type MOSFETs it can be expressed as Will Substitution Available In summary, it can be determined that at a specific gate voltage V gs (1) Under the trap energy level in the oxide layer of MOSFETs device The relative position in the band gap, for the trap level position E of the n-type 4H-SiC MOSFETs studied in this example c -E t ,like Figure 9 shown.

[0073] 4.4, Change multiple gate voltages V gs (j), calculation of multiple trap energy levels The relationship between the trap density at the location and the thickness position It can be further summarized as the trap density varies with the trap energy E t Joint distribution N with thickness position z t (E t ,z), qualitatively analyze the trap center location that causes leakage current noise in MOSFETs devices.

[0074] For multiple gate voltages V gs Leakage current noise spectrum data S under Id -f Repeat 4.2 and 4.3 to calculate the gate voltage V for each groupgs (j) Multiple quasi-continuous trap energy levels E t The change of trap density along position z is summarized to obtain the joint distribution of traps in the oxide layer of MOSFETs devices with position and energy N t (E t ,z), where the location with the highest and most concentrated trap density is the trap center. This embodiment uses 10 sets of measured gate voltages (from 3.2V to 5V, with one selected every 0.2V) for n-type 4H-SiC MOSFET. The resulting joint distribution relationship of trap density, position, and energy is as follows: Figure 9 As shown, it can be qualitatively analyzed that the center of the trap is roughly located in the near-interface oxide layer of 1-2.7 nm, at the trap energy level position of 0.41-0.43 eV from the bottom of the conduction band.

[0075] Step 5: Compare the theoretically calculated defect energy level positions (i.e., the electrically neutral defect energy level positions and the charged defect energy level positions) with the experimentally analyzed trap center positions to identify the trap atom configuration that causes device leakage current noise.

[0076] Specifically, the defect energy level positions of each major defect configuration obtained by first-principles modeling and calculation in steps 2 and 3 are compared with the trap center positions obtained by experimental measurement and noise model analysis in step 4. For the 4H-SiC MOSFETs studied in this example, the comparison between the theoretical calculation and experimental analysis results is as follows: Figure 10 As shown, the defect configuration selected for analysis on the left is O vacancy. It can be seen that the electronic state density peak and ε(0 / -1) defect energy level introduced by the O vacancy defect configuration are located at a distance of 0.419 eV from the bottom of the conduction band of the defect system, which is consistent with the oxide layer trap center position of 0.41-0.43 eV calculated based on the 1 / f noise measurement of the 4H-SiCMOSFETs device sample. It is identified that the main trap configuration that causes the leakage current noise of the device should be the O vacancy defect.

Claims

1. A method for identifying the configuration of trapped atoms in the gate oxide layer of MOSFETs, characterized in that: The steps include: Step 1: Build an atomic-level model of the oxide layer near the interface of MOSFETs and introduce various single defect configurations to form several defect models containing single defect configurations; Step 2: Calculate the electronic state density for each defect model to qualitatively characterize the electronic state density peak introduced by the corresponding defect, that is, the position of the electrically neutral defect energy level; Step 3: Using the definition of defect formation energy, fit and solve the charge transition energy level ε(q / q') between different charge states of each defect model, that is, the position of the charged defect energy level, where q and q' are the charge states of the defect configuration before and after the transition, respectively; Step 4: Measure the low-frequency 1 / f leakage current noise power spectrum S of the MOSFETs device Id -f, based on the theoretical model of low-frequency noise and the device physical model, solves the trap distribution N in the gate oxide layer of MOSFETs devices t (E t ,z), analyze the center position of the trap; Step 5: Compare the positions of the electrically neutral defect energy level, the charged defect energy level, and the trap center position to identify the trap atom configuration that causes leakage current noise in the MOSFET device; Wherein, the step 4 includes: Step 4.1: Transfer characteristics of the MOSFETs to be tested and the drain current noise power spectrum S at different gate voltages Id -f is measured and the transconductance curve g is calculated from the transfer characteristic m -V gs ; Step 4.2, at a specific gate voltage V gs (1) below, i.e. at a specific trap level The discrete low-frequency noise analysis model and device physical model are numerically solved to obtain the relationship between the trap density in the device oxide layer and the thickness position. Step 4.3, calculate the gate voltage V gs (1) The trap level under location; Step 4.4, change multiple gate voltages V gs , calculate multiple trap levels The relationship between the trap density at the location and the thickness position It can be further summarized as the trap density varies with the trap energy E t Joint distribution N with thickness position z t (E t ,z), analyze the center position of the trap that causes the leakage current noise of MOSFETs devices.

2. The method for identifying the configuration of trapped atoms in the gate oxide layer of MOSFETs according to claim 1, wherein: The step 1 comprises: First, during the first-principles modeling process, atomic-level single-crystal material models of the oxide layer near the interface of MOSFETs were constructed. These models were then sectioned perpendicular to the atomic stacking direction, i.e., the direction of oxide layer growth. The models were then expanded and spliced while maintaining a lattice mismatch ratio of <3%. The exposed upper and lower surfaces of the models were treated with pseudo-H to construct the initial heterojunction interface model of the MOSFET oxide layer. The initial heterojunction interface model of the MOSFET oxide layer is then input into the first-principles calculation software VASP. Under the condition that the substrate is fixed, the first-principles molecular dynamics simulation calculation is performed on the crystalline oxide layer to amorphize it, thereby obtaining a MOSFET near-interface oxide layer model that does not contain any coordination defects. Finally, various single defect configurations that may exist in real devices are introduced into the MOSFETs near-interface oxide layer model that does not contain any coordination defects, thereby obtaining a defect model containing single defect configurations.

3. The method for identifying the configuration of trapped atoms in the gate oxide layer of MOSFETs according to claim 2, wherein: The defect model performs a structural optimization to minimize the lattice stress.

4. The method for identifying the configuration of trapped atoms in the gate oxide layer of MOSFETs according to claim 2 or 3, wherein: The single defect configuration is an O vacancy defect, a Si2-C=O defect configuration or other defects.

5. The method for identifying the configuration of trapped atoms in the gate oxide layer of MOSFETs according to claim 1, 2 or 3, wherein: The step 2 comprises: Add LORBIT and NEDOS parameters to INCAR of the first-principles quantum computing software VASP to perform static calculations, output the projected electronic density of states DOSCAR and .xml files, and process the data using Vaspkit scripts or P4vasp software. The density of states of the defect model and the contribution of various single defect configurations to DOS are obtained. By comparing the two, the electronic density of states peak introduced by the corresponding defects, that is, the position of the electrically neutral defect energy level, can be qualitatively analyzed.

6. The method for identifying the configuration of trapped atoms in the gate oxide layer of MOSFETs according to claim 1, 2 or 3, wherein: In step 3, the defect formation energy formula is used to change the electron chemical potential E F By fitting the formation energies of the various defect models constructed in step 1 under different charge states, the charge transition energy levels of the corresponding defect configurations and their relative positions in the band gap can be solved; the defect formation energy formula is as follows: Where, is the defect formation energy, that is, the theoretical energy required to form or introduce a defect D with a charge state of q. is the total free energy of the system containing defect D and charge state q, is the total free energy of the system without any defects, n α It represents the number of additional atoms of α-type elements added or reduced to the system due to the introduction of defect D, n α >0 means adding, n α <0 means decrease, μ α is the atomic average chemical potential of the α-type elements obtained from the phase diagram, E V is the maximum value of the valence band of the corresponding material, namely the substrate or oxide, ΔE V is the E of the defect system after band alignment calibration V difference; The horizontal coordinate of the intersection point where the defect formation energy is fitted under different charge states is the position of the charged defect energy level of the defect configuration.

7. The method for identifying the configuration of trapped atoms in the gate oxide layer of MOSFETs according to claim 6, characterized in that: For the same defect configuration, the defect formation energy formula is rewritten as: Then, static calculation of the system energy is performed in VASP. By changing the NELECT parameter to change the number of valence electrons in the defect system, that is, the charge state of the defect, the energy of the defect system under different charge states can be obtained. and ΔE relative to the electroneutrality defect configuration V Finally, the data of the defect configuration is brought into the above formula and E is changed F Fitting is performed to obtain the defect formation energy of each defect configuration in the oxide layer near the interface of MOSFETs at different charge states. F The changing relationship.

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