A zq calibration method, memory and storage system

Abstract

Embodiments of the present application provide a ZQ calibration method, a memory and a storage system. The method comprises: obtaining a maximum number of cycles configured for short ZQ calibration; the maximum number of cycles is used to indicate a calibration range of the short ZQ calibration; after receiving a short ZQ calibration command, performing the short ZQ calibration on an interface impedance of the memory until a number of cycles of calibration reaches the maximum number of cycles and / or a calibration result meets a requirement.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a ZQ calibration method, a memory, and a storage system. Background Technology

[0002] Semiconductor memories, which include integrated circuits such as microprocessors, memory circuits, and gate array circuits, are currently used in various electronic devices, such as personal computers, server computers, and workstations. As the operating speed of electronic devices increases, impedance mismatch at the memory interface makes high-speed data transmission difficult. Therefore, ZQ calibration is introduced into the memory to calibrate the impedance at the memory interface, thereby ensuring high-speed data transmission. However, the currently used ZQ calibration methods cannot meet the calibration requirements. Summary of the Invention

[0003] In view of this, the present invention provides a ZQ calibration method, a memory, and a storage system. Specifically, for short ZQ calibration, the impedance of the memory is calibrated within the maximum number of calibration cycles configured by the user until the maximum number of calibration cycles is reached and / or the calibration result meets the requirements. This not only allows for flexible setting of the calibration range for short ZQ calibration, but also, when the maximum number of calibration cycles is set appropriately, can correct errors that occur in long ZQ calibration.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] In a first aspect, embodiments of the present invention provide a ZQ calibration method, the method comprising:

[0006] Obtain the maximum number of cycles configured for the short ZQ calibration; the maximum number of cycles is used to indicate the calibration range of the short ZQ calibration;

[0007] Upon receiving the short ZQ calibration command, the interface impedance of the memory is calibrated using the short ZQ calibration until the number of calibration cycles reaches the maximum number of cycles and / or the calibration result meets the requirements.

[0008] In the above scheme, when the memory supports the Open NAND Flash Interface (ONFI) protocol, the maximum number of cycles is set in the memory by the memory controller coupled to the memory based on the Set Feature command in the ONFI protocol.

[0009] In the above scheme, when the maximum number of cycles includes multiple values, obtaining the maximum number of cycles for the short ZQ calibration configuration includes:

[0010] Determine the extent of changes in the current work environment;

[0011] The maximum number of cycles for short ZQ calibration configuration is obtained based on the degree of change in the current working environment and the mapping relationship.

[0012] The degree of change in the working environment is measured by changes in ambient temperature and / or changes in the output voltage of the memory; the mapping relationship is used to reflect the correspondence between the degree of change in the working environment and the maximum number of cycles.

[0013] In the above scheme, the method further includes:

[0014] When the number of calibration cycles reaches the maximum number of cycles and the calibration result does not meet the requirements, a first identifier indicating calibration failure is fed back to the memory controller coupled to the memory.

[0015] In the above scheme, the method further includes:

[0016] Upon reaching the next calibration cycle, the system receives a long ZQ calibration command sent by the memory controller after receiving the first identifier; upon receiving the long ZQ calibration command, the system performs long ZQ calibration on the interface impedance of the memory.

[0017] The calibration period is the time interval between two adjacent memory controllers sending the short ZQ calibration command to the memory.

[0018] In the above scheme, the method further includes: after the calibration result meets the requirements, feeding back a second identifier to the memory controller coupled to the memory to indicate that the calibration is successful; wherein the second identifier is used to increase the calibration period for the memory controller to send the short ZQ calibration command.

[0019] In the above scheme, after performing long ZQ calibration on the interface impedance of the memory, the method further includes: continuing to perform short ZQ calibration on the interface impedance of the memory according to the calibration cycle.

[0020] Secondly, embodiments of the present invention provide a memory, comprising: a memory array for storing data; and peripheral circuitry coupled to the memory array and used for controlling the memory array; wherein,

[0021] The peripheral circuit is configured to: acquire the maximum number of cycles configured for short ZQ calibration; the maximum number of cycles is used to indicate the calibration range of the short ZQ calibration; and, upon receiving a short ZQ calibration command, perform the short ZQ calibration on the interface impedance of the memory until the number of calibration cycles reaches the maximum number of cycles and / or the calibration result meets the requirements.

[0022] In the above scheme, the peripheral circuit includes: a control logic unit and a ZQ calibration unit, wherein;

[0023] The control logic unit is configured to: obtain the maximum number of cycles configured for short ZQ calibration; and, upon receiving a short ZQ calibration command, control the ZQ calibration unit to perform short ZQ calibration on the interface impedance of the memory until the number of calibration cycles reaches the maximum number of cycles and / or the calibration result meets the requirements.

[0024] In the above scheme, when the memory supports the Open NAND Flash Interface (ONFI) protocol, the maximum number of cycles is set in the memory by the memory controller coupled to the memory based on the Set Feature command in the ONFI protocol.

[0025] In the above scheme, the peripheral circuit further includes: a register configured to store a first identifier and / or a second identifier, wherein the first identifier is a flag fed back to the memory controller coupled to the memory to indicate calibration failure when the number of calibration cycles reaches the maximum number of cycles and the calibration result does not meet the requirements; the second identifier is a flag fed back to the memory controller coupled to the memory to indicate calibration success after the calibration result meets the requirements.

[0026] In the above scheme, the memory is a dual data rate dynamic random access memory (DDR DRAM).

[0027] Thirdly, embodiments of the present invention also provide a storage system, including: one or more of the above-described memories; and a memory controller coupled to the memories; the memory controller is configured to: send a short ZQ calibration command or a long ZQ calibration command to the memories.

[0028] In the above solution, the storage system is a solid-state drive or a memory card.

[0029] This invention provides a ZQ calibration method, a memory, and a storage system. The method includes: obtaining a maximum number of cycles configured for short ZQ calibration; the maximum number of cycles indicating the calibration range of the short ZQ calibration; and, upon receiving a short ZQ calibration command, performing short ZQ calibration on the interface impedance of the memory until the number of calibration cycles reaches the maximum number of cycles and / or the calibration result meets the requirements. The ZQ calibration method provided by this invention utilizes a user-configured number of calibration cycles to flexibly set the calibration range of short ZQ calibration, enabling accurate calibration of the memory's interface impedance. Furthermore, when the maximum number of calibration cycles is set appropriately, it can also correct errors in the memory's interface impedance caused by long ZQ calibration, among other advantages. Attached Figure Description

[0030] When read in conjunction with the accompanying drawings, aspects of the invention can be best understood from the following specific embodiments. Note that, according to standard practice in industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0031] Figure 1 A block diagram of an exemplary system with memory in the related art is shown;

[0032] Figure 2 A schematic diagram of an exemplary memory card with memory is shown;

[0033] Figure 3 A schematic diagram showing an exemplary solid-state drive (SSD) with memory is shown;

[0034] Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown;

[0035] Figure 5 A side view showing a cross-section of an exemplary memory array containing NAND memory strings;

[0036] Figure 6 A block diagram of an exemplary memory including a storage array and peripheral circuitry is shown.

[0037] Figure 7 A block diagram of the ZQ calibration circuit in the related art is shown;

[0038] Figure 8 This diagram illustrates the structure of the pull-up resistor network in the relevant technology.

[0039] Figure 9 This diagram illustrates the structure of a pull-up resistor in the relevant technology.

[0040] Figure 10 This diagram illustrates the structure of a pull-down resistor network in the relevant technology.

[0041] Figure 11 This diagram illustrates the structure of a pull-down resistor in the relevant technology.

[0042] Figure 12 A schematic diagram of the ZQ calibration process in related technologies is shown;

[0043] Figure 13 A schematic diagram illustrating the specific implementation process of long ZQ calibration or short ZQ calibration in related technologies is shown.

[0044] Figure 14 The diagram shows a schematic flow chart of a ZQ calibration method provided in an embodiment of the present invention;

[0045] Figure 15 A comparison diagram is shown between the prior ZQ calibration scheme provided in the embodiments of the present invention and the ZQ calibration scheme provided in the embodiments of the present invention.

[0046] Figure 16 This diagram illustrates the specific operation flow of ZQ calibration provided in an embodiment of the present invention.

[0047] Figure 17 An example diagram illustrating the maximum number of loops provided in an embodiment of the present invention is shown. Detailed Implementation

[0048] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0049] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (one or more) another element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0050] In Double Data Rate Synchronous Dynamic Random Access Memory (DDR DRAM) technology, ZQ calibration commands are used to periodically calibrate the DRAM input / output interface impedance. Specifically, the memory controller typically issues short ZQ calibration commands (corresponding to short ZQ calibration) or long ZQ calibration commands (corresponding to long ZQ calibration) to compensate for any system voltage and temperature (VT) variations in the input / output (I / O) drivers associated with the DRAM. Long ZQ calibration commands are typically used during DRAM power-on initialization and reset conditions; short ZQ calibration commands tend to be used to track small voltage and temperature variations during normal operation and periodically calibrate the DRAM when idle to maintain linear output driver and interface impedance across the entire voltage and temperature range. Typically, a short ZQ calibration command takes 128 DRAM clock cycles to complete, while a long ZQ calibration command takes a longer time, such as 512 DRAM clock cycles, but it compensates for larger voltage and temperature deviations compared to the ZQ calibration performed by the short ZQ calibration command. However, the currently used long ZQ calibration cannot obtain precise adjustment control signals, and therefore cannot accurately calibrate the interface impedance of DRAM; while the short ZQ calibration sets a default adjustment range, and its calibration range is limited, making it unable to adapt to the calibration of DRAM interface impedance under drastic environmental changes.

[0051] To address the aforementioned technical problems, this invention provides a ZQ calibration method. For short ZQ calibration, the impedance of the memory is calibrated within the maximum number of calibration cycles configured by the user until the maximum number of calibration cycles is reached and / or the calibration result meets the requirements. This not only allows for flexible setting of the calibration range for short ZQ calibration, but also, when the maximum number of calibration cycles is set appropriately, can correct errors that occur during long ZQ calibration.

[0052] The specific technical solutions are explained in detail below with reference to the accompanying drawings.

[0053] Figure 1 A block diagram of an exemplary system with memory in the related art is shown. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. For example... Figure 1As shown, system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory 104. Specifically, the memory 104 may be any memory disclosed in this invention, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0054] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108, and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as on Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones in low duty cycle environments. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as on solid-state drives (SSDs) or embedded multimedia cards (eMMCs), where SSDs or eMMCs are used as data storage for mobile devices in high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0055] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for the memory card to a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 3 In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 302. The SSD may also include components for connecting the SSD to a host computer (e.g., Figure 1 The SSD connector 304 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 106 can also be configured to control erase, read, and write operations of the memory 104.

[0056] Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown. Figure 4As shown, memory 104 may include a memory array 401 and peripheral circuitry 402 coupled to the memory array 401. The memory array 401 may be a NAND flash memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0057] In some embodiments, each memory cell 406 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 406 is a multi-level cell (MLC) capable of storing a single bit of data in multiple four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to that memory cell. A fourth nominal storage value may be used for the erase state.

[0058] like Figure 4As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. SSG 410 and DSG 412 can be configured to activate a selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of NAND memory strings 408 in the same block 404 are coupled via the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG412) or a deselection voltage (e.g., 0 volts (V)) to the corresponding DSG412 via one or more DSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG410) or a deselection voltage (e.g., 0V) to the corresponding SSG410 via one or more SSG lines 415.

[0059] like Figure 4As shown, NAND memory strings 408 can be organized into multiple blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 404 is a basic data unit with an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase memory cells 406 in a selected block 404, a source line 414 biased to the selected block 404 and unselected blocks 404 on the same plane as the selected block 404 can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same word line 418 are referred to as pages 420. A page 420 is a basic unit of data used for programming or reading operations, and the size of a page 420, measured in bits, can be related to the number of NAND memory strings 408 coupled by word lines 418 in a block 404. Each word line 418 may include multiple control gates (gate electrodes) at each memory cell 406 within the corresponding page 420, as well as gate lines coupling the control gates.

[0060] Figure 5 A side view of a cross-section of an exemplary memory array containing NAND memory strings is shown. Figure 5 As shown, the NAND memory string 408 may extend vertically through the memory stack layer 504 above the substrate 502. The substrate 502 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0061] The memory stack 504 may include alternating gate conductive layers 506 and gate-to-gate dielectric layers 508. The number of pairs of gate conductive layers 506 and gate-to-gate dielectric layers 508 in the memory stack 504 determines the number of memory cells 406 in the memory array 401. The gate conductive layers 506 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 506 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 506 includes a doped polysilicon layer. Each gate conductive layer 506 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack 504 as a DSG line 413, at the bottom of the memory stack 504 as an SSG line 415, or between DSG lines 413 and SSG lines 415 as a word line 418.

[0062] like Figure 5 As shown, the NAND memory string 408 includes a channel structure 512 extending vertically through the memory stack layer 504. In some embodiments, the channel structure 512 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel 520) and one or more dielectric materials (e.g., as a memory film 518). In some embodiments, the semiconductor channel 520 includes silicon, for example, polysilicon. In some embodiments, the memory film 518 is a composite dielectric layer including a tunneling layer 526, a storage layer 524 (also referred to as a "charge trap / storage layer"), and a barrier layer 522. The channel structure 512 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 520, tunneling layer 526, storage layer 524, and barrier layer 522 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 526 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 524 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 522 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 518 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0063] According to some implementation methods, such as Figure 5As shown, a well 514 (e.g., a P-well and / or an N-well) is formed in a substrate 502, and the source terminal of the NAND memory string 408 is in contact with the well 514. For example, a source line 414 may be coupled to the well 514 to apply an erase voltage to the well 514 (i.e., the source of the NAND memory string 408) during an erase operation. In some embodiments, the NAND memory string 408 also includes a channel plug 516 at the drain terminal of the NAND memory string 408. It should be understood that, although in Figure 5 Although not shown, these are additional components that can form the memory array 401. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc. It should be noted that... Figure 5 This is merely an exemplary structure. The ZQ calibration method provided in this embodiment of the invention is applicable to memory structures of any kind.

[0064] Return to reference Figure 4 Peripheral circuitry 402 can be coupled to memory array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. Peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. Peripheral circuitry 402 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic unit 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional components may be included. Figure 6 Additional peripheral circuitry not shown.

[0065] Page buffer / sensor amplifier 604 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic unit 612. In one example, page buffer / sensor amplifier 604 can store a page of programming data (write data) to be programmed into a page 420 of memory array 401. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic unit 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 610.

[0066] The row decoder / word line driver 608 can be configured to be controlled by the control logic unit 612 and to select / deselect block 404 of the memory array 401 and to select / deselect word line 418 of block 404. The row decoder / word line driver 608 can also be configured to drive word line 418 using word line voltages generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive SSG line 415 and DSG line 413. As described in detail below, the row decoder / word line driver 608 is configured to perform an erase operation on memory cell 406 coupled to one or more selected word lines 418. The voltage generator 610 can be configured to be controlled by the control logic unit 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0067] Control logic unit 612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 614 can be coupled to control logic unit 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic unit 612 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 612, as well as to buffer status information received from control logic unit 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bit line driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0068] For the aforementioned memory, as the operating speed of the electronic device containing the memory increases, the swing width of signal transmission between memories within the electronic device decreases to minimize the latency of signal transmission. However, as the swing width decreases, signal transmission becomes more susceptible to external noise, and signal reflection at the interface increases due to impedance mismatch. This impedance mismatch is caused by variations in the memory's manufacturing process, supply voltage, and operating temperature (PVT). This impedance mismatch can distort the signal output from the memory, leading to setup / hold failures or misjudgments of signal levels in another memory with distorted signals, thus hindering high-speed data transmission. Generally, the peripheral circuitry of a memory can include input circuitry for receiving external signals through input pads and output circuitry for outputting internal signals through the pads. In particular, high-speed operating memories can include impedance matching circuitry to match the interface impedance with another memory near the pads to mitigate the aforementioned faults. However, these impedances vary with environmental changes; therefore, to reduce these impedance discontinuities, impedance calibration, or ZQ calibration, must be introduced.

[0069] like Figure 7 As shown, it illustrates a principle block diagram of a ZQ calibration circuit in the related art. Figure 7 The calibration circuit 70 includes: a ZQ calibration control unit 701, a pull-up resistor network 702, a pull-down resistor network 703, a reference voltage generator 704, a pull-up comparator 705, a pull-down comparator 706, a P-code counter 707, and an N-code counter 708, wherein the pull-up resistor network is as follows: Figure 8 As shown, it includes multiple parallel pull-up resistors; each pull-up resistor, as... Figure 9As shown, this includes multiple parallel-coupled MOS transistors. Similarly, the pull-down resistor network is as follows: Figure 10 As shown, it includes multiple parallel pull-down resistors; each pull-down resistor, as... Figure 11 As shown, it includes multiple parallel-coupled MOS transistors. It should be noted that ZQ calibration includes calibrating the pull-up resistors in each pull-up resistor network and the pull-down resistors in each pull-down resistor network.

[0070] For the calibration of a specific pull-up resistor, the supply voltage VDDQ is divided by the pull-up resistor network and a reference resistor, thus providing voltage to node ZQ. The reference resistor coupled to node ZQ typically has 240 ohms. The pull-up comparator compares the voltage at node ZQ with the reference voltage VREF output from the reference voltage generator, thereby generating a pull-up adjustment signal. The reference voltage VREF is typically set to half of the supply voltage, i.e., VDDQ / 2. The P-code comparator receives the pull-up adjustment signal, thereby generating a binary code PCODE<0:N>. This binary code PCODE<0:N> turns the parallel-coupled MOS transistors in the pull-up resistors of the pull-up resistor network on / off, thereby calibrating the pull-up resistors. Since the value of the pull-up resistor being calibrated affects the voltage at node ZQ, this process is repeated until the resistance value of the pull-up resistor is equal to the resistance value of the reference resistor 709. During the pull-up resistor calibration, the generated binary code PCODE<0:N> is also fed into other pull-up resistors in the pull-up resistor network to determine the resistance values ​​of the other pull-up resistors.

[0071] For pull-down calibration, similar to pull-up calibration, a binary code NCODE<0:N> is generated by a pull-down comparator and an N-code counter. At node ZQ', the voltage becomes equal to the reference voltage VREF, so that the pull-down resistors in the pull-down resistor network are equal to the pull-up resistors in the pull-up resistor network.

[0072] It should be noted that ZQ calibration includes calibrating the pull-up resistors in each pull-up resistor network and / or calibrating the pull-down resistors in each pull-down resistor network. For example, if the output driver contained in the memory uses both pull-up and pull-down resistor networks, its ZQ calibration includes calibrating the pull-up resistors in the pull-up resistor network and the pull-down resistors in the pull-down resistor network; as another example, if the input buffer contained in the memory only uses pull-up resistor networks, its ZQ calibration only includes calibrating the pull-up resistors in the pull-up resistor network.

[0073] The ZQ calibration control unit in the ZQ calibration circuit receives a short ZQ calibration command ZQCS, generates a calibration start signal based on the ZQCS, and then performs ZQ calibration.

[0074] From the above Figures 7 to 11This describes a schematic diagram of the ZQ calibration circuit. Based on the above ZQ calibration circuit, see... Figure 12 The diagram illustrates a ZQ calibration process in related technologies. In these technologies, ZQ calibration comprises two parts: long ZQ calibration and short ZQ calibration. After memory initialization or reset, long ZQ calibration is performed first to configure the memory with an interface impedance of a fixed initial value. Then, based on this, periodic short ZQ calibrations are performed to calibrate for changes in interface impedance caused by environmental variations. In summary, the combined effect of long and short ZQ calibrations enables the memory to obtain an accurate calibration resistance value.

[0075] The foregoing Figures 7 to 11 The principle of the ZQ calibration circuit is described, and its specific implementation process is as follows: Figure 13 As shown. Regardless of whether it is a long ZQ calibration or a short ZQ calibration, the process can be roughly divided into three stages.

[0076] The first stage is the preparation stage (or ZQ Dummy Cycle). In this stage, it is necessary to prepare the required calibration algorithm. For example, when performing long ZQ calibration, a calibration algorithm adapted to long ZQ calibration must be prepared; similarly, when performing short ZQ calibration, a calibration algorithm adapted to short ZQ calibration must be prepared.

[0077] The second stage, the calibration stage (or ZQ Calibration Cycle), is which uses... Figures 7 to 11 The described calibration circuit uses the aforementioned calibration algorithm to calibrate the interface impedance of the memory.

[0078] The third stage, the verification stage (or Out of Boundary Check Cycle), involves verifying the results obtained after the calibration stage to confirm whether they exceed the upper or lower limits. If they do, a ZQ calibration failure flag needs to be sent to the memory controller or host.

[0079] Based on the aforementioned description of the ZQ calibration principle, in related technologies, the binary code PCODE<0:N> or NCODE<0:N> controls the on / off state of the MOS transistor contained in the pull-up or pull-down resistor to calibrate its resistance value. Research has found that for long ZQ calibration, the adjustment of the binary code PCODE<0:N> or NCODE<0:N> is performed bit by bit from the most significant bit to the least significant bit. In this case, if an error occurs in the most significant bit, the resulting pull-up or pull-down resistor value will deviate significantly from the correct value, ultimately causing the entire ZQ calibration to fail and requiring recalibration. As is well known, long ZQ calibration is already time-consuming, and recalibrating would waste even more time. For example, suppose the binary code PCODE<0:N> is a 5-bit PCODE<0:5>, which contains 5 binary bits. Each comparison calibrates only one bit, starting from the most significant bit. If the most significant bit is incorrect, the pull-up or pull-down resistor values ​​obtained from PCODE<0:5> will differ significantly from the correct values. Short ZQ calibration, performed after long ZQ calibration, is a small-scale calibration based on the long ZQ calibration. It has a default adjustment range, which is limited and cannot adapt to the calibration of DRAM interface impedance under drastic environmental changes.

[0080] Based on this, embodiments of the present invention provide a ZQ calibration method, see details below. Figure 14 The diagram illustrates a flowchart of a ZQ calibration method provided by an embodiment of the present invention. This method is applied to a memory and specifically includes:

[0081] S1401: Obtain the maximum number of cycles configured for the short ZQ calibration; the maximum number of cycles is used to indicate the calibration range of the short ZQ calibration;

[0082] S1402: Upon receiving the short ZQ calibration command, perform the short ZQ calibration on the interface impedance of the memory until the number of calibration cycles reaches the maximum number of cycles and / or the calibration result meets the requirements.

[0083] It should be noted that, since long ZQ calibration takes a relatively long time and is only used after memory initialization or reset, short ZQ calibration is used most of the time. Furthermore, the calibration range of long ZQ calibration is relatively large. Therefore, the maximum number of loops provided in this embodiment of the invention refers to short ZQ calibration. This maximum number of loops indicates the calibration range of the short ZQ calibration. Here, the maximum number of loops refers to the number of loops used in a single short ZQ calibration command. Figures 7 to 11 The maximum number of times the calibration circuit can be calibrated also reflects the number of times a short ZQ calibration command is used. Figures 7 to 11 The calibration circuit calibrates the interface impedance of the memory within a specified range. The maximum number of cycles can be greater than the default number of cycles stored in the memory.

[0084] In some embodiments, when the memory supports the Open NAND Flash Interface (ONFI) protocol, the maximum number of cycles is set in the memory by the memory controller coupled to the memory based on the Set Feature command in the ONFI protocol.

[0085] It should be noted that in the ONFI protocol, the Set Feature function is used to configure specific memory performance settings. For example, this function can enable a feature that disables upon power-on. A dedicated space is allocated in the memory for setting parameters related to a specific function; these settings can be placed in this space for future memory access. The maximum number of loops required in this embodiment of the invention is also placed in this space for future memory access.

[0086] Specifically, firstly, one or more bits are defined in the memory at the free address specified for the Set Feature function to represent the maximum number of cycles. Then, the memory controller writes the configured maximum number of cycles into the aforementioned one or more free address in the memory via the Set Feature command. Then, when short ZQ calibration is required, the memory can obtain the stored maximum number of cycles to initiate short ZQ calibration based on the short ZQ calibration command, until the calibration result meets the requirements and / or the number of calibration cycles reaches the maximum number of cycles.

[0087] In some embodiments, when the maximum number of cycles may include multiple values, obtaining the maximum number of cycles configured for short ZQ calibration may include:

[0088] Determine the extent of changes in the current work environment;

[0089] The maximum number of cycles for short ZQ calibration configuration is obtained based on the degree of change in the current working environment and the mapping relationship.

[0090] The degree of change in the working environment is measured by changes in ambient temperature and / or changes in the output voltage of the memory; the mapping relationship is used to reflect the correspondence between the degree of change in the working environment and the maximum number of cycles.

[0091] It should be noted that, for flexibility, multiple maximum cycle counts can be set based on the degree of change in the working environment. Then, an appropriate maximum cycle count is selected based on the actual measured degree of change in the working environment to obtain a more reasonable calibration range and accurate impedance calibration values. Here, the degree of change in the working environment is positively correlated with changes in ambient temperature and / or changes in the output voltage of the memory. That is, the greater the change in ambient temperature and / or the change in the output voltage of the memory, the greater the degree of change in the working environment. How to quantify this is determined based on specific circumstances and will not be elaborated upon here.

[0092] In one optional implementation, the mapping relationship can be a correspondence between the degree of change in the working environment and the maximum number of cycles within a preset range. In other words, a degree of change in the working environment corresponds to a maximum number of cycles within a preset range. For example, assuming the degree of change in the working environment is 1, the corresponding maximum number of cycles ranges from 1 to 3. Due to the nature of the maximum number of cycles, the value of the maximum number of cycles can be any one of 1, 2, or 3. The specific choice of which one to use depends on the user's settings. For example, the user may set multiple maximum number of cycles such as 2, 5, 8, 10, etc. After obtaining the preset range of maximum number of cycles from 1 to 3, it is matched with the user's settings of 2, 5, 8, 10, etc., through the Set Feature function, resulting in a maximum number of cycles of 2. Other degrees of change in the working environment are then used in the same way to obtain a suitable maximum number of cycles.

[0093] After obtaining the maximum number of cycles, upon receiving a short ZQ calibration command, the interface impedance of the memory is calibrated until the calibration cycle count reaches the maximum number of cycles and / or the calibration result meets the requirements.

[0094] Here, "meeting the calibration requirements" can mean that the impedance obtained after calibration meets the requirements. For example, the resistance value of the pull-up resistor is equal to the resistance value of the reference resistor, and the resistance value of the pull-down resistor is equal to the resistance value of the pull-up resistor. This is one case where the calibration result meets the requirements. The short ZQ calibration is divided into three cases: one is stopping calibration after the maximum number of calibration cycles is reached; another is stopping calibration after the calibration result meets the requirements; and the third is that the calibration result meets the requirements exactly when the maximum number of calibration cycles is reached, in which case calibration also needs to be stopped.

[0095] In some embodiments, the method may further include:

[0096] When the number of calibration cycles reaches the maximum number of cycles and the calibration result does not meet the requirements, a first identifier indicating calibration failure is fed back to the memory controller coupled to the memory.

[0097] This describes a situation where, if the calibration result still does not meet the requirements until the maximum number of calibration cycles has been performed, a first identifier indicating calibration failure needs to be fed back to the memory controller coupled to the memory.

[0098] In some embodiments, the method further includes:

[0099] Upon reaching the next calibration cycle, the system receives a long ZQ calibration command sent by the memory controller after receiving the first identifier; upon receiving the long ZQ calibration command, the system performs long ZQ calibration on the interface impedance of the memory.

[0100] The calibration period is the time interval between two adjacent memory controllers sending the short ZQ calibration command to the memory.

[0101] It should be noted that, as explained earlier, short ZQ calibration is performed periodically, where the calibration period is the time interval between two consecutive short ZQ calibrations. The description here is that after a short ZQ calibration, when the next calibration period arrives, the memory controller receives the first flag. At this point, performing another short ZQ calibration is clearly inappropriate. Therefore, the memory controller sends a long ZQ calibration command to perform a long ZQ calibration, thus achieving a larger range of calibration.

[0102] In some embodiments, the method further includes: after the calibration result meets the requirements, feeding back a second identifier to a memory controller coupled to the memory to indicate that the calibration was successful; wherein the second identifier is used to increase the calibration period for the memory controller to send the short ZQ calibration command.

[0103] It should be noted that upon successful calibration, the memory provides a second identifier. This second identifier not only indicates the success of the calibration but also triggers the memory control to adjust the time interval for sending the short ZQ calibration command, typically by increasing this interval. Since the short ZQ calibration is performed using the maximum number of cycles configured, its calibration range is relatively large. Therefore, the difference between the interface impedance value obtained based on the calibration result and the target impedance value (the resistance value of the reference resistor) is relatively small, allowing for a longer time to meet the requirements of high-speed data transmission. Thus, the short ZQ calibration cycle can be increased, meaning the time interval between two adjacent short ZQ calibration commands is lengthened.

[0104] Here, the first and second identifiers are stored in a register. The register can be a general-purpose register.

[0105] In some embodiments, after performing long ZQ calibration on the interface impedance of the memory, the method further includes: continuing to perform short ZQ calibration on the interface impedance of the memory according to the calibration cycle.

[0106] To understand this invention, see [link / reference] Figure 15 and Figure 16 , Figure 15 A comparison diagram is shown between the prior ZQ calibration scheme provided in the embodiments of the present invention and the ZQ calibration scheme provided in the embodiments of the present invention; Figure 16 The diagram illustrates the implementation process of the ZQ calibration scheme provided in this embodiment of the invention.

[0107] exist Figure 15 In prior art, the maximum number of cycles used for short ZQ calibration is a default value, and the corresponding calibration range is usually relatively small. In the present invention, the maximum number of cycles used for short ZQ calibration is user-configurable and can be flexibly configured according to design requirements.

[0108] exist Figure 16 In this embodiment of the invention, the implementation process of the ZQ calibration scheme may include: configuring the maximum number of short ZQ calibration cycles through the Set Feature command of the ONFI protocol; the ZQ calibration control unit receives the short ZQ calibration command and obtains the configured maximum number of cycles, and then performs short ZQ calibration based on the short ZQ calibration command and the maximum number of cycles to finally obtain the calibration result.

[0109] Compared with prior art solutions, the ZQ calibration method provided in this invention allows for flexible configuration of the maximum number of calibration cycles for short ZQ calibration, providing a wider adjustment range and saving calibration time. See details below. Figure 17 When the target calibration result falls between the calibration range of long ZQ calibration and short ZQ calibration, long ZQ calibration is time-consuming, while short ZQ calibration in prior art has an insufficient calibration range, failing to obtain an accurate calibration result in one step. In this case, the ZQ calibration method provided in this embodiment of the invention can obtain an accurate calibration result in one step, eliminating the need for long ZQ calibration and saving time. Furthermore, with a reasonable maximum calibration cycle count, it can not only cope with drastic changes in the working environment but also correct errors that occur during long ZQ calibration.

[0110] Based on the same inventive concept, embodiments of the present invention also provide a memory, comprising: a memory array for storing data; and peripheral circuitry coupled to the memory array and used for controlling the memory array; wherein,

[0111] The peripheral circuit is configured to: acquire the maximum number of cycles configured for short ZQ calibration; the maximum number of cycles is used to indicate the calibration range of the short ZQ calibration; and, upon receiving a short ZQ calibration command, perform the short ZQ calibration on the interface impedance of the memory until the number of calibration cycles reaches the maximum number of cycles and / or the calibration result meets the requirements.

[0112] In some embodiments, the peripheral circuitry includes: a control logic unit and a ZQ calibration unit, wherein;

[0113] The control logic unit is configured to: obtain the maximum number of cycles configured for short ZQ calibration; and, upon receiving a short ZQ calibration command, control the ZQ calibration unit to perform short ZQ calibration on the interface impedance of the memory until the number of calibration cycles reaches the maximum number of cycles and / or the calibration result meets the requirements.

[0114] In some embodiments, when the memory supports the Open NAND Flash Interface (ONFI) protocol, the maximum number of cycles is set by the user in the memory via a memory controller coupled to the memory based on the Set Feature command in the ONFI protocol.

[0115] In some embodiments, the peripheral circuitry further includes a register configured to store a first identifier and / or a second identifier, wherein the first identifier is a flag fed back to a memory controller coupled to the memory to indicate calibration failure when the number of calibration cycles reaches the maximum number of cycles and the calibration result does not meet the requirements; and the second identifier is a flag fed back to a memory controller coupled to the memory to indicate calibration success after the calibration result meets the requirements.

[0116] In some embodiments, the memory is a dual data rate dynamic random access memory (DDR DRAM).

[0117] It should be noted that the technical solution described in the memory and the technical solution of the aforementioned ZQ calibration method belong to the same inventive concept and have the same technical features. The specific solution of the ZQ calibration method and the terms appearing in the technical solution of this invention have been described in detail above. Therefore, the terms appearing here can be understood according to the meanings described above, and will not be repeated here.

[0118] This invention also provides a storage system, including one or more of the aforementioned memories; and a memory controller coupled to the memories; the memory controller is configured to: send the short ZQ calibration command or the long ZQ calibration command to the memories.

[0119] In some embodiments, the storage system is a solid-state drive (SSD) or a memory card.

[0120] It should be noted that the storage system mentioned here includes the aforementioned memory, and the two have the same technical features. The structure of the memory and the terms appearing in the technical solution of this invention have been described in detail above. Therefore, the terms appearing here can be understood according to the meanings described above, and will not be repeated here.

[0121] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A ZQ calibration method, characterized by, The method is applied to a memory, and comprises: obtaining one of a plurality of maximum cycle numbers configured for short ZQ calibration; the maximum cycle number is used to indicate a calibration range of the short ZQ calibration; after receiving a short ZQ calibration command, performing the short ZQ calibration on an interface impedance of the memory until a cycle number of calibration reaches the maximum cycle number and / or a calibration result meets a requirement.

2. The method of claim 1, wherein, When the memory supports an open NAND flash interface (ONFI) protocol, the maximum cycle number is set in the memory by a memory controller coupled with the memory based on a SetFeature command in the ONFI protocol.

3. The method of claim 1, wherein, The obtaining one of the plurality of maximum cycle numbers configured for the short ZQ calibration comprises: determining a current working environment change degree; obtaining the maximum cycle number configured for the short ZQ calibration based on the current working environment change degree and a mapping relationship; wherein the working environment change degree is measured by a change in an environmental temperature and / or a change in an output voltage of the memory; and the mapping relationship is used to reflect a corresponding relationship between the working environment change degree and the maximum cycle number.

4. The method of claim 1, wherein, The method further comprises: when the cycle number of calibration reaches the maximum cycle number and the calibration result does not meet the requirement, feeding back, to a memory controller coupled with the memory, a first identifier used to indicate calibration failure.

5. The method of claim 4, wherein, The method further comprises: when a next calibration period is reached, receiving a long ZQ calibration command sent by the memory controller after receiving the first identifier; and performing long ZQ calibration on the interface impedance of the memory when the long ZQ calibration command is received; wherein the calibration period is a time interval between adjacent short ZQ calibration commands sent by the memory controller to the memory.

6. The method of claim 1, wherein, The method further comprises, after the calibration result meets the requirement, feeding back, to the memory controller coupled with the memory, a second identifier used to indicate calibration success; wherein the second identifier is used to make the memory controller increase a calibration period of sending the short ZQ calibration command.

7. The method of claim 5, wherein, After performing long ZQ calibration on the interface impedance of the memory, the method further comprises: continuing to perform the short ZQ calibration on the interface impedance of the memory according to the calibration period.

8. A memory, comprising: comprise: a storage array for storing data; and a peripheral circuit coupled with the storage array and used to control the storage array; wherein the peripheral circuit is configured to obtain one of a plurality of maximum cycle numbers configured for short ZQ calibration; the maximum cycle number is used to indicate a calibration range of the short ZQ calibration; and after receiving a short ZQ calibration command, performing the short ZQ calibration on an interface impedance of the memory until a cycle number of calibration reaches the maximum cycle number and / or a calibration result meets a requirement.

9. The memory of claim 8, wherein, the peripheral circuit comprises a control logic unit and a ZQ calibration unit, wherein The control logic unit is configured to: acquire a maximum number of cycles configured for short ZQ calibration; after receiving a short ZQ calibration command, control the ZQ calibration unit to perform the short ZQ calibration on the interface impedance of the memory until the number of cycles of calibration reaches the maximum number of cycles and / or the calibration result meets the requirement.

10. The memory of claim 9, wherein, When the memory supports an open NAND flash interface (ONFI) protocol, the maximum number of cycles is set in the memory by a memory controller coupled with the memory based on a Set Feature command in the ONFI protocol.

11. The memory of claim 9, wherein, The peripheral circuit further includes a register configured to save a first identifier and / or a second identifier, wherein the first identifier is an identifier for indicating a calibration failure fed back to the memory controller coupled with the memory when the number of cycles of calibration reaches the maximum number of cycles and the calibration result does not meet the requirement, and the second identifier is an identifier for indicating a successful calibration fed back to the memory controller coupled with the memory after the calibration result meets the requirement.

12. The memory of claim 8, wherein, The memory is a double data rate dynamic random access memory (DDR DRAM).

13. A storage system, characterized by Comprise: one or more memories according to any one of claims 8 to 12; and a memory controller coupled with the memory; The memory controller is configured to: send the short ZQ calibration command or the long ZQ calibration command to the memory.

14. The storage system of claim 13, wherein, The storage system is a solid state drive (SSD) or a memory card.

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