Multi-chip package interconnection structure, manufacturing method and electronic device

Abstract

The present invention relates to the technical field of chip packaging, and discloses a multi-chip packaging interconnection structure, a manufacturing method and an electronic device. Among them, the multi-chip packaging interconnection structure includes: a packaging substrate having internal interconnection lines; an assembly mounted on the packaging substrate and interconnected with the packaging substrate; the assembly includes a plurality of interposer boards and a plurality of wafers, and the plurality of interposer boards are arranged in sequence in a direction perpendicular to the main plane of the packaging substrate, and the plurality of wafers and the plurality of interposer boards are alternately arranged, and the plurality of wafers are interconnected through the plurality of interposer boards to form a plurality of packaging interconnection levels with interconnection interfaces, realizing a packaging interconnection structure that can integrate multiple wafers and has multiple packaging interconnection levels.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and further relates to a multi-chip packaging interconnection structure, a manufacturing method and an electronic device. Background Art

[0002] In recent years, due to factors such as the gradually decreasing space and speed of wafer manufacturing process miniaturization, and the significant impact of chip wafer yield and cost on process nodes and wafer size, it is necessary to consider optimizing the packaging structure and process combination during the process selection and design and development stages of chips to reduce the comprehensive cost of chips and achieve complete performance. Therefore, the integration degree of chip packaging has been continuously improved with the development of product requirements and the evolution of technology.

[0003] The development of packaging technology can be divided into multiple stages. The first stage is the development from wire bonding technology to flip-chip bonding technology, which can be said to belong to the category of two-dimensional packaging. The development from two-dimensional packaging to three-dimensional packaging can be divided into the second stage of POP (Package on Package, package stacking), and the third stage based on through-silicon via (TSV) technology that is currently being further researched and developed. Since the package can be stacked to improve the integration degree, the interconnection structure of the packaging microsystem has also decreased from the millimeter scale to the micron scale, and even to the sub-micron scale in different stages, and the wiring density and the interconnection interface also need to increase accordingly. Moreover, when stacking packages, it is necessary to consider wafers of different sizes and processes, as well as more complex packaging processing equipment and process plans to handle high-density interconnections at different levels.

[0004] In the current TSV-based stacked packaging structure, a TSV array is usually directly set on a silicon substrate, and at the same time, wiring is performed on the surface of the silicon substrate to form a TSV interposer. The TSV interposer, as a carrier connected to the packaging substrate, directly places other chips side by side or stacked on the carrier to achieve the interconnection between multiple chips. However, such stacked packaging often has the following deficiencies to varying degrees:

[0005] (1) The number of co-packaged wafers in the package is small, and the function types and interconnection interfaces are relatively single;

[0006] (2) The stacking gap space in the package is not reasonably utilized, and the heat dissipation path is insufficient;

[0007] (3) For packages with many interconnection interfaces, they mostly extend in a plane, and the utilization method of vertical space is relatively single;

[0008] (4) The process of burying the TSV interposer or other interposers in the packaging substrate is difficult and the yield is low;

[0009] (5) When the TSV adapter or other adapter board is connected to the packaging substrate, the interconnection density is difficult to increase, which does not meet the development needs of high bandwidth. Summary of the invention

[0010] In order to solve the above technical problems, the present invention provides a multi-chip packaging interconnection structure, including a plurality of adapter plates arranged in sequence in a direction perpendicular to the main plane of the packaging substrate, and a plurality of chips interconnected with the adapter plates, thereby realizing a packaging interconnection structure that can integrate multiple chips and has multiple packaging interconnection levels.

[0011] Specifically, the present invention provides a multi-chip package interconnection structure, comprising:

[0012] a package substrate having internal interconnection circuits;

[0013] An assembly body, mounted on the packaging substrate and interconnected with the packaging substrate;

[0014] The assembly includes multiple adapter plates and multiple chips. The multiple adapter plates are arranged in sequence in the vertical direction of the main plane of the packaging substrate. The multiple chips and the multiple adapter plates are arranged alternately. The multiple chips are interconnected through the multiple adapter plates to form multiple packaging interconnection levels with interconnection interfaces.

[0015] In some embodiments, a gap is provided between the transfer plate and the wafer, and the gap is filled with a curable gap filling glue and / or a resin compound and / or a thermal conductive glue.

[0016] In some embodiments, the adapter board includes a first adapter board and a second adapter board, the chip includes a first chip, a second chip, and a third chip, the first chip is installed between the first adapter board and the substrate, the second chip is installed between the first adapter board and the second adapter board, and the third chip is installed on the side of the second adapter board opposite to the packaging substrate.

[0017] In some embodiments, a plurality of the chips are mounted on the packaging substrate, and the plurality of the chips are distributed in a symmetrical array on the packaging substrate.

[0018] In some embodiments, a receiving structure is installed between the second adapter plate and the packaging substrate.

[0019] In some embodiments, the second adapter board is an organic carrier board having internal interconnection circuits, or the second adapter board is an organic medium board having a redistribution layer, or the second adapter board is a silicon process adapter board;

[0020] The first adapter board is a silicon process adapter board, or the first adapter board is an organic medium board with a redistribution layer.

[0021] According to another aspect of the present invention, there is further provided a method for manufacturing a multi-chip package interconnection structure, including the following steps:

[0022] Arrange a plurality of interposer boards in sequence in the vertical direction of the main plane of the package substrate, alternately arrange a plurality of wafers and a plurality of the interposer boards, and communicate with the interposer boards to form an assembly with a preset interconnection interface;

[0023] Mount the assembly on the main plane of the package substrate;

[0024] Mount the package body solder balls on the back of the package substrate.

[0025] In some embodiments, the interposer board includes a first interposer board and a second interposer board, the wafer includes a first wafer, a second wafer, and a third wafer, and the step of alternately arranging a plurality of wafers and a plurality of the interposer boards specifically includes the following steps:

[0026] Mount the first interposer board on the back of the first wafer and align it, and form a preset interconnection interface through microbumps;

[0027] Mount the second wafer in a flip-chip manner at a preset position on the bottom layer of the second interposer board;

[0028] Align the back of the second wafer with the first interposer board and form a preset interconnection interface through microbumps;

[0029] Mount the third wafer to a preset position on the top layer of the second interposer board.

[0030] In some embodiments, the step of mounting the assembly on the main plane of the package substrate specifically includes the following steps:

[0031] Mount the second interposer board on the main plane of the package substrate through a receiving structure;

[0032] Mount the first wafer on the main plane of the package substrate in a flip-chip manner.

[0033] According to another aspect of the present invention, there is further provided an electronic device, including:

[0034] The multi-chip package interconnection structure as described in any one of the above.

[0035] Based on the existing stacking technology, the present invention sets multiple interposer boards at different vertical spatial positions, and as much as possible adopts or is compatible with different manufacturing methods in the packaging process, accurately docks with multiple wafers with through-silicon vias and micro-bumps to form an interconnection interface, thereby achieving further high-density signal connections and more power supply paths in the stacked package space.

[0036] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0037] 1. The present invention sets multiple interposer boards in the vertical direction of the main plane of the packaging substrate, and alternately arranges multiple wafers and multiple interposer boards. Through physical structures such as interposer boards, through-silicon vias, and micro-bumps, multiple wafers are interconnected, forming multiple interconnected packaging levels between the wafers and the interposer boards. When the multiple wafers are wafers with different wafer processes, materials, and particle sizes, the computing capabilities of different types of wafers can be integrated to achieve a new type of stacked package with high-density heterogeneous integration.

[0038] 2. Compared with the traditional packaging process in which signals can only be sequentially transmitted from one wafer to another through the interconnection lines on the packaging substrate, the signal transmission path of the present invention can be from the wafer to the interposer board and then to the wafer on another plane level, or can be mutually transmitted by wafers on the same plane level through the interposer board, increasing the signal transmission path and achieving multi-level and high-bandwidth signal interconnection.

[0039] 3. Compared with the disadvantages of insufficient adjustment range of the spacing between the wafer and the packaging substrate and the interposer board and poor heat dissipation ability in the traditional POP stacked package, in the present invention, the wafer and the interposer board are connected by micro-bumps, and there is a reasonably matched spacing between them. By filling a high thermal conductivity adhesive between the interposer board and the wafer, the thermal conduction path in the vertical direction is enhanced, and the heat dissipation performance of the packaging structure is improved, solving the problems such as the unreasonable utilization of the gap space and insufficient thermal conduction path in the general stacked package. At the same time, the interposer board can use a silicon process interposer board with better thermal conductivity, which can also improve the heat dissipation performance of the packaging interconnection structure to a certain extent.

[0040] 4. The present invention stacks the wafers in the vertical direction and uses structures such as micro-bumps and interposer boards for interconnection, enabling the wafers to be stacked multiple times in the vertical direction. At the connection interface between the wafer and the interposer board, the preset vertical direction signal and power supply interconnection in the packaging interconnection structure and the high-density interconnection of signals between adjacent regions edge to edge in the array arrangement of the multiple wafers can be completed, solving the problem of relatively single utilization mode of the vertical space in the traditional packaging or general stacked package.

[0041] 5. The present invention connects the chip through an adapter plate, and connects the chip to the packaging substrate through bumps, thereby avoiding the problems of burying the silicon process adapter plate in the packaging substrate, which is difficult and has a low yield, and difficulty in improving the interconnection density when the silicon process adapter plate is connected to the packaging substrate.

[0042] 6. The present invention arranges a plurality of adapter plates in the vertical direction of the main plane of the packaging substrate, and arranges a plurality of chips connected to the adapter plates alternately with the adapter plates, so that when the packaging interconnection structure is powered, the current can pass through the packaging substrate in multiple vertical directions such as the receiving structure and the vertical power supply areas of the adapter plates and chips, reach the chips and the adapter plates, and be conducted upward layer by layer, and the conduction paths on the power distribution network are greatly reduced; the power supply path is shortened, thereby reducing energy loss and heat dissipation, and improving the power supply performance and service life of the packaging interconnection structure.

[0043] 7. The present invention applies the above-mentioned packaging interconnection structure to electronic devices. By connecting chips with different functions on the packaging substrate and the adapter board, an electronic device with multiple comprehensive functions such as storage computing or sensing processing is realized, which can match the overall demand of different application electronic devices for integrated circuit devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The preferred implementation modes will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present invention.

[0045] Figure 1 It is a schematic diagram of the longitudinal structure of an embodiment of the present invention;

[0046] Figure 2 is a top view of the first wafer layer structure in a preferred embodiment of the present invention;

[0047] Figure 3 It is a flow chart of the method for manufacturing the packaging structure of the present invention;

[0048] Figure 4 It is a schematic diagram of a longitudinal section structure of a specific embodiment of the electronic device of the present invention;

[0049] Figure 5 It is a schematic diagram of the longitudinal structure of a specific embodiment of the electronic device of the present invention.

[0050] Description of Figure Numbers:

[0051] Package substrate 1, package body solder ball 2, first chip layer 3, first chip 31, signal and power supply interconnection area 310, high-density interconnection area 311, first adapter board 4, high-density interconnection wiring 401, second chip layer 5, second chip 51, second adapter board 6, third chip 7, receiving structure 8. Detailed implementation manners

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will describe the specific implementation manners of the present invention with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other implementation manners can also be obtained.

[0053] To make the drawings concise, only the parts and structural features related to the invention are schematically shown in each drawing, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, components with the same structure or function are only schematically shown for one of them, or only one of them is marked. In this document, "one" not only means "only this one", but also means "more than one" situation.

[0054] It should also be further understood that the term "and / or" used in the specification and claims of this application refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0055] In this document, it should be noted that unless otherwise clearly specified and defined, the terms "mount", "connect", and "couple" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] In addition, in the description of this application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0057] In one embodiment, referring to the attached Figure 1 , a multi-chip package interconnection structure provided by the present invention is described, including: a package substrate 1 and an assembly body. The assembly body is mounted on the package substrate 1 and is interconnected with the package substrate 1; the assembly body includes a plurality of interposer boards and a plurality of wafers. The plurality of interposer boards are arranged in sequence in the direction perpendicular to the main plane of the package substrate 1, and the plurality of wafers and the plurality of interposer boards are alternately arranged. The plurality of wafers are interconnected through the plurality of interposer boards to form a plurality of package interconnection levels.

[0058] In this packaged interconnection structure, micro-bumps or metal solder pads are provided on the wafer. The interposer plays a role in connecting and supporting the wafer. The interposer is generally a silicon process interposer, or an organic carrier board with internal interconnection lines, or an organic dielectric board with a redistribution layer. When the wafer contacts the interposer, the micro-bumps or metal solder pads are connected to the corresponding interfaces formed by the metal interconnection lines or through-silicon vias on the interposer, forming an interconnected path to achieve the interconnection effect.

[0059] In one embodiment, based on the above embodiment, there is a suitable gap between the interposer and the wafer, and the gap is filled with a curable high thermal conductivity adhesive. The heat generated during the use of this packaged interconnection structure can be dissipated through the enhanced heat conduction path of the high thermal conductivity adhesive, avoiding overheating of the chip product and other situations, improving the heat dissipation performance of the packaging structure, and solving problems such as unreasonable voids and low thermal conductivity in traditional packages.

[0060] In one embodiment, based on the above embodiment, solder balls 2 of the package are installed on the package substrate 1 as welding materials to meet electrical interconnection and mechanical connection, and can be used as a circuit connection path to facilitate connection with other devices.

[0061] In a specific embodiment, referring to the attached Figure 1 , the interposer includes a first interposer 4 and a second interposer 6, and the wafer includes a first wafer 31, a second wafer 51, and a third wafer 7. The first wafer 31 is installed between the first interposer 4 and the substrate, the second wafer 51 is installed between the first interposer 4 and the second interposer 6, and the third wafer 7 is installed on the side of the second interposer 6 that is not opposite to the package substrate 1. The wafer layer directly interconnected with the package substrate 1 is the first wafer layer 3, and the wafer layer with an interconnection interface at the bottom of the second interposer 6 is the second wafer layer 5.

[0062] Among them, the first interposer 4 is generally a silicon process interposer, or an organic dielectric board with a redistribution layer; the second interposer 6 is generally an organic carrier board with internal interconnection lines, or an organic dielectric board with a redistribution layer, or a silicon process interposer, but it does not exclude that the first interposer 4 and the second interposer 6 are other forms of interposers. Since the wafers are all made of silicon material and silicon has good thermal conductivity, when the used interposer is a silicon process interposer, the overall packaging structure has good thermal conductivity.

[0063] Referring to the attached Figure 2, the chip in the first chip layer 3 can be a whole chip, or multiple chips of the same type or different types. When the chips between the first adapter board 4 and the packaging substrate 1 are multiple chips of different types, the packaging structure has different computing functions and can realize heterogeneous interconnection; if there are multiple chips, they are generally distributed in a symmetrical array in the plane layout, but it does not rule out that the above-mentioned multiple chips are arranged in other ways on the packaging substrate 1. There is a signal and power supply interconnection area 310 in the vertical direction of the chip in the first chip layer 3, and different chips are interconnected through the high-density interconnection area 311 on the first adapter board 4, and the high-density interconnection area 311 has a high-density interconnection wiring 401.

[0064] The wafer in the second wafer layer 5 can be a whole wafer, or multiple wafers of the same type or different types. When the wafer in the first wafer layer 3 and the wafer in the second wafer layer 5 are both wafers with through silicon vias, metal welding pads or micro bumps can be formed on the back of the above-mentioned wafers, which can contact and bond with the top layer and the bottom layer of the first adapter plate 4 in the vertical direction of the structure to form interconnection interfaces respectively.

[0065] Among them, another chip can be used for packaging on the topmost transfer board layer to interconnect the package structure with other package structures, thereby realizing a multi-package structure and a high-density heterogeneous interconnection structure. A chip with an interconnection interface directly on the top layer of the upper transfer board can also be used to make it a complete and independent package structure.

[0066] The upper adapter plate is connected to the packaging substrate 1 through a supporting structure 8, which can be a metal ball or column, which can not only support the upper metal plate, but also connect the upper adapter plate and the packaging substrate 1 to increase the interconnection packaging level.

[0067] In this packaging interconnection structure, the signal can be transmitted through the packaging substrate 1 to the third chip 7, then to the first adapter board 4, and then transmitted upward in sequence. It can also be transmitted to the first adapter board 4 through other chips arranged on the packaging substrate 1, or directly transmitted to the second adapter board 6 through the metal balls or columns that serve as the receiving body, with multiple signal transmission paths.

[0068] Preferably, there is a suitable gap between the connection structure between the second adapter board 6 and the packaging substrate 1 and the first adapter board 4, which can be filled with curable thermal conductive adhesive. After curing, the thermal conductive adhesive has a certain protective effect on the chip or the adapter board, overcoming the problems of the traditional POP packaging structure due to process problems, the inability to fill high thermal conductive adhesive between the chip and the adapter board, resulting in insufficient heat dissipation performance, easy heating of the packaging structure, and short service life.

[0069] According to another aspect of the present invention, Figure 3, the present invention further provides a method for manufacturing a multi-chip package interconnection structure, including the following steps:

[0070] Arrange a plurality of interposer boards in sequence in a direction perpendicular to the main plane of the package substrate 1, alternately set a plurality of wafers and a plurality of interposer boards, and interconnect them with the interposer boards to form an assembly with a preset interconnection interface;

[0071] Mount the assembly on the package substrate 1;

[0072] Mount the package body solder balls 2 on the back of the package substrate 1.

[0073] In a preferred embodiment, the interposer board includes a first interposer board 4 and a second interposer board 6, and the wafers include a first wafer 31, a second wafer 51, and a third wafer 7. The specific steps of alternately setting a plurality of wafers and a plurality of interposer boards include the following steps:

[0074] Mount the first interposer board 4 on the back of the first wafer 31 and align it to form a preset interconnection interface;

[0075] Mount the second wafer 51 at a preset position on the bottom layer of the second interposer board 6 by means of flip-chip bonding;

[0076] Align the back of the second wafer 51 with the first interposer board 4 and form a preset interconnection interface through micro-bumps;

[0077] Mount the third wafer 7 at a preset position on the top layer of the second interposer board 6.

[0078] In a preferred embodiment, the specific steps of mounting the assembly on the package substrate 1 include the following steps:

[0079] Mount the second interposer board 6 on the package substrate 1 through a receiving structure 8;

[0080] Mount the first wafer 31 on the package substrate 1 by means of flip-chip bonding.

[0081] For the above manufacturing method, two specific embodiments are provided below for illustration.

[0082] In a specific embodiment, the manufacturing method of this multi-chip package interconnection structure mainly includes the following steps:

[0083] Step P1S1: Fabricate and prepare the package substrate 1 and the second interposer board 6, as well as the first wafer 31 and the second wafer 51 with through-silicon vias;

[0084] Step P1S2: Fabricate and prepare the first interposer board 4;

[0085] Step P1S3: Place and connect the first wafer 31 to the corresponding position on the top layer of the packaging substrate 1 in an inverted bonding manner;

[0086] Step P1S4: Place the first interposer 4 on the back of the first wafer 31 and align it, and form a correct interconnect interface through micro-bumps or the like;

[0087] Step P1S5: Place and connect the second wafer 51 to the corresponding position on the bottom layer of the second interposer 6 in an inverted bonding manner;

[0088] Step P1S6: Connect the combined structure with the second interposer 6 and the second wafer 51 having an interconnect interface to the packaging substrate 1 through the receiving structure 8. At the same time, the back of the second wafer 51 is also aligned with the first interposer 4 and a correct interconnect interface is formed through micro-bumps or the like;

[0089] Step P1S7: Install the package solder balls 2 and the third wafer 7 onto the combined structure formed in P1S6 in a certain manner to form the typical structure as shown in the attached Figure 1 as shown.

[0090] Among them, in step P1S1, multiple wafers can be used instead of the first wafer 31. The above multiple wafers can be multiple wafers of the same type or different types.

[0091] In another specific embodiment, the manufacturing method of this multi-wafer package interconnect structure mainly includes the following steps:

[0092] Step P2S1: Fabricate and prepare the packaging substrate 1 and the second interposer 6, as well as the first wafer 31 and the second wafer 51 with through-silicon vias;

[0093] Step P2S2: Fabricate and prepare the first interposer 4;

[0094] Step P2S3: In a certain manner such as using wafer particles and / or wafers, with the first interposer 4 as the base carrier or in combination with other auxiliary carriers, place the first wafer 31 and the second wafer 51 onto the bottom layer and the top layer of the first interposer 4 through structures such as back micro-bumps in an aligned manner to form a combined structure with a correct interconnect interface of the first wafer 31 / the first interposer 4 / the second wafer 51;

[0095] Step P2S4: Bond the combined structure formed in step P2S3 to the packaging substrate 1;

[0096] Step P2S5: Connect the first interposer 4 to the packaging substrate 1 through the receiving structure 8. At the same time, the bottom layer of the second interposer 6 is aligned with the front bumps of the second wafer 51 in the combined structure formed in step P2S3 and a second interposer 6 / second wafer 51 interconnect interface is formed;

[0097] Step P2S6: In a certain manner, the encapsulation body solder balls 2 and the third wafer 7 are mounted on the combined structure formed in P2S5 to form a typical structure as shown in the attached Figure 1 description.

[0098] The present invention does not exclude, other than the above two specific embodiments, all manufacturing methods for implementing the typical structure as shown in the attached Figure 1 description by other reasonable processes.

[0099] According to another aspect of the present invention, there is further provided an electronic device with multiple computing functions, including an electronic device main body and the above multi-wafer package interconnection structure. By changing the types of wafers on the package interconnection structure, the comprehensive requirements of integrated circuit devices for different application electronic devices can be met.

[0100] In a specific embodiment, referring to the attached Figure 4 description, the second wafer 51 can be a system processor wafer mainly applied to artificial intelligence logic computing, the first wafer 31 or multiple wafers in the first wafer layer 3 can be high-bandwidth memory wafers, and the third wafer 7 can be a general flash memory chip package, thus realizing the integration of intelligent computing and multiple types of storage capabilities in one package device, which is applicable to mobile terminals, Internet of Things edge computing power devices, etc.

[0101] In a specific embodiment, referring to the attached Figure 5 description, the second wafer 51 can be a wafer mainly applied to video encoding and decoding and intelligent computing, multiple wafers in the first wafer layer 3 can be graphics processor wafers and high-bandwidth memory wafers, and the third wafer 7 can be an image sensor, thus integrating the technical capabilities of intelligent perception and high-computing-power graphics computing in one package device, which is applicable to machine vision, security monitoring, imaging terminals such as drones, action cameras, etc.

[0102] In summary, the present invention provides a multi-wafer package interconnection structure. By sequentially arranging an interposer and multiple wafers connected to the interposer on the main plane of the vertical package substrate 1 and making them communicate with each other, a package interconnection structure that can integrate multiple wafers and has multiple package interconnection levels is realized.

[0103] It should be noted that the above embodiments can be freely combined according to needs. The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. Multi-chip package interconnection structure, characterized in that, include: a package substrate having internal interconnection circuits; An assembly body, mounted on the packaging substrate and interconnected with the packaging substrate; The assembly includes a plurality of adapter plates and a plurality of chips, wherein the plurality of adapter plates are sequentially arranged in a vertical direction of the main plane of the packaging substrate, the plurality of chips and the plurality of adapter plates are alternately arranged, and the plurality of chips are interconnected through the plurality of adapter plates to form a plurality of packaging interconnection levels with interconnection interfaces; The adapter plate includes a first adapter plate and a second adapter plate, the wafer includes a first wafer, a second wafer, and a third wafer, the first wafer is mounted between the first adapter plate and the substrate, the second wafer is mounted between the first adapter plate and the second adapter plate, and the third wafer is mounted on a side of the second adapter plate opposite to the packaging substrate; A receiving structure is installed between the second adapter board and the packaging substrate, and a signal is transmitted from the packaging substrate to the second adapter board through the receiving structure.

2. The multi-chip package interconnect structure according to claim 1, wherein A gap is provided between the adapter plate and the wafer, and the gap is filled with curable gap filling glue and / or resin compound and / or thermal conductive glue.

3. The multi-chip package interconnect structure according to claim 1, wherein, A plurality of the chips are mounted on the packaging substrate, and the plurality of the chips are distributed in a symmetrical array on the packaging substrate.

4. The multi-chip package interconnection structure according to claim 1, wherein The second adapter board is an organic carrier board with internal interconnection circuits, or the second adapter board is an organic medium board with a redistribution layer, or the second adapter board is a silicon process adapter board; The first adapter board is a silicon process adapter board, or the first adapter board is an organic medium board with a redistribution layer.

5. A method for manufacturing an interconnection structure of a multi-chip package, characterized in that, The following steps are involved: Arrange a plurality of adapter plates in sequence in a direction perpendicular to the main plane of the packaging substrate, alternately arrange a plurality of wafers and the plurality of adapter plates, and connect the wafers to each other to form an assembly having a preset interconnection interface; Mounting the assembly on the main plane of the packaging substrate; Mounting the package body solder balls on the back of the package substrate; The adapter plate includes a first adapter plate and a second adapter plate, the wafer includes a first wafer, a second wafer, and a third wafer, and the alternate arrangement of the plurality of wafers and the plurality of adapter plates specifically includes the following steps: Mounting the first adapter plate on the back of the first wafer and aligning the first adapter plate to form a preset interconnection interface through micro-bumps; The second chip is mounted at a preset position on the bottom layer of the second adapter board by flip-chip method; Aligning the back of the second wafer with the first adapter plate and forming a preset interconnection interface through micro bumps; Mounting the third chip to a preset position on the top layer of the second adapter plate; The step of mounting the assembly on the main plane of the packaging substrate specifically comprises the following steps: Mounting the second adapter board on the main plane of the packaging substrate via a receiving structure, so that the signal is transmitted from the packaging substrate to the second adapter board via the receiving structure; The first chip is mounted on the main plane of the packaging substrate in a flip-chip manner.

6. An electronic device, characterized in that, include: A multi-chip package interconnection structure as described in any one of claims 1-4.

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