Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the forming method comprises: providing an initial substrate, the initial substrate comprising a first region and a second region, the initial substrate comprising a first substrate, a first insulating layer on the first substrate, and a second substrate on the first insulating layer; removing the second substrate of the second region; after removing the second substrate of the second region, forming a second insulating layer on the first insulating layer of the second region; forming a plurality of passive devices on the second insulating layer; and after forming the passive devices, forming a plurality of active devices in the first region. By forming the active devices and the passive devices on the same wafer, the process of package integration is avoided, the production cost is effectively reduced, and the thickness of the finally formed semiconductor structure is reduced, which is beneficial to the miniaturization of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As VLSI (Very Large Scale Integration) continues to evolve towards being "faster, smaller, lighter, and cheaper," chip area is constantly decreasing with the advancement of manufacturing processes.

[0003] Currently, IPD (Integrated Devices) technology is commonly used to integrate large-area passive devices onto a single chip, and then packaging is used to integrate the passive devices with active devices. This approach has promoted the miniaturization of chips to some extent.

[0004] However, existing technologies for integrating passive and active devices through packaging still present many challenges. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce the thickness of the semiconductor structure and reduce production costs.

[0006] To address the above problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a first region and a second region, the substrate including a first base, a first insulating layer located on the first base, a second insulating layer located on the first insulating layer, and a plurality of active devices, the active devices being located in the first region and the second insulating layer being located in the second region; and a plurality of passive devices located on the second insulating layer.

[0007] Optionally, it may further include: a third insulating layer on the passive device; a fourth insulating layer on the active device, the top surface of the fourth insulating layer being flush with the top surface of the third insulating layer; and a fifth insulating layer on the third and fourth insulating layers.

[0008] Optionally, it may also include a grating layer located within the third insulating layer.

[0009] Optionally, an electrical interconnection structure is located within the fourth and fifth insulating layers, and the electrical interconnection structure is connected to the active device.

[0010] Optionally, a passivation layer is located on the fifth insulating layer; a first light inlet is located within the passivation layer, the first light inlet being located on the active device; and a second light inlet is located within the passivation layer, the fifth insulating layer, and the third insulating layer, the second light inlet being located on the passive device.

[0011] Optionally, the material of the passive device includes silicon nitride.

[0012] Optionally, the active device may be made of silicon.

[0013] Optionally, the active device includes one or more of a modulator or a detector.

[0014] Optionally, the passive device includes: waveguide components.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing an initial substrate, the initial substrate including a first region and a second region, the initial substrate including a first substrate, a first insulating layer located on the first substrate and a second substrate located on the first insulating layer; removing the second substrate of the second region; after removing the second substrate of the second region, forming a second insulating layer on the first insulating layer of the second region; forming a plurality of passive devices on the second insulating layer; and after forming the passive devices, forming a plurality of active devices in the first region.

[0016] Optionally, the method for forming the passive device includes: forming a passive device material layer on the second insulating layer; performing a number of first patterning processes on the passive device material layer to form a number of initial passive devices; and performing an annealing process on the initial passive devices to form the passive device.

[0017] Optionally, the material of the passive device material layer includes silicon nitride.

[0018] Optionally, the material of the second substrate includes silicon.

[0019] Optionally, the process parameters for the annealing treatment include: an annealing temperature greater than 1000℃.

[0020] Optionally, the active device includes one or more of a modulator or a detector.

[0021] Optionally, the method for forming the active device includes performing several ion implantation processes on the first region.

[0022] Optionally, before performing the ion implantation process, the method for forming the active device further includes forming a plurality of device structures on the first region.

[0023] Optionally, the device structure includes one or both of a gate structure and an epitaxial layer located within a second substrate.

[0024] Optionally, while forming a plurality of the initial passive devices, the method further includes: forming a plurality of stop layers, the stop layers being located on the device structure.

[0025] Optionally, the ion implantation method includes: forming a third insulating layer on the passive device and the stop layer; removing a portion of the third insulating layer and the stop layer, forming a processing opening in the third insulating layer, the processing opening being located on the device structure; and performing the ion implantation process on the device structure to form the active device.

[0026] Optionally, the third insulating layer has a grating layer.

[0027] Optionally, after forming the active device, the method further includes forming an electrical interconnect structure on the active device.

[0028] Optionally, after forming the active device, the method further includes: forming a fourth insulating layer on the active device, the top surface of the fourth insulating layer being flush with the top surface of the third insulating layer; forming a fifth insulating layer on the third insulating layer and the fourth insulating layer, the electrical interconnect structure being located within the fourth insulating layer and the fifth insulating layer.

[0029] Optionally, after forming the active device, the method further includes: forming a passivation layer on the fifth insulating layer; forming a first light inlet in the passivation layer, the first light inlet being located on the active device; and forming a second light inlet in the passivation layer, the fifth insulating layer, and the third insulating layer, the second light inlet being located on the passive device.

[0030] Optionally, the method for forming the second light inlet includes: removing a portion of the passivation layer, the fifth insulating layer, and the third insulating layer to form the second light inlet.

[0031] Optionally, the method for forming the second light inlet further includes: removing the grating layer.

[0032] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0033] In the structure of the technical solution of the present invention, the substrate includes a plurality of active devices and a plurality of passive devices located on the second insulating layer. By forming the active devices and the passive devices on the same wafer, the packaging integration process is avoided, effectively reducing production costs. At the same time, the thickness of the final semiconductor structure is reduced, which is beneficial to the miniaturization of the device.

[0034] Furthermore, the passive device is made of silicon nitride; the active device is made of silicon. This reduces the light propagation loss of both the active and passive devices.

[0035] In the method for forming the technical solution of the present invention, the substrate includes a plurality of active devices, and a plurality of passive devices are formed on the second insulating layer. By forming the active devices and the passive devices on the same wafer, the packaging integration process is avoided, effectively reducing production costs. At the same time, the thickness of the final semiconductor structure is reduced, which is beneficial for device miniaturization.

[0036] Furthermore, the passive device material layer is made of silicon nitride; the active device material layer is made of silicon. This reduces the light propagation loss of the final active and passive devices.

[0037] Furthermore, the third insulating layer contains a grating layer. Depending on the application requirements of the device structure, if the grating layer is required, it will be retained when the second light inlet is subsequently formed; if the grating layer is not required, it will be used as an etch stop layer when the second light inlet is subsequently formed. Attached Figure Description

[0038] Figures 1 to 10 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0039] As described in the background section, existing technologies for integrating passive and active devices through packaging still present numerous problems. These will be explained in detail below.

[0040] Most existing silicon photonics chips use silicon-on-insulator (SOI) wafers, allowing passive and active devices to be fabricated on the silicon (Si) layer using traditional CMOS processes. However, silicon has relatively high propagation loss (~1-2 dB / cm), making it unsuitable for passive devices. Silicon nitride (SiN) has very low optical propagation loss (<0.2 dB / cm), making it an excellent material for passive optical waveguide devices, but active devices cannot be fabricated on SiN. Integrating the characteristics of SOI and SiN onto a single chip remains a significant challenge in the industry.

[0041] Currently, the industry mainly uses SOI for active devices and SiN for passive devices, then integrates the two chips together through packaging. However, integrating two chips through packaging technology is not only complex in process but also expensive. In addition, the thickness of the chip formed after packaging increases, which is not conducive to device miniaturization.

[0042] Based on this, the present invention provides a semiconductor structure and a method for forming the same, wherein a plurality of active devices are formed on the substrate, and a plurality of passive devices are formed on the second insulating layer. By forming the active devices and the passive devices on the same wafer, the use of packaging integration processes is avoided, effectively reducing production costs, while also reducing the thickness of the final semiconductor structure, which is beneficial for device miniaturization.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 1 to 10 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0045] Please refer to Figure 1 An initial substrate is provided, the initial substrate including a first region I and a second region II, the initial substrate including a first substrate 100, a first insulating layer 101 located on the first substrate 100 and a second substrate 102 located on the first insulating layer 101.

[0046] In this embodiment, the initial substrate is silicon-on-insulator (SOI).

[0047] In this embodiment, the first substrate 100 and the second substrate 102 are made of silicon.

[0048] In this embodiment, the first insulating layer 101 is made of silicon oxide.

[0049] After providing the initial substrate, the process further includes: removing the second substrate 102 of the second region II; after removing the second substrate 102 of the second region II, forming a second insulating layer on the first insulating layer 101 of the second region II; forming a plurality of passive devices on the second insulating layer; and after forming the passive devices, forming a plurality of active devices in the first region I. For details of the formation process, please refer to [link to documentation]. Figures 2 to 7 .

[0050] Please refer to Figure 2 Several device structures 103 are formed on the first region I.

[0051] In this embodiment, after forming a plurality of the device structures 103 on the first region I, the initial substrate is formed into a substrate.

[0052] In this embodiment, the method for forming the plurality of device structures 103 includes: performing a plurality of second patterning processes on the second substrate 102 on the first region I to form the device structure 103.

[0053] In this embodiment, while performing several second patterning processes on the second substrate 102 of the first region I, the second substrate 102 of the second region II is removed.

[0054] In this embodiment, the device structure 103 is a passive device.

[0055] In this embodiment, the device structure 103 includes one or both of a gate structure and an epitaxial layer located within a second substrate.

[0056] Please refer to Figure 3 After the device structure 103 is formed, a second insulating layer 104 is formed on the first insulating layer 101 of the second region II.

[0057] In this embodiment, the method for forming the second insulating layer 104 includes: forming an initial insulating layer (not shown) on the first insulating layer 101 of the second region II and on the device structure 103, the initial insulating layer covering the device structure 103; and planarizing the initial second insulating layer to form the second insulating layer 104.

[0058] In this embodiment, the material of the second insulating layer 104 is silicon oxide.

[0059] In this embodiment, the planarization process for the initial second insulating layer is performed using a chemical mechanical polishing process.

[0060] Please refer to Figure 4 After forming the second insulating layer 104, a passive device material layer is formed on the second insulating layer 104; the passive device material layer is subjected to several first patterning processes to form several initial passive devices; the initial passive devices are subjected to annealing to form the passive device 105.

[0061] In this embodiment, the passive device material layer is made of silicon nitride. Silicon nitride is an excellent material for passive optical waveguide devices due to its very low optical propagation loss (<0.2 dB / cm).

[0062] In this embodiment, annealing can reduce hydrogen ions in passive devices, thereby reducing light propagation loss.

[0063] In this embodiment, the process parameters for the annealing treatment include: an annealing temperature greater than 1000°C.

[0064] In this embodiment, while forming a plurality of the initial passive devices, it also includes forming a plurality of sacrificial layers 106, the sacrificial layers 106 being located on the device structure 103.

[0065] In this embodiment, the passive device 105 is a waveguide component.

[0066] Please refer to Figure 5 After the passive device 105 is formed, a third insulating layer 107 is formed on the passive device 105 and the sacrificial layer 106.

[0067] In this embodiment, the material of the third insulating layer 107 is silicon oxide.

[0068] In this embodiment, the passive device 105 is covered by the third insulating layer 107 first, so as to avoid affecting the passive device 105 during the subsequent ion implantation process of the device structure 103, thereby damaging the function of the passive device 105.

[0069] In this embodiment, the third insulating layer 107 includes a grating layer 108. The grating layer 108 can be selectively removed or retained in subsequent processes depending on the functional requirements of the device. If the grating layer 108 is removed, it can also serve as an etching stop layer for the subsequent formation of the second light inlet.

[0070] In this embodiment, the grating layer 108 is made of polycrystalline silicon.

[0071] Please refer to Figure 6 After the third insulating layer 107 is formed, a portion of the third insulating layer 107 and the sacrificial layer 106 are removed, and a processing opening 109 is formed in the third insulating layer 107. The processing opening 109 is located on the device structure 103.

[0072] In this embodiment, the processing opening 109 facilitates subsequent ion implantation of the device structure 103.

[0073] In this embodiment, the sacrificial layer 106 serves as an etching stop layer for etching the third insulating layer 107 during the formation of the processing opening 109.

[0074] Please refer to Figure 7 After forming the processing opening 109, the first region I is subjected to several ion implantation processes.

[0075] In this embodiment, specifically, the ion implantation process is performed on several device structures 103 on the first region I, so that the device structures 103 form active devices 110.

[0076] In this embodiment, the active device 110 includes a modulator and a detector; in other embodiments, the active device may also be one of a modulator and a detector.

[0077] In this embodiment, since annealing is required during the formation of the passive device 105, to prevent the annealing process from heating and diffusing the ions implanted in the active device 110, thereby reducing the function of the active device 110, the active device 110 is formed after the passive device 105. This process makes it possible for the active device 110 and the passive device 105 to be formed simultaneously on the same wafer.

[0078] In this embodiment, by forming the active device 110 and the passive device 105 on the same wafer, the packaging integration process is avoided, which effectively reduces the production cost. At the same time, the thickness of the final semiconductor structure is reduced, which is beneficial to the miniaturization of the device.

[0079] Please refer to Figure 8 After the active device 110 is formed, a fourth insulating layer 111 is formed on the active device 110, the top surface of the fourth insulating layer 111 being flush with the top surface of the third insulating layer 107; a fifth insulating layer 112 is formed on the third insulating layer 107 and the fourth insulating layer 111.

[0080] In this embodiment, the method for forming the fourth insulating layer 111 includes: forming an initial fourth insulating layer (not shown) on the active device 110 and the third insulating layer 107; planarizing the initial fourth insulating layer until the top surface of the third insulating layer 107 is exposed, thereby forming the fourth insulating layer 111.

[0081] In this embodiment, the fourth insulating layer 111 is made of silicon oxide.

[0082] In this embodiment, the planarization process for the fourth insulating layer 111 is performed using a chemical mechanical polishing process.

[0083] In this embodiment, the fifth insulating layer 112 is made of silicon oxide.

[0084] Please refer to Figure 9 After the fifth insulating layer 112 is formed, an electrical interconnection structure 113 is formed in the fourth insulating layer 111 and the fifth insulating layer 112, and the electrical interconnection structure 113 is connected to the active device 110.

[0085] In this embodiment, the electrical interconnection structure 113 includes a conductive layer and a conductive plug (not shown).

[0086] Please refer to Figure 10After forming the electrical interconnect structure 113, a passivation layer 114 is formed on the fifth insulating layer 112; a first light inlet 115 is formed in the passivation layer 114, and the first light inlet 115 is located on the active device 110; a second light inlet 116 is formed in the passivation layer 114, the fifth insulating layer 112, and the third insulating layer 107, and the second light inlet 116 is located on the passive device 105.

[0087] In this embodiment, the method for forming the second light inlet 116 includes: removing a portion of the passivation layer 114, the fifth insulating layer 112, and the third insulating layer 107 to form the second light inlet 116.

[0088] In other embodiments, the method for forming the second light inlet further includes: removing the grating layer, as well as a portion of the passivation layer, the fifth insulating layer, and the third insulating layer, to form the second light inlet.

[0089] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 10 The device includes: a substrate, the substrate including a first region I and a second region II, the substrate including a first base 100, a first insulating layer 101 located on the first base 100, a second insulating layer 104 located on the first insulating layer 101, and a plurality of active devices 110, the active devices 110 being located in the first region I and the second insulating layer 104 being located in the second region II; and a plurality of passive devices 105 located on the second insulating layer 104.

[0090] In this embodiment, the substrate includes a plurality of active devices 110 and a plurality of passive devices 105 located on the second insulating layer 104. By forming the active devices 110 and the passive devices 105 on the same wafer, the packaging integration process is avoided, effectively reducing production costs. At the same time, the thickness of the final semiconductor structure is reduced, which is beneficial for device miniaturization.

[0091] In this embodiment, it further includes: a third insulating layer 107 located on the passive device 105; a fourth insulating layer 111 located on the active device 110, the top surface of the fourth insulating layer 111 being flush with the top surface of the third insulating layer 107; and a fifth insulating layer 112 located on the third insulating layer 107 and the fourth insulating layer 111.

[0092] In this embodiment, it further includes a grating layer 108 located within the third insulating layer 107; in other embodiments, the third insulating layer may not contain the grating layer.

[0093] In this embodiment, an electrical interconnection structure 113 is located within the fourth insulating layer 111 and the fifth insulating layer 112, and the electrical interconnection structure 113 is connected to the active device 110.

[0094] In this embodiment, a passivation layer 114 is located on the fifth insulating layer 112; a first light inlet 115 is located within the passivation layer 114, and the first light inlet 115 is located on the active device 110; a second light inlet 116 is located within the passivation layer 114, the fifth insulating layer 112, and the third insulating layer 107, and the second light inlet 116 is located on the passive device 105.

[0095] In this embodiment, the passive device 105 is made of silicon nitride, and the active device 110 is made of silicon. This reduces the light propagation loss of both the active device 110 and the passive device 105.

[0096] In this embodiment, the active device 110 includes a modulator and a detector; in other embodiments, the active device may also be one of a modulator and a detector.

[0097] In this embodiment, the passive device 105 is a waveguide component.

[0098] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An initial substrate is provided, the initial substrate including a first region and a second region, the initial substrate including a first substrate, a first insulating layer located on the first substrate, and a second substrate located on the first insulating layer; Remove the second substrate in the second region; After removing the second substrate in the second region, a second insulating layer is formed on the first insulating layer in the second region; Several passive devices are formed on the second insulating layer; After forming passive devices, a plurality of active devices are formed in the first region. The passive devices are made of silicon nitride, and the active devices are made of silicon. The method for forming the active device includes: forming a plurality of device structures on the first region before forming the passive device, wherein the device structures are passive devices; After the passive device is formed, the device structure is subjected to ion implantation to form the active device, so as to avoid the annealing process during the formation of the passive device from heating and diffusing the implanted ions in the active device, thereby reducing the performance of the active device.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the passive device includes: forming a passive device material layer on the second insulating layer; performing a number of first patterning processes on the passive device material layer to form a number of initial passive devices; and performing an annealing process on the initial passive devices to form the passive device.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the passive device material layer includes silicon nitride.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second substrate includes silicon.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process parameters for the annealing treatment include: annealing temperature greater than 1000℃.

6. The method for forming a semiconductor structure as described in claim 2, characterized in that, The active device includes one or more of a modulator or a detector.

7. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method for forming the active device includes performing several ion implantation processes on the first region.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Prior to the ion implantation process, the method for forming the active device further includes forming a plurality of device structures on the first region.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The device structure includes one or both of a gate structure and an epitaxial layer located within a second substrate.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, In addition to forming a plurality of the initial passive devices, the method further includes forming a plurality of stop layers located on the device structure.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The ion implantation method includes: forming a third insulating layer on the passive device and the stop layer; removing a portion of the third insulating layer and the stop layer, forming a processing opening in the third insulating layer, the processing opening being located on the device structure; and performing the ion implantation process on the device structure to form the active device.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The third insulating layer contains a grating layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the active device, the method further includes forming an electrical interconnect structure on the active device.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the active device, the method further includes: forming a fourth insulating layer on the active device, the top surface of the fourth insulating layer being flush with the top surface of the third insulating layer; forming a fifth insulating layer on the third insulating layer and the fourth insulating layer, the electrical interconnection structure being located within the fourth insulating layer and the fifth insulating layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, After forming the active device, the method further includes: forming a passivation layer on the fifth insulating layer; forming a first light inlet in the passivation layer, the first light inlet being located on the active device; and forming a second light inlet in the passivation layer, the fifth insulating layer, and the third insulating layer, the second light inlet being located on the passive device.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the second light inlet includes: removing a portion of the passivation layer, the fifth insulating layer, and the third insulating layer to form the second light inlet.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the second light inlet further includes removing the grating layer.

18. A semiconductor structure formed by any one of claims 1 to 17, characterized in that, include: The substrate includes a first region and a second region. The substrate includes a first base, a first insulating layer located on the first base, a second insulating layer located on the first insulating layer, and a plurality of active devices. The active devices are located in the first region, and the second insulating layer is located in the second region. Several passive devices located on the second insulating layer.

19. The semiconductor structure as described in claim 18, characterized in that, Also includes: The third insulating layer located on the passive device; A fourth insulating layer is located on the active device, the top surface of the fourth insulating layer being flush with the top surface of the third insulating layer; a fifth insulating layer is located on the third insulating layer and the fourth insulating layer.

20. The semiconductor structure as described in claim 19, characterized in that, Also includes: The grating layer is located within the third insulating layer.

21. The semiconductor structure as described in claim 19, characterized in that, An electrical interconnection structure located within the fourth and fifth insulating layers, the electrical interconnection structure being connected to the active device.

22. The semiconductor structure as described in claim 19, characterized in that, A passivation layer located on the fifth insulating layer; a first light inlet located within the passivation layer, the first light inlet being located on the active device; and a second light inlet located within the passivation layer, the fifth insulating layer, and the third insulating layer, the second light inlet being located on the passive device.

23. The semiconductor structure as described in claim 18, characterized in that, The passive device is made of silicon nitride.

24. The semiconductor structure as described in claim 18, characterized in that, The active device is made of silicon.

25. The semiconductor structure as described in claim 18, characterized in that, The active device includes one or more of a modulator or a detector.

26. The semiconductor structure as described in claim 18, characterized in that, The passive devices include waveguide components.

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