Cross-coupled charge pump circuit

Abstract

The present invention relates to the field of analog integrated circuit design, and proposes a cross-coupled charge pump circuit structure to achieve the omission of the clock boost circuit, and the voltage difference at each end of each transistor does not exceed the power supply voltage, so as to solve the delay problem caused by the clock boost and the transistor aging caused by the high voltage; at the same time, the MOS tube connected by the diode is not used in the whole structure to avoid the threshold loss. To this end, the technical solution adopted by the present invention is that the cross-coupled charge pump circuit includes twelve transistors M1-M12, five capacitors C1-C5, and four inverters as input clock buffers, the source electrodes of transistors M1 and M2 are connected to the positive electrode of the power supply, and the drain electrodes are respectively connected to the gate of the other party and are respectively connected to the positive plates of the two capacitors C1 and C2 to form a cross-coupled structure. The present invention is mainly used in the design and manufacturing of analog integrated circuit charge pumps.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, and in particular to a cross-coupled charge pump circuit. Background Art

[0002] The charge pump circuit is a DC-DC (direct current-to-direct current) conversion circuit that can generate a voltage higher or lower than the power supply. The switch structure in the charge pump circuit is its core. The charge pump circuit that uses a diode-connected MOS device as a switch device has a low output voltage due to threshold loss. The conventional charge pump circuit that uses a clock-controlled MOS tube as a switch device must boost the clock. The level-converting boost circuit will bring a large delay, causing reverse leakage of the switching transistor, reducing the output efficiency; in addition, the transistor in the boost circuit and the switch transistor of the charge pump have a high source-drain and gate-to-substrate voltage difference, which can easily cause transistor aging and affect the circuit performance and life. Summary of the invention

[0003] In order to overcome the deficiencies of the prior art, the present invention aims to propose a cross-coupled charge pump circuit structure, which does not require a clock boost circuit, and the voltage difference between each end of each transistor does not exceed the power supply voltage, thereby solving the delay problem caused by clock boosting and transistor aging caused by high voltage; at the same time, no diode-connected MOS tubes are used in the entire structure to avoid threshold loss. To this end, the technical solution adopted by the present invention is that the cross-coupled charge pump circuit includes twelve transistors M1-M12, five capacitors C1-C5, and four inverters as input clock buffers, the source electrodes of transistors M1 and M2 are connected to the positive electrode of the power supply, and the drain electrodes are respectively connected to the gate of each other and are respectively connected to the positive plates of the two capacitors C1 and C2, forming a cross-coupled structure; the source electrodes of transistors M3 and M4 are connected to the positive electrode of the power supply, and the drain electrodes are respectively connected to the gate of each other and are respectively connected to the positive plates of the two capacitors C3 and C4, also forming a The four groups of input clocks are connected to the negative plates of four capacitors after passing through the inverters; the positive plate of C1 is connected to the output through transistors M5 and M7, and the positive plate of C2 is also connected to the output through transistors M6 and M8; the gate of M6 is connected to the positive plate of C1, the gate of M5 is connected to the positive plate of C2, and the gates of M7 and M8 are connected to the positive plate of C3; M9 and M10 form a floating well structure and are connected to the substrates of M5 and M7, and M11 and M12 also form a floating well structure and are connected to the substrates of M6 and M8, and C5 is an output filter capacitor.

[0004] The voltage level of the substrate end of NMOS tubes M1~M4 is VDD higher than the drain end, forming a forward-biased PN junction, charging capacitors C1~C4, and starting the circuit quickly. After the clock is established, when Clk1 is 0 and Clk2 is 1, the voltage of node X is 2VDD, and the output is used to charge capacitor C5. At the same time, M2 is turned on, M6 is turned off, and the power supply charges C2 to make its voltage reach VDD; when Clk1 is 1 and Clk2 is 0, the voltage of node Y is 2VDD, and the output is used to charge capacitor C5. At the same time, M1 is turned on, M5 is turned off, and the power supply charges C1 to make its voltage reach VDD. After several cycles, the output voltage reaches 2VDD.

[0005] Since the clock has a certain rise time and fall time, in order to avoid reverse leakage caused by M1, M2, M5, and M6 being turned on at the same time, clocks Clk1 and Clk2 use non-overlapping clocks and introduce Clk3 and Clk4. During the time of 2t to 3t, the Y node level is ensured to rise and stabilize. After M1 is completely closed, the node X level drops. This operation will cause M5 and M6 to be turned on at the same time for a period of time. Therefore, M3, M4, C3, and C4 are introduced to form another cross-coupling structure. During the time of t to 4t, the Z node is ensured to be at a high level, and M7 and M8 are turned off to avoid reverse leakage from the output node to the X and Y nodes.

[0006] The characteristics and beneficial effects of the present invention are:

[0007] 1. This structure avoids the delay problem caused by the clock boost circuit and avoids the reverse leakage of the switching transistor through the four-phase clock.

[0008] 2. This structure does not use diode-connected MOS devices, thus avoiding the problem of output voltage reduction caused by threshold loss.

[0009] 3. During operation, the voltage difference at each end of all transistors in this structure does not exceed the power supply voltage VDD, and all high-voltage areas are isolated from other structures by deep N-wells, solving the transistor aging problem caused by large voltage differences. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Cross-coupled charge pump circuit structure;

[0011] Figure 2 Cross-coupled charge pump control timing diagram. DETAILED DESCRIPTION

[0012] The charge pump includes twelve transistors M1-M12, five capacitors C1-C5, and four inverters as input clock buffers. The sources of transistors M1 and M2 are connected to the positive pole of the power supply, and the drains are connected to the gates of each other and the positive plates of the two capacitors C1 and C2, respectively, to form a cross-coupled structure. M3, M4, C3, and C4 are connected in the same way: the sources of transistors M3 and M4 are connected to the positive pole of the power supply, and the drains are connected to the gates of each other and the positive plates of the two capacitors C3 and C4, respectively, to form a cross-coupled structure. Cross-coupling structure; four groups of input clocks are connected to the negative plates of four capacitors after passing through inverters; the positive plate of C1 is connected to the output through transistors M5 and M7, and the positive plate of C2 is also connected to the output through transistors M6 and M8; the gate of M6 is connected to the positive plate of C1, the gate of M5 is connected to the positive plate of C2, and the gates of M7 and M8 are connected to the positive plate of C3; M9 and M10 form a floating well structure and are connected to the substrates of M5 and M7, M11 and M12 also form a floating well structure and are connected to the substrates of M6 and M8, and C5 is an output filter capacitor. Figure 1 The circuit structure of the present invention is given, wherein the dotted line box represents a deep N well, Figure 2 The timing of the four-phase clock that controls the circuit is given. When the circuit starts, the clock is not established, and the substrate terminal level (VDD) of the NMOS tubes M1~M4 is higher than the drain terminal (0), forming a forward-biased PN junction to charge the capacitors C1~C4, so that the circuit starts quickly. After the clock is established, when Clk1 is 0 and Clk2 is 1, the voltage of node X is 2VDD, and the backward output charges the capacitor C5. At the same time, M2 is turned on, M6 is turned off, and the power supply charges C2 to make its voltage reach VDD; when Clk1 is 1 and Clk2 is 0, the voltage of node Y is 2VDD, and the backward output charges the capacitor C5. At the same time, M1 is turned on, M5 is turned off, and the power supply charges C1 to make its voltage reach VDD. After several cycles, the output voltage reaches 2VDD.

[0013] Since the clock has a certain rise time and fall time, in order to avoid reverse leakage caused by M1, M2, M5, and M6 being turned on at the same time, clocks Clk1 and Clk2 use non-overlapping clocks and introduce Clk3 and Clk4. During the time of 2t to 3t, the Y node level is ensured to rise and stabilize, and the node X level will drop only after M1 is completely turned off. This operation will cause M5 and M6 to be turned on at the same time for a period of time, so M3, M4, C3, and C4 are introduced to form another cross-coupling structure, ensuring that the Z node is at a high level during the time of t to 4t, and M7 and M8 are turned off to avoid reverse leakage from the output node to the X and Y nodes.

[0014] Since the source of M1 and M2 is connected to VDD, they are isolated by a deep N-well, and the same is true for M3 and M4. The source-drain voltage of M5 and M7 changes alternately, so M9 and M10 are introduced to form a floating well to ensure that the substrate is connected to the highest level, and the same is true for M6 and M8.

[0015] Figure 1 All NMOS (including those in inverters) have W=8um, L=400nm, and all PMOS (including those in inverters) have W=12um, L=400nm. Capacitors C1 and C2 use MIM capacitors (metal-insulator-metal capacitors), with a capacitance of 12pf. C3 and C4 also use MIM capacitors with a capacitance of 2pf. C5 uses a combination of MIM capacitors and MOS capacitors to reduce the layout area, with a capacitance of 150pf. Figure 2 The clocks in the 4 groups are obtained by performing digital logic operations on the nodes in a delay chain, with a period of T = 40ns and a non-overlapping time of t = 0.5ns.

[0016] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A cross-coupled charge pump circuit, characterized in that it includes Twelve transistors M1-M12, five capacitors C1-C5, and four inverters as input clock buffers. The sources of transistors M1 and M2 are connected to the positive pole of the power supply, and the drains are connected to each other's gate and the positive plates of capacitors C1 and C2, respectively, forming a cross-coupling structure; the sources of transistors M3 and M4 are connected to the positive pole of the power supply, and the drains are connected to each other's gate and the positive plates of capacitors C3 and C4, respectively, also forming a cross-coupling structure; the four groups of input clocks are connected to the negative plates of four capacitors after passing through the inverters; C1 The positive plate is connected to the source of transistor M5, the drain of M5 is connected to the source of M7, the drain of M7 is connected to the output, the positive plate of C2 is connected to the source of transistor M6, the drain of M6 is connected to the source of M8, the drain of M8 is connected to the output, the positive plates of C1 and C2 are connected to nodes X and Y respectively; the gate of M6 is connected to the positive plate of C1, the gate of M5 is connected to the positive plate of C2, and the gates of M7 and M8 are connected to the positive plate of C3; the sources of M9 and M10 are connected and connected to the substrates of M5 and M7, the drain of M9 and the gate of M10 are connected to the node X, and the gate of M9 and the drain of M10 are connected to the output; the sources of M11 and M12 are connected and connected to the substrates of M6 and M8, the drain of M11 and the gate of M12 are connected to the node Y, and the gate of M11 and the drain of M12 are connected to the output; the output filter capacitor C5 is connected between the power supply and the output.

2. The cross-coupled charge pump circuit according to claim 1, wherein: The voltage level of the substrate end of the NMOS tubes M1-M4 is VDD, which is higher than the drain end, forming a forward-biased PN junction to charge the capacitors C1-C4, so that the circuit starts quickly. After the clock is established, when Clk1 is 0 and Clk2 is 1, the voltage of node X is 2VDD, and the backward output is to charge the capacitor C5. At the same time, M2 is turned on, M6 is turned off, and the power supply charges C2 to make its voltage reach VDD; when Clk1 is 1 and Clk2 is 0, the voltage of node Y is 2VDD, and the backward output is to charge the capacitor C5. At the same time, M1 is turned on, M5 is turned off, and the power supply charges C1 to make its voltage reach VDD. After several cycles, the output voltage reaches 2VDD.

3. The cross-coupled charge pump circuit according to claim 1, wherein: Since the clock has a certain rise time and fall time, in order to avoid reverse leakage caused by M1, M2, M5, and M6 being turned on at the same time, clocks Clk1 and Clk2 use non-overlapping clocks, and introduce Clk3 and Clk4; within 2t-3t, ensure that the Y node level rises and stabilizes, and the node X level drops only after M1 is completely turned off. This operation will cause M5 and M6 to be turned on at the same time for a period of time. Therefore, M3, M4, C3, and C4 are introduced to form another cross-coupling structure. Within t-4t, ensure that the Z node, that is, the gate of M8, is at a high level, and M7 and M8 are turned off to avoid reverse leakage from the output node to the X and Y nodes.

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