An improved folded cascode operational amplifier

Abstract

The application discloses an improved folding cascode operational amplifier, which comprises a folding cascode operational amplifier, an adaptive bias circuit and a local positive feedback circuit. In the application, the adaptive bias circuit is used to generate a dynamic current for a large input signal on a differential input pair without being limited by a tail current source, so that the dynamic current and gain are improved; the local positive feedback circuit is used to convert the current generated by an input transistor and the current in the adaptive bias circuit into a voltage to drive an idle folding current source transistor, so that the transconductance of an input stage is improved; in addition, the operational amplifier allows a large dynamic current without being limited by a static current, and the slew rate is significantly improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an improved folded cascode operational amplifier. Background Technology

[0002] With the continued growth of the mobile and portable electronic device market and the development of CMOS technology, operational transconductance amplifiers (OTAs), as a fundamental building block in analog integrated circuits, have gradually become key design modules for many systems in reducing power consumption and improving performance. More and more products need to operate under low supply voltage and low power consumption conditions, and maintaining high performance under these conditions is one of the goals of OTA design today. One of the most commonly used structures for the first stage of single-stage and multi-stage amplifiers is the folded cascode operational amplifier, which has high gain and input / output swing. However, it is not well-suited to the current requirement of achieving the highest performance with the lowest power consumption, mainly because it drives the maximum current with a current source without providing any transconductance to the OTA and limiting the slew rate.

[0003] Currently, the common approach to improve op-amp performance is to replace the current source with an active current mirror. However, this results in a complex structure with low-frequency zero-pole pairs, limiting its application at high frequencies. Alternatively, adding an additional DC current mirror can improve gain and slew rate, but this leads to the replication of large dynamic currents within the additional branches, reducing power efficiency. Therefore, there is an urgent need for a high-gain and high-slew rate folded cascode operational amplifier. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an improved folded cascode operational amplifier.

[0005] The present invention adopts the following technical solution:

[0006] An improved folded cascode operational amplifier (CCA) is disclosed for amplifying a signal to be processed. The CCA includes a folded cascode operational amplifier, an adaptive bias circuit, and a local positive feedback circuit. The signal to be processed is input to the input transistor of the folded cascode operational amplifier, and the output of the folded cascode operational amplifier outputs the amplified signal corresponding to the signal to be processed. The adaptive bias circuit is connected to the input transistor of the folded cascode operational amplifier, and the local positive feedback circuit is connected to both the folded cascode operational amplifier and the adaptive bias circuit. The adaptive bias circuit provides an adaptive bias current to the folded cascode operational amplifier. Based on the current of the input transistor of the folded cascode operational amplifier and the current of the adaptive bias circuit, the local positive feedback circuit drives the folded current source transistor in the folded cascode operational amplifier, thereby improving the gain and slew rate of the folded cascode operational amplifier. The signal to be processed is amplified by the folded cascode operational amplifier in combination with the adaptive bias circuit and the local positive feedback circuit, and the output of the folded cascode operational amplifier outputs the amplified signal corresponding to the signal to be processed.

[0007] In a preferred embodiment of the present invention, the signal to be processed includes a differential signal. The folded cascode operational amplifier includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor. The first and second MOS transistors serve as the input transistors of the folded cascode operational amplifier. The sources and gates of the first and second MOS transistors are connected to an adaptive bias circuit. The third and fourth MOS transistors serve as the folded current source transistors of the folded cascode operational amplifier. The gates of the third and fourth MOS transistors are connected to a local positive feedback circuit. The gate of the first MOS transistor receives one end of the signal to be processed, and its drain is connected to the drain of the third MOS transistor. The gate of the second MOS transistor receives the other end of the signal to be processed, and its drain is connected to the drain of the fourth MOS transistor. The sources of the third and fourth MOS transistors are connected to GND, and the gate of the fifth MOS transistor is connected to a preset bias voltage V. bn1 The drain of the fifth MOSFET is connected to the drain of the seventh MOSFET, the source of the fifth MOSFET is connected to the drain of the first MOSFET, and the gate of the sixth MOSFET is connected to a preset bias voltage V. bn1 The drain of the sixth MOSFET is connected to the drain of the eighth MOSFET. This connection point serves as the output terminal of the folded cascode operational amplifier, outputting the amplified signal corresponding to the signal to be processed. The source of the sixth MOSFET is connected to the drain of the second MOSFET, and the gate of the seventh MOSFET is connected to a preset bias voltage V. bp1 The source of the seventh MOSFET is connected to the drain of the ninth MOSFET, and the gate of the eighth MOSFET is connected to a preset bias voltage V. bp1The source of the eighth MOSFET is connected to the drain of the tenth MOSFET. The gate of the ninth MOSFET is connected to the gate of the tenth MOSFET and the drain of the fifth MOSFET. The sources of the ninth and tenth MOSFETs are connected to the power supply VDD. The substrates of the first, second, seventh, eighth, ninth, and tenth MOSFETs are connected to the power supply VDD. The substrates of the third, fourth, fifth, and sixth MOSFETs are grounded to GND.

[0008] In a preferred embodiment of the present invention, the adaptive bias circuit includes an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, and a sixteenth MOSFET. The gate of the eleventh MOSFET is connected to the gate of the first MOSFET, the drain of the eleventh MOSFET is connected to the drain of the fifteenth MOSFET, and the connection point is connected to the gate of the thirteenth MOSFET. The source of the eleventh MOSFET is connected to the drain of the thirteenth MOSFET, and the connection point is connected to the source of the second MOSFET. The gate of the twelfth MOSFET is connected to the gate of the second MOSFET, the drain of the twelfth MOSFET is connected to the drain of the sixteenth MOSFET, and the connection point is connected to the gate of the fourteenth MOSFET. The source of the twelfth MOSFET is connected to the drain of the fourteenth MOSFET, and the connection point is connected to the source of the first MOSFET. The sources of the thirteenth and fourteenth MOSFETs are connected to the power supply VDD, and the gates of the fifteenth and sixteenth MOSFETs are connected to a preset bias voltage V. bias1 The source terminals of the fifteenth and sixteenth MOSFETs are grounded to GND. The substrates of the eleventh, twelfth, thirteenth, and fourteenth MOSFETs are connected to the power supply VDD, and the substrates of the fifteenth and sixteenth MOSFETs are grounded to GND.

[0009] In a preferred embodiment of the present invention, the local positive feedback circuit includes a seventeenth MOSFET, an eighteenth MOSFET, a nineteenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, and a twenty-second MOSFET. The gate of the seventeenth MOSFET is connected to the gate of the thirteenth MOSFET. The drain of the seventeenth MOSFET is connected to the drain of the twenty-first MOSFET, the source of the nineteenth MOSFET, and the gate of the third MOSFET. The source of the seventeenth MOSFET is connected to the power supply VDD. The gate of the eighteenth MOSFET is connected to the gate of the fourteenth MOSFET. The drain of the eighteenth MOSFET is connected to the drain of the twenty-second MOSFET, the source of the twentieth MOSFET, and the gate of the fourth MOSFET. The source of the eighteenth MOSFET is connected to the power supply VDD. The gate of the nineteenth MOSFET is connected to a preset bias voltage V. bias2 The drain of the nineteenth MOSFET is connected to the gate of the twenty-first MOSFET, and the gate of the twentieth MOSFET is connected to a preset bias voltage V. bias2The drain of the twentieth MOSFET is connected to the drain of the nineteenth MOSFET, the gate of the twenty-first MOSFET is connected to the gate of the twenty-second MOSFET, the sources of the twenty-first and twenty-second MOSFETs are grounded to GND, the substrates of the seventeenth and eighteenth MOSFETs are connected to the power supply VDD, and the substrates of the nineteenth, twentieth, twenty-first, and twenty-second MOSFETs are grounded to GND.

[0010] The beneficial effects of this invention are as follows: This invention provides an improved folded cascode operational amplifier. It utilizes an adaptive bias circuit to generate a dynamic current on the differential input pair that is not limited by the tail current source for large input signals, thereby improving dynamic current and gain. It also utilizes a local positive feedback circuit to convert the current from the adaptive bias circuit and the current generated by the input transistors into voltage through a transconductance circuit to drive idle folded transistors, thus improving the input stage transconductance. Furthermore, the improved folded cascode operational amplifier provided by this invention allows for large dynamic currents without being limited by static current, resulting in improved slew rate. Attached Figure Description

[0011] Figure 1 This is a block diagram of the improved folded cascode operational amplifier of the present invention;

[0012] Figure 2 This is a circuit schematic diagram of the improved folded cascode operational amplifier in an embodiment of the present invention;

[0013] Figure 3 This is the gain curve of the improved folded cascode operational amplifier in an embodiment of the present invention;

[0014] Figure 4 The phase curve of the improved folded cascode operational amplifier in this embodiment of the invention is shown.

[0015] Figure 5 This is the slew rate curve of the improved folded cascode operational amplifier in an embodiment of the present invention. Detailed Implementation

[0016] The present invention will be further described below with reference to the accompanying drawings. The following embodiments will enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way.

[0017] This invention proposes an improved folded cascode operational amplifier: an adaptive bias circuit replaces the tail current source, which allows for setting a low quiescent current while generating dynamic current for large input signals on the differential input pair; a local positive feedback circuit drives idle folded transistors by reusing the current from the adaptive bias circuit and the current generated by the input transistors, thereby improving the gain and slew rate of the op-amp.

[0018] like Figure 1 As shown, this invention designs an improved folded cascode operational amplifier for amplifying signals to be processed. It includes a folded cascode operational amplifier, an adaptive bias circuit, and a local positive feedback circuit. The signal to be processed is connected to the input transistor of the folded cascode operational amplifier, and the output terminal of the folded cascode operational amplifier outputs the amplified signal corresponding to the signal to be processed. The adaptive bias circuit is connected to the input transistor of the folded cascode operational amplifier, and the local positive feedback circuit is connected to both the folded cascode operational amplifier and the adaptive bias circuit. The adaptive bias circuit provides an adaptive bias current to the folded cascode operational amplifier. Based on the current of the input transistor of the folded cascode operational amplifier and the current of the adaptive bias circuit, the local positive feedback circuit drives the folded current source transistor in the folded cascode operational amplifier, improving the gain and slew rate of the folded cascode operational amplifier. The signal to be processed is amplified by the folded cascode operational amplifier in combination with the adaptive bias circuit and the local positive feedback circuit, and the output terminal of the folded cascode operational amplifier outputs the amplified signal corresponding to the signal to be processed.

[0019] In this embodiment, the folded cascode operational amplifier receives an input signal and an output signal. After processing the input signal, it outputs the amplified signal corresponding to the differential signal. Figure 2 As shown, the signal to be processed includes a differential signal V. in+ and V in- The folded cascode operational amplifier includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, and a tenth MOSFET M10. The first MOSFET M1 and the second MOSFET M2 serve as the input transistors of the folded cascode operational amplifier. The sources and gates of the first MOSFET M1 and the second MOSFET M2 are connected to an adaptive bias circuit. The third MOSFET M3 and the fourth MOSFET M4 serve as the folded current source transistors of the folded cascode operational amplifier. The gates of the third MOSFET M3 and the fourth MOSFET M4 are connected to a local positive feedback circuit. The gate of the first MOSFET M1 receives the signal processing terminal V. in+ The drain of the first MOSFET M1 is connected to the drain of the third MOSFET M3, and the gate of the second MOSFET M2 receives the other end V of the signal being processed. in- The drain of the second MOSFET M2 is connected to the drain of the fourth MOSFET M4. The source of the third MOSFET M3 and the source of the fourth MOSFET M4 are connected to GND. The gate of the fifth MOSFET M5 is connected to a preset bias voltage V. bn1The drain of the fifth MOSFET M5 is connected to the drain of the seventh MOSFET M7, the source of the fifth MOSFET M5 is connected to the drain of the first MOSFET M1, and the gate of the sixth MOSFET M6 is connected to a preset bias voltage V. bn1 The drain of the sixth MOSFET M6 is connected to the drain of the eighth MOSFET M8. This connection point serves as the output terminal of the folded common-source cascode operational amplifier, outputting the amplified signal corresponding to the signal to be processed. The source of the sixth MOSFET M6 is connected to the drain of the second MOSFET M2, and the gate of the seventh MOSFET M7 is connected to a preset bias voltage V. bp1 The source of the seventh MOSFET M7 is connected to the drain of the ninth MOSFET M9, and the gate of the eighth MOSFET M8 is connected to a preset bias voltage V. bp1 The source of the eighth MOSFET M8 is connected to the drain of the tenth MOSFET M10. The gate of the ninth MOSFET M9 is connected to the gate of the tenth MOSFET M10 and the drain of the fifth MOSFET M5. The sources of the ninth MOSFET M9 and the tenth MOSFET M10 are connected to the power supply VDD. The substrates of the first MOSFET M1, the second MOSFET M2, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 are connected to the power supply VDD. The substrates of the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are grounded to GND. The preset bias voltage V... bp1 Select 1.5V, the preset bias voltage V bn1 The voltage is 1.8V, and the power supply VDD is 3.3V.

[0020] In this embodiment, the adaptive bias circuit is implemented using two flip-flop voltage followers (FVFs). Eleventh MOSFET M11, thirteenth MOSFET M13, and fifteenth MOSFET M15 form one FVF, and twelfth MOSFET M12, fourteenth MOSFET M14, and sixteenth MOSFET M16 form the other FVF. These two FVFs are cross-coupled to the differential input pair. By using the adaptive bias circuit instead of a conventional tail current source, a low quiescent current can be set, while simultaneously generating dynamic current for large input signals on the differential input pair, unaffected by the tail current source. This is connected to the folded cascode operational amplifier, providing adaptive bias current to the amplifier.

[0021] In this embodiment, the adaptive bias circuit includes an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, and a sixteenth MOSFET M16. The gate of the eleventh MOSFET M11 is connected to the gate of the first MOSFET M1, the drain of the eleventh MOSFET M11 is connected to the drain of the fifteenth MOSFET M15, and this connection point is connected to the gate of the thirteenth MOSFET M13. The source of the eleventh MOSFET M11 is connected to the drain of the thirteenth MOSFET M13, and this connection node is connected to the gate of the thirteenth MOSFET M16. The source of MOSFET M2 is connected to the gate of MOSFET M12. The drain of MOSFET M12 is connected to the drain of MOSFET M16, and this connection point is connected to the gate of MOSFET M14. The source of MOSFET M12 is connected to the drain of MOSFET M14, and this connection point is connected to the source of MOSFET M1. The sources of MOSFETs M13 and M14 are connected to the power supply VDD. The gates of MOSFETs M15 and M16 are connected to a preset bias voltage V. bias1 The sources of the fifteenth MOSFET M15 and the sixteenth MOSFET M16 are grounded to GND. The substrates of the eleventh MOSFET M11, twelfth MOSFET M12, thirteenth MOSFET M13, and fourteenth MOSFET M14 are connected to the power supply VDD. The substrates of the fifteenth MOSFET M15 and the sixteenth MOSFET M16 are grounded to GND. The preset bias voltage V bias1 Select 1.6V.

[0022] In this embodiment, the local positive feedback circuit includes a seventeenth MOSFET M17, an eighteenth MOSFET M18, a nineteenth MOSFET M19, a twentieth MOSFET M20, a twenty-first MOSFET M21, and a twenty-second MOSFET M22. The gate of the seventeenth MOSFET M17 is connected to the gate of the thirteenth MOSFET M13. The drain of the seventeenth MOSFET M17 is connected to the drain of the twenty-first MOSFET M21, the source of the nineteenth MOSFET M19, and the gate of the third MOSFET M3. The source of the seventeenth MOSFET M17 is connected to the power supply VDD. The gate of the eighteenth MOSFET M18 is connected to the gate of the fourteenth MOSFET M14. The drain of the eighteenth MOSFET M18 is connected to the drain of the twenty-second MOSFET M22, the source of the twentieth MOSFET M20, and the gate of the fourth MOSFET M4. The source of the eighteenth MOSFET M18 is connected to the power supply VDD. The gate of the nineteenth MOSFET M19 is connected to a preset bias voltage V. bias2 The drain of the nineteenth MOSFET M19 is connected to the gate of the twenty-first MOSFET M21, and the gate of the twentieth MOSFET M20 is connected to a preset bias voltage V. bias2The drain of the twentieth MOSFET M20 is connected to the drain of the nineteenth MOSFET M19, and the gate of the twenty-first MOSFET M21 is connected to the gate of the twenty-second MOSFET M22. The sources of the twenty-first MOSFET M21 and the twenty-second MOSFET M22 are grounded to GND. The substrates of the seventeenth MOSFET M17 and the eighteenth MOSFET M18 are connected to the power supply VDD, and the substrates of the nineteenth MOSFET M19, the twentieth MOSFET M20, the twenty-first MOSFET M21, and the twenty-second MOSFET M22 are grounded to GND. The preset bias voltage V bias2 A voltage of 1.6V is selected. Both the adaptive bias circuit and the folded cascode operational amplifier are connected simultaneously. The current generated by the folded cascode operational amplifier and the current in the adaptive bias circuit are converted into voltage to drive the folded current source transistor of the folded cascode operational amplifier.

[0023] Based on the connection of a local positive feedback circuit and an adaptive bias circuit, the seventeenth MOSFET M17 and the thirteenth MOSFET M13 form a 1:2 current mirror, the twenty-first MOSFET M21 and the third MOSFET M3 form a 1:3 current mirror, and symmetrically, the eighteenth MOSFET M18 and the fourteenth MOSFET M14 also form a 1:2 current mirror, and the twenty-second MOSFET M22 and the fourth MOSFET also form a 1:3 current mirror. By reusing the current generated by the input transistors M1 and M2 to drive the idle folded current source transistors M3 and M4, the gain and slew rate of the operational amplifier are improved.

[0024] Based on such Figure 2 The circuit diagram shown in this embodiment illustrates the improved folded cascode operational amplifier. The operation of this embodiment is as follows: Under static conditions, FVF biases the eleventh MOSFET M11 with a DC current of 0.5I through the fifteenth MOSFET M15, and biases the twelfth MOSFET M12 with a DC current of 0.5I through the sixteenth MOSFET M16. Furthermore, under static conditions, the gate-source voltages of the first MOSFET M1, the second MOSFET M2, the eleventh MOSFET M11, and the twelfth MOSFET M12 are equal, i.e., V... SG1 =V SG2 =V SG11 =V SG12Therefore, the current flowing through the first MOSFET M1 and the second MOSFET M2 is 0.5I. The thirteenth MOSFET M13 and the fourteenth MOSFET M14 are biased with a DC current I. The seventeenth MOSFET M17 and the thirteenth MOSFET M13 form a 1:2 current mirror, and the eighteenth MOSFET M18 and the fourteenth MOSFET M14 also form a 1:2 current mirror. Therefore, the current flowing through the seventeenth MOSFET M17 and the eighteenth MOSFET M18 is 0.5I. There is no voltage drop across the nineteenth MOSFET M19 and the twentieth MOSFET M20. The twenty-first MOSFET M21 and the third MOSFET M3 form a 1:3 current mirror, and the twenty-second MOSFET M22 and the fourth MOSFET M4 also form a 1:3 current mirror. Therefore, the current flowing through the third MOSFET M3 and the fourth MOSFET M4 is 1.5I. The current flowing through the output circuit is I, that is, the output circuit current of the folded common-source common-gate operational amplifier is I.

[0025] Under dynamic conditions, when V id =V in+ -V in- When the current I1 flowing through the first MOSFET M1 is greater than 0, the current I2 flowing through the second MOSFET M2 is less than the current I2 flowing through the second MOSFET M2. Through the local positive feedback circuit, the current I1 flowing through the eighteenth MOSFET M18 is reduced to 0. 18 Less than the current I flowing through the seventeenth MOSFET M17 17 Therefore, r is generated on the nineteenth MOSFET M19. o19 The voltage drop of (I2-I1) / 2 is added to the gate voltage of the third MOSFET M3, thereby increasing the output current and slew rate; when V id =V in+ -V in- When I<0, the current I1 flowing through the first MOSFET M1 is greater than the current I2 flowing through the second MOSFET M2. Through the local positive feedback circuit, the current I1 flowing through the eighteenth MOSFET M18 is increased. 18 Greater than the current I flowing through the seventeenth MOSFET M17 17 Therefore, r is generated on the twentieth MOSFET M20. o20 The voltage drop of (I1-I2) / 2 is added to the gate voltage of the fourth MOSFET M4, thereby increasing the output current and slew rate. Thus, the output current is increased and the slew rate is also increased without increasing the quiescent current.

[0026] The transconductance and output impedance of the improved folded cascode operational amplifier proposed in this scheme are as follows:

[0027] G m =g m1 [(r o19 / / ro17 / / r o21 )g m3 -2]

[0028] R o =g m6 r o6 (r o2 / / r o4 ) / / g m8 r o8 r o10

[0029] Gain A v =G m *R o , where g m1 g m3 g m6 g m8 The transconductances of the first MOSFET M1, the third MOSFET M3, the sixth MOSFET M6, and the eighth MOSFET M8 are respectively, r o2 r o4 r o6 r o8 r o10 r o17 r o19 r o21 The output impedances of the second MOSFET M2, fourth MOSFET M4, sixth MOSFET M6, eighth MOSFET M8, tenth MOSFET M10, seventeenth MOSFET M17, nineteenth MOSFET M19, and twenty-first MOSFET M21 are shown below. The gain curves of the operational amplifiers are as follows: Figure 3 As shown, the phase curve is as follows Figure 4 As shown. The slew rate of the op-amp is:

[0030]

[0031] Where I1, I2, I3, and I4 are the currents of the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4, respectively, and C L It is the load capacitor, and the slew rate curve of the op-amp is as follows: Figure 5 As shown.

[0032] This invention designs an improved folded cascode operational amplifier. It utilizes an adaptive bias circuit to generate a dynamic current on the differential input pair for large input signals, unaffected by tail current sources, thus improving dynamic current and gain. A local positive feedback circuit converts the current from the adaptive bias circuit and the current generated by the input transistors into a voltage through a transconductance circuit to drive idle folded transistors, improving the input stage transconductance. Furthermore, the improved folded cascode operational amplifier provided by this invention allows for large dynamic currents without being limited by static current, resulting in improved slew rate.

[0033] The above are merely preferred embodiments of the present invention, but do not limit the patent scope of the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of the present invention specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the patent protection scope of the present invention.

Claims

1. An improved folded cascode operational amplifier for amplifying a signal to be processed, characterized by: The application relates to a folded cascode operational amplifier, an adaptive bias circuit and a local positive feedback circuit, a to-be-processed signal is connected to the input transistor of the folded cascode operational amplifier, the folded cascode operational amplifier outputs an amplified signal corresponding to the to-be-processed signal, the adaptive bias circuit is connected to the input transistor of the folded cascode operational amplifier, and the local positive feedback circuit is simultaneously connected to the folded cascode operational amplifier and the adaptive bias circuit; The adaptive bias circuit provides an adaptive bias current for the folded cascode operational amplifier; based on the current of the input transistor of the folded cascode operational amplifier and the current of the adaptive bias circuit, the local positive feedback circuit drives the folded current source transistor in the folded cascode operational amplifier, so that the gain and the slew rate of the folded cascode operational amplifier are improved; the to-be-processed signal is amplified by the folded cascode operational amplifier in combination with the adaptive bias circuit and the local positive feedback circuit, and the folded cascode operational amplifier outputs an amplified signal corresponding to the to-be-processed signal; The signal to be processed includes a differential signal, and the folded cascode operational amplifier includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a tenth MOS transistor, the first MOS transistor and the second MOS transistor are input transistors of the folded cascode operational amplifier, the source and the gate of the first MOS transistor and the second MOS transistor are connected to an adaptive bias circuit, the third MOS transistor and the fourth MOS transistor are folded current source transistors of the folded cascode operational amplifier, the gate of the third MOS transistor and the fourth MOS transistor is connected to a local positive feedback circuit, the gate of the first MOS transistor is connected to one end of the signal to be processed, the drain of the first MOS transistor is connected to the drain of the third MOS transistor, the gate of the second MOS transistor is connected to the other end of the signal to be processed, the drain of the second MOS transistor is connected to the drain of the fourth MOS transistor, the source of the third MOS transistor and the source of the fourth MOS transistor are connected to GND, the gate of the fifth MOS transistor is connected to a preset bias voltage V bn1 , the drain of the fifth MOS transistor is connected to the drain of the seventh MOS transistor, the source of the fifth MOS transistor is connected to the drain of the first MOS transistor, the gate of the sixth MOS transistor is connected to a preset bias voltage V bn1 , the drain of the sixth MOS transistor is connected to the drain of the eighth MOS transistor, and the connected position is used as an output end of the folded cascode operational amplifier to output an amplified signal corresponding to the signal to be processed, the source of the sixth MOS transistor is connected to the drain of the second MOS transistor, the gate of the seventh MOS transistor is connected to a preset bias voltage V bp1 , the source of the seventh MOS transistor is connected to the drain of the ninth MOS transistor, the gate of the eighth MOS transistor is connected to a preset bias voltage V bp1 , the source of the eighth MOS transistor is connected to the drain of the tenth MOS transistor, the gate of the ninth MOS transistor is connected to the gate of the tenth MOS transistor and the drain of the fifth MOS transistor, respectively, the source of the ninth MOS transistor and the source of the tenth MOS transistor are connected to a power supply VDD, the substrate of the first MOS transistor, the second MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor and the tenth MOS transistor is connected to the power supply VDD, respectively, and the substrate of the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor is connected to ground GND, respectively.

2. The improved folded cascode operational amplifier of claim 1, wherein: The adaptive bias circuit comprises an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor and a sixteenth MOS transistor, a gate of the eleventh MOS transistor is connected to a gate of the first MOS transistor, a drain of the eleventh MOS transistor, a drain of the fifteenth MOS transistor and a gate of the thirteenth MOS transistor are connected together, a source of the eleventh MOS transistor is connected to a drain of the thirteenth MOS transistor, and the connected position is connected to a source of the second MOS transistor, a gate of the twelfth MOS transistor is connected to a gate of the second MOS transistor, a drain of the twelfth MOS transistor, a drain of the sixteenth MOS transistor and a gate of the fourteenth MOS transistor are connected together, a source of the twelfth MOS transistor, a drain of the fourteenth MOS transistor and a source of the first MOS transistor are connected together, a source of the thirteenth MOS transistor and a source of the fourteenth MOS transistor are connected to a power supply VDD, gates of the fifteenth MOS transistor and the sixteenth MOS transistor are connected to a preset bias voltage V bias1 , sources of the fifteenth MOS transistor and the sixteenth MOS transistor are connected to a ground GND, substrates of the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor are connected to the power supply VDD respectively, and substrates of the fifteenth MOS transistor and the sixteenth MOS transistor are connected to the ground GND respectively.

3. The improved folded cascode operational amplifier of claim 2, wherein: The local positive feedback circuit comprises a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor and a twenty-second MOS transistor, the gate of the seventeenth MOS transistor is connected to the gate of the thirteenth MOS transistor, the drain of the seventeenth MOS transistor is respectively connected to the drain of the twenty-first MOS transistor, the source of the nineteenth MOS transistor, the gate of the third MOS transistor, the source of the seventeenth MOS transistor is connected to a power supply VDD, the gate of the eighteenth MOS transistor is connected to the gate of the fourteenth MOS transistor, the drain of the eighteenth MOS transistor is respectively connected to the drain of the twenty-second MOS transistor, the source of the twentieth MOS transistor, the gate of the fourth MOS transistor, the source of the eighteenth MOS transistor is connected to the power supply VDD, the gate of the nineteenth MOS transistor is connected to a preset bias voltage V bias2 , the drain of the nineteenth MOS transistor is connected to the gate of the twenty-first MOS transistor, the gate of the twentieth MOS transistor is connected to a preset bias voltage V bias2 , the drain of the twentieth MOS transistor is connected to the drain of the nineteenth MOS transistor, the gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor, the sources of the twenty-first MOS transistor and the twenty-second MOS transistor are connected to ground GND, the substrates of the seventeenth MOS transistor and the eighteenth MOS transistor are respectively connected to the power supply VDD, and the substrates of the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor and the twenty-second MOS transistor are respectively connected to ground GND.

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