Single-Event Transient Hardening Circuit Applied to DC-DC Converter

Abstract

The present invention discloses a single-event transient hardening circuit applied to a DC-DC converter, including an RHBD circuit. The positive terminal of the RHBD circuit is sequentially connected to the upper plate of the sampling capacitor C S and the sampling switch S1. The other end of the sampling switch S1 is connected to the output terminal of the analog buffer. The positive input terminal of the buffer is directly connected to the output node of the error amplifier EA. The output terminal of the RHBD circuit is directly connected to the output terminal of the error amplifier EA. The Control circuit collects the load transient information from the error amplifier EA and outputs an EN signal to control the RHBD circuit. When the system is stable, the above circuit outputs a low level, and the hardening circuit operates normally to detect the single-event transient effect and compensate it in a timely manner. When the system has a load transient response, the above circuit outputs a high level to turn off the hardening circuit, avoiding the system oscillation problem caused by the misoperation of the hardening circuit on the load transient response.

Description

Technical Field

[0001] The present invention belongs to the technical field of radiation hardening for switching power supplies, and relates to a single event transient hardening circuit applied to a DC-DC converter. Background Art

[0002] DC-DC converters play a crucial role in the power systems of aerospace power systems. DC-DC converters are typically used to generate a regulated DC output voltage with high power efficiency from a DC input source, and any change in the output voltage caused by irradiation may affect the operation of other circuits powered by the converter. With the development of deep submicron processes, the failure rate caused by single event transient pulses (SETs) has increased significantly. SETs have attracted great attention. Currently, domestic research in the field of radiation-hardened integrated circuits for aerospace applications mainly focuses on radiation hardening technologies for processes and radiation hardening technologies for digital integrated circuits, and there is less research on radiation-hardened analog integrated circuits.

[0003] The error amplifier (EA) is one of the core modules of the voltage loop of a DC-DC converter. It amplifies the difference between the feedback voltage V FB and the reference voltage V REF . Its output serves as the input signal for the inverting terminal of the PWM comparator. At the same time, the EA provides sufficient gain for the loop to ensure the accuracy of feedback regulation. When a heavy ion or high-energy electron bombards the output node of the EA and triggers an analog single event transient pulse (ASET), it will cause a large transient voltage change at this node. And due to the large capacitor C C of the frequency compensation module, the recovery is slow, resulting in narrow and wide pulses in the PWM output, and then causing a change in the duty cycle D, resulting in an increase in the ripple voltage of the output voltage V OUT or a large fluctuation in the output voltage V OUT .

[0004] The hardening effects of traditional layout-level or process-level hardening solutions cannot provide a good reliability assessment during circuit-level design, which brings great trouble to circuit design. Currently, there is an urgent need to introduce a hardening solution at the circuit level to evaluate the radiation resistance of the circuit. Summary of the Invention

[0005] The purpose of the present invention is to provide a single event transient hardening circuit applied to a DC-DC converter, which solves the problem that the ripple voltage of the output voltage V OUT increases or the output voltage V OUT fluctuates due to the influence of ASET at the output node of the EA in the voltage loop of the DC-DC converter.

[0006] The technical solution adopted by the present invention is a single-event transient hardening circuit applied to a DC-DC converter, which includes an OTA transconductance amplifier. The positive terminal of the OTA transconductance amplifier is sequentially connected to the sampling capacitor C S upper plate and the sampling switch S1. The other end of the sampling switch S1 is connected to the output terminal of the analog buffer. The positive input terminal of the buffer is directly connected to the output node of the error amplifier EA. The output terminal of the OTA transconductance amplifier is directly connected to the output terminal of the error amplifier EA. The Control circuit collects the load transient information from the error amplifier EA and outputs an EN signal to control the OTA transconductance amplifier.

[0007] The characteristics of the present invention also lie in:

[0008] The Control circuit includes a current mirror I, and the current mirror I is connected to a current mirror II, and a current subtraction circuit I is formed between the current mirror I and the current mirror II;

[0009] It also includes a current mirror III, and the current mirror III is connected to a current mirror IV, and a current subtraction circuit II is formed between the current mirror III and the current mirror IV;

[0010] The current mirror II is connected to a two-input XNOR gate XNOR through an inverter INV1, and the current mirror IV is connected to the two-input XNOR gate XNOR through an inverter INV2.

[0011] The current mirror I includes a MOS transistor M1. The source terminal of the MOS transistor M1 is grounded. The drain terminal of the MOS transistor M1 is connected to the source terminal of a MOS transistor M2. The drain terminal of the MOS transistor M2 is the output node of the error amplifier EA. The MOS transistors M1 and M2 are the pull-down branches of the output branch of the error amplifier EA. The gates of the MOS transistors M3 and M4 are respectively connected to the gates of the MOS transistors M1 and M2 to copy the pull-down branch current. The source terminal of the MOS transistor M3 is grounded and the drain terminal is connected to the source terminal of the MOS transistor M4.

[0012] The cascode circuit composed of the MOS transistors M3 and M4 serves as the input signal of the current subtraction circuit I. The drain terminal of the MOS transistor M4 is connected to the bias current I bias1 connected. The cascode circuit composed of the MOS transistors M5 and M6 serves as the output signal of the current subtraction circuit I; the gate and drain of the MOS transistor M5 are connected to the drain of M4, the gate and drain of the MOS transistor M6 are connected to the source of the MOS transistor M5, and the source of the MOS transistor M6 is connected to VDD.

[0013] The current mirror II includes MOS transistors M7 and M8. The gates of MOS transistors M7 and M8 are respectively connected to the gates of MOS transistors M5 and M6. The source of MOS transistor M8 is connected to VDD, the drain of MOS transistor M8 is connected to the source of MOS transistor M7, and the drain of MOS transistor M7 serves as the output of the current mirror II and is connected to the reference current I REF1 and the input of the inverter INV1.

[0014] The current mirror III includes MOS transistors M1' and M2'. MOS transistors M1' and M2' are the pull-up branches on the output branch of the error amplifier EA. The source of MOS transistor M2' is connected to VDD, the drain of MOS transistor M2' is connected to the source of MOS transistor M1', and the drain of MOS transistor M1' is the output node of the error amplifier EA. The gates of MOS transistors M3' and M4' are respectively connected to the gates of MOS transistors M1' and M2' for copying the pull-up branch current. The source of MOS transistor M4' is connected to VDD, and the drain is connected to the source terminal of MOS transistor M3'.

[0015] The cascode circuit composed of MOS transistors M3' and M4' serves as the input signal of the current subtraction circuit II. The drain of MOS transistor M3' is connected to the output of the bias current I bias2 The cascode circuit composed of MOS transistors M5' and M6' serves as the output signal of the current subtraction circuit II. The gate and drain of MOS transistor M6' are connected to the drain of M3'. The gate and drain of MOS transistor M5' are connected to the source of MOS transistor M6', and the source of MOS transistor M5' is grounded.

[0016] The current mirror IV includes MOS transistors M7' and M8'. The gates of MOS transistors M7' and M8' are respectively connected to the gates of MOS transistors M5' and M6'. The source of MOS transistor M7' is grounded, the drain of MOS transistor M7' is connected to the source of MOS transistor M8', and the drain of MOS transistor M8' serves as the output of the current mirror II and is connected to the reference current I REF2 and the input of the inverter INV2;

[0017] The outputs of the inverters INV1 and INV2 are respectively connected to the two input terminals A and B of the XNOR gate. The output terminal of the XNOR gate outputs the EN control signal to control the OTA transconductance amplifier.

[0018] The beneficial effects of the present invention are as follows. A single-event transient hardening circuit applied to a DC-DC converter provided by the present invention has a simple hardening circuit structure. Both the circuit to be hardened and the hardening circuit achieve the suppression of single-event transient effects. At the same time, the distinction between load transients and single-event transients is realized, avoiding misoperation of the hardening circuit. Compared with the traditional layout-level hardening scheme, the present invention can evaluate and design the radiation resistance of the circuit at the circuit schematic design stage. At the same time, it solves the problem that the ripple voltage of the output voltage V OUT increases or the output voltage V OUT fluctuates at the EA output node in the voltage loop of the DC-DC converter, and accelerates the recovery time of the DC-DC converter loop after being disturbed by single particles. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. is a schematic structural diagram of a single-event transient hardening circuit applied to a DC-DC converter according to the present invention.

[0020] Figure 2 FIG. is a schematic diagram of a control circuit of a single-event transient hardening circuit applied to a DC-DC converter according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described in detail below with reference to the drawings and specific embodiments.

[0022] The single-event transient hardening circuit applied to a DC-DC converter according to the present invention, as Figure 1 shown, includes an OTA transconductance amplifier. The positive terminal of the OTA transconductance amplifier is sequentially connected to the upper plate of the sampling capacitor C S and one end of the sampling switch S1. The lower plate of the sampling capacitor C S is grounded. The other end of the sampling switch S1 is connected to the output terminal of the analog buffer. The positive input terminal of the buffer is directly connected to the output node of the error amplifier EA. The output terminal of the OTA transconductance amplifier is directly connected to the output terminal of the error amplifier EA to provide a charge and discharge circuit. A resistor Rc is connected between the error amplifier EA and the analog buffer, and a compensation capacitor Cc is connected to the resistor Rc; The Control circuit collects load transient information from the error amplifier EA and outputs an EN signal to control the OTA transconductance amplifier.

[0023] As Figure 2 shown, the Control circuit includes current mirror I, current mirror II, current mirror III, current mirror IV, current subtraction circuit I, current subtraction circuit II, bias current I bias1 , I bias2 , reference current I REF1 , reference current I REF2, inverter INV1, inverter INV2 and two-input XNOR gate XNOR.

[0024] Current mirror I includes MOS transistors M1 to M4. M1 and M2 are the pull-down branches of the output branch of error amplifier EA. The source of MOS transistor M1 is grounded. The drain of MOS transistor M1 is connected to the source of MOS transistor M2. The drain of MOS transistor M2 is the output node of error amplifier EA. The gates of MOS transistors M3 and M4 are respectively connected to the gates of MOS transistors M1 and M2 for copying the pull-down branch current. Among them, the source of MOS transistor M3 is grounded and the drain is connected to the source of current transistor M4.

[0025] The cascode circuit composed of MOS transistors M3 and M4 serves as the input signal of current subtraction circuit I. The drain of MOS transistor M4 is connected to the output of bias current I bias1 The cascode circuit composed of MOS transistors M5 and M6 serves as the output signal of current subtraction circuit I;

[0026] The gate and drain of MOS transistor M5 are connected to the drain of M4. The gate and drain of MOS transistor M6 are connected to the source of MOS transistor M5. The source of MOS transistor M6 is connected to VDD.

[0027] MOS transistors M5 to M8 form current mirror II. The gates of MOS transistors M7 and M8 are respectively connected to the gates of MOS transistors M5 and M6. The source of MOS transistor M8 is connected to VDD, the drain of MOS transistor M8 is connected to the source of MOS transistor M7, and the drain of MOS transistor M7 serves as the output of current mirror II and is connected to reference current I REF1 and the input of inverter INV1.

[0028] Current mirror III includes MOS transistors M1’, MOS transistors M2’, MOS transistors M3’, MOS transistors M4’. MOS transistors M1’ and MOS transistors M2’ are the pull-up branches of the output branch of error amplifier EA. The source of MOS transistor M2’ is connected to VDD. The drain of MOS transistor M2’ is connected to the source terminal of M1’. The drain of MOS transistor M1’ is the output node of error amplifier EA. The gates of MOS transistors M3’ and MOS transistors M4’ are respectively connected to the gates of MOS transistors M1’ and M2’ for copying the pull-up branch current. Among them, the source of MOS transistor M4’ is connected to VDD and the drain is connected to the source of MOS transistor M3’.

[0029] The cascode circuit composed of MOS transistors M3’ and MOS transistors M4’ serves as the input signal of current subtraction circuit II. The drain of MOS transistor M3’ is connected to bias current I bias2is connected to the output. The cascode circuit composed of MOS transistors M5’ and M6’ serves as the output signal of current subtraction circuit II. The gate and drain of MOS transistor M6’ are connected to the drain of M3’. The gate and drain of MOS transistor M5’ are connected to the source of MOS transistor M6’, and the source of MOS transistor M5’ is grounded.

[0030] MOS transistors M5’ to M8’ form current mirror IV. The gates of MOS transistors M7’ and M8’ are respectively connected to the gates of current transistors M5’ and M6’. The source of MOS transistor M7’ is grounded, the drain of MOS transistor M7’ is connected to the source of MOS transistor M8’, and the drain of MOS transistor M8’ serves as the output of current mirror II and is connected to reference current I REF2 and the input of inverter INV2.

[0031] The outputs of inverters INV1 and INV2 are respectively connected to the two input terminals A and B of the XNOR gate. The output terminal of the XNOR gate outputs the EN control signal to control the OTA transconductance amplifier.

[0032] The present invention uses an analog buffer to isolate the EA output stage and the sampling circuit. Sampling switch S1 and sampling capacitor C S sample the EA output V C and use the sampled signal as the input signal of the positive terminal of the OTA transconductance amplifier. The negative terminal of the OTA transconductance amplifier is directly connected to the EA output terminal to perform real-time single-event detection on the EA output node. By comparing their magnitudes, rapid charge and discharge operations are performed on the EA output node. When the output terminal of the OTA transconductance amplifier is directly connected to the EA output terminal, the detection and suppression of single-event transient effects can be achieved.

[0033] The present invention Figure 2 The circuit in detects the transient process of the load current. M1, M2, M1’, and M2’ are the output stages of the error amplifier. The cascode stage composed of M3 and M4 is used to copy the current flowing through M1 and M2. The drain of M4 is connected to the bias current I bias1 and the gate and drain of M5. The cascode stage composed of M5 and M6 serves as the mirror source of current mirror II. The cascode stage composed of M7 and M8 is used to copy the current flowing through M5 and M6 and amplify it. The drain of M7 is connected to the reference current I REF1 and the input terminal of inverter INV1. The output terminal of inverter INV1 is connected to the A input terminal of the XNOR. The cascode stage composed of M3’ and M4’ is used to copy the current flowing through M1’ and M2’. The drain of M3’ is connected to the bias current I bias2It is connected to the gates and drains of M6'. The common-source common-gate stage formed by M5' and M6' serves as the mirror source of current mirror II. The common-source common-gate stage formed by M7' and M8' is used to copy and amplify the current flowing through M5' and M6'. The drain of M8' is connected to the reference current I REF2 and the input terminal of inverter INV2. The output terminal of inverter II is connected to the B input terminal of the XNOR gate; the EN signal output by the XNOR gate is used to control the OTA transconductance amplifier.

[0034] The pull-down current of the branch where the EA output node is located is copied by current mirror I, that is, the current flowing through M1 and M2, and is input as the minuend to current subtraction circuit 1, that is, the current I3 flowing through M4 and M3. The result I4 of current subtraction circuit 1 is amplified by current mirror 2. The output of current mirror II and the reference current I are shaped by inverter INV1 REF1 The pull-up current of the branch where the EA output node is located is copied by current mirror III, that is, the current flowing through M2' and M1', and is input as the minuend to current subtraction circuit II, that is, the current I3' flowing through M4' and M3'. The result I4' of current subtraction circuit II is amplified by current mirror IV. The output of current mirror IV and the reference current I are shaped by inverter INV2 REF2 The result is input to Figure 2 the B terminal of the XNOR gate in

[0035] When the system is stable, the output common-mode level of the error amplifier is stable. The currents I1 = I2 in the branch where the output node is located. The current I3 copied by current mirror I is equal to I1 and is less than I bias1 , I bias1 is the bias current of the output branch of the error amplifier. To meet the requirements of practical applications, this current is slightly larger than the bias current of the error amplifier. At this time, the output of the current subtraction circuit is 0, that is, I4 = 0. The copied result I5 of current mirror II is 0. The input terminal of inverter INV1 is pulled low by IREF1, and the output of inverter INV1 is logic "1"; the current I3' copied by current mirror III is equal to I2 and is less than I bias2 , I bias2 is the bias current of the output branch of the error amplifier. To meet the requirements of practical applications, this current is slightly larger than the bias current of the error amplifier. At this time, the output of the current subtraction circuit is 0, that is, I4' = 0. The copied result I5' of current mirror IV is 0. The input terminal of inverter INV2 is pulled high by IREF2, and the output of inverter INV2 is logic "0"; the output signals A and B of inverter INV1 and inverter INV2 are operated by the XNOR gate and then output logic "0", which controls the normal operation of the OTA transconductance amplifier.

[0036] When the system load current jumps from a large load to a light load, the output voltage V of the error amplifier CDecrease, generating a discharge current I from the compensation capacitor C C through M2, M1 to GND tran1 , increasing the pull - down current, and the replicated current I3 of current mirror I = I1 + I tran1 , the subtracted quantity I3 of current subtractor I exceeds I bias1 , I4 increases, I4 = I3 - I bias , current mirror II amplifies I4 by m times to obtain I5 = mI4 = m(I3 - I bias1 ), and at this time I5 is greater than I REF1 , the input terminal of inverter INV1 is pulled high, the output of inverter INV1 is logic "0", the output of inverter INV2 is logic "0", the output of the XNOR gate is logic "1", and the OTA transconductance amplifier is turned off.

[0037] When the system load current jumps from a light load to a heavy load, the output voltage V of the error amplifier C increases, generating a charging current I from VDD through M2', M1' to the EA compensation capacitor C C tran2 , increasing the pull - up current, and the replicated current I3' of current mirror III = I1 + I tran2 , the subtracted quantity I3' of current subtractor II exceeds I bias , I4' increases, I4' = I3' - I bias , current mirror IV amplifies I4' by m times to obtain I5' = mI4' = m(I3' - I bias ), and at this time I5' is greater than I REF2 , the input terminal of inverter INV2 is pulled low, the output of inverter INV2 is logic "1", the output of inverter 1 is logic "1", the output of the XNOR gate is logic "1", and the OTA transconductance amplifier is turned off.

[0038] When the system is working normally, the control circuit outputs a low level to control the normal operation of the reinforcement circuit and detect single - event transient effects.

[0039] When a load transient occurs in the system, if it jumps from a heavy load to a light load, the error amplifier generates a discharge path from the compensation capacitor C C through M2, M1 to GND, V C decreases, the pull - down current of the error amplifier increases, the output current of current mirror I increases, the output current of the current subtraction circuit I increases, the output current of current mirror II increases, pulling the input terminal of inverter INV1 to a high level, the output of inverter INV1 is logic "0", after XNOR operation, the control circuit outputs a high level to control the reinforcement circuit to turn off and avoid misoperation of the reinforcement circuit.

[0040] When a load transient occurs in the system, if it jumps from a light load to a heavy load, the error amplifier generates a path from VDD through M2'​、 The charging path from M1’ to the compensation capacitor C C V increases, the pull-up current of the error amplifier increases, the output current of current mirror III increases, the output current of current subtraction circuit II increases, the output current of current mirror IV increases, pulling the input terminal of inverter INV2 to a low level. The output of inverter INV2 is logic "1". After exclusive-NOR operation, the control circuit outputs a high level to control the reinforcement circuit to turn off, avoiding misoperation of the reinforcement circuit. C

[0041] Through the above method, the single-event transient pulse detection and reinforcement circuit of the error amplifier of the present invention can distinguish single-event transients from load transients, thereby avoiding the misoperation of detecting load transients as single-event transients by the proposed reinforcement circuit.​

Claims

1. A single-event transient hardening circuit applied to a DC-DC converter, characterized in that: It includes an OTA transconductance amplifier. The positive terminal of the OTA transconductance amplifier is sequentially connected to the sampling capacitor C S upper plate and the sampling switch S1. The other end of the sampling switch S1 is connected to the output terminal of the analog buffer. The positive input terminal of the buffer is directly connected to the output node of the error amplifier EA. The output terminal of the OTA transconductance amplifier is directly connected to the output terminal of the error amplifier EA. The Control circuit collects the load transient information from the error amplifier EA and outputs an EN signal to control the OTA transconductance amplifier; The Control circuit includes current mirror I, and current mirror I is connected to current mirror II, and a current subtraction circuit I is formed between current mirror I and current mirror II; It further includes current mirror III, and current mirror III is connected to current mirror IV, and a current subtraction circuit II is formed between current mirror III and current mirror IV; Current mirror II is connected to the two-input XNOR gate XNOR through inverter INV1, and current mirror IV is connected to the two-input XNOR gate XNOR through inverter INV2.

2. The single-event transient hardening circuit applied to a DC-DC converter according to claim 1, characterized in that: The current mirror I includes MOS transistor M1. The source terminal of MOS transistor M1 is grounded. The drain of MOS transistor M1 is connected to the source of MOS transistor M2. The drain of MOS transistor M2 is the output node of error amplifier EA. MOS transistors M1 and M2 are the pull-down branches of the output branch of error amplifier EA. The gates of MOS transistors M3 and M4 are respectively connected to the gates of MOS transistors M1 and M2 for copying the pull-down branch current. The source of MOS transistor M3 is grounded, and the drain is connected to the source of MOS transistor M4.

3. The single-event transient hardening circuit applied to the DC-DC converter according to claim 2, wherein: The cascode circuit composed of MOS transistor M3 and MOS transistor M4 serves as the input signal of current subtraction circuit I, and the drain of MOS transistor M4 is connected to bias current I bias1 The cascode circuit composed of MOS transistor M5 and MOS transistor M6 serves as the output signal of current subtraction circuit I; the gate and drain of MOS transistor M5 are connected to the drain of M4, the gate and drain of MOS transistor M6 are connected to the source of MOS transistor M5, and the source of MOS transistor M6 is connected to VDD.

4. The single-event transient hardening circuit applied to the DC-DC converter according to claim 3, characterized in that: The current mirror II includes an MOS transistor M7 and an MOS transistor M8. The gates of the MOS transistors M7 and M8 are respectively connected to the gates of the MOS transistors M5 and M6. The source of the MOS transistor M8 is connected to VDD, the drain of the MOS transistor M8 is connected to the source of the MOS transistor M7, and the drain of the MOS transistor M7 serves as the output of the current mirror II and is connected to the reference current I REF1 and the input of the inverter INV1.

5. The single-event transient hardening circuit applied to the DC-DC converter according to claim 1, characterized in that: The current mirror III includes MOS transistors M1' and M2'. MOS transistors M1' and M2' are the pull-up branches of the output branch of error amplifier EA. The source of MOS transistor M2' is connected to VDD. The drain of MOS transistor M2' is connected to the source of MOS transistor M1'. The drain of MOS transistor M1' is the output node of error amplifier EA. The gates of MOS transistors M3' and M4' are respectively connected to the gates of MOS transistors M1' and M2' for copying the pull-up branch current. The source of MOS transistor M4' is connected to VDD, and the drain is connected to the source terminal of MOS transistor M3'.

6. The single-event transient hardening circuit applied to the DC-DC converter according to claim 5, characterized in that: The cascode circuit composed of the MOS transistors M3' and M4' serves as the input signal of the current subtraction circuit II. The drain of the MOS transistor M3' is connected to the output of the bias current I bias2 . The cascode circuit composed of the MOS transistors M5' and M6' serves as the output signal of the current subtraction circuit II. The gate and drain of the MOS transistor M6' are connected to the drain of M3'. The gate and drain of the MOS transistor M5' are connected to the source of the MOS transistor M6'. The source of the MOS transistor M5' is grounded.

7. The single-event transient hardening circuit applied to the DC-DC converter according to claim 6, characterized in that: The current mirror IV includes MOS transistors M7' and M8'. The gates of MOS transistors M7' and M8' are respectively connected to the gates of MOS transistors M5' and M6'. The source of MOS transistor M7' is grounded, the drain of MOS transistor M7' is connected to the source of MOS transistor M8', and the drain of MOS transistor M8' serves as the output of the current mirror IV and is connected to the reference current I REF2 and the input of the inverter INV2; The outputs of inverters INV1 and INV2 are respectively connected to the two inputs A and B of the XNOR gate. The output terminal of the XNOR gate outputs an EN control signal to control the OTA transconductance amplifier.

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