FPGA-based ldpc decoder

Abstract

The application provides an FPGA-based LDPC decoder, comprising a receiving unit, a control unit, an iterative updating unit and a checking unit; the receiving unit receives channel initial information, sends the channel initial information to the iterative updating unit and informs the control unit; the control unit controls the iterative updating unit to start iterative updating according to the information informed by the receiving unit, and decides whether to perform the next iteration according to the checking result of the checking unit; the iterative updating unit stores the channel initial information and starts iterative updating according to the control command of the control unit, generates decision information at each time of iterative updating and outputs the decision information to the checking unit; the checking unit checks according to the decision information and outputs the result to the control unit; through multiple iterative updating and checking, the overlapping part of the channel initial information is decoded in parallel, the parallel high-speed decoding efficiency is obtained while the low operation complexity is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of communication, and particularly relates to an FPGA-based LDPC decoder. BACKGROUND

[0002] LDPC code, i.e. Low Density Parity Check Code, was first proposed by Dr. Gallager in 1962 and rediscovered by Mackey and Neal in 1996. LDPC code itself has superior error correction performance and lower hardware implementation complexity, and is therefore widely applied in deep space communication fields.

[0003] With the progress of technology, various decoding algorithms for LDPC have been proposed in the academic field. Among them, the probability domain BP decoding algorithm is one of the mainstream decoding algorithms for LDPC code, but the algorithm needs a large number of multiplication operations and is difficult to realize through a hardware circuit. The log domain LLR (Log Likely Rate) BP decoding algorithm changes the multiplication operation in the probability domain BP decoding algorithm into an addition operation, reducing the operation complexity, but the hardware circuit implementation complexity is still high due to the existence of logarithmic operation. The minimum sum decoding algorithm (MSA) is a further simplification of the log domain LLR BP decoding algorithm, and the simplified MSA only needs addition and comparison operations. The multiplicative correction minimum sum decoding algorithm (NMSA) is a correction of MSA, which further approaches the error correction performance of the log domain LLR BP decoding algorithm. Although NMSA has low operation complexity and is extremely suitable for hardware circuit implementation, it has a lot of invalid waiting time due to its decoding mechanism based on two-phase message passing (TPMP).

[0004] With the development of communication technology, further requirements for decoding speed and efficiency are put forward, and how to design a corresponding FPGA-based decoder for LDPC decoding and obtain parallel high-speed decoding efficiency is a problem faced by those skilled in the art. SUMMARY

[0005] The technical problem solved by the present application is to provide an FPGA-based LDPC decoder which can achieve low operation complexity and obtain parallel high-speed decoding efficiency.

[0006] To solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0007] Provided is an FPGA-based LDPC decoder, comprising a receiving unit, a control unit, an iterative updating unit and a check unit.

[0008] The receiving unit receives channel initial information, sends the channel initial information to the iterative updating unit, and notifies the control unit.

[0009] The control unit controls the iterative updating unit to start iterative updating according to the notification information of the receiving unit, and decides whether to perform the next iteration according to the checking result of the checking unit;

[0010] The iterative updating unit stores the channel initial information, and starts iterative updating according to the control command of the control unit. At each iteration, the iterative updating unit generates decision information and outputs the decision information to the checking unit;

[0011] The checking unit checks according to the decision information, and outputs the checking result to the control unit;

[0012] Through the cooperation of the receiving unit, the control unit, the iterative updating unit and the checking unit, multiple iterative updating and checking are performed, and the overlapping part of the channel initial information is parallel decoded to obtain correct decoding information.

[0013] Further, the iterative updating unit includes an initialization storage unit, an addressing unit, a variable node updating unit library, a check node updating unit library, a data bit sequence adjustment unit and corresponding storage RAMs;

[0014] The storage RAMs include a first storage RAM for storing the channel initial information, and a second storage RAM and a third storage RAM for storing intermediate transfer information;

[0015] The intermediate transfer information includes longitudinal updating information and transverse updating information, the second storage RAM is used for storing the longitudinal updating information, and the third storage RAM is used for storing the transverse updating information;

[0016] The initialization storage unit is used for storing the channel initial information, and initializing the second storage RAM and the third storage RAM at the beginning of each iteration;

[0017] The variable node updating unit library contains a plurality of variable node updating units, and the check node updating unit library contains a plurality of check node updating units. The variable node updating units and the check node updating units are used for reading the intermediate transfer information, performing iterative updating processing on the intermediate transfer information, and storing the processed intermediate transfer information into the second storage RAM and the third storage RAM;

[0018] The addressing unit is used for generating a read address and an offset address of the storage RAMs, and the data bit sequence adjustment unit is used for shifting the read intermediate transfer information according to the offset address and sending the shifted intermediate transfer information to the variable node updating unit library and the check node updating unit library.

[0019] Further, 16 blocks of RAM are allocated to the first storage RAM, 64 blocks of RAM are allocated to the second storage RAM, and 64 blocks of RAM are allocated to the third storage RAM, wherein each block of RAM can store 511 pieces of data with a length of 7 bits.

[0020] Further, the check matrix of the LDPC code is evenly divided into 14 blocks according to rows and 112 blocks according to columns, and each block after the division has a minimum sub-matrix size of 73x73; the sub-circulation matrix with a size of 511x511 is divided into 7 minimum sub-matrices with a size of 73x73, and the iteration update unit simultaneously performs iteration update on each minimum sub-matrix.

[0021] Further, the channel initial information is stored in a bit splicing manner: each block of RAM contains 0-72 storage addresses, each storage address stores 7 data, and each data contains 7 bits; the 7 data are sequentially assigned with offset addresses 1-7 from left to right, and adjacent data are spaced 73 bit sequences from each other during storage, and the data are data of the channel initial information.

[0022] Further, the initialization storage unit further includes a write register; and the storage in the bit splicing manner is implemented.

[0023] The channel initial information is grouped, and each group of channel initial information contains 511 data; the bit width of each block of RAM is set to 49, and the depth is set to 73.

[0024] Starting from the 0 address of each block of RAM in the first storage RAM, the original data in the address are sequentially read out, and each time the address 72 is read, the address 0 is returned;

[0025] The low 42 bits of the original data are assigned to the high 42 bits of the write register, and the low 7 bits of the write register are assigned after adding a bit 0 at the end of the channel initial information; and then the value in the write register is sent to the first storage RAM and the second storage RAM for storage.

[0026] After the above reading and writing steps are repeated 7 times, one group of channel initial information is stored in a bit splicing manner.

[0027] After 8158 initial channel information are stored, the initialization storage unit notifies the control unit that the storage is completed.

[0028] Further, at the beginning of each iteration, the initialization storage unit initializes the second storage RAM and the third storage RAM, including:

[0029] The second storage RAM and the third storage RAM are cleared;

[0030] The channel initial information stored in the first storage RAM in a splicing manner is written into the second storage RAM.

[0031] Further, the reading and writing of the intermediate transfer information include:

[0032] After reading according to the read address generated by the addressing unit in real time and data bit sequence adjustment according to the offset address generated by the addressing unit in real time, output to the variable node update unit library or the check node update unit library; when writing, directly splice the intermediate transfer information processed by the variable node update unit or the check node update unit, and then write into the corresponding RAM with 0 address as the starting address.

[0033] Further, the data bit sequence adjustment unit comprises a barrel shifter.

[0034] The 3bit offset address generated in the addressing unit is replaced by a 1bit offset enable variable, when the offset enable variable is 0, the barrel shifter performs cyclic left shift on the input data according to the starting offset address, when the offset enable variable is 1, the offset address is updated to the starting offset address plus 1, and the barrel shifter performs cyclic left shift on the input data according to the updated offset address.

[0035] Further, when the variable node update unit and / or the check node update unit performs iterative update processing, a pipeline is added.

[0036] The present application has the advantages that: by designing a FPGA-based LDPC decoder, multiple iterative updates and checks are performed by the receiving unit, the control unit, the iterative update unit and the check unit, the overlapping partial parallel decoding of the initial information of the channel is completed, correct decoding information is obtained, and parallel high-speed decoding efficiency is obtained while realizing low operation complexity. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a trace diagram of element 1 of the sub-circulation matrix A of the check matrix H of an embodiment of the present application;

[0038] Figure 2 is a sending frame structure of an embodiment of the (8176, 7154) LDPC code of the present application;

[0039] Figure 3 is a transverse update and longitudinal update schematic diagram of an embodiment of the overlapping partial parallel decoding algorithm of the present application;

[0040] Figure 4 is a calculation flowchart of an embodiment of the overlapping partial parallel decoding algorithm of the present application;

[0041] Figure 5 is a schematic diagram of the architecture of an embodiment of the decoder of the present application;

[0042] Figure 6 is a schematic diagram of the architecture of an embodiment of the iterative update unit of the present application;

[0043] Figure 7is a flow chart of an embodiment of the storage addressing method of the present application;

[0044] Figure 8 is an array distribution diagram of a first storage RAM in an embodiment of the present application;

[0045] Figure 9 is an array distribution diagram of a storage RAM in an embodiment of the present application;

[0046] Figure 10 is a storage diagram of a group of channel initial information in an embodiment of the present application;

[0047] Figure 11 is a "complex read simple write" storage addressing method diagram in an embodiment of the present application;

[0048] Figures 12a-12c is a horizontal updating process diagram in an embodiment of the present application;

[0049] Figures 13a-13c is a vertical updating process diagram in an embodiment of the present application;

[0050] Figure 14 is an initialization channel initial information diagram of an initialization storage unit in an embodiment of the present application;

[0051] Figure 15 is a corresponding relation diagram of writing the initialization channel initial information into the first storage RAM and the second storage RAM in an embodiment of the present application;

[0052] Figure 16 is a structure diagram of a check node updating unit in an embodiment of the present application;

[0053] Figure 17 is a structure diagram of a variable node updating unit in an embodiment of the present application;

[0054] Figure 18 is a timing diagram of a decoder iteration process in an embodiment of the present application;

[0055] Figure 19 is a flow chart of a check method in an embodiment of the present application;

[0056] Figure 20 is a check storage diagram of a check unit in an embodiment of the present application;

[0057] Figure 21 is a check sub-flow chart of a check method in an embodiment of the present application;

[0058] Figure 22 is a structure block diagram of a check device in an embodiment of the present application;

[0059] Figure 23 is a quantization effect comparison chart of an embodiment of the present application;

[0060] Figure 24 is a maximum iteration number effect comparison chart of an embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to facilitate the understanding of the present application, the present application will be described in more detail below in conjunction with the accompanying drawings and specific embodiments. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described in the specification. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0062] It should be noted that, unless otherwise defined, all technical and scientific terms used in the specification have the same meaning as commonly understood by those skilled in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0063] The abbreviations used in the present application have the following meanings:

[0064] QC-LDPC: Quasi-Cyslic-Low-Density Parity-Check Codes, quasi-cyclic LDPC code

[0065] CCSDS: Consultative Committee for Space Data Systems, Space Data Systems Consultative Committee

[0066] C2V: Check to Variable, horizontal update

[0067] V2C: Variable to Check, vertical update

[0068] CNU: Check Node Unit, check node update unit

[0069] VNU: Variable Node Unit, variable node update unit

[0070] RAM: Random Access Memory, register

[0071] The selected LDPC code is QC-LDPC code, specifically, (8176, 7154) LDPC code recommended by the Consultative Committee for Space Data Systems (CCSDS) channel coding standard, which has quasi-cyclic characteristics and low hardware implementation complexity. The check matrix H of the (8176, 7154) LDPC code is a regular quasi-cyclic matrix with a size of 1022*8176, the value of row weight of each row is 32, and the value of column weight of each column is 4. The row weight is the number of "1" in each row, and the column weight is the number of "1" in each column. Therefore, there are only a few "1"s in the check matrix H, and most of the matrix elements are zero. The specific construction of the check matrix H is as follows:

[0072]

[0073] Wherein, A represents a sub-cyclic matrix of the check matrix H, the subscript of A represents its position in the check matrix H, and the size of each A is 511*511, the value of row weight of each row and the value of column weight of each column is 2. The element 1 of the lth row (l=2, 3, …, 511) in A is a cyclic right shift of the element 1 of the (l-1)th row, and the point set formed by continuously cyclically right shifting a certain element 1 in A for 510 times is defined as the trajectory of the element 1 in the application, as shown in Figure 1 It can be seen that there are two trajectories of element 1 in A: L1 and L2.

[0074] Figure 2 The sending frame structure of the (8176, 7154) LDPC code specified by CCSDS is given. As shown in Figure 2 Since the first 18 bits are frozen bits 0 and are not sent, a complete sending frame only contains 8160 bits, of which the first 7136 bits are information bits, the middle 1022 bits are check bits, and the last two bits are padding bits 0.

[0075] The BP decoding algorithm for the LDPC code mainly includes two processes of horizontal updating and vertical updating. Among them, the horizontal updating completes the parallel updating of the check node to the variable node (horizontal updating), and the module responsible for this updating process is called check node updating unit, which is abbreviated as CNU in the application. The vertical updating completes the parallel updating of the variable node to the check node (vertical updating), and the module responsible for this updating process is called variable node updating unit, which is abbreviated as VNU in the application. The BP decoding algorithm is based on the decoding mechanism of two-phase information transmission (TPMP), that is, the horizontal updating process and the vertical updating process are alternately performed. The advantage of this decoding mechanism is that the check node updating unit and the variable node updating unit can utilize new transmission information, and the disadvantage is that the hardware utilization rate is low, only 50%. The NMSA algorithm based on the optimization of the BP decoding algorithm still uses the two-phase information transmission (TPMP) mechanism, so there is still a problem of a lot of invalid waiting time.

[0076] In order to obtain higher parallel decoding rate, the present application uses overlapped partial parallel decoding algorithm to decode LDPC. The overlapped partial parallel decoding algorithm (overlapped NMSA) is proposed based on NMSA algorithm to solve the problem of much invalid waiting time in NMSA algorithm.

[0077] Further, as shown in Figure 3 , when applying the overlapped partial parallel decoding algorithm, the check matrix H is first divided into blocks, for the horizontal update process, H is divided into blocks uniformly according to rows; for the vertical update process, H is divided into blocks uniformly according to columns, the number of rows and columns contained in the sub-circulant matrix after division is the same, and is set as K, Figure 3 A1 in the above formula is a sub-circulant matrix, containing K rows and K columns. When iterating, the horizontal and vertical updates of each sub-circulant matrix are started at the same time. As shown in the figure, in the first period, the first row of the sub-circulant matrix A1 is updated horizontally, and the first column of the sub-circulant matrix A1 is updated vertically, in the second period, the second row of the sub-circulant matrix A1 is updated horizontally, and the second column of the sub-circulant matrix A1 is updated vertically, and so on, until the Kth period, the Kth row of the sub-circulant matrix A1 is updated horizontally, and the Kth column of the sub-circulant matrix A1 is updated vertically, thus completing one iteration of the sub-circulant matrix A1. Similarly, for other sub-circulant matrices, iterations are also performed in the same K periods, and one iteration of all sub-circulant matrices is completed at the Kth period.

[0078] In this way, the horizontal and vertical updates can complete iterations at the same time, and iterations are completed at the same time, so that the algorithm can obtain one more iteration times than NMSA in the same time.

[0079] Specifically, referring to Figure 4 , the calculation process of the overlapped partial parallel decoding algorithm is as follows:

[0080] S101: initialization, storing the initial information of the channel, and obtaining intermediate transfer information;

[0081] S102: iterative update, simultaneously performing horizontal update and vertical update;

[0082] S103: decision, making a decision to obtain the corresponding decoding codeword according to the sub-circulant matrix obtained after the update;

[0083] S104: check, checking after each iteration, when the check result is true, or the number of iterations reaches the maximum value, stopping decoding; otherwise, jumping to S102 to continue the next iteration update;

[0084] S105: stop decoding, outputting the decoding result.

[0085] Further, the step S101 comprises the following calculation:

[0086]

[0087]

[0088] l = 1.

[0089] wherein, represents the log-likelihood ratio of , L( ) represents the log-likelihood ratio of j is the channel initial information, K is the row number or column number of the sub-circulation matrix after blocking, q ji represents the information (vertical update information) transmitted by the jth variable node to the ith check node, r ij represents the information (horizontal update information) transmitted by the ith check node to the jth variable node, represents the initialized vertical update information, represents the initialized horizontal update information. l represents the current iteration number, l = 1, 2, …, max, and max is the maximum iteration number.

[0090] Further, the step S102 comprises the following calculation:

[0091] for (j = i = 1; j < K; j++, i++)

[0092] {

[0093] Horizontal update, check node update unit calculation processing

[0094]

[0095] wherein, j' ∈ R i\j represents the deletion of the jth variable node in the variable node set connected with the ith check node. η represents the correction value, which is 0.75 in the present application.

[0096] Vertical update, variable node update unit calculation processing is as follows:

[0097]

[0098]

[0099] wherein, i' ∈ C j\i represents the deletion of the ith check node in the check node set connected with the jth variable node.

[0100] };

[0101] Further, the step S103 comprises the following calculation:

[0102] If L(q j )<0, then c j =1, otherwise c j =0. Wherein, c j represents the decoded code word.

[0103] Further, the step S104 comprises the following calculation:

[0104] If H·c T =0 or l=max, then stop decoding, otherwise l=l+1 and return to step S102 to continue iteration.

[0105] The main idea of the algorithm is the simultaneous performance of horizontal and vertical updating processes, and this updating mode causes the check node updating unit and the variable node updating unit to not utilize the brand-new transfer information, so that the convergence speed of the algorithm is indeed slower than that of NMSA in terms of iteration times, but the algorithm can obtain one time more iteration times than NMSA in the same time, which is sufficient to compensate for the slow convergence speed.

[0106] Example One

[0107] Further, as shown in Figure 5 , 6 the application provides an FPGA-based LDPC decoder for implementing the above QC-LDPC code overlapping partial parallel decoding algorithm, which can obtain parallel high-speed decoding efficiency while realizing low operation complexity.

[0108] Figure 5 The figure is a structural diagram of the decoder, comprising a receiving unit 101, a control unit 102, an iteration updating unit 103 and a check unit 104.

[0109] The receiving unit 101 is responsible for receiving channel initial information and sending the information to the iteration updating unit 103 for storage, and notifying the control unit 102 to start decoding.

[0110] The control unit 102 controls the iteration updating unit 103 to start iteration updating according to the notification of the receiving unit 101, and decides whether to perform the next iteration according to the check result of the check unit 104.

[0111] The iteration updating unit 103 stores the channel initial information received by the receiving unit 101, and starts iteration updating according to the control command of the control unit 102, and outputs the decision information generated by each iteration updating result to the check unit 104.

[0112] The check unit 104 performs checking according to the decision information and outputs the result to the control unit 102.

[0113] Further, referring to Figure 6 , Figure 6 is a detailed architecture diagram of the iterative update unit 103, including: an initialization storage unit 1031, an addressing unit 1032, a variable node update unit library 1033, a check node update unit library 1034, a data bit sequence adjustment unit 1035, and corresponding storage RAMs.

[0114] Further, the storage RAMs include a first storage RAM 1036 for storing channel initial information, and a second storage RAM 1037 and a third storage RAM 1038 for storing intermediate transfer information.

[0115] Further, the intermediate transfer information includes longitudinal update information (generated when longitudinal updating) and transverse update information (generated when transverse updating), the second storage RAM 1037 is used to store the longitudinal update information, and the third storage RAM 1038 is used to store the transverse update information.

[0116] Further, each variable node update unit library 1033 contains 112 variable node update units, and each check node update unit library 1034 contains 14 check node update units, which are used to process the intermediate transfer information. This is because in order to further improve the parallelism, the sub-cycle matrix is divided into minimum sub-matrices, where the size of the minimum sub-matrix is 73*73, and the iterative update is performed on each minimum sub-matrix at the same time. Accordingly, if each minimum sub-matrix needs to be updated transversely and longitudinally at the same time, 14 check node update units and 112 variable node update units are needed.

[0117] For the channel initial information of each frame, N times of iterative decoding will be performed until the decoding of the channel initial information of this time is successfully completed, the iteration task is ended, and the decoding of the channel initial information of the next frame is entered. Wherein, the structure of the channel initial information of each frame is as shown in Figure 2 The first 18 bits of frozen bits are not transmitted, and the last two padding bits do not need to be processed during iteration, so when stored locally, the storage information of the 18 bits of frozen bits needs to be regenerated, and the last two padding bits are discarded. That is, when stored, each frame corresponds to 8176 data, of which the first 18 data are fixed values, and the real change is the last 8158 data.

[0118] At the beginning of each frame iterative decoding, the initialization storage unit 1031 stores the channel initial information into the first storage RAM 1036, and also stores the channel initial information into the second storage RAM 1037.

[0119] During each iteration initialization of the same frame, the initialization storage unit 1031 reads the channel initial information from the first storage RAM 1036 and stores it in the second storage RAM 1037. When the current iteration ends, the initialization storage unit 1031 clears the second storage RAM 1037 and the third storage RAM 1038.

[0120] When all iterations of decoding of the channel initial information belonging to the same frame are completed, the initialization storage unit 1031 not only clears the third storage RAM 1038 and the second storage RAM 1037, but also clears the first storage RAM 1036, so as to receive the channel initial information of the next frame and start the decoding work of the new frame.

[0121] During an iterative update process, after the initialization storage unit 1031 completes its initialization, the control unit 102 immediately sends a read enable signal to the addressing unit 1032. During the period when the read enable signal is present, the addressing unit 1032 continuously generates read addresses for the RAM. The intermediate transmission information read from the second storage RAM 1037 and the third storage RAM 1038 is processed by the data bit order adjustment unit 1035 and then sent to the verification node update unit library 1034 and the variable node update unit library 1033, respectively. The intermediate transmission information processed by the verification node update unit library 1034 and the variable node update unit library 1033 is then sent back to the third storage RAM 1038 and the second storage RAM 1037 for storage.

[0122] After an iteration update is completed, the variable node update unit library 1033 will generate decision information. The verification unit 104 will perform verification based on the decision information and output the verification result. The control unit 102 will choose to continue the iteration or control the verification unit 104 to output the decoding result based on the verification result of the verification unit 104.

[0123] Furthermore, in order to implement the addressing method in Embodiment 2, the present invention optimizes the initialization storage unit 1031, the addressing unit 1032, and the data bit order adjustment unit 1035 as follows.

[0124] After the initial channel information arrives, refer to Figure 14 The initialization storage unit 1031 starts from address 0 of the first storage RAM 1036 and reads the data at each address sequentially. It returns to address 0 after reading address 72. The read data is the raw data, abbreviated as DB. The lower 42 bits of DB are assigned to the higher 42 bits of the write register. Correspondingly, a bit 0 is added to the end of the channel initial information and assigned to the lower 7 bits of the write register. Then, the value in the write register is sent to the first storage RAM 1036 and the second storage RAM 1037 for storage. After this cycle is repeated 7 times, one set (511) of channel initial information can be stored in RAM according to...Figure 10 The initial channel information (8158 data) is stored in the first storage RAM 1036 and the second storage RAM 1037. After the storage of the initial channel information, the initialization storage unit 1031 informs the control unit 102 of the completion of the initialization storage.

[0125] Further, when the value in the write register is sent to the first storage RAM 1036 and the second storage RAM 1037, the corresponding relationship between the two is as shown in the table. Figure 15 WE represents write enable. Thus, the synchronous initialization storage of the first storage RAM 1036 and the second storage RAM 1037 is completed. Note that the initial information is not stored in the third storage RAM 1038, but the result of the horizontal update is stored in the third storage RAM 1038 in the subsequent iterative update process.

[0126] Further, the addressing unit 1032 is responsible for generating the read address of the RAM in the second storage RAM 1037 (the third storage RAM 1038) and the offset address used by the data bit sequence adjustment unit 1035. The method of generation is the same as that in Embodiment 2. The data bit sequence adjustment unit 1035 is implemented by a barrel shifter.

[0127] In one iteration process, the offset address changes at most once. If the starting read address of a block of RAM is 0, the offset address will not change throughout the iteration process, i.e., it remains the starting offset address. In this case, if the barrel shifter performs a complete function description on the offset address (3 bits), it is a great waste of hardware resources. Therefore, further, the present application changes the offset address (3 bits) generated by the addressing unit 1032 to an offset enable variable (1 bit). When the offset enable is 0, the barrel shifter performs a cyclic left shift on the input data according to the corresponding starting offset address. When the offset enable is 1, it represents an increment of one on the original starting offset address, and the barrel shifter performs a cyclic left shift on the input data according to the updated offset address.

[0128] In order to cooperate with the above optimization adjustment, the present application divides the barrel shifter into 7 modules, SL_1, SL_2, …, SL_7.

[0129] SL_1 outputs the input data after one storage when the offset enable is 0, and does not perform a cyclic left shift. When the offset enable is 1, it outputs the input data after a cyclic left shift of 7 bits.

[0130] SL_2 outputs the input data after a cyclic left shift of 7 bits when the offset enable is 0, and outputs the input data after a cyclic left shift of 14 bits when the offset enable is 1.

[0131] SL_3 outputs the input data after being cyclically left shifted 14 bits when the shift enable is 0, and outputs the input data after being cyclically left shifted 21 bits when the shift enable is 1;

[0132] SL_4 outputs the input data after being cyclically left shifted 21 bits when the shift enable is 0, and outputs the input data after being cyclically left shifted 28 bits when the shift enable is 1;

[0133] SL_5 outputs the input data after being cyclically left shifted 28 bits when the shift enable is 0, and outputs the input data after being cyclically left shifted 35 bits when the shift enable is 1;

[0134] SL_6 outputs the input data after being cyclically left shifted 35 bits when the shift enable is 0, and outputs the input data after being cyclically left shifted 42 bits when the shift enable is 1;

[0135] SL_7 outputs the input data after being cyclically left shifted 42 bits when the shift enable is 0, and outputs the input data after being cyclically left shifted 49 bits when the shift enable is 1.

[0136] According to the different starting shift address of the RAM in the second storage RAM 1037 (or the third storage RAM 1038), the output data of the RAM is connected with the corresponding SL_i, i=1, 2, …, 7, for example, if the starting shift address of a block of RAM is 2, the output data of the RAM is connected with SL_2. In this way, the barrel shifter can achieve the function of the original circuit, and the hardware resources consumed can be greatly reduced.

[0137] Further, Figure 16 The structure diagram of the check node updating unit, wherein the symbol operation unit is based on a tree operation structure, and is divided into 6 levels, and is responsible for completing the calculation and processing of the symbol bits of the input data in the horizontal update.

[0138] Further, the application inserts a 6-level pipeline in the check node updating unit, the first level completes the absolute value operation of the input data, the second to fifth levels of the "companion minimum value comparator" find the second minimum value, the minimum value and the position index of the minimum value of the input data, and the sixth level assigns the corrected minimum value or second minimum value to the low 6 bits of the 32 output data according to the minimum value position index obtained by the comparator, and assigns the output bits of the symbol operation unit to the highest bits of the 32 output data. Here, 32 data are processed in parallel, because the row weight of the H matrix is 32.

[0139] Further, Figure 17This is a schematic diagram of the variable node update unit. In this invention, a 6-stage pipeline is inserted into the variable node update unit. Stage 1 converts the input data into signed numbers. Stages 2 through 5 complete the vertical update. Stage 6 limits the output data from stage 5 and outputs it. Four data points are processed in parallel because the H matrix has four column weights.

[0140] In the initial addition operations, the number of bits is increased to prevent overflow. For example, the number of signed bits is increased from 7 to 9. However, the final processed data is still converted back to a 7-bit signed number for storage in RAM. Therefore, the banding operation converts the 9-bit signed number to a 7-bit signed number. In other words, the data range is converted from [-128, 127] to [-32, 31].

[0141] The calculation process of the above-described pipeline from level 2 to level 5 is similar to the calculation process of the variable node update unit in step S102 of the overlapping partial parallel decoding algorithm described above.

[0142] like Figure 18 This is a complete timing diagram of the decoder's iterative process after the addition of the pipeline, where CNU is the check node update unit and VNU is the variable node update unit. At time t0, VNU has reached the 4th stage of the pipeline, meaning it has completed the vertical update. The calculation has been completed, thus satisfying the preconditions for the decision, and the decision calculation in step S103 can be performed, that is: if L(q) j If ) < 0, then c j =1, otherwise c j =0. Therefore, at time t0, the verification enable is started, and the decision bit is generated immediately.

[0143] In the pipeline of the variable node update unit, the first stage, which converts the input data into signed numbers, should ideally be completed by the check node update unit in the last stage. This invention assigns this part of the combinational logic circuit to the variable node update unit, thereby balancing the delay path lengths of the check node update unit and the variable node update unit. In other words, the pipeline stages of the variable node update unit and the check node update unit are equal, allowing them to complete their respective iterative update processes synchronously within the same clock cycle. Conversely, if the two pipeline stages are different, for example, one is 4 stages and the other is 8 stages, then one iteration requires waiting for the 8-stage update unit to complete its iteration before it can be completed. This invention's design of setting the pipeline stages of both equal not only reduces the number of clock cycles required for the decoder to complete one iteration but also synchronizes the operating speeds of the check node update unit and the variable node update unit, reducing the design complexity of the control unit 102 state machine.

[0144] Example Two

[0145] Further, as shown in Figure 7 the present application provides a storage addressing method more suitable for high parallel decoder, which not only avoids address access conflict problem, but also is simple and efficient.

[0146] As shown in Figure 7 the method comprises:

[0147] S201: allocating a RAM array;

[0148] S202: storing channel initial information in the RAM array by means of bit splicing;

[0149] S203: calculating the starting read address and starting offset address of the RAM in the RAM array, and saving;

[0150] S204: generating the read address and offset address of the RAM;

[0151] S205: reading the information in the RAM according to the read address of the RAM, and sending the information after data bit sequence adjustment according to the offset address to the check node update unit or variable node update unit for processing;

[0152] S206: writing the information processed by the check node update unit or variable node update unit into the corresponding RAM in sequence.

[0153] The above steps S204 to S206 are executed in sequence at each iteration.

[0154] Further, for step S201, it includes allocating a RAM array for channel initial information and allocating a RAM array for intermediate transmission information.

[0155] Further, Figure 8 as shown in the array distribution diagram of the RAM in the first storage RAM 1036 for storing channel initial information, there are 16 RAMs in total, according to the definition of the sub-cyclic matrix A in the check matrix H, two sub-cyclic matrices A in each column in the following formula share the same RAM, for example, A1,1 and A2,1 share the same RAM.

[0156]

[0157] Among them, each 511 channel initial information is divided into a group, and one RAM is responsible for storing one group of channel initial information. The first group only contains 493 channel initial information, because there are 18 frozen bits 0 before the information bits, and the last two channel initial information are padding information, which can not be received.

[0158] Further, Figure 9 The array distribution of the storage RAMs for storing the intermediate passing information is shown. Since the element 1 in the check matrix represents the certain connection between the check node and the variable node for passing information, the intermediate passing information in the present application is set to include the vertical update information (generated in vertical update) and the horizontal update information (generated in horizontal update), and the storage RAMs for storing the intermediate passing information are divided into the second storage RAM 1037 and the third storage RAM 1038, the second storage RAM 1037 is used for storing the vertical update information, and the third storage RAM 1038 is used for storing the horizontal update information.

[0159] Specifically, according to the definition of the check matrix H, there are two elements 1 in a trace of a sub-cyclic matrix A, thus four blocks of RAMs are allocated to each sub-cyclic matrix A, two belong to the second storage RAM 1037 and are used for storing the vertical update information of the sub-cyclic matrix A in the iterative update, and the other two belong to the third storage RAM 1038 and are used for storing the horizontal update information of the sub-cyclic matrix A in the iterative update. Thus, Figure 9 The array distribution of the storage RAMs for storing the vertical update information or the horizontal update information is shown, that is, the RAM array for storing the vertical update information includes 64 blocks of RAMs, and the RAM array for storing the horizontal update information also includes 64 blocks of RAMs.

[0160] Further, for the step S202, further comprising:

[0161] The check matrix H is evenly divided into 14 blocks according to the rows and evenly divided into 112 blocks according to the columns, and each block of the divided minimum sub-matrix has a size of 73x73, and the iterative update is simultaneously performed on each minimum sub-matrix. In this way, the sub-cyclic matrix A with a size of 511x511 can be refined into 7 minimum sub-matrices B with a size of 73x73, so as to further improve the parallel computing rate. When the minimum sub-matrix is 73x73, the decoder only needs 73+α clock cycles to complete one iteration process, wherein α is related to the number of pipeline stages inserted in the decoder. As shown in Embodiment 1, 6-stage pipelines are added in the check node update unit and the variable node update unit, respectively, and then 73+5=78 clock cycles are required to complete one iteration process.

[0162] Further, each channel initial information input to the LDPC decoder after demodulation is also stored after amplitude quantization, that is, a (6, 7) quantization mode is adopted, that is, the channel initial information is quantized by 6 bits and the intermediate transfer information is quantized by 7 bits. That is, the channel initial information adopts 1 bit sign bit and 5 bits absolute value, and the intermediate transfer information has one more decimal bit than the initial information. For example, for a frame of received channel initial information, which contains 8176 bits of channel initial information, each bit of the channel initial information to be processed is quantized into 6 bits and then stored.

[0163] Specifically, referring to Figure 23 In designing the LDPC decoder, the information variable in the decoding process needs to be fixed-point quantized, thus causing a partial loss of decoding performance. Obviously, the more the number of quantization bits, the smaller the loss of decoding performance, but the more the hardware resource consumption. To determine the final number of quantization bits of the decoder, three quantization modes are simulated, which are expressed in the form of (x, y), where x represents the number of quantization bits of the channel initial information by the decoder, and y represents the number of quantization bits of the intermediate transfer information by the decoder. Since a correction factor less than 1 is needed in the transverse update, one decimal bit is added to the number of quantization bits of the channel initial information, so as to ensure the quantization accuracy of the decoder to the greatest extent.

[0164] From Figure 23 It can be seen that the three values (6, 7), (7, 8) and (8, 9) of the quantization mode (x, y) correspond to three different curves, the horizontal axis is the bit signal-to-noise ratio Eb / N0, and the vertical axis is the bit error rate (also referred to as the error rate).

[0165] When the bit signal-to-noise ratio Eb / N0 is less than 3.0, the three curves are basically coincident, that is, when the bit signal-to-noise ratio Eb / N0 < 3.0, the bit error rates of the three curves decrease at a consistent rate with the increase of the bit signal-to-noise ratio Eb / N0.

[0166] When the bit signal-to-noise ratio Eb / N0 > 3.0, the bit error rates of the three curves decrease at different rates with the increase of the bit signal-to-noise ratio Eb / N0. It can be seen that at this time, at any bit signal-to-noise ratio value (for example, when the bit signal-to-noise ratio Eb / N0 = 3.5), the bit error rate gradually decreases with the increase of the number of quantization bits in the quantization mode, that is:

[0167] The bit error rate of (8, 9) < the bit error rate of (7, 8) < the bit error rate of (6, 7).

[0168] Furthermore, when the bit signal-to-noise ratio (Eb / N0) > 3.0, as the Eb / N0 increases, the bit error rate (BER) of (7, 8) decreases less compared to (6, 7), while (8, 9) shows a greater BER decrease compared to (6, 7), but higher quantization bits also require more hardware resources. Therefore, this invention selects (6, 7) quantization as the optimal method.

[0169] Furthermore, multiple initial channel information or intermediate transmission information are stored in a single address in RAM by bit concatenation, specifically by linking the first and last bits together. For example... Figure 10 The diagram shown illustrates the storage of a set of initial channel information. Figure 10 Seven squares of the same gray level represent a memory address in RAM. The seven data points in an address are assigned offsets of 1-7 in order from left to right, and adjacent data points are spaced 73 bits apart. Each data point contains seven bits.

[0170] Furthermore, by setting the bit width of a RAM block to 49 and the depth to 73, a set of initial channel information of length 511 can be stored in a single RAM block through bit concatenation, where 511 represents the number of data items, and each data item contains 6 bits. This concatenation method improves the parallelism of decoded data processing and simplifies the implementation of simultaneous horizontal and vertical updates.

[0171] Furthermore, in steps S203 to S206, in order to more efficiently realize the reading and writing of intermediate transmitted information by the verification node update unit and the variable node update unit, the following steps were used: Figure 11 The "simplified reading and simplified writing" memory addressing mode is shown. During reading, the data is read from the real-time generated read address, and the data bit order is adjusted according to the real-time generated offset address before being output to the variable node update unit or the check node update unit. During writing, the information processed by the variable node update unit or the check node update unit is directly concatenated bit by bit and written sequentially to the corresponding RAM, starting at address 0, without requiring the calculation and addressing operations of the read address and offset address during reading.

[0172] Specifically, each RAM block in the second storage RAM 1037 and the third storage RAM 1038 has a corresponding start read address, start offset address, and offset address. The offset address is marked as OA (3 bits).

[0173] Further, step S203 calculates the starting read address and the starting offset address using the following method:

[0174] For the 64 RAM blocks in the second storage RAM1037:

[0175] Firstly, the positions of the 64 elements 1 in the first and 512th rows of the check matrix H are searched to obtain first position indexes;

[0176] Secondly, the first position indexes are all normalized to the interval (1, 511) to obtain second position indexes; wherein the second position index is the remainder obtained by dividing the first position index by 511, and if the first position index is less than 511, the second position index is also assigned the value of the first position index.

[0177] Thirdly, the interval (1, 511) is divided into 7 sub-intervals with an interval of 73, and the starting offset addresses of 1-7 are respectively assigned to the corresponding RAMs according to the different sub-intervals in which the second position indexes are located; wherein the starting offset address is obtained by dividing the second position index by 73 and then rounding up.

[0178] Fourthly, the second position indexes are all normalized to the interval (1, 73) to obtain third position indexes, and the starting read addresses are obtained by subtracting 1 from the third position indexes; wherein the third position index is the remainder obtained by dividing the second position index by 73.

[0179] For the 64 blocks of RAM in the third storage RAM 1038, the position indexes of the 64 elements 1 in the 511*n+1th column (n=0, 1, …, 15) of the check matrix H are searched first, and other operations are the same as described above, which are as follows:

[0180] Firstly, the positions of the 64 elements 1 in the 511*n+1th column of the check matrix H are searched to obtain first position indexes, wherein n is an integer and takes values of n=0, 1, …, 15 in turn;

[0181] Secondly, the first position indexes are all normalized to the interval (1, 511) to obtain second position indexes; wherein the second position index is the remainder obtained by dividing the first position index by 511;

[0182] Thirdly, the interval (1, 511) is divided into 7 sub-intervals with an interval of 73, and the starting offset addresses of 1-7 are respectively assigned to the corresponding RAMs according to the different sub-intervals in which the second position indexes are located; wherein the starting offset address is obtained by dividing the second position index by 73 and then rounding up.

[0183] Fourthly, the second position indexes are all normalized to the interval (1, 73) to obtain third position indexes, and the starting read addresses are obtained by subtracting 1 from the third position indexes; wherein the third position index is the remainder obtained by dividing the second position index by 73.

[0184] Further, the calculation process of the starting read addresses and the starting offset addresses of the 64 blocks of RAM in the second storage RAM 1037 is given as follows:

[0185] where the first index position of the element 1 in the 1st row and the 512th row of the check matrix H is denoted as RA1st 1,j and RA1st 512,j , j = 1, 2, …, 32, the starting offset address is denoted as OA1st 1,j and OA1st 512,j , j = 1, 2, …, 32.

[0186] First step, search the first position index of the element 1 in the 1st row of the check matrix H:

[0187] P 1,j = find(H(1, :) == 1); j = 1, 2, …, 32;

[0188] Second step, normalize P 1,j and P 512,j to the interval [1-511]:

[0189] for j = 1:32

[0190] while P 1,j > 511

[0191] P 1,j = P 1,j - 511;

[0192] end

[0193] End

[0194] Third step, according to the different intervals of P 1,j , assign different starting offset addresses:

[0195] Switch P 1,j

[0196] Case [1, 73]

[0197] OA1st 1,j = 1;

[0198] Case [74, 146]

[0199] OA1st 1,j = 2;

[0200] Case [147, 219]

[0201] OA1st 1,j = 3;

[0202] Case [220, 292]

[0203] OA1st1,j = 4;

[0204] Case [293, 365]

[0205] OA1st 1,j = 5;

[0206] Case [366, 438]

[0207] OA1st 1,j = 6;

[0208] Case [439, 511]

[0209] OA1st 1,j = 7;

[0210] end

[0211] Fourth step, P 1,j and P 512,j normalized to the interval [0~72]:

[0212] for j = 1:32

[0213] while P 1,j > 73

[0214] P 1,j = P 1,j - 73;

[0215] end

[0216] while P 512,j > 73

[0217] P 512,j = P 512,j - 73;

[0218] end

[0219] P 1,j = P 1,j - 1;

[0220] P 512,j = P 512,j - 1;

[0221] End

[0222] Further, after the start read address and the start offset address are calculated by the above method in step S203, the start read address and the start offset address are saved for subsequent multiple iterations. Once the start read address and the start offset address are calculated, they will not be modified, that is, they are unique constant data for the decoder in the present application. Therefore, the start read address and the start offset address can be saved in a local file readable by the decoder, or can be initialized and written into the addressing unit of the decoder when the decoder is started, for subsequent iterations to calculate new read addresses and offset addresses.

[0223] Further, step S204 includes: in each iteration, the read address is sequentially increased by 1 with the arrival of the system clock rising edge, and when the read address is 72, the next clock will return to address 0. The offset address is increased by 1 when the read address returns from address 72 to address 0, and remains unchanged at other times.

[0224] Further, step S205 includes: the data bit sequence adjustment is implemented by using a barrel shift register, and the input data is output after being circularly left shifted according to the value of the offset address OA. For example: OA = 1, the input data remains unchanged; OA = 2, the input data is circularly left shifted by 7 bits; OA = 3, the input data is circularly left shifted by 14 bits; and so on, the value of OA is an integer from 1 to 7. After such circular processing, the output data is sent to the variable node update unit and the check node update unit for subsequent calculation and processing.

[0225] Further, step S206 includes: the output data of the variable node update unit or the check node update unit is bit spliced according to a specific order, and then written into the corresponding RAM with 0 address as the start address.

[0226] Specifically, the present application takes the L1 trajectory in Figure 1 as an example to illustrate the specific data reading and writing process of the corresponding horizontal update and vertical update of the trajectory.

[0227] As shown in Figure 1 , the position index of the first row element 1 is 177, and the start read address of the second storage RAM 1037 is calculated to be 30 and the start offset address is calculated to be 3. Specifically, at this time, 177 is less than 511, so the second position index is 177, and the start offset address is obtained by dividing 73 and taking the integer part. The third position index is the remainder 31 after 177 is divided by 73, and 31-1 = 30, so 30 is the start read address.

[0228] Specific reference is made to Figure 12a- The transverse updating process shown in Fig. 8: When the iteration process starts, the read address will slide back from address 30 one by one, while the offset address will remain unchanged until the read address returns to address 0 from address 72, then the offset address will be increased by 1 to 4. When the check node updating unit (variable node updating unit) starts to output data, the output data of the check node updating unit will be bit-spliced in the order from top to bottom, and then written into the third storage RAM 1038 starting from address 0.

[0229] Figure 12a The read pointer points to the starting read address 30 of the second storage RAM, and the starting offset address OA is 3. The data read out from the starting read address 30 of the second storage RAM is obtained, and then the bit sequence of the read-out data is adjusted. Since the starting offset address OA = 3, it needs to be left-shifted by two data bits. For example, it can be seen that the "3" in the input data in Fig. 8 is obtained by circularly left-shifting the "3" in the read-out data by 2 data bits. Then, the input data is processed into check node updating unit output data D1D2D3D4D5D6D7, which is bit-spliced into write data D1D2D3D4D5D6D7 and then written into the third storage RAM at the address 0 corresponding to the write pointer for storage. It should be noted that the adjustment of the bit sequence here refers to the adjustment of the data bits, and when each data is represented by 7 bits, the corresponding bit positions adjusted by the circular left shift are 2*7 = 14 bit positions. Figure 12a

[0230] Figure 12b The read pointer points to the read address 72 of the second storage RAM, and the offset address OA is 3. The data read out from the read address 72 of the second storage RAM is obtained, and then the bit sequence of the read-out data is adjusted. Since the offset address OA = 3, it needs to be left-shifted by two data bits, similar to Fig. 8. Then, the input data is processed into check node updating unit output data D1D2D3D4D5D6D7, which is bit-spliced into write data D1D2D3D4D5D6D7 and then written into the third storage RAM at the address 42 corresponding to the write pointer for storage. Figure 12a

[0231] Figure 12c The read pointer points to the read address 0 of the second storage RAM, and the offset address OA is increased by 1 to 4. The data read out from the read address 0 of the second storage RAM is obtained, and then the bit sequence of the read-out data is adjusted. Since the offset address OA = 4, it needs to be left-shifted by three data bits, that is, 3*7 = 21 bits. Then, the input data is processed into check node updating unit output data D1D2D3D4D5D6D7, which is bit-spliced into write data D1D2D3D4D5D6D7 and then written into the third storage RAM at the address 43 corresponding to the write pointer for storage. As shown in Fig. 8, the "3" in the input data is obtained by circularly left-shifting the "3" in the read-out data by 2 data bits.​​Figure 12a As shown in -c, the write pointers correspond to 0, 42 and 43 respectively, so the third storage RAM is sequentially written without offset address. Thus, the process of complicated reading and simple writing is realized.

[0232] Further, referring to Figure 1 , when updating vertically, the position index of the first column element 1 is 336, and after calculation, the starting read address of the third storage RAM 1038 is 43 and the starting offset address is 5. Specifically, at this time, 336 is less than 511, so the second position index is 336, and the starting offset address is obtained by dividing 73 and rounding up. The third position index is the remainder 44 after 336 is divided by 73, and 44-1=43, so 43 is the starting read address.

[0233] Specifically referring to Figure 13a The vertical updating process shown in -c is similar to the horizontal updating process, which is also complicated reading and simple writing.

[0234] Figure 13a The read pointer points to the starting read address 43 of the third storage RAM, and the offset address OA is 5, so the read data is read from the starting read address 43 of the third storage RAM, and the read data is adjusted in bit sequence. Since the offset address OA=5, it needs to be left shifted by 4 data bits, for example, it can be seen that Figure 13a The "5" in the input data in -c is obtained by cyclically left shifting the "5" in the read data by 4 data bits. Then, the input data is processed into variable node update unit output data D1D2D3D4D5D6D7, which is spliced into write data D1D2D3D4D5D6D7 and stored in the address 0 corresponding to the write pointer in the second storage RAM. It should be noted that here the bit sequence adjustment refers to the adjustment of data bits, and when each data is represented by 7 bits, the corresponding cyclically left shifted bit is 2*7=14 bits.

[0235] Figure 13b The read pointer points to the read address 72 of the third storage RAM, and the offset address OA is 5, so the read data is read from the read address 72 of the third storage RAM, and the read data is adjusted in bit sequence. Since the offset address OA=5, it needs to be left shifted by 4 data bits, similar to Figure 13a Then, the input data is processed into variable node update unit output data D1D2D3D4D5D6D7, which is spliced into write data D1D2D3D4D5D6D7 and stored in the address 29 corresponding to the write pointer in the second storage RAM.

[0236] Figure 13cThe read pointer points to the read address 0 of the third storage RAM, the offset address OA is added 1 at this time, and becomes 6. Then, the read data is read out from the read address 0 of the third storage RAM, the read data is obtained, and the bit sequence of the read data is adjusted. Since the offset address OA is 6, the read data needs to be left shifted by 5 data bits, that is, 5*7=35 bits. Then, the input data is processed into the variable node update unit output data D1D2D3D4D5D6D7, and is spliced into the write data D1D2D3D4D5D6D7 according to the bit, and is stored in the address 30 corresponding to the write pointer in the second storage RAM.

[0237] Example Three

[0238] Further, with reference to Figures 18-22 , the present application optimizes the design of the check unit.

[0239] The check unit is mainly responsible for checking the decoding result generated after each iteration and counting the number of iterations. The conventional check method is H·c T =0, that is, the decoding result is substituted into the check matrix H to calculate the check value. If the check value is 0, the decoding is correct, and the decision bits are output. Otherwise, the decoding is incorrect, and the iteration is selected to continue or the decoding is exited. However, this check method is complex to realize through a hardware circuit, and the clock cycle required in the check process is long, which does not meet the design requirements of high-speed decoding.

[0240] The present application proposes a more practical check method suitable for an LDPC decoder, as shown in Figure 19 , comprising the steps of:

[0241] S301: In the Nth iteration update, the decision result generated by the iteration update is stored as the Nth decision result, wherein N is a positive integer greater than or equal to 1;

[0242] S302: The Nth decision result is compared and checked with the (N-1)th decision result to obtain the Nth check result. The Nth check result is the same or different.

[0243] S303: The Nth check result is judged. If the Nth check result is the same or N reaches the maximum iteration number, the step S304 is jumped to. Otherwise, the present check is ended.

[0244] S304: The decoding result is output.

[0245] Specifically, the decision result is composed of bits with values of 1 or 0. All the decision results obtained when one iteration is completed are spliced to obtain the complete decoding result.

[0246] The above method is actually comparing the decoding result of the current iteration with the decoding result of the last iteration. If the two decoding results are the same, it is considered that the decoding is completed, otherwise the iteration is continued until the maximum number of iterations is reached. This method is based on the convergence of the decoding algorithm, that is, when the decoding is correct, the result of the iteration should also be correct, so the complexity of the hardware circuit implementation is reduced.

[0247] Further, the step S302 further comprises:

[0248] S3021: the Nth decision result comprises a plurality of Nth decision bits generated in real time at different times;

[0249] S3022: comparing each newly generated Nth decision bit at a time with the N-1th decision bit at the corresponding time;

[0250] S3023: when the comparison result is different, stopping the comparison and verification, and confirming that the Nth verification result is different.

[0251] Among them, the N-1th decision bit at the corresponding time refers to the N-1th decision bit generated at the same time in the last iteration update.

[0252] Specifically, assuming that the Nth decision result is a bit set b = [b1, b2, …, bM], wherein bM is the Nth decision bit newly generated at the Mth time;

[0253] Correspondingly, assuming that the N-1th decision result is a bit set a = [a1, a2, …, aM], wherein aM is the N-1th decision bit newly generated at the Mth time;

[0254] Then, step S3022 refers to comparing bM and aM at the Mth time.

[0255] Specifically, as described in Embodiment Two, the iteration update time is equal to the iteration update time of a minimum sub-matrix each time, for example, the minimum sub-matrix is 73*73, and 73 clocks are needed to complete one iteration update. Correspondingly, each minimum sub-matrix will generate decision bits at 73 times in turn. Assuming that the comparison result is the same from the 1st time to the 49th time, the comparison and verification at the 50th time is continued. When the comparison and verification result at the 50th time is different, the comparison and verification is stopped, and it is confirmed that the verification result of the current iteration update is different, so it is not necessary to compare all the decision bits at 73 times to get the result.

[0256] It can be seen that, since the code length of the LDPC code adopted by the present application is 8176 bits, if a direct check is performed, two registers with a length of 8176 bits are required, one for storing the decoding result of the last iteration and one for storing the decoding result of the current iteration, and then the two are compared completely. However, by using the method of comparing in real time at each moment, the continuously input decision bits can be compared in real time, and once a decision bit is detected to be inconsistent with the last iteration, the decoding result of the current iteration is determined to be wrong regardless of whether the subsequent decision bits are the same or not. In this way, the LDPC code generated by the complete comparison of two iterations is not required, and once a different bit is detected in the middle, the current check result is confirmed to be different, so that the decoding result of the current iteration is determined to be wrong, thereby obtaining the check result before obtaining the complete decoding result of the current iteration, further improving the efficiency and saving the storage resources.

[0257] Further, in order to save storage space and further improve the calculation efficiency, the storage scheme of the check unit adopted by the present application is specifically described as follows.

[0258] Further, step S301 further comprises:

[0259] The check matrix H of the LDPC code is evenly divided into 14 blocks according to the rows and evenly divided into 112 blocks according to the columns, so as to divide the sub-circulation matrix A with a size of 511x511 into 7 minimum sub-matrices B with a size of 73x73, and each minimum sub-matrix B is simultaneously updated at each iteration update.

[0260] The number of bits in a group of decision bits generated in real time at the same moment is determined to be 98;

[0261] Correspondingly, 98 decision bit registers with a length of 73 bits are set for storing the decision bits.

[0262] Specifically, Figure 2 The transmission frame structure of the (8176, 7154) LDPC code specified by CCSDS is given. As shown in Figure 2 Since the first 18 bits are frozen bits 0 and are not transmitted, a complete transmission frame only contains 8160 bits, of which the first 7136 bits are information bits, the middle 1022 bits are check bits, and the last two bits are padding bits 0. As known from the foregoing embodiment, the check matrix H of the LDPC code is evenly divided into 14 blocks according to the rows and evenly divided into 112 blocks according to the columns, so as to divide the sub-circulation matrix A with a size of 511x511 into 7 minimum sub-matrices B with a size of 73x73, and each minimum sub-matrix B is simultaneously updated at each iteration update.

[0263] 7136+18=7154=73*98;

[0264] From the above calculation, it can be deduced that the 7136-bit information bits of the LDPC code contain at most 98 73x73 minimum sub-matrices B, so the number of the decision bits generated at the same time is determined to be 98 when updating each iteration.

[0265] Further, the step S301 further comprises:

[0266] The decision bits generated at different times are stored in the decision bit registers in order from low to high;

[0267] When a group of decision bits is stored, the bit data in each decision bit register is first shifted left by one bit, and then each decision bit is stored in the 0th bit of a decision bit register, respectively, and each decision bit register stores one decision bit, and the 0th bit is the lowest bit.

[0268] When the Nth decision result is stored, the (N-1)th decision result stored in the decision bit register is overwritten, so that the decision bit register is recycled.

[0269] Further, the step S302 further comprises:

[0270] When a group of decision bits is stored, the highest decision bit in the decision bit register is removed and forms another group of decision bits, and the two groups of decision bits are compared and verified, and the comparison result is recorded, which is the same or different.

[0271] Further, the step S302 further comprises:

[0272] When the comparison and verification is performed, the 98 decision bits generated in the current iteration are obtained by bit splicing to obtain the current decision comparison signal, the highest decision bit in the decision bit register before left shifting is obtained by bit splicing to obtain the last decision comparison signal, and then the current decision comparison signal and the last decision comparison signal are compared to obtain the comparison result.

[0273] The specific implementation is as follows:

[0274] Reference Figure 18 , wherein CNU is a check node update unit, and VNU is a variable node update unit. When the decoder proceeds to the fourth level of the variable node update unit (or the check node update unit), i.e. Figure 18 , the t0 moment, the first group (98) of decision bits is generated, the check enable CE is pulled high at this time, and the check unit starts to check and store the decision bits.

[0275] Specifically, why is the number of decision bits generated each time 98? The reasons are as follows:

[0276] Reference Figure 2The frozen bits and information bits in a frame of initial channel information are 18+7136=7154. Therefore, only the first 7154 data need to be judged to obtain the real information, and the following check bits need not be considered. In the present application, the minimum sub-matrix is 73*73, and 7154=73*98. Therefore, 98 decision bits are generated each time.

[0277] Figure 20 In order to check the storage schematic diagram, in the diagram, Msg_i, i=1, 2,..., 98 are registers responsible for storing decision bits, each register has a length of 73 bits, Err is an error flag signal, the initial value is 0, 0 represents no error, and 1 represents error, Bin[97:0] is a signal obtained by bit splicing of 98 decision bits generated in this iteration, and Ref_Bin[97:0] is a signal obtained by bit splicing of the highest bits of the registers Msg_i, i=1, 2,..., 98. When the check unit detects that the check enable CE is high, the register Msg_i is left shifted by one bit and the corresponding decision bit is stored in the 0th bit. At the same time, Bin[97:0] is compared with Ref_Bin[97:0], and if they are the same, the error signal (error value) remains unchanged, otherwise the error signal (error value) is set to 1. After 73 clocks, the check unit completes the storage and preliminary check of 7154 decision bits.

[0278] The subsequent check sub-process is shown in Figure 21 The error value corresponds to the error signal described above, the current signal is Bin[97:0], and the last signal is Ref_Bin[97:0]. First, the iteration number is assigned an initial value of 0, and then the first iteration check is entered. At the beginning of each iteration check, the error value is assigned an initial value of 0, and then it is determined whether the decision bits are inputted completely. Since the decision bits are continuously generated, every time a new group of decision bits is inputted, it is necessary to determine whether the decision bits are inputted completely. If it is determined that there are new inputted decision bits, the current decision bit signal is compared with the last decision bit signal, and if the comparison result is different, the error value is assigned a value of 1, and if the comparison result is the same, the error value remains unchanged as 0. When all the decision bits are inputted completely and the comparison is completed, the error value and the iteration number are judged. If the error value is 0 or the maximum iteration number has been reached, the decoding result is outputted, otherwise the iteration number is increased by 1 and the next round of check is waited. The preferred maximum iteration number of the present application is 15.

[0279] The maximum iteration number is a key parameter affecting the performance of the LDPC decoder. Generally, the larger the iteration number, the better the decoding performance, but the decoding delay will also be increased. Therefore, in order to balance the decoding performance and the decoding delay, a suitable maximum iteration number needs to be selected.

[0280] Figure 24 The decoding performance curves corresponding to different maximum iteration numbers are given, including three maximum iteration numbers of 10, 15 and 20. In the figure, the horizontal axis is the bit signal-to-noise ratio Eb / N0, and the vertical axis is the bit error rate (also referred to as the error rate).

[0281] When the bit signal-to-noise ratio Eb / N0 is less than 3.5, the three curves are basically coincident, that is, when the bit signal-to-noise ratio Eb / N0 < 3.5, the bit error rates of the three curves decrease at a consistent rate with the increase of the bit signal-to-noise ratio Eb / N0.

[0282] When the bit signal-to-noise ratio Eb / N0 > 3.5, the bit error rates of the three curves decrease at different rates with the increase of the bit signal-to-noise ratio Eb / N0. It can be seen that at this time, at any bit signal-to-noise ratio value (for example, when the bit signal-to-noise ratio Eb / N0 = 3.8), the bit error rate gradually decreases with the increase of the maximum iteration number, that is:

[0283] The bit error rate of 20 < the bit error rate of 15 < the bit error rate of 10.

[0284] Further, when the bit signal-to-noise ratio Eb / N0 > 3.5, with the increase of the bit signal-to-noise ratio Eb / N0, the bit error rate of the maximum iteration number of 15 decreases at a larger rate relative to the maximum iteration number of 10, and the bit error rate of the maximum iteration number of 20 decreases at a smaller rate relative to the maximum iteration number of 15, thereby indicating that the decoding performance is significantly improved when the maximum iteration number changes from 10 to 15, and the decoding performance is relatively small when the maximum iteration number changes from 15 to 20. Therefore, in the case of ensuring the decoding performance, in order to obtain a higher decoding rate (lower decoding delay), the maximum iteration number is selected as 15 in this paper.

[0285] The above verification storage mode only needs 98 registers with a length of 73 bits, the length of the compared bit vectors is reduced from 8176 bits to 98 bits, and the consumption of hardware resources is greatly reduced. More importantly, the verification rate is improved from Figure 18 It can be seen that it can give the verification result at t1, that is, before the end of the current iteration process, which meets the design requirements of the high-speed decoder.

[0286] Further, the step S302 further includes:

[0287] When a group of decision bits is stored, the comparison result of the previous group of decision bits is read and judged, and when the comparison result is the same, the comparison is continued; when the comparison result is different, the current comparison is not performed.

[0288] Specifically, when a group of decision bits is stored, the comparison result of the previous group of decision bits is read and judged, and when the comparison result is the same, the comparison is continued; when the comparison result is different, the current comparison is not performed. In this way, CPU resources can be further saved, for example, when the 50th clock arrives, the comparison result is different, and the 51st clock starts to compare, saving 23 comparison calculations of two 98-bit sequences for the next 23 clocks.

[0289] Further, step S304 further comprises:

[0290] The decoding result is obtained by splicing the decision results generated by iteration update. In fact, the code word corresponding to the decoding is the decision bit in the decision result.

[0291] On the other hand, as Figure 22 shown, the present application provides a check device 201 suitable for LDPC decoder, comprising: a receiving unit 2011, a storage unit 2012, a comparison unit 2013, a control unit 2014;

[0292] The receiving unit 2011 receives the decision results generated by iteration update in the LDPC decoder and stores them in the storage unit 2012;

[0293] The storage unit 2012 stores the decision bits in the decision results generated at different times in the register according to the order from low to high, and each time a new bit is stored, the register is shifted left by one bit, so that the register is recycled;

[0294] The control unit 2014 determines when to start comparison and stop comparison, and whether to output the decoding result generated by iteration update in the LDPC decoder;

[0295] The comparison unit 2013 receives the instructions of the control unit 2014, reads the decision bits of the storage unit 2012 and performs comparison and check.

[0296] In another aspect, the present application provides an LDPC decoder comprising the above check device 201 suitable for LDPC decoder.

[0297] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structural transformation made by using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, is included in the patent protection scope of the present application.​

Claims

1. An FPGA-based LDPC decoder, characterized in that, The LDPC decoder based on FPGA comprises a receiving unit, a control unit, an iterative updating unit and a checking unit. The receiving unit receives channel initial information, sends the channel initial information to the iterative updating unit and informs the control unit. The control unit controls the iterative updating unit to start iterative updating according to the information from the receiving unit, and decides whether to proceed with the next iteration according to the checking result from the checking unit. The iterative updating unit stores the channel initial information and starts iterative updating according to the control command from the control unit, generates decision information at each iteration and outputs the decision information to the checking unit. The checking unit checks according to the decision information and outputs the checking result to the control unit. The receiving unit, the control unit, the iterative updating unit and the checking unit cooperate to perform multiple iterations and checks, complete the overlapping partial parallel decoding of the channel initial information and obtain correct decoding information. The iterative updating unit comprises an initialization storage unit, an addressing unit, a variable node updating unit library, a check node updating unit library, a data bit sequence adjustment unit and corresponding storage RAM. The storage RAM comprises a first storage RAM for storing channel initial information and a second storage RAM and a third storage RAM for storing intermediate transmission information. The intermediate transmission information comprises longitudinal updating information and transverse updating information, the second storage RAM is used for storing the longitudinal updating information and the third storage RAM is used for storing the transverse updating information. The initialization storage unit is used for storing the channel initial information and initializing the second storage RAM and the third storage RAM at the start of each iteration. The variable node updating unit library comprises a plurality of variable node updating units and the check node updating unit library comprises a plurality of check node updating units, the variable node updating units and the check node updating units are used for reading intermediate transmission information, performing iterative updating processing on the intermediate transmission information and storing the processed intermediate transmission information into the second storage RAM and the third storage RAM. The addressing unit is used for generating read addresses and offset addresses of the storage RAM, and the data bit sequence adjustment unit is used for shifting the read intermediate transmission information according to the offset addresses and sending the shifted intermediate transmission information to the variable node updating unit library and the check node updating unit library.

2. The LDPC decoder based on FPGA according to claim 1, wherein 16 blocks of RAM are allocated to the first storage RAM, 64 blocks of RAM are allocated to the second storage RAM and 64 blocks of RAM are allocated to the third storage RAM, and each block of RAM can store 511 pieces of data with a length of 7 bits.

3. The LDPC decoder based on FPGA according to claim 2, wherein ​ ​ The check matrix H of the LDPC is evenly divided into 14 blocks by rows and 112 blocks by columns, each block being a 73*73 minimum sub-matrix; a 511*511 sub-cyclic matrix is divided into 7 73*73 minimum sub-matrices, and the iteration updating unit simultaneously performs iteration updating on each minimum sub-matrix.

4. The FPGA-based LDPC decoder of claim 3, wherein, The channel initial information is stored in a bit splicing manner: each block of the RAM contains 0-72 storage addresses, each of which stores 7 data, each of which contains 7 bits; the 7 data are sequentially assigned offset addresses 1-7 from left to right, and adjacent data are spaced 73 bit sequences apart during storage, and the data are channel initial information data.

5. The FPGA-based LDPC decoder of claim 4, wherein, The initialization storage unit further comprises a write register; the bit splicing manner of storage is implemented by: Grouping the channel initial information, each group of the channel initial information containing 511 data, setting the bit width of each block of the RAM to 49 and the depth to 73; Starting from the 0 address of each block of the first storage RAM, the original data in the address are sequentially read out, and each time the address 72 is read, the address 0 is returned; The low 42 bits of the original data are assigned to the high 42 bits of the write register, and the corresponding low 7 bits of the write register are assigned after adding a bit 0 at the end of the channel initial information, and then the value in the write register is sent to the first storage RAM and the second storage RAM for storage; After the above reading and writing steps are repeated 7 times, one group of the channel initial information is stored in a bit splicing manner; After 8158 initial channel information are stored, the initialization storage unit notifies the control unit that the storage is completed.

6. The FPGA-based LDPC decoder of claim 5, wherein, At the beginning of each iteration, the initialization storage unit initializes the second storage RAM and the third storage RAM, comprising: Clearing the second storage RAM and the third storage RAM; Writing the channel initial information stored in the first storage RAM in a splicing manner into the second storage RAM.

7. The FPGA-based LDPC decoder of claim 6, wherein, The reading and writing of the intermediate transfer information comprises: Reading according to the read address generated by the addressing unit in real time, and outputting to the variable node updating unit library or the check node updating unit library after adjusting the data bit sequence according to the offset address generated by the addressing unit in real time; when writing, the intermediate transfer information processed by the variable node updating unit or the check node updating unit is directly spliced and written into the corresponding RAM with 0 address as the starting address.

8. The FPGA-based LDPC decoder of claim 7, wherein, The data bit sequence adjustment unit comprises a barrel shifter. The 3-bit offset address generated in the addressing unit is replaced by a 1-bit offset enable variable, when the offset enable variable is 0, the barrel shifter performs cyclic left shift on the input data according to the initial offset address, when the offset enable variable is 1, the offset address is updated to the initial offset address plus 1, and the barrel shifter performs cyclic left shift on the input data according to the updated offset address.

9. The FPGA-based LDPC decoder of claim 8, wherein, When the variable node updating unit and / or the check node updating unit performs iterative updating processing, a pipeline is added.

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