Memory operation using composite memory command

Abstract

Memory operations using composite memory commands are disclosed that include receiving, by a memory module, a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module, generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command, and executing the plurality of memory commands.

Description

BACKGROUND

[0001] To perform in-memory operations, the processor will need to send a large number of fine-grained memory commands. The throughput of in-memory operations will depend on the bandwidth available to send such fine-grained commands to the memory. In addition to any in-core bottlenecks that limit this command bandwidth, the bandwidth will also be impacted by the bandwidth utilization of other co-scheduled computations running in parallel on the associated core. BRIEF DESCRIPTION OF DRAWINGS

[0002] Figure 1 is a block diagram of an exemplary processor for memory operations using composite memory commands in accordance with some embodiments.

[0003] Figure 2 is a flowchart of an exemplary method for memory operations using composite memory commands in accordance with some embodiments.

[0004] Figure 3 is a flowchart of an exemplary method for memory operations using composite memory commands in accordance with some embodiments.

[0005] Figure 4 is a flowchart of an exemplary method for memory operations using composite memory commands in accordance with some embodiments.

[0006] Figure 5 is a flowchart of an exemplary method for memory operations using composite memory commands in accordance with some embodiments.

[0007] Figure 6 is a flowchart of an exemplary method for memory operations using composite memory commands in accordance with some embodiments.

[0008] Figure 7 is a flowchart of an exemplary method for memory operations using composite memory commands in accordance with some embodiments. DETAILED DESCRIPTION

[0009] In some embodiments, a method of memory operations using composite memory commands includes receiving, by a memory module, a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; generating, based on the composite memory command, a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

[0010] In some embodiments, the composite memory command indicates a start address and an end address of the plurality of portions of contiguous memory. In some embodiments, generating the plurality of memory commands comprises: determining one or more required row activation commands; and generating the one or more required row activation commands. In some embodiments, determining the one or more required row activation commands comprises: maintaining a finite state machine; and determining the one or more required row activation commands based on the finite state machine, the start address, and the end address. In some embodiments, the method further comprises determining, by the memory controller, a latency associated with the composite memory command. In some embodiments, the method further comprises prioritizing, by the memory controller, issuance of one or more other commands based on the latency. In some embodiments, the method further comprises generating, by the memory controller, a plurality of other composite memory commands based on the composite memory command in response to the latency exceeding a threshold.

[0011] In some embodiments, an apparatus for memory operations using composite memory commands comprises: a processor; and a memory controller communicatively coupled to the processor; and a memory module communicatively coupled to the memory controller, the memory module performing steps comprising: receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command; and executing the plurality of memory commands.

[0012] In some embodiments, the composite memory command indicates a start address and an end address of the plurality of portions of contiguous memory. In some embodiments, generating the plurality of memory commands comprises: determining one or more required row activation commands; and generating the one or more required row activation commands. In some embodiments, determining the one or more required row activation commands comprises: maintaining a finite state machine; and determining the one or more required row activation commands based on the finite state machine, the start address, and the end address. In some embodiments, the memory controller determines a latency associated with the composite memory command. In some embodiments, the memory controller prioritizes issuance of one or more other commands based on the latency. In some embodiments, the memory controller generates a plurality of other composite memory commands based on the composite memory command in response to the latency exceeding a threshold.

[0013] A memory controller for memory operations using a composite memory command performs steps comprising: receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in a memory module; generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command; and executing the plurality of memory commands.

[0014] In some embodiments, the composite memory command indicates a starting memory address and a number of columns as the plurality of portions of contiguous memory. In some embodiments, the composite memory command indicates a starting address and an ending address of the plurality of portions of contiguous memory. In some embodiments, generating the plurality of memory commands comprises: determining one or more required row activation commands; and generating the one or more required row activation commands.

[0015] Figure 1 is a block diagram of a non-limiting example system 100. The example system 100 can be implemented in a variety of computing devices including mobile devices, personal computers, servers, peripheral hardware components, gaming devices, set-top boxes, and the like. The system 100 includes a processor 102. The processor 102 issues instructions or commands to access a memory module 104 by issuing commands to a memory controller 106. The memory controller 106 is circuitry that manages the flow of data to and from the memory module 104. For example, the memory controller 106 manages instructions to read from and / or write to the memory module 104 from the memory module 104. The memory controller 106 also refreshes the memory module 104. In some embodiments, the memory controller 106 is an integrated component of the processor 102. In other embodiments, the memory controller 106 is a component separate from the processor 102.

[0016] The memory module 104 is a memory (e.g., volatile or non-volatile) for storing data. In example embodiments, the memory module 104 is a volatile memory module. The memory module 104 can include, for example, dynamic random access memory (DRAM). Each memory module 104 includes one or more memory banks 108. Each memory bank 108 includes a plurality of rows 110, each row 110 including a plurality of columns 112. To access data from a particular row 110, the row 110 is “activated” and stored in a row buffer of the memory bank 108. Columns 112 from the row 110 in the row buffer can then be read or written. Thus, accessing data from a particular row 110 requires closing an “open” row 110 if the particular row 110 is not already the open row 110 in the row buffer, and the particular row 110 is opened and stored in the row buffer for access.

[0017] Operations such as batch copy, batch "zeroing," or in-memory processing commands often require the processor 102 to issue multiple fine-grained commands to the memory controller 106 in order to issue to the memory module 104. Using this approach, the bandwidth between the processor 102 and the memory controller 106 is consumed by these multiple fine-grained commands and impacts the bandwidth available for other computations running on the processor 102.

[0018] In contrast, the memory module 106 is configured to receive composite memory commands from the processor 102 via the memory controller 106. A composite memory command is a single command that causes one or more operations to be applied to a contiguous region of memory (e.g., in the memory module 104). In some embodiments, the operations are operations to be applied to a particular column 112 of the memory module 104. Some examples of operations to be applied resulting from a composite memory command include a column 112 read operation, a column 112 write operation, or a column 112 move to near memory register. For example, a composite memory command for batch zeroing would cause a column 112 write operation to be applied to each column 112 in a contiguous region of memory. As another example, a memory in-memory processing command to add two arrays (e.g., two contiguous arrays in memory) is represented as multiple composite memory commands (e.g., a composite memory command to read multiple portions of each array, a composite memory command to add the multiple portions of the two arrays, and a composite memory command to write the result sum in another contiguous region of memory). In some embodiments, the composite memory command is generated by the compiler in response to determining that one or more operations are to be applied to a contiguous region of memory. In other embodiments, the composite memory command is generated by the compiler in response to an explicit declaration of the composite memory command in the program code.

[0019] In response to receiving the composite memory command, the memory module 104 generates multiple memory commands to apply the one or more operations to each of the multiple portions of contiguous memory. For example, in response to receiving a composite memory command for batch zeroing of an adjoining region of memory, the memory module 104 generates multiple column 112 write commands that, when executed, cause zero values to be written to each column 112 in the adjoining region of memory. Using this example, the memory module 104 generates the necessary row open commands (if any) and multiple write commands to the adjoining region of memory. Thus, multiple memory commands (e.g., dynamic random access memory commands) are generated from a single composite memory command. Those skilled in the art will appreciate that, in alternative embodiments, the memory controller 106 generates the multiple memory commands in response to receiving the composite memory command from the memory client (e.g., the processor 102). The memory controller 106 then provides the generated memory commands to the memory module 104 for execution.

[0020] In some embodiments, the composite memory command indicates a starting address of a region of contiguous memory and a number of columns to which the operations indicated in the composite memory command are to be applied. In other embodiments, the composite memory command indicates a starting address and an ending address of a region of contiguous memory. In some embodiments, the multiple portions of contiguous memory are contiguous within the same row 110. In other words, one or more operations are applied to portions of memory that are within the same row 110 in the memory module 104. In response to such a composite memory command, the memory module 104 generates commands that are memory commands to implement the indicated operations for each column in the region of contiguous memory. In some embodiments, the memory module 104 determines whether a row activation command (e.g., to store the row 110 in a row buffer) is needed as one of the multiple memory commands. Whether a row activation command is needed is based on whether the particular row 110 is currently activated or whether the row 110 is to be activated in response to another memory command.

[0021] In other embodiments, the multiple portions of contiguous memory are contiguous over multiple rows 110. Since the portions of contiguous memory are contiguous over multiple rows 110, at least one row activation command is needed. Accordingly, in some embodiments, the memory module 104 maintains a finite state machine. Based on the one or more memory commands needed to implement the composite memory command and the finite state machine, the memory module 104 then determines the one or more row activation commands needed.

[0022] Since the composite memory command results in multiple memory commands that occupy the storage banks 108 for a particular duration, in some embodiments, the memory controller 106 implements fairness logic to ensure that the storage banks 108 are not occupied by other commands. Accordingly, in some embodiments, the memory controller 106 is configured to calculate a delay associated with the composite memory command. In the case where the region of contiguous memory of the composite memory command is contiguous over the same row 110, the delay is estimated as, for example, a predefined delay timing for issuing a memory command to a column 112 multiplied by the number of columns 112 associated with the particular composite memory command. In some embodiments, the predefined delay timing is set as a configuration setting of the memory module, a firmware setting, or otherwise defined. In some embodiments, the memory controller 106 also uses the delay to deterministically schedule memory commands (e.g., the memory controller 106 knows to wait for a number of cycles based on the delay before issuing another command to the same memory region).

[0023] In cases where the contiguous memory region is contiguous across multiple rows 110, the latency is calculated by determining which banks 108 are associated with the contiguous memory region based on the start and end addresses of the contiguous memory region (e.g., indicated in the compound memory command or determined based on the start address in the compound memory command and the number of affected columns indicated in the compound memory command), determining the number of rows 110 associated with the compound memory command, and determining whether the first row 110 accessed in each bank 108 has already been open, thus not requiring a row activate command. These values and one or more memory timing values are then used to calculate the latency.

[0024] In some embodiments, based on the latency, the memory controller 106 prioritizes issuance of other commands (e.g., memory commands) prior to the compound memory command. For example, in some embodiments, the latency or a weighted latency is used as a threshold. Prior to issuance of the compound memory command to the memory module 104, other commands having a latency below the threshold are prioritized and issued to the memory module 104.

[0025] In other embodiments where the latency exceeds the threshold, the memory controller 106 generates multiple other compound memory commands based on the compound memory command. In some embodiments, the compound memory command associated with the contiguous memory region is generated as multiple compound memory commands corresponding to sub-portions of the contiguous memory region. For example, a compound memory command associated with a memory region that is contiguous across multiple rows 110 can be generated as multiple compound memory commands, each corresponding to one row 110 in the contiguous memory region. As another example, a compound memory command associated with a memory region that is contiguous across multiple columns 112 in the same row 110 can be generated as multiple compound memory commands, each associated with a sub-portion of the columns 112. In some embodiments, the latency of the generated compound memory commands is recalculated. Other instructions are prioritized based on the recalculated latency and / or the other compound memory commands are generated accordingly. In some embodiments, the memory controller 106 breaks up the compound memory command into multiple compound memory commands based on other rules or criteria. For example, in some embodiments, the memory controller 106 breaks up a multiple-row compound memory command into multiple single-row compound memory commands independent of latency. As another example, in some embodiments, the memory controller 106 breaks up a compound memory command into multiple compound memory commands independent of latency based on a threshold number of operations caused by the single compound memory command.

[0026] To further explain, Figure 2A flowchart showing an exemplary method for memory operations using a composite memory command is presented, the method including receiving 202 (e.g., by a memory module 104 from a memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module 104. In some embodiments, the operations are operations to be applied to a particular column 112 of the memory module 104. Examples of operations to be applied resulting from the composite memory command 204 include a column 112 read operation, a column 112 write operation, or a column 112 move to near memory register. For example, a composite memory command 204 for a bulk zeroing would result in a column 112 write operation being applied to each column 112 in the contiguous memory region.

[0027] In some embodiments, the composite memory command 204 indicates a starting address of the contiguous memory region and a number of columns to which the operations indicated in the composite memory command are to be applied. In other embodiments, the composite memory command 204 indicates a starting address and an ending address of the plurality of portions of contiguous memory. In some embodiments, the plurality of portions of contiguous memory are contiguous within the same row 110. In other embodiments, the plurality of portions of contiguous memory are contiguous across multiple rows 110.

[0028] Figure 2 The method of FIG. 1 further includes generating 206 (e.g., by the memory module 104) a plurality of memory commands 210 to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204. Generating 206 the plurality of memory commands 210 includes generating one memory command 210 for each column 112 in the contiguous memory. The memory command 210 indicates the operation in the composite memory command 204. In some embodiments, generating 206 the plurality of memory commands 210 further includes generating one or more row activation commands required to activate the row 110 affected by the memory command 210.

[0029] Figure 2 The method of FIG. 1 further includes executing 208 (e.g., by the memory module 104) the plurality of memory commands 210. Thus, only a single composite memory command 204 needs to be communicated over the bus or connection between the processor 102 and the memory controller 106 and the bus or connection between the memory controller 106 and the memory module to cause the memory module 104 to execute the plurality of memory commands 210.

[0030] To further explain, Figure 3A flow diagram showing an exemplary method for memory operations using a composite memory command is presented, the method including receiving 202 (e.g., by a memory module 104 from a memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module 104; generating 206 (e.g., by the memory module 104) a plurality of memory commands 210 to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204; and executing 208 (e.g., by the memory module 104) the plurality of memory commands 210.

[0031] Figure 3 The method of Figure 2 differing from the method of generating 206 (e.g., by the memory module 104) the plurality of memory commands 210 to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204 includes determining 302 one or more required row activation commands. In some embodiments, where the contiguous memory is contiguous on the same row 110, determining 302 the one or more required row activation commands includes determining whether the row 110 is activated (e.g., open, stored in a row buffer). In some embodiments, where the contiguous memory is contiguous on a plurality of rows 110, determining 302 the one or more row activation commands includes determining whether a first accessed row 110 in each bank 108 of the contiguous memory is open. In other embodiments, where the contiguous memory is contiguous on a plurality of rows 110, the one or more row activation commands are determined 302 based on a finite state machine.

[0032] generating 206 (e.g., by the memory module 104) the plurality of memory commands 210 to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204 includes generating 304 the one or more required row activation commands. Thus, the memory commands 210 executed 208 include the one or more required row activation commands.

[0033] Figure 4 To further explain,A flow diagram illustrating an exemplary method for memory operations using a composite memory command is presented, the method comprising (e.g., by a memory module 104 from a memory controller 106) receiving 202 a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of a plurality of portions of contiguous memory within the memory module 104; generating 206 (e.g., by the memory module 104) a plurality of memory commands 210 to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204 including: determining 302 one or more required row activation commands; and generating 304 the one or more required row activation commands; and executing 208 (e.g., by the memory module 104) the plurality of memory commands 210.

[0034] Figure 4 The method of Figure 3 differs from the method of in that determining 302 the one or more required row activation commands includes maintaining 402 a finite state machine. The finite state machine can indicate which one or more rows 110 (e.g., one or more rows 110 stored in a row buffer of a respective bank 108) are activated are memory commands 210 to be executed. The finite state machine can be maintained (e.g., updated) by generating the plurality of memory commands and then updating the finite state machine to determine which rows 110 need to be activated and in what order the rows 110 should be activated to execute a particular memory command.

[0035] Determining 302 the one or more required row activation commands further includes determining 404 the one or more row activation commands based on the finite state machine. For example, a row activation command is generated in response to a transition in the finite state machine indicating that a particular row 110 needs to be activated.

[0036] Figure 5 To further explain, A flow diagram illustrating an exemplary method for memory operations using a composite memory command is presented, the method comprising (e.g., by a memory module 104 from a memory controller 106) receiving 202 a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of a plurality of portions of contiguous memory within the memory module; generating 206 (e.g., by the memory module 104) a plurality of memory commands 210 to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204; and executing 208 (e.g., by the memory module 104) the plurality of memory commands 210.

[0037] Figure 5 The method of Figure 2 differs from the method of Figure 5The method of includes determining 502 (e.g., by the memory controller 106) a delay associated with the composite memory command 204. In cases where the contiguous memory region of the composite memory command 204 is contiguous on the same row 110 of the memory module 104, the delay is estimated as a predefined delay timing for issuing memory commands to the column 112 multiplied by the number of columns 112 associated with the particular composite memory command 204. In some embodiments, the predefined delay timing is set as a configuration setting, firmware setting, or otherwise defined for the memory module 104.

[0038] In cases where the contiguous memory region is contiguous on multiple rows 110 of the memory module 104, the delay is calculated by determining which banks 108 are associated with the contiguous memory region based on the start and end addresses indicated in the composite memory command 204, determining the number of rows 110 associated with the composite memory command 204, and determining whether the first row 110 accessed in each bank 108 has already been open, thus not requiring a row activation command. These values are then used with one or more memory timing values to calculate the delay.

[0039] To further explain, Figure 6 A flowchart showing an example method for memory operations using composite memory commands is presented, the method including determining 502 (e.g., by the memory controller) a delay associated with the composite memory command 204; receiving 202 (e.g., by the memory module 104 from the memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of a plurality of portions of contiguous memory of the memory module 104; generating 206 (e.g., by the memory module 104) a plurality of memory commands 210 to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204; and executing 208 (e.g., by the memory module 104) the plurality of memory commands 210.

[0040] Figure 6 The method of differs from Figure 5 in that, Figure 6 The method of includes prioritizing 602 issuance of one or more other commands based on the delay. For example, in some embodiments, the delay or a weighted delay is used as a threshold. Prior to the composite memory command 204, other commands having a delay below the threshold are prioritized and issued to the memory module 104.

[0041] To further explain, Figure 7A flowchart showing an exemplary method of memory operations for using a composite memory command is presented, the method comprising (e.g., by a memory controller) determining 502 a delay associated with a composite memory command 204; receiving 202 (e.g., by a memory module 104 from a memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of a plurality of portions of contiguous memory of a memory module 104; generating 206 (e.g., by the memory module 104) a plurality of memory commands 210 to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204; and executing 208 (e.g., by the memory module 104) the plurality of memory commands 210.

[0042] Figure 7 The method of Figure 5 differs from the method of Figure 6 in that the method of comprises generating 206 (e.g., by the memory controller 106) a plurality of other composite memory commands based on the composite memory command 204 in response to the delay exceeding the threshold. In some embodiments, the composite memory command 204 associated with a contiguous memory region is generated as a plurality of composite memory commands corresponding to sub-portions of the contiguous memory region. For example, a composite memory command 204 associated with a memory region that is contiguous over a plurality of rows 110 can be generated as a plurality of composite memory commands, each corresponding to one row 110 of the contiguous memory region. As another example, a composite memory command 204 associated with a memory region that is contiguous over a plurality of columns 112 in the same row 110 can be generated as a plurality of composite memory commands, each associated with a sub-portion of the columns 112. In some embodiments, the delay of the generated composite memory commands is recalculated. The other instructions are prioritized and / or the other composite memory commands are generated accordingly based on the recalculated delay. The generated composite memory commands are then provided to the memory module 104.

[0043] In view of the explanations set forth above, the reader will recognize that the beneficial effects of memory operations using a composite memory command include:

[0044] • improving the performance of a computing system by improving the use of bandwidth between a processor, a memory controller, and a memory module by compositing a single memory command into a composite memory command.

[0045] Advantages and features of the present disclosure can be further described through the following statements:

[0046] Statement 1. A method of memory operation using a composite memory command, the method comprising: receiving, by a memory module, a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; generating, based on the composite memory command, a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

[0047] Statement 2. The method according to Statement 1, wherein the composite memory command indicates the starting memory address and column number as multiple portions of contiguous memory.

[0048] Statement 3. The method according to any one of Statements 1 to 2, wherein the composite memory command indicates the start address and end address of a plurality of portions of contiguous memory.

[0049] Statement 4. The method according to any one of statements 1 to 3, wherein generating a plurality of memory commands comprises: determining one or more desired row activation commands; and generating one or more memory commands.

[0050] Multiple required line activation commands.

[0051] Statement 5. The method according to any one of statements 1 to 4, wherein determining one or more desired row activation commands comprises: maintaining a finite state machine; and determining one or more desired row activation commands based on the finite state machine, a start address, and an end address. Statement 6. The method according to any one of statements 1 to 5, further comprising determining a delay associated with a composite memory command by a memory controller.

[0052] Statement 7. The method according to any one of statements 1 to 6 further includes prioritizing one or more other commands issued to the memory module by the memory controller based on latency.

[0053] Statement 8. The method according to any one of statements 1 to 7 further includes generating a plurality of additional composite memory commands by the memory controller based on the composite memory command in response to a delay exceeding a threshold.

[0054] Statement 9. An apparatus for memory operations using composite memory commands, the apparatus...

[0055] The device includes: a processor; a memory controller communicatively coupled to the processor; and a memory module communicatively coupled to the memory controller, the memory module being configured to perform the following steps: receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; generating a plurality of memory commands based on the composite memory command to apply one or more operations to each of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

[0056] Statement 10. The apparatus of statement 9, wherein the composite memory command indicates a starting memory address and a column number for the plurality of portions of contiguous memory.

[0057] Statement 11. The apparatus of any one of statements 9-10, wherein the composite memory command indicates a starting address and an ending address for the plurality of portions of contiguous memory.

[0058] Statement 12. The apparatus of any one of statements 9-11, wherein generating the plurality of memory commands comprises: determining one or more required row activation commands; and generating the one or more required row activation commands.

[0059] Statement 13. The apparatus of any one of statements 9-12, wherein determining the one or more required row activation commands comprises: maintaining a finite state machine; and determining the one or more required row activation commands based on the finite state machine, the starting address, and the ending address.

[0060] Statement 14. The apparatus of any one of statements 9-13, wherein the memory control is configured to determine a latency associated with the composite memory command.

[0061] Statement 15. The apparatus of any one of statements 9-14, wherein the memory control is configured to prioritize issuing one or more other commands to the memory module based on the latency.

[0062] Statement 16. The apparatus of any one of statements 9-15, wherein the memory control is configured to generate a plurality of other composite memory commands based on the composite memory command in response to the latency exceeding a threshold.

[0063] Statement 17. A memory module for memory operations using composite memory commands, the memory module configured to perform steps comprising: receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; generating a plurality of memory commands based on the composite memory command to apply the one or more operations to each of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

[0064] Statement 18. The memory controller of statement 17, wherein the composite memory command indicates a starting memory address and a column number for the plurality of portions of contiguous memory.

[0065] Statement 19. The memory controller of any one of statements 17-18, wherein the composite memory command indicates a starting address and an ending address for the plurality of portions of contiguous memory.

[0066] Statement 20. The memory controller of any one of statements 17-19, wherein the memory controller is configured to determine one or more required row activation commands based on the composite memory command.

[0067] Statement 21. The memory controller of any one of statements 17-20, wherein the memory controller is configured to determine the one or more required row activation commands based on a finite state machine, the starting address, and the ending address.

[0068] Statement 19. The memory controller of any one of statements 17 to 18, wherein the composite memory command indicates a start address and an end address of the plurality of portions of contiguous memory.

[0069] Statement 20. The memory controller of any one of statements 17 to 19, wherein generating the plurality of memory commands comprises: determining one or more required row activation commands; and generating the one or more required row activation commands.

[0070] Statement 21. A method of memory operations using composite memory commands, the method comprising: receiving, by a memory controller from a processor, a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in a memory module; transmitting the composite memory command to the memory module.

[0071] Statement 22. The method of statement 21, further comprising determining, by the memory controller, a delay associated with the composite memory command.

[0072] Statement 23. The method of any one of statements 21 to 22, further comprising prioritizing, by the memory controller, issuance of one or more other commands to the memory module based on the delay.

[0073] the delay exceeding a threshold.

[0074] Statement 24. The method of any one of statements 21 to 23, further comprising generating, by the memory controller, a plurality of other composite memory commands based on the composite memory command in response to the delay exceeding a threshold.

[0075] Exemplary embodiments of the present disclosure are primarily described in the context of a fully functional computer system for memory operations using composite memory commands. However, those skilled in the art will appreciate that the present disclosure is equally applicable in a computer program product setting to program a computer to implement a method as described in the present disclosure. Such a computer program product can be a storage medium or memory having stored therein instructions which can be used to program a computer to perform a method as described in the present disclosure. The storage medium or memory can include any storage medium or memory for machine- readable information including magnetic media, optical media, or other suitable media. Examples of such media include magnetic disks in hard drives or floppy drives, optical disks in optical drives, magnetic tapes, and others as will be apparent to those skilled in the art. Those skilled in the art will immediately appreciate that any computer system having suitable programming means will be capable of executing the steps of a method as described in the present disclosure as embodied in a computer program product. Those skilled in the art will also realize that, although some exemplary embodiments described in this specification are oriented to software running on computers, alternative embodiments implemented as firmware or as hardware are well within the scope of the present disclosure.

[0076] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0077] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non- exhaustive list of more specific examples of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted via a wire cable. Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions to a computer readable storage medium within the respective computing / processing device for storage and / or execution. Computer readable program instructions for carrying out aspects of the present disclosure can be any desirable set of instructions to be executed on a computer or computing / processing device. The computer readable program instructions may

[0078] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions to a computer readable storage medium within the respective computing / processing device for storage and / or execution. Computer readable program instructions for carrying out aspects of the present disclosure can be any desirable set of instructions to be executed on a computer or computing / processing device. The computer readable program instructions may

[0079] Computer readable program instructions for carrying out operations of the present disclosure can be in assembly code, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or source code in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on a user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0080] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0081] The computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including

[0082] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0083] The flow diagrams and block diagrams in the drawings are illustrative of the architecture, functionality, and operations of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams or block diagrams can represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations of blocks in the block diagrams and / or flow diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0084] From the foregoing description, it will be apparent that modifications and variations can be effected while remaining within the scope of the various embodiments of the present disclosure. The description in this specification has been given by way of illustration only and should not be taken as limiting. The scope of the present disclosure is defined only by the language of the appended claims.

Claims

1. An apparatus for memory operations using composite memory commands, the apparatus comprising: processor; The memory controller is communicatively coupled to the processor; as well as A memory module communicatively coupled to the memory controller, the memory module being configured to: Receive a composite memory command that indicates one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; Based on the composite memory command, a plurality of memory commands are generated to apply the one or more operations to each of the plurality of portions of contiguous memory; as well as Execute the plurality of memory commands.

2. The apparatus of claim 1, wherein the composite memory command indicates the starting memory address and column number as the plurality of portions of contiguous memory.

3. The apparatus of claim 1, wherein the composite memory command indicates the start address and end address of the plurality of portions of the contiguous memory.

4. The apparatus of claim 3, wherein generating the plurality of memory commands comprises: Determine one or more desired row activation commands; as well as Generate one or more of the required row activation commands.

5. The apparatus of claim 4, wherein determining the one or more desired row activation commands comprises: Maintaining the finite state machine; as well as The one or more required row activation commands are determined based on the finite state machine, the start address, and the end address.

6. The apparatus of claim 1, wherein the memory controller is configured to determine a latency associated with the composite memory command.

7. The apparatus of claim 6, wherein the memory controller is configured to prioritize one or more other commands issued to the memory module based on the latency.

8. The apparatus of claim 6, wherein the memory controller is configured to generate a plurality of other composite memory commands based on the composite memory command in response to the latency exceeding a threshold.

9. A memory module for memory operation using composite memory commands, the memory module being configured to: Receive a composite memory command that indicates one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; Based on the composite memory command, a plurality of memory commands are generated to apply the one or more operations to each of the plurality of portions of contiguous memory; as well as Execute the plurality of memory commands.

10. The memory module of claim 9, wherein the composite memory command indicates the starting memory address and column number as the plurality of portions of contiguous memory.

11. The memory module of claim 9, wherein the composite memory command indicates the start address and end address of the plurality of portions of the contiguous memory.

12. The memory module of claim 9, wherein generating the plurality of memory commands comprises: Determine one or more desired row activation commands; as well as Generate one or more of the required row activation commands.

13. A method for memory operation using composite memory commands, the method comprising: The memory controller receives from the processor a composite memory command instructing one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; Transmit the composite memory command to the memory module; as well as Based on the composite memory command, a plurality of memory commands are generated to apply the one or more operations to each of the plurality of portions of contiguous memory.

14. The method of claim 13, further comprising determining a latency associated with the composite memory command by the memory controller.

15. The method of claim 14, further comprising prioritizing one or more other commands issued to the memory module by the memory controller based on the latency.

16. The method of claim 14, further comprising generating a plurality of other composite memory commands by the memory controller based on the composite memory command in response to the delay exceeding a threshold.

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