Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

Abstract

A microelectronic device includes a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure includes a stack structure having layers, each layer including a conductive structure and an insulative structure; a staircase structure confined within the staircase region and having a step, the step including edges of the layers in the stack structure within the deck and the additional deck; and a semiconductive pillar structure confined within the memory array region and extending through the stack structure. The stack structure includes a deck including a set of the layers, an additional deck overlying the deck and including an additional set of the layers, and a deck-to-deck section between the deck and the additional deck and including a dielectric structure confined within the memory array region and another set of the layers within vertical boundaries of the dielectric structure and confined within the staircase region.

Description

[0001] Priority requirements

[0002] This application is a national phase entry of international patent application PCT / US2021 / 017430, filed on February 10, 2021, designating the People's Republic of China, and published in English on September 2, 2021 as international patent publication WO 2021 / 173346 A1. It claims the benefit of U.S. patent application No. 16 / 799,254, filed on February 24, 2020, entitled "Methods of forming microelectronic devices, and associated microelectronic devices and electronic systems," pursuant to Article VIII of the Patent Cooperation Treaty. Technical Field

[0003] This disclosure generally relates to the field of microelectronic device design and fabrication, in various embodiments. More specifically, this disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices, memory devices, and electronic systems. Background Technology

[0004] A persistent goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory arrays”) architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in one or more stacked structures containing conductive structures and dielectric material layers. Each vertical memory string may contain at least one selection device series-coupled to a series combination of vertically stacked memory cells. Compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by constructing the array upwards (e.g., vertically) on the die.

[0005] Vertical memory array architectures typically include electrical connections between conductive structures of layers in a stacked structure of memory devices and access lines (e.g., word lines), allowing memory cells in a vertical memory array to be uniquely selected for write, read, or erase operations. One method of forming such electrical connections involves creating a so-called “step” (or “step”) structure at the edges (e.g., horizontal ends) of the stacked layers of the memory devices. The step structure includes various “steps” defining contact areas of conductive structures, on which conductive contact structures can be positioned to provide electrical pathways for the conductive structures.

[0006] With the development of vertical memory array technology, memory density has been increased by forming memory devices in a multi-stack (e.g., dual-stack) configuration. For example, in a conventional dual-stack configuration, some vertical memory strings are located in an upper stack including a first stack structure, and additional vertical memory strings are located in a lower stack below the upper stack and including a second stack structure. The vertical memory strings in the upper stack can be electrically isolated from the additional vertical memory strings in the lower stack (e.g., via an inter-stack dielectric structure), or the vertical memory strings in the upper stack can be electrically coupled to the additional vertical memory strings in the lower stack (e.g., via conductive interconnect structures extending through the inter-stack dielectric structure). Unfortunately, conventional methods of forming multi-stack (e.g., dual-stack) configurations can produce relatively thick inter-stack dielectric structures that are vertically positioned between different stacks, which can hinder the efficient formation of stepped structures within the relatively lower stacks. For example, inter-stack dielectric structures can disrupt the vertical alternation sequence of first structures (e.g., insulating structures) and second structures (e.g., additional insulating structures, conductive structures) within different stacks, thereby blocking the simple and efficient transfer of one or more step structure configurations from relatively high stacks to relatively low stacks using conventional dicing processes. Therefore, forming the desired step structure within stacked structures of different stacks may require complex, inefficient, and expensive processes for each different stack (e.g., separate step formation processes, each involving a series of masking and etching actions).

[0007] Therefore, there is still a need for new methods for forming microelectronic devices (e.g., memory devices such as 3D-NAND flash memory devices) that can help increase memory density while alleviating the problems of conventional methods for forming microelectronic devices, as well as new microelectronic devices and new electronic systems formed using such methods. Summary of the Invention

[0008] In some embodiments, a microelectronic device includes a microelectronic device structure having a memory array region and a stepped region. The microelectronic device structure includes a stacked structure, a stepped structure, and a semiconductive pillar structure. The stacked structure has layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stacked structure includes a stack comprising a set of layers, an additional stack vertically covering the stack and including an additional set of layers, and an inter-stack section vertically located between the stack and the additional stack. The inter-stack section includes a dielectric structure horizontally confined within the memory array region, and another set of layers located within the vertical boundary of the dielectric structure and horizontally confined within the stepped region. The stepped structure is horizontally confined within the stepped region and has steps, the steps including edges of layers in the stacked structure located within the stack and the additional stack. The semiconductive pillar structure is horizontally confined within the memory array region and extends vertically through the stacked structure.

[0009] In an additional embodiment, a method of forming a microelectronic device includes forming a microelectronic device structure having a memory array region and a stepped region. The microelectronic device structure is formed to include a first preliminary stack structure, the first preliminary stack structure including a vertically alternating sequence of first and second insulating structures arranged in layers. A dielectric structure is formed within an upper portion of the first preliminary stack structure and generally confined within a horizontal boundary of the memory array region. A second preliminary stack structure is formed above the first preliminary stack structure and the dielectric structure. The second preliminary stack structure includes a vertically alternating sequence of additional first and second insulating structures arranged in additional layers. A semiconductive pillar structure is formed, the semiconductive pillar structure extending vertically through the second preliminary stack structure, the dielectric structure, and the portion of the first preliminary stack structure within the memory array region. A stepped structure is formed within the portions of the second preliminary stack structure and the first preliminary stack structure within the stepped region. Some of these stepped structures have steps at horizontal ends including layers of the first preliminary stack structure. Other stepped structures have additional steps at horizontal ends including additional layers of the second preliminary stack structure. The second insulating structure and the additional second insulating structure are at least partially replaced with conductive structures.

[0010] In an additional embodiment, a microelectronic device includes a microelectronic device structure comprising a stacked structure, a stepped structure, and a semiconductive pillar structure. The stacked structure has layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stacked structure includes a lower stack including some of these layers, an upper stack overlying the stack and including other layers, and an inter-stack section between the lower and upper stacks. The inter-stack section includes an inter-stack dielectric structure and additional layers horizontally positioned between the inter-stack dielectric structures. Each of the additional layers includes an additional insulating structure and another insulating structure vertically adjacent to the additional insulating structure. The stepped structure has steps, the steps including the edges of layers within the lower and upper stacks of the stacked structure. The semiconductive pillar structure extends vertically through the stacked structure.

[0011] In other embodiments, a method of forming a microelectronic device includes forming a microelectronic device structure including a first preliminary stack structure, the first preliminary stack structure including a vertically alternating sequence of first and second insulating structures arranged in layers. A dielectric structure is formed to extend vertically into the first preliminary stack structure. The dielectric structures are horizontally spaced apart from each other in a first direction and extend horizontally in a generally linear manner in a second direction orthogonal to the first direction. A second preliminary stack structure is formed over the first preliminary stack structure and the dielectric structure. The second preliminary stack structure includes a vertically alternating sequence of additional first and second insulating structures arranged as additional layers. A semiconductive pillar structure is formed, the semiconductive pillar structure extending vertically through portions of the second and first preliminary stack structures horizontally positioned between the dielectric structures. A stepped structure is formed within the second and first preliminary stack structures. Some of these stepped structures have steps including the edges of the layers of the first preliminary stack structure. Other stepped structures have additional steps including the edges of the additional layers of the second preliminary stack structure. The additional second insulating structures of the second preliminary stack structure and the second insulating structures of the first preliminary stack structure, positioned outside the vertical boundaries of the dielectric structures, are replaced with conductive structures.

[0012] In another embodiment, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device and including at least one microelectronic device structure having a memory array region and a step region. The at least one microelectronic device structure includes a stacked structure, a step structure, and a semiconductive pillar structure. The stacked structure has layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stacked structure includes a stack comprising some of these layers, an additional stack vertically covering the stack and including other layers, and an inter-stack section vertically located between the stacked and additional stacks. The inter-stack section includes at least one dielectric structure located within the horizontal boundary of the memory array region and substantially not present in or partially extending across the horizontal region of the step region. The step structure is located within the step region and has steps, the steps including edges of layers in the stacked structure located within the stacked and additional stacks. The semiconductive pillar structure is located within the memory array region and extends vertically through the stacked structure. Attached Figure Description

[0013] Figures 1A to 10B This is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device according to an embodiment of the present disclosure. Figure 1B , 2B 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are respectively around Figure 1A , 2A Simplified partial cross-sectional views of line AA depicted in 3A, 4A, 5A, 6A, 7A, 8A, 9A and 10A.

[0014] Figures 11A to 20B This is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device according to an additional embodiment of the present disclosure. Figure 11B , 12B 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B are respectively around Figure 11A , 12A Simplified partial cross-sectional views of line BB depicted in 13A, 14A, 15A, 16A, 17A, 18A, 19A and 20A.

[0015] Figure 21 This is a simplified partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure.

[0016] Figure 22 This is a schematic block diagram illustrating an electronic system according to embodiments of the present disclosure. Detailed Implementation

[0017] The following description provides specific details, such as material composition, shape, and size, to provide a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In practice, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions for forming a complete microelectronic device according to the structures can be performed using conventional manufacturing techniques.

[0018] The diagrams presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Shapes depicted in the diagrams are expected to vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas shown, but rather include deviations in shape, for example, due to manufacturing processes. For instance, an area shown or described as box-shaped may have coarse and / or non-linear characteristics, and an area shown or described as circular may contain some coarse and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The diagrams are not necessarily drawn to scale. Additionally, common elements between the diagrams may retain the same numerical designations.

[0019] As used herein, “memory device” means and includes microelectronic devices that exhibit, but are not limited to, memory functionality.

[0020] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure that has a relatively large area compared to the other surfaces of the structure.

[0021] As used herein, features described as “adjacent” to each other (e.g., areas, structures, devices) refer to and include features that are most closely (e.g., closest to) each other and have the disclosed identifiers (or more identifiers). Additional features (e.g., additional areas, additional structures, additional devices) that do not match the disclosed identifiers (or more identifiers) of “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other refer to and include features that are most closely (e.g., closest to) each other and have the disclosed identifiers (or more identifiers). Furthermore, features described as “horizontally adjacent” to each other refer to and include features that are most closely (e.g., closest to) each other and have the disclosed identifiers (or more identifiers).

[0022] As used herein, the terms “comprising,” “including,” “having,” and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unlisted elements or method steps, and include the more restrictive terms “consisting of” and “mainly consisting of” and their grammatical equivalents. As used herein, the term “may” relating to materials, structures, features, or method actions indicates that an embodiment of this disclosure is intended to be used, and this term is preferred over the more restrictive term “is” to avoid implying that other compatible materials, structures, features, and methods that may be used in combination should or must be excluded.

[0023] As used herein, spatial relation terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” and “right” are used for convenience of description to describe the relationship between one element or feature and another element(s) as shown in the figures. Unless otherwise specified, spatial relation terms inherently cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is reversed, an element described as being “below,” “under,” “lower,” or “bottom” of other elements or features will be oriented “above” or “top” of said other elements or features. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relation descriptors used herein may be interpreted accordingly.

[0024] As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0025] As used in this article, “and / or” includes any and all combinations of one or more of the associated listed items.

[0026] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of the structures and devices that facilitate the operation of one or more of the structures and devices in a predetermined manner.

[0027] As used herein, the term "generally" with respect to a given parameter, characteristic, or condition means and includes the degree to which a given parameter, characteristic, or condition conforms to a degree of variability (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, characteristic, or condition being generally satisfied, the parameter, characteristic, or condition may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0028] As used herein, the term "about" or "approximately" with respect to a particular parameter includes the value, and those skilled in the art will understand that the degree of variation relative to the value is within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​that are within 90.0% to 110.0% of the value, such as 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0029] Unless the context otherwise indicates, the materials described herein can be formed by any suitable process, including but not limited to spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma-enhanced ALD, physical vapor deposition (“PVD”) (including sputtering, evaporation, ionization PVD and / or plasma-enhanced CVD), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by a person skilled in the art. Additionally, unless the context otherwise indicates, the removal of the materials described herein can be achieved by any suitable process, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, flux planarization, or other known methods.

[0030] Figures 1A to 10BThis is a simplified partial cross-sectional view illustrating an embodiment of a method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). Figure 1B , 2B 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are respectively around Figure 1A , 2A Simplified partial cross-sectional views of line AA depicted in 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A. From the description provided below, it will be apparent to those skilled in the art that the methods and structures described herein can be used in a variety of devices and electronic systems.

[0031] refer to Figure 1A A microelectronic device structure 100 may be formed, comprising a substrate structure 102 and a first preliminary stacked structure 104 on or above the substrate structure 102. The microelectronic device structure 100 includes a memory array region 112 and a stepped region 114 horizontally adjacent to the memory array region 112 (e.g., in the X direction). As described in further detail below, the microelectronic device structure 100 further includes additional components (e.g., features, structures, devices) located within the boundaries of its different horizontal regions (e.g., memory array region 112, stepped region 114). Figure 1B It revolves around Figure 1A The line AA shown in the figure is in Figure 1A A simplified cross-sectional view of the microelectronic device structure 100 in the processing stage depicted in the figure.

[0032] The substrate structure 102 of the microelectronic device structure 100 may include a substrate material or construction for forming additional materials and structures of the microelectronic device structure 100. In some embodiments, the substrate structure 102 includes a conductive structure formed of at least one conductive material, such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based alloys, base alloys, etc.). Alloys based on Fe, Ni, Fe and Ni, Co and Ni, Fe and Co, Co, Ni and Fe, Al, Cu, Magnesium (Mg), Ti, steel, low-carbon steel, stainless steel, conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)), and conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). For example, substrate structure 102 can be used as a source structure (e.g., a source plate) for a microelectronic device, as described in further detail below.

[0033] The first preliminary stacked structure 104 of the microelectronic device structure 100 includes a vertically alternating (e.g., in the Z direction) sequence of first insulating structures 106 and second insulating structures 108 arranged as layers 110. Each layer 110 of the first preliminary stacked structure 104 may include at least one of the first insulating structures 106 that is vertically adjacent to at least one of the second insulating structures 108. The first preliminary stacked structure 104 may include a desired number of layers 110. For example, the first preliminary stacked structure 104 may include more than or equal to ten (10) layers 110, more than or equal to twenty-five (25) layers 110, more than or equal to fifty (50) layers 110, more than or equal to one hundred (100) layers 110, more than or equal to one hundred and fifty (150) layers 110, or more than or equal to two hundred (200) layers 110 of the first insulating structures 106 and the second insulating structures 108.

[0034] The first insulating structure 106 of layer 110 of the first preliminary stacked structure 104 may be formed of at least one electrically insulating material and may contain at least one electrically insulating material, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y This document contains one or more of the chemical formulas “x”, “y”, and “z” (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N yThe formula (x) represents the average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if any) to each atom of the other element (e.g., Si, Al, Hf, Nb, Ti). Because these formulas represent relative atomic ratios rather than strict chemical structures, the first insulating structure 106 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, where the values ​​of "x", "y", and "z" (if any) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" refers to and includes compounds whose elemental composition cannot be expressed by a well-defined ratio of natural numbers and violates a definite law of proportion. Each of the first insulating structures 106 may respectively contain a substantially uniform or substantially non-uniform distribution of at least one electrically insulating material. As used herein, the term "uniform distribution" means that the amount of material does not vary in different parts of the structure (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "non-uniform distribution" means that the amount of material varies in different parts of the structure. In some embodiments, each of the first insulating structures 106 exhibits a generally uniform distribution of electrical insulating material. In other embodiments, at least one of the first insulating structures 106 exhibits a generally non-uniform distribution of at least one electrical insulating material. For example, one or more of the first insulating structures 106 may be formed and comprised of a stack (e.g., a laminate) of at least two different electrical insulating materials (e.g., at least two different dielectric materials). In some embodiments, each of the first insulating structures 106 is formed of and comprises a dielectric oxide material, such as SiO2. x (e.g., silicon dioxide (SiO2)). Each of the first insulating structures 106 may be substantially planar and may each exhibit a desired thickness. Furthermore, each of the first insulating structures 106 may be substantially identical to each other (e.g., exhibiting substantially the same material composition, material distribution, size, and shape), or at least one of the first insulating structures 106 may differ from at least one of the other first insulating structures 106 (e.g., exhibiting one or more different material compositions, different material distributions, different sizes, and different shapes). In some embodiments, each of the first insulating structures 106 is substantially identical to each of the other first insulating structures 106.

[0035] The second insulating structure 108 of layer 110 of the first preliminary stacked structure 104 may be formed of and contain at least one additional electrically insulating material. The material compositions of the second insulating structure 108 and the first insulating structure 106 may be selected such that the first insulating structure 106 and the second insulating structure 108 can be selectively removed relative to each other. The second insulating structure 108 may be selectively etched relative to the first insulating structure 106 during common (e.g., collective, mutual) exposure to a first etchant, and the first insulating structure 106 may be selectively etched relative to the second insulating structure 108 during common exposure to different second etchants. As used herein, if a material exhibits an etch rate at least about five times (5x), such as about ten times (10x), about twenty times (20x), or about forty times (40x), greater than the etch rate of another material, then the material may be “selectively etched” relative to the other material. The material composition of the second insulating structure 108 differs from the material composition of the first insulating structure 106. The second insulating structure 108 may include one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbon oxynitride material (e.g., SiO2) x C z N y In some embodiments, each of the second insulating structures 108 is formed of and contains a dielectric nitride material, such as SiN. y(e.g., Si3N4). Each of the second insulating structures 108 may individually comprise a substantially uniform distribution of the at least one additional electrical insulating material or a substantially non-uniform distribution of the at least one additional electrical insulating material. In some embodiments, each of the second insulating structures 108 of the first preliminary stack structure 104 exhibits a substantially uniform distribution of the additional electrical insulating material. In additional embodiments, at least one of the second insulating structures 108 of the first preliminary stack structure 104 exhibits a substantially non-uniform distribution of the at least one additional electrical insulating material. For example, the second insulating structures 108 may be formed and comprised of stacks (e.g., laminates) of at least two different additional electrical insulating materials. The second insulating structures 108 may each be substantially planar and may each exhibit a desired thickness.

[0036] Continue to refer to Figure 1A The microelectronic device structure 100 may further include contact structures 116 located within its memory array region 112. For example, the contact structure 116 may serve as a source contact structure. The contact structure 116 may be configured (e.g., size, shape, material composition) and positioned to facilitate electrical connections between one or more features of the microelectronic device structure 100 (e.g., substrate structure 102) and one or more additional structures or devices (e.g., post structures, vertical memory cell strings) to be formed on or above the contact structure 116, as described in further detail below. Contact structures 116 may each be formed of and contain at least one conductive material, such as metals (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni, and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped Ge, conductive doped SiGe), conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), or combinations thereof. In some embodiments, contact structures 116 are formed of and contain W. Each of the contact structures 116 may respectively contain a substantially uniform distribution of the at least one conductive material, or a non-uniform distribution of the at least one conductive material. In some embodiments, each of the contact structures 116 exhibits a substantially uniform distribution of the conductive material. In additional embodiments, at least one of the contact structures 116 exhibits a non-uniform distribution of the at least one conductive material.

[0037] The substrate structure 102, the first preliminary stacked structure 104 (including a layer 110 containing a first insulating structure 106 and a second insulating structure 108 therein), and the contact structure 116 can be formed using conventional processes (e.g., conventional material deposition processes, conventional photolithography patterning processes, conventional material removal processes) and conventional processing equipment that are not described in detail herein.

[0038] Next reference Figure 2A A photoresist structure 118 may be formed on or above a portion of the first preliminary stacked structure 104 located within or above the horizontal boundary of the stepped region 114 of the microelectronic device structure 100. For example... Figure 2A As shown, the photoresist structure 118 may be formed to be substantially confined within the stepped region 114, such that the photoresist structure 118 does not extend horizontally into the memory array region 112 of the microelectronic device structure 100. In other words, the photoresist structure 118 may be formed such that the photoresist structure 118 is substantially (e.g., completely) absent from the memory array region 112 of the first preliminary stack structure 104. Figure 2B Is in Figure 2A The processing stages described in the text revolve around Figure 2A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0039] The photoresist structure 118 can be used as a mask to protect portions of the first preliminary stacked structure 104 (e.g., layer 110 containing its first insulating structure 106 and second insulating structure 108) vertically below and within its horizontal boundaries from removal during subsequent processing, as described in further detail below. The photoresist structure 118 may be formed of and contain a photoresist material, such as a positive or negative photoresist material. Suitable photoresist materials (e.g., positive or negative photoresist materials) are known in the art and therefore will not be described in detail herein. For example, the photoresist structure 118 may be compatible with: 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm wavelength systems; 193 nm wavelength immersion systems; and / or electron beam lithography systems.

[0040] The photoresist structure 118 can be formed using conventional processes (e.g., conventional deposition processes such as one or more PVD, CVD, ALD, and spin coating; conventional photolithography; conventional material removal processes). Such processes are known in the art and therefore will not be described in detail herein.

[0041] Next reference Figure 3AThe microelectronic device structure 100 can undergo a material removal process to selectively remove portions of the relatively vertically higher layers 110 (e.g., the uppermost layer) of the first preliminary stacked structure 104 within the memory array region 112 of the microelectronic device structure 100. For example... Figure 3A As shown, the material removal process can form a recess 120 (e.g., a trench, an opening) that extends vertically into the first preliminary stacked structure 104 within the memory array region 112 of the microelectronic device structure 100. Photoresist structure 118 ( Figure 2A The photoresist structure 118 can be used as a mask during the material removal process to impede or prevent the removal of additional portions of the relatively vertically higher layer 110 of the first preliminary stacked structure 104 within the stepped region 114 of the microelectronic device structure 100. Therefore, the recess 120 can be formed to be generally confined within the memory array region 112, such that the recess 120 does not extend substantially horizontally into the stepped region 114 of the microelectronic device structure 100. After the recess 120 is formed, the photoresist structure 118 can be removed. Figure 2A The remaining (e.g., not removed) parts (if they exist). Figure 3B Is in Figure 3A The processing stages described in the text revolve around Figure 3A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0042] The material removal process can be controlled to remove a desired number of layers 110 of the first preliminary stacked structure 104 (e.g., the photoresist-free structure 118). Figure 2A (The protected part). For example Figure 3A As shown, in some embodiments, the material removal process removes portions of two (2) relatively vertically highest layers 110 (e.g., two (2) uppermost layers) of the first preliminary stack structure 104, including portions of its first insulating structure 106 and second insulating structure 108. In additional embodiments, the material removal process may remove portions of a different number of relatively vertically higher layers 110 of the first preliminary stack structure 104. As a non-limiting example, the material removal process may be controlled to remove a portion of a single (e.g., only one) relatively vertically highest layer 110 (e.g., the uppermost layer) of the first preliminary stack structure 104. As another non-limiting example, the material removal process may be controlled to remove more than two (2) portions of the first preliminary stack structure 104 of the relative vertical top layers 110, such as three (3) portions of the first preliminary stack structure 104 of the relative vertical top layers 110 (e.g., three (3) top layers), four (4) portions of the first preliminary stack structure 104 of the relative vertical top layers 110 (e.g., four (4) top layers), or five (5) or more portions of the first preliminary stack structure 104 of the relative vertical top layers 110 (e.g., five (5) top layers).

[0043] A portion of the relatively vertically higher layer 110 of the first preliminary stacked structure 104 within the memory array region 112 of the microelectronic device structure 100 can be removed using conventional material removal processes (e.g., conventional etching processes, such as conventional anisotropic etching processes), which are not described in detail herein. For example, a portion of the uppermost layer 110 of the first preliminary stacked structure 104 within the memory array region 112 of the microelectronic device structure 100 can be removed using an etching cycle comprising removing the exposed portion of the second insulating structure 108 of the uppermost layer 110 using a first etching action (e.g., a first anisotropic etching action), and then removing the exposed portion of the first insulating structure 106 of the uppermost layer 110 using a second etching action (e.g., a second anisotropic etching action). Subsequently, portions of one or more additional layers 110 of the first preliminary stacked structure 104 within the memory array region 112 can be removed using one or more additional etching cycles similar to the etching cycle described above to form a recess 120 to the desired vertical depth within the memory array region 112 of the microelectronic device structure 100.

[0044] After forming the recess 120 extending vertically into the first preliminary stacked structure 104, the photoresist structure 118 ( Figure 2A The remainder (if present) of the photoresist structure 118 can be selectively removed using one or more conventional material removal processes, which are not described in detail herein. For example, the microelectronic device structure 100 may be exposed to a developer (e.g., a positive developer, a negative developer) formulated to selectively remove the photoresist structure 118. Figure 2A The remainder of the mixture (e.g., to develop it). Suitable developers are known in the art and therefore will not be described in detail herein.

[0045] Next reference Figure 4A It can be in the recess 120 ( Figure 3A Dielectric filling material 122 is formed inside and outside the exposed surface of the first preliminary stacked structure 104 or on it. Figure 4A As shown, dielectric filling material 122 may be formed to cover the surface of the first preliminary stacked structure 104 within the memory array region 112 and the step region 114 of the microelectronic device structure 100 and extend substantially across said surface (e.g., extend substantially continuously). Dielectric filling material 122 may substantially fill the recess 120 within the memory array region 112. Figure 3A ); and can cover the recessed area 120 ( Figure 3AThe dielectric filler 122 may be at least partially (e.g., substantially) adapted to the surface morphology defined by the surface on which the dielectric filler 122 is formed (e.g., horizontal or vertical) and extends substantially across said surface, such as at and within the boundary of the stepped region 114 of the microelectronic device structure 100. Figure 4B Is in Figure 4A The processing stages described in the text revolve around Figure 4A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0046] The dielectric filler 122 may be formed of and contain at least one dielectric material. The material composition of the dielectric filler 122 may be selected relative to the material composition of the second insulating structure 108 of the initial stacked structure 100, such that the second insulating structure 108 and the dielectric filler 122 may be selectively removed relative to each other. The second insulating structure 108 may be selectively etched relative to the dielectric filler 122 during common (e.g., collectively, mutually) exposure to a first etchant, and the dielectric filler 122 may be selectively etched relative to the second insulating structure 108 during common exposure to different second etchants. The material composition of the dielectric filler 122 may differ from the material composition of the second insulating structure 108 and may include one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbon oxynitride material (e.g., SiO2) x C z N y The material composition of the dielectric filler 122 may be selected to be substantially the same as that of one or more (e.g., each) of the first insulating structures 106 of the first preliminary stacked structure 104, or may be selected to be different from the material composition of the first insulating structures 106 of the first preliminary stacked structure 104. In some embodiments, the dielectric filler 122 is composed of a dielectric oxide material (e.g., SiO2). xThe dielectric filler 122 may comprise a generally uniform or generally non-uniform distribution of dielectric material (e.g., SiO2). In some embodiments, the dielectric filler 122 exhibits a generally uniform distribution of dielectric material. In additional embodiments, the dielectric filler 122 exhibits a generally non-uniform distribution of dielectric material. For example, the dielectric filler 122 may be formed from and comprise a stack of at least two different dielectric materials (e.g., a laminate).

[0047] The dielectric filler material 122 can be formed using conventional processes (e.g., conventional conformal deposition processes), which are not described in detail herein. As a non-limiting example, the dielectric filler material 122 can be formed using one or more of conventional CVD processes (e.g., conventional PECVD processes) and conventional ALD processes. In some embodiments, the dielectric filler material 122 is formed on the exposed surface of the first preliminary stacked structure 104 using a PECVD process.

[0048] Next reference Figure 5A Dielectric filler material 122 can be removed. Figure 4A ) in the concave part 120 ( Figure 3A The portion outside the boundary (e.g., horizontal boundary, vertical boundary) of the dielectric filling material 122 is retained. Figure 4A ) in the concave part 120 ( Figure 3A The additional portion within the boundary of the stack is used to form at least one inter-stack dielectric structure 124. For example... Figure 5A As shown, the removal process can expose the uppermost surface of the first preliminary stacked structure 104 within the stepped region 114 of the microelectronic device structure 100. The uppermost boundary (e.g., the uppermost surface) of the inter-stack dielectric structure 124 within the memory array region 112 of the microelectronic device structure 100 can be substantially coplanar with the uppermost boundary (e.g., the uppermost surface) of the first preliminary stacked structure 104 within the stepped region 114 of the microelectronic device structure 100. Figure 5B Is in Figure 5A The processing stages described in the text revolve around Figure 5A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0049] like Figure 5AAs shown, the inter-stack dielectric structure 124 can be substantially confined within the horizontal boundary of the memory array region 112 of the microelectronic device structure 100. In other words, the inter-stack dielectric structure 124 is formed such that it does not extend horizontally into the stepped region 114 of the microelectronic device structure 100. For example, confining the inter-stack dielectric structure 124 substantially within the horizontal boundary of the memory array region 112 can alleviate the conventional problems and complexities of forming stepped structures within the stepped region 114 of the microelectronic device structure 100, as described in further detail below.

[0050] The dielectric filler material 122 can be removed using conventional processes (e.g., conventional planarization processes). Figure 4A ) in the concave part 120 ( Figure 3A The portion outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the dielectric material 122 is used to form the inter-stack dielectric structure 124; these processes are not described in detail herein. For example, at least one chemical mechanical planarization (CMP) process can be used to remove the dielectric filler material 122. Figure 4A ) in the concave part 120 ( Figure 3A The portion outside the boundary of the stack is used to form an inter-stack dielectric structure 124.

[0051] Next reference Figure 6A An opening 126 (e.g., a through-hole) may be formed in the memory array region 112 of the microelectronic device structure 100, and a plug structure 128 may be formed at the upper vertical boundary (e.g., in the Z direction) of the opening 126 to substantially plug (e.g., cover) the opening 126. Figure 6B Is in Figure 6A The processing stages described in the text revolve around Figure 6A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0052] like Figure 6BAs shown, opening 126 may extend vertically (e.g., in the Z direction) through the inter-stack dielectric structure 124 and a portion of the first preliminary stack structure 104 vertically subordinate to the inter-stack dielectric structure 124 to a contact structure 116 within the memory array region 112 of the microelectronic device structure 100. Each opening 126 may be at least partially (e.g., substantially) horizontally aligned (e.g., in the X and Y directions) with a contact structure 116 vertically subordinate to it. The lower vertical boundary of opening 126 may be defined by a surface (e.g., an upper surface) of contact structure 116, and the horizontal boundary of opening 126 may be defined by a surface (e.g., a side surface) of the first preliminary stack structure 104 (e.g., the surfaces of the first insulating structure 106 and the second insulating structure 108 of its layers 110) and the inter-stack dielectric structure 124. Subsequently, opening 126 may be filled with material to form a post structure within the memory array region 112 of the microelectronic device structure 100, as described in further detail below.

[0053] Each opening 126 may be individually formed to exhibit a desired geometric configuration (e.g., desired shape and desired size). In some embodiments, each opening 126 is individually formed to exhibit a columnar shape (e.g., a circular column shape, a rectangular column shape, an oval column shape, a guide post shape) and is sized and positioned to expose a single (e.g., only one) contact structure 116. For example, each opening 126 may exhibit a circular columnar shape, having a generally circular horizontal cross-sectional area and being sized and positioned to be at least partially (e.g., generally) located within the horizontal boundary of the contact structure 116 that is thus at least partially exposed. In some embodiments, each opening 126 is generally confined within the horizontal boundary of the contact structure 116, thereby defining a lower vertical boundary of the opening 126. In additional embodiments, one or more of the openings 126 extend horizontally (e.g., in the X and / or Y directions) beyond the horizontal boundary of the contact structure 116, thereby defining a portion of the lower vertical boundary of the opening 126.

[0054] A desired number of openings 126 may be formed in the memory array region 112 of the microelectronic device structure 100. In some embodiments, the number of openings 126 formed in the memory array region 112 is the same as the number of contact structures 116 within the memory array region 112. In additional embodiments, the number of openings 126 formed in the memory array region 112 differs from the number of contact structures 116 within the memory array region 112. For example, the number of openings 126 may be less than the number of contact structures 116, such that less than all of the contact structures 116 are exposed through the openings 126.

[0055] The opening 126 can be formed using conventional processes (e.g., conventional photolithography patterning processes, conventional etching processes) and conventional processing equipment, which are not described in detail herein.

[0056] Continue to refer to Figure 6B The plug structure 128 may extend vertically (e.g., in the Z direction) into the inter-stack dielectric structure 124 and may plug the opening 126. The plug structure 128 may be configured and positioned to protect the opening 126 from being filled with material during additional processing operations to form an additional preliminary stack structure on top of the first preliminary stack structure 104, as described in further detail below. Each plug structure 128 may be at least partially (e.g., substantially) horizontally aligned (e.g., in the X and Y directions) with one of the openings 126 vertically below it. The lower vertical boundary of the plug structure 128 may be defined by the upper vertical boundary of the remaining unfilled portion of the opening 126 and the horizontally extending surface of the inter-stack dielectric structure 124 vertically above the lowermost vertical boundary of the inter-stack dielectric structure 124. The plug structure 128 may be confined within the vertical boundaries (e.g., the upper vertical boundary and the lower vertical boundary) of the inter-stack dielectric structure 124. For example, the plug structure 128 may not extend vertically into the portion of the first preliminary stack structure 104 that lies vertically beneath the inter-stack dielectric structure 124. The horizontal boundary of the plug structure 128 may be defined by the vertically extending surface (e.g., side surface) of the inter-stack dielectric structure 124.

[0057] Each plug structure 128 may be configured to exhibit a desired geometry (e.g., desired shape and desired size) to facilitate plugging (e.g., enclosing) at least one of its underlying openings 126. In some embodiments, each plug structure 128 may be configured to exhibit a cylindrical shape (e.g., a circular cylindrical shape, a rectangular cylindrical shape, an oval cylindrical shape, a guide post shape) and is sized and positioned to plug a single (e.g., only one) opening 126. For example, each plug structure 128 may exhibit a circular cylindrical shape, having a generally circular horizontal cross-sectional area and being sized and positioned to completely cover the horizontal cross-sectional area of ​​the opening 126 of that plug. Each plug structure 128 may extend beyond the horizontal boundary of the opening 126 of that plug. In additional embodiments, one or more of the plug structures 128 may exhibit different shapes and / or different sizes, provided that the one or more plugs in the plug structures 128 are operatively associated with their openings 126 (e.g., within their horizontal boundaries).

[0058] The plug structures 128 may each be formed of and contain at least one material capable of bridging the upper portion of the opening 126 within the inter-staple dielectric structure 124 that is operatively associated with it (e.g., thus plugging it), and capable of protecting the lower portion of the opening 126 within the first preliminary stack structure 104 from material filling during additional processing operations to form a second preliminary stack structure over the first preliminary stack structure 104. For example, the plug structures 128 may include one or more of the following: at least one semiconductive material (e.g., silicon, such as polycrystalline silicon); at least one conductive material (e.g., at least one or more of the following metals: W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, and Al); at least one alloy, such as a Co-based alloy, an Fe-based alloy, a Ni-based alloy, an Fe and Ni-based alloy, a Co and Ni-based alloy, an Fe and Co-based alloy, etc. The plug structure 128 comprises one or more of the following: alloys of Co and Ni and Fe, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel; at least one conductive metal material, such as one or more of conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides; and at least one conductive doped semiconductor material, such as one or more of conductive doped silicon, conductive doped germanium, and conductive doped silicon-germanium; and at least one dielectric material (e.g., one or more of dielectric oxides, dielectric nitrides, dielectric oxynitrides, and dielectric carbon oxynitrides). In some embodiments, the plug structure 128 is formed of and comprises polycrystalline silicon. In an additional embodiment, the plug structure 128 is formed of and comprises tungsten (W). In other embodiments, the plug structure 128 is formed of and comprises titanium nitride (TiN).

[0059] The plug structure 128 can be formed using conventional processes (e.g., conventional material removal processes, such as conventional etching and planarization processes; conventional deposition processes, such as conventional non-conformal deposition processes) and conventional processing equipment, which are not described in detail herein. As a non-limiting example, after the opening 126 is formed, the inter-stack dielectric structure 124 can undergo an etching process to expand (e.g., increase) the horizontal dimension of the upper portion of the opening 126 vertically positioned within the inter-stack dielectric structure 124; plug material can be non-conformally formed inside and outside the horizontally expanded upper portion of the opening 126, and can bridge and close the opening 126 without extending vertically into and filling the portion of the opening 126 vertically below the inter-stack dielectric structure 124; and a portion of the plug material covering the upper vertical boundary of the inter-stack dielectric structure 124 can be removed (e.g., by a planarization process, such as a CMP process) to form the plug structure 128.

[0060] Next reference Figure 7A A second preliminary stacking structure 130 may be formed on or above the first preliminary stacking structure 104, the inter-stack dielectric structure 124, and the plug structure 128; then, a guide pillar structure 138 extending vertically through the second preliminary stacking structure 130, the plug structure 128, the inter-stack dielectric structure 124, and the first preliminary stacking structure 104 may be formed within the memory array region 112 of the microelectronic device structure 100. For example... Figure 7A As shown, the second preliminary stacking structure 130 can extend horizontally through the memory array region 112 and the step region 114 of the microelectronic device structure 100, and the guide pillar structure 138 can be horizontally confined within the memory array region 112 of the microelectronic device structure 100. Figure 7B Is in Figure 7A The processing stages described in the text revolve around Figure 7A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0061] The second preliminary stack structure 130 may be formed as a vertically alternating (e.g., in the Z direction) sequence comprising additional first insulating structures 132 and additional second insulating structures 134 arranged as additional layers 136. Each additional layer 136 of the second preliminary stack structure 130 may comprise at least one additional first insulating structure 132 vertically adjacent to at least one of the additional second insulating structures 134. The second preliminary stack structure 130 may comprise a desired number of additional layers 136. For example, the second preliminary stack structure 130 may comprise ten or more (10) additional layers 136, twenty-five or more (25) additional layers 136, fifty or more (50) additional layers 136, one hundred or more (100) additional layers 136, one hundred and fifty (150) additional layers 136, or two hundred or more (200) additional layers 136. The number of additional layers 136 in the second preliminary stack structure 130 may be equal to the number of layers 110 in the first preliminary stack structure 104 (e.g., the same as them), or the number of additional layers 136 in the second preliminary stack structure 130 may be different from (e.g., less than or greater than) the number of layers 110 in the first preliminary stack structure 104.

[0062] The etch selectivity of the additional first insulating structure 132 of the second preliminary stack structure 130 may be substantially similar to the etch selectivity of the first insulating structure 106 of the first preliminary stack structure 104. For example, the material composition of the additional first insulating structure 132 may be substantially the same as that of the first insulating structure 106. The etch selectivity of the additional first insulating structure 132 may also be substantially similar to the etch selectivity of the inter-stack dielectric structure 124. For example, the material composition of the additional first insulating structure 132 may be substantially the same as that of the inter-stack dielectric structure 124. In some embodiments, each additional first insulating structure 132 of the second preliminary stack structure 130 is formed of and comprises a dielectric oxide material, such as SiO2. x (For example, SiO2).

[0063] The etch selectivity of the additional second insulating structure 134 of the second preliminary stack structure 130 may be substantially similar to the etch selectivity of the second insulating structure 108 of the first preliminary stack structure 104. For example, the material composition of the additional second insulating structure 134 may be substantially the same as that of the second insulating structure 108. The etch selectivity of the additional second insulating structure 134 may differ from the etch selectivity of the first insulating structure 106, the inter-stack dielectric structure 124 of the first preliminary stack structure 104, and the additional first insulating structure 132 of the second preliminary stack structure 130. The additional second insulating structure 134 and the second insulating structure 108 may be selectively etched relative to the first insulating structure 106, the inter-stack dielectric structure 124, and the additional first insulating structure 132 during common (e.g., collectively, mutually) exposure to the first etchant; and the first insulating structure 106, the inter-stack dielectric structure 124, and the additional first insulating structure 132 may be selectively etched relative to the additional second insulating structure 134 and the second insulating structure 108 during common exposure to different second etchants. In some embodiments, each additional second insulating structure 134 of the second initial stacked structure 130 is formed of and contains a dielectric nitride material, such as SiN. y (For example, Si3N4).

[0064] The second preliminary stacked structure 130, which includes an additional layer 136 comprising an additional first insulating structure 132 and an additional second insulating structure 134, can be formed using conventional processes (e.g., conventional material deposition processes) and conventional processing equipment, which are not described in detail herein.

[0065] like Figure 7B As shown, within the memory array region 112 of the microelectronic device structure 100, a guide pillar structure 138 may be formed to extend vertically from the upper surface of the second preliminary stack structure 130 to the upper surface of the contact structure 116. The guide pillar structure 138 may at least partially (e.g., substantially) rest on and be in physical contact with the contact structure 116. The guide pillar structure 138 may be formed to substantially fill the opening 126 that extends vertically through the inter-stack dielectric structure 124 and the first preliminary stack structure 104. Figure 6A and 6B The remaining portion and the portion formed to extend vertically through the second preliminary stack structure 130 and the plug structure 128 to connect to the opening 126 ( Figure 6A and 6B Additional openings. In other words, the guide post structure 138 can be configured to substantially fill relatively large openings, each of which is formed by opening 126 ( Figure 6A and 6B One of them is formed to extend vertically through the second preliminary stack structure 130 and the plug structure 128 to reach the opening 126. Figure 6A and6B The combination of additional openings in the unfilled portion of one of the components forms the basis of the structure.

[0066] Each of the pillar structures 138 may be formed of and comprise one or more materials that facilitate the formation of a vertical memory cell string within the memory array region 112 of the microelectronic device structure 100 after subsequent processing of the microelectronic device structure 100 (e.g., so-called “gate replacement” or “gate persistence” processing), as described in further detail below. As a non-limiting example, each pillar structure 138 may be formed to comprise a semiconductive structure (e.g., a semiconductive pillar) that is at least partially surrounded horizontally by at least one charge storage structure. For example, the semiconductive structure may comprise a polysilicon structure (e.g., a polysilicon pillar) or a silicon-germanium structure (e.g., a silicon-germanium pillar). For example, the charge storage structure may comprise a charge trapping structure (e.g., a charge trapping structure comprising an oxide-nitride-oxide (“ONO”) material).

[0067] The post structure 138, which includes its semiconducting structure and charge storage structure, can be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein.

[0068] Next reference Figure 8A An upper stadium structure 140 may be formed within a portion of the second preliminary stacked structure 130 within the horizontal boundary of the stepped region 114 of the microelectronic device structure 100. Each upper stadium structure 140 may each include opposing stepped structures 144, each having a step 146 defined by the horizontal end of the additional layer 136 of the second preliminary stacked structure 130. The boundaries (e.g., vertical boundaries, horizontal boundaries) of trenches 142 (e.g., openings) formed to extend vertically into the second preliminary stacked structure 130 may be at least partially defined by the upper stadium structure 140. Each trench 142 may be horizontally interposed between the opposing stepped structures 144 of one of the upper stadium structures 140. Figure 8B Is in Figure 8A The processing stages described in the text revolve around Figure 8A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0069] like Figure 8AAs shown, multiple (e.g., more than one) upper stadium structures 140 may be configured to be positioned within a second preliminary stacking structure 130 at substantially the same elevation (e.g., vertical position) as each other. In some embodiments, the vertical boundary (e.g., uppermost vertical boundary, lowermost vertical boundary) of at least one of the upper stadium structures 140 is substantially the same as the vertical boundary (e.g., uppermost vertical boundary, lowermost vertical boundary) of at least one other of the upper stadium structures 140. In additional embodiments, at least one of the upper stadium structures 140 is configured to be positioned within the second preliminary stacking structure 130 at one or more elevations (e.g., vertical positions) different from at least one other of the upper stadium structures 140. For example, at least one of the upper stadium structures 140 may be configured to exhibit at least one vertical boundary (e.g., a different uppermost vertical boundary, a different lowermost vertical boundary) different from at least one other of the upper stadium structures 140.

[0070] Any desired number and distribution (e.g., spacing and arrangement) of upper stadium structures 140 can be formed in the portion of the second preliminary stacked structure 130 located within the stepped area 114 of the microelectronic device structure 100. For example... Figure 8A As shown, in some embodiments, two (2) upper stadium structures 140 are formed in the portion of the second preliminary stacking structure 130 within the stepped area 114 of the microelectronic device structure 100. In additional embodiments, more than two (2) (e.g., more than or equal to three (3), more than or equal to four (4), more than or equal to five (5), more than or equal to ten (10), more than or equal to twenty-five (25)) upper stadium structures 140 are formed in the portion of the second preliminary stacking structure 130 within the stepped area 114 of the microelectronic device structure 100. In this embodiment, the upper stadium structures 140 may be spaced substantially uniformly (e.g., equally, evenly) such that each of the upper stadium structures 140 is separated from each other of the upper stadium structures 140 that are horizontally adjacent to the stadium structure 12 (e.g., in the X direction) by substantially the same distance; or the upper stadium structures 140 may be spaced at least partially unevenly (e.g., unequally, non-uniformly) such that at least one of the upper stadium structures 140 is separated from at least two other of the upper stadium structures 140 that are horizontally adjacent to the upper stadium structure 140 (e.g., in the X direction) by different (e.g., unequal) distances.

[0071] like Figure 8AAs shown, each upper stadium structure 140 may include a forward step structure 144a and a reverse step structure 144b mirroring the forward step structure 144a. A dashed line extending from the top of the forward step structure 144a to its bottom may have a positive slope, and another dashed line extending from the top of the reverse step structure 144b to its bottom may have a negative slope. In an additional embodiment, one or more of the upper stadium structures 140 (e.g., each) may be modified to include a forward step structure 144a but not a reverse step structure 144b (e.g., the reverse step structure 144b may not exist). In an additional embodiment, one or more of the upper stadium structures 140 (e.g., each) may be modified to include a reverse step structure 144b but not a forward step structure 144a (e.g., the forward step structure 144a may not exist).

[0072] Each upper stadium structure 140 may be configured to include a desired number of steps 146. Each of the upper stadium structures 140 may include substantially the same number of steps 146 as each of the others in the upper stadium structure 140, or at least one of the upper stadium structures 140 may include a different number of steps 146 than at least one of the others in the upper stadium structure 140. In some embodiments, the steps 146 of each upper stadium structure 140 are arranged in an ordered manner such that steps 146 that are horizontally adjacent to each other (e.g., in the X direction) correspond to additional layers 136 of the second preliminary stacking structure 130 that are vertically adjacent to each other (e.g., in the Z direction). In an additional embodiment, one or more of the steps 146 of the upper stadium structure 140 are arranged in a disordered manner such that at least some of the steps 146 of the upper stadium structure 140 that are horizontally adjacent to each other (e.g., in the X direction) correspond to layers 136 of the second preliminary stacking structure 130 that are not vertically adjacent to each other (e.g., in the Z direction).

[0073] The upper stadium structure 140 may be formed in the portion of the second preliminary stacked structure 130 within the stepped region 114 of the microelectronic device structure 100 using conventional processes (e.g., conventional photolithography patterning processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein.

[0074] Next reference Figure 9A The microelectronic device structure 100 may undergo one or more material removal processes (e.g., one or more cleaving processes) to increase the depth of one or more upper stadium structures 140 relative to one or more others (e.g., in the Z direction) and form at least one lower stadium structure 148. Figure 9AAs shown, the lower stadium structure 148 can be configured to be vertically positioned within the first preliminary stacking structure 104, while the upper stadium structure 140 can remain vertically positioned within the second preliminary stacking structure 130. Figure 9B Is in Figure 9A The processing stages described in the text revolve around Figure 9A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0075] The lower stadium structure 148 may be generally similar to the upper stadium structure 140 used to form the lower stadium structure 148, except that it is located at a relatively low vertical position within the microelectronic device structure 100 (e.g., within the first preliminary stacking structure 104 rather than within the second preliminary stacking structure 130). Figure 9A As shown, each lower stadium structure 148 may include opposing stepped structures 150 (e.g., a forward stepped structure 150a and a reverse stepped structure 150b mirroring the forward stepped structure 150a), each opposing stepped structure having a step 152 defined by the horizontal end of the layer 110 of the first preliminary stacking structure 110. The boundaries (e.g., vertical boundaries, horizontal boundaries) of one or more additional trenches 149 (e.g., additional openings) formed to extend vertically through the second preliminary stacking structure 130 and into the first preliminary stacking structure 104 may be partially defined by the lower stadium structure 148. The additional trenches 149 may each be horizontally interposed between the opposing stepped structures 150 of one of the lower stadium structures 148. In addition to being located at the horizontal end of layer 110 of the first preliminary stacked structure 104, the relative stepped structure 150 of the lower stadium structure 148 (including the configuration of its steps 152) may also be formed in a manner generally similar to the relative stepped structure 144 of the upper stadium structure 140 used to form the lower stadium structure 148 (including the configuration of its steps 146).

[0076] like Figure 9AAs shown, layer 110 of the first preliminary stack structure 104, located at the same vertical position (e.g., in the Z direction) as at least a portion of the inter-stack dielectric structure 124, may substantially exclude portions of the lower stadium structure 148 (e.g., steps 152). For example, all steps 152 of the lower stadium structure 148 may be vertically positioned below layer 110 of the first preliminary stack structure 104, located at the same vertical position (e.g., in the Z direction) as at least a portion of the inter-stack dielectric structure 124. Layer 110 of the first preliminary stack structure 104, located at the same vertical position (e.g., in the Z direction) as at least a portion of the inter-stack dielectric structure 124, may form a passive (e.g., dummy) region, subsequently forming a stack structure from the first preliminary stack structure 104 and the second preliminary stack structure 130, as described in further detail below. In an additional embodiment, one or more of the layers 110 of the first initial stacked structure 104, located in the same vertical position (e.g., in the Z direction) as at least a portion of the inter-stack dielectric structure 124, may include portions of the lower stadium structure 148 (e.g., one or more steps 152).

[0077] The lower stadium structure 148 can be formed by placing at least one masking material in at least one of the trenches 142 formed in the second preliminary stack structure 130, while ensuring that at least one other trench 142 formed in the second preliminary stack structure 130 is free of (e.g., unfilled) masking material. The at least one other trench 142 can then be vertically extended into the first preliminary stack structure 104 using at least one material removal process (e.g., at least one cleaving process) to terminate vertically below the lower vertical boundary of the inter-stack dielectric structure 124. Vertically extending the at least one other trench 142 can form additional trenches 149 and the lower stadium structure 148. The masking material can substantially protect portions of the second preliminary stack structure 130 and the first preliminary stack structure 104 that are vertically subordinate to and within the horizontal boundaries of the at least one trench 142 filled therein from removal during the material removal process.

[0078] Next reference Figure 10A It can be found in trench 142 ( Figure 9A ) and additional trench 149 ( Figure 9A An insulating material 154 is formed within the structure, and the microelectronic device structure 100 can undergo a so-called "gate replacement" or "gate persistence" process to at least partially replace the first initial stacked structure 104 with a conductive structure 156. Figure 9A The second insulation structure 108 () Figure 9A ) and the second preliminary stacked structure 130 ( Figure 9A Additional second insulation structure 134 () Figure 9AThis forms a stacked structure 160. The stacked structure 160 includes a vertically alternating (e.g., in the Z direction) sequence of conductive structures 156 and insulating structures 157 arranged as layers 158. The insulating structure 157 may correspond to a first preliminary stacked structure 104. Figure 9A The first insulating structure 106 () Figure 9A ) and the second preliminary stacked structure 130 ( Figure 9A Additional first insulation structure 132 () Figure 9A The remaining portion (e.g., the rest). Each layer 158 of the stacked structure 160 includes at least one of the conductive structures 156 that are vertically adjacent to at least one of the insulating structures 157. Figure 10B Is in Figure 10A The processing stages described in the text revolve around Figure 10A The simplified cross-sectional view of the microelectronic device structure 100 of line AA shown is illustrated.

[0079] The insulating material 154 may be formed of at least one dielectric material and may contain at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbon oxynitride material (e.g., SiO2) x C z N y The insulating material 154 may comprise a substantially uniform or substantially non-uniform distribution of the at least one dielectric material. In some embodiments, the insulating material 154 is made of SiO2. x (For example, SiO2) is formed and contains SiO x The isolation material 154 can be formed using conventional processes (e.g., conventional material deposition processes) and conventional processing equipment, which are not described in detail herein.

[0080] The conductive structure 156 of layer 158 of stacked structure 160 may be formed of and contain at least one conductive material, such as one or more of the following: metals (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe). In some embodiments, the conductive structure 156 is formed of and contains tungsten (W).

[0081] refer to Figure 10B In order to form the conductive structure 156 (and thus the stacked structure 160 comprising the conductive structure 156 and the insulating structure layer 158), a slit 168 (e.g., a gap, a trench) may be formed, which extends vertically through the second preliminary stacked structure 130. Figure 9A and 9B ), inter-stack dielectric structure 124 and first preliminary stacked structure 104 ( Figure 9A and 9B To form discrete blocks 170. Then, the first preliminary stacking structure 104 ( Figure 9A and 9B The second insulation structure 108 () Figure 9A and 9B ) part and second preliminary stacked structure 130 ( Figure 9A and 9B Additional second insulation structure 134 () Figure 9A and 9B A portion of the conductive structure 156 can be selectively removed (e.g., selectively etched and mined) through slit 168 and replaced with a conductive material to form a conductive structure 156. Some of these conductive structures 156 can be used as access line structures (e.g., word line structures) of the microelectronic device structure 100, while others can be used as select gate structures of the microelectronic device structure 100. After forming the conductive structure 156, slit 168 can be filled with at least one dielectric filler material 172 and optionally at least one dielectric liner material 174, such as... Figure 10B As depicted in the text.

[0082] The dielectric filling material 172 formed within and at least partially filling the slit 168 may include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbon oxynitride material (e.g., SiO2) x C z N y The dielectric filler 172 may comprise a substantially uniform or substantially non-uniform distribution of the at least one dielectric material. In some embodiments, the dielectric filler 172 exhibits a substantially uniform distribution of the dielectric material. In other embodiments, the dielectric filler 172 exhibits a substantially non-uniform distribution of at least one dielectric material. For example, the dielectric filler 172 may be formed and comprised of a stack (e.g., a laminate) of at least two different dielectric materials. In some embodiments, the dielectric filler 172 is formed and comprises SiO2. Additionally, if formed, the dielectric liner 174 may be formed to intersect between the dielectric filler 172 and the conductive structure 156 of the stacked structure 160. For example, the dielectric liner material may comprise a non-oxide dielectric material (e.g., a dielectric nitride material, such as SiN). y This is used to hinder or prevent the oxidation of the conductive structure 156 during the formation of the dielectric filler 172 (e.g., if the dielectric filler 172 is formed to include a dielectric oxide material, such as SiO2).

[0083] Refer again Figure 10AAfter forming the stacked structure 160, the microelectronic device structure 100 may include a lower stack 162, an upper stack 164 vertically overlying the lower stack 162, and an inter-stack section 166 vertically intervening between the lower stack 162 and the upper stack 164. The lower stack 162 may include a layer 158 in the stacked structure 160 that vertically lies beneath the inter-stack dielectric structure 124. The upper stack 164 may include a layer 158 in the stacked structure 160 that vertically overly over the inter-stack dielectric structure 124. The inter-stack section 166 may include the inter-stack dielectric structure 124 and a layer 158 in the stacked structure 160 that is horizontally adjacent to and within the vertical boundary of the inter-stack dielectric structure 124. Within the inter-stack section 166, layers 158 of the stacked structure 160 may be horizontally confined within the stepped region 114 of the microelectronic device structure 100, and the inter-stack dielectric structure 124 may be horizontally confined within the memory array region 112 of the microelectronic device structure 100. Layers 158 within the inter-stack section 166 of the stacked structure 160 may include so-called "dummy layers" that do not facilitate electrical connectivity between two or more components (e.g., memory cells, string drivers) of the microelectronic device containing the microelectronic device structure 100. Conversely, at least some layers 158 within the lower stack 162 and upper stack 164 of the microelectronic device structure 100 in the stacked structure 160 include so-called "active layers" that facilitate electrical connectivity between two or more components (e.g., memory cells, string drivers) of the microelectronic device containing the microelectronic device structure 100. Optionally, one or more of the layers 158 of the stacked structure 160 located in the lower stack 162 that are vertically adjacent to (e.g., vertically adjacent to) the inter-stack section 166 may include dummy layers, provided that one or more of the other layers 158 in the lower stack 162 of the stacked structure 160 include active layers; and / or one or more of the layers 158 of the stacked structure 160 located in the upper stack 164 that are vertically adjacent to (e.g., vertically adjacent to) the inter-stack section 166 may include dummy layers, provided that one or more of the other layers 158 in the upper stack 164 of the stacked structure 160 include active layers.

[0084] Therefore, according to embodiments of this disclosure, a microelectronic device includes a microelectronic device structure having a memory array region and a stepped region. The microelectronic device structure includes a stacked structure, a stepped structure, and a semiconductive pillar structure. The stacked structure has layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stacked structure includes a stack comprising a set of layers, an additional stack vertically covering the stack and including an additional set of layers, and an inter-stack section vertically located between the stack and the additional stack. The inter-stack section includes a dielectric structure horizontally confined within the memory array region, and another set of layers located within the vertical boundary of the dielectric structure and horizontally confined within the stepped region. The stepped structure is horizontally confined within the stepped region and has steps, the steps including edges of layers in the stacked structure located within the stack and the additional stack. The semiconductive pillar structure is horizontally confined within the memory array region and extends vertically through the stacked structure.

[0085] Furthermore, according to embodiments of this disclosure, a method of forming a microelectronic device includes forming a microelectronic device structure having a memory array region and a stepped region. The microelectronic device structure is formed to include a first preliminary stack structure, the first preliminary stack structure including a vertically alternating sequence of first and second insulating structures arranged in layers. A dielectric structure is formed within an upper portion of the first preliminary stack structure and generally confined within a horizontal boundary of the memory array region. A second preliminary stack structure is formed above the first preliminary stack structure and the dielectric structure. The second preliminary stack structure includes a vertically alternating sequence of additional first and second insulating structures arranged in additional layers. A semiconducting pillar structure is formed, the semiconducting pillar structure extending vertically through the second preliminary stack structure, the dielectric structure, and the portion of the first preliminary stack structure within the memory array region. A stepped structure is formed within the portions of the second preliminary stack structure and the first preliminary stack structure within the stepped region. Some of these stepped structures have steps at the horizontal ends of layers of the first preliminary stack structure. Other stepped structures have additional steps at the horizontal ends of additional layers of the second preliminary stack structure. The second insulating structure and the additional second insulating structure are at least partially replaced with conductive structures.

[0086] Figures 11A to 20B This is a simplified partial cross-sectional view illustrating an embodiment of another method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). Figure 11B , 12B 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B are respectively around Figure 11A , 12A Partial cross-sectional views of line BB depicted in 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A. (The following text is repeated throughout.) Figures 11A to 20BAnd related descriptions, functioning similarly to previous references. Figures 1A to 10B Features (e.g., structure, material, regions) of the described microelectronic device structure 100 are referred to by similar reference numerals with 100 added. To avoid repetition, Figures 11A to 20B Not all of the features shown are described in detail herein. Instead, unless otherwise described below, they are not all described in detail. Figures 11A to 20B In this context, features indicated by reference numerals with an additional 100 (regardless of whether the previously described features were described before or after this paragraph) should be understood to be substantially similar to the previously described features and formed in substantially the same manner as the previously described features.

[0087] refer to Figure 11A This can form a microelectronic device structure 200, which includes a substrate structure 202, contact structures 216 on or above the substrate structure 202, and a first preliminary stacked structure 204 on or above the substrate structure 202 and contact structures 216. The first preliminary stacked structure 204 includes a vertically alternating (e.g., in the Z direction) sequence of first insulating structures 206 and second insulating structures 208 arranged in layers 210. Figure 11A As shown, the microelectronic device structure 200 includes a memory array region 212 and a stepped region 214 horizontally adjacent (e.g., in the X direction) to a first horizontal boundary of the memory array region 212. A substrate structure 202 and a first preliminary stack structure 204 extend horizontally through the memory array region 212 and the stepped region 214. The substrate structure 202, contact structure 216, first preliminary stack structure 204 (including a layer 210 containing its first insulating structure 206 and second insulating structure 208), the memory array region 212 of the microelectronic device structure 200, and the stepped region 214 of the microelectronic device structure 200 can each be formed in a manner substantially similar to the previously described... Figure 1A The substrate structure 102, contact structure 116, first preliminary stack structure 104 (including layer 110 containing first insulating structure 106 and second insulating structure 108), memory array region 112 of microelectronic device structure 100, and step region 114 of microelectronic device structure 100 are described with reference to the description. Figure 11B Is in Figure 11A The processing stages described in the text revolve around Figure 11A The simplified cross-sectional view of the microelectronic device structure 200 of line BB shown is illustrated.

[0088] Next reference Figure 12A A photoresist structure 218 may be formed on or above the first preliminary stack structure 204. The photoresist structure 218 may extend horizontally above the portions of the first preliminary stack structure 204 located within the memory array region 212 and the stepped region 214 of the microelectronic device structure 200. Figure 12B Is in Figure 12A The processing stages described in the text revolve around Figure 12A The simplified cross-sectional view of the microelectronic device structure 200 of line BB shown is illustrated.

[0089] refer to Figure 12B The photoresist structure 218 may be formed to include an opening 219 extending vertically through it. Each opening 219 may extend vertically to and expose a portion of the upper surface of the first preliminary stack structure 204, and may extend horizontally, generally linearly, through the memory array region 212 and the stepped region 214 of the microelectronic device structure 200, respectively. Figure 12B As shown, opening 219 may be positioned horizontally (e.g., in the Y direction) outside the horizontal boundary (e.g., in the Y direction) of contact structure 216. The horizontal position of opening 219 may correspond to the horizontal position of the slit to be formed through the first preliminary stack structure 204 (and the second preliminary stack structure to be formed on the first preliminary stack structure 204), as described in further detail below. Each opening 219 may be formed with a width W1 (e.g., a horizontal dimension in the Y direction) that is larger than the predetermined width of the slit subsequently formed in the first preliminary stack structure 204 at the horizontal position of opening 219.

[0090] Photoresist structure 218 can be used as a mask to protect the portion of the first preliminary stacked structure 204 (e.g., layer 210 containing its first insulating structure 206 and second insulating structure 208) vertically below it from being removed during subsequent processing, as described in further detail below. Photoresist structure 218 may be formed of and contain photoresist material, such as a positive or negative photoresist material. Suitable photoresist materials (e.g., positive or negative photoresist materials) are known in the art and therefore will not be described in detail herein. For example, photoresist structure 118 may be compatible with: 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm wavelength systems; 193 nm wavelength immersion systems; and / or electron beam lithography systems. Additionally, the photoresist structure 218, including the opening 219 extending therethrough, can be formed using conventional processes (e.g., conventional deposition processes such as PVD, CVD, ALD, and spin coating one or more; conventional photolithography; conventional material removal processes). Such processes are known in the art and therefore will not be described in detail herein.

[0091] Next reference Figure 13AThe microelectronic device structure 200 can undergo a material removal process to selectively remove the relatively vertically higher layer 210 (e.g., the uppermost layer) of the first preliminary stacked structure 204 vertically subordinate to the photoresist structure 218. Figure 12A and 12B Opening 219 in ) Figure 12B The portion of the horizontal boundary that is within the horizontal boundary. Figure 13B Is in Figure 13A The processing stages described in the text revolve around Figure 13A A simplified partial cross-sectional view of the microelectronic device structure 200 of line BB shown. Figure 13B As shown, the material removal process can form recesses 220 (e.g., trenches, openings) that extend partially vertically into the first preliminary stack structure 104. The recesses 220 can each extend substantially linearly horizontally through the memory array region 212 and the stepped region 214 of the microelectronic device structure 200, respectively. Each recess 220 may have a photoresist structure 218 for forming the recess 220. Figure 12A and 12B Opening 219 in ) Figure 12B The photoresist structure 218 has a substantially the same horizontal position (e.g., in the Y direction) and horizontal dimensions (e.g., width W1 in the Y direction and length in the X direction). After forming the recess 220, the photoresist structure 218 can be removed. Figure 12A and 12B The remaining (e.g., not removed) parts (if they exist).

[0092] The material removal process can be controlled to remove a desired number of layers 210 of the first preliminary stacked structure 204 (e.g., the photoresist-free structure 218). Figure 12A and 12B (The protected part). For example Figure 13BAs shown, in some embodiments, the material removal process removes portions of two (2) relatively vertically highest layers 210 (e.g., two (2) uppermost layers) of the first preliminary stack structure 204, including portions of its first insulating structure 206 and second insulating structure 208. In additional embodiments, the material removal process may remove portions of a different number of relatively vertically higher layers 210 of the first preliminary stack structure 204. As a non-limiting example, the material removal process may be controlled to remove a portion of a single (e.g., only one) relatively vertically highest layer 210 (e.g., the uppermost layer) of the first preliminary stack structure 204. As another non-limiting example, the material removal process may be controlled to remove more than two (2) portions of the first preliminary stack structure 204 of the relative vertical highest layer 210, such as three (3) portions of the first preliminary stack structure 204 of the relative vertical highest layer 210 (e.g., three (3) uppermost layers), four (4) portions of the first preliminary stack structure 204 of the relative vertical highest layer 210 (e.g., four (4) uppermost layers), or five (5) or more portions of the first preliminary stack structure 204 of the relative vertical highest layer 210 (e.g., five (5) uppermost layers).

[0093] The first preliminary stacked structure 204 is vertically lower than the photoresist structure 218 in the relatively vertical higher layer 210. Figure 12A and 12B Opening 219 in ) Figure 12B The portion of the horizontal boundary within the horizontal boundary can be removed using conventional material removal processes (e.g., conventional etching processes, such as conventional anisotropic etching processes), which are not described in detail herein. For example, the uppermost layer 210 of the first preliminary stacked structure 204 vertically rests on the photoresist structure 218 ( Figure 12A and 12B Opening 219 in ) Figure 12B The portion of the uppermost layer 210 within the horizontal boundary can be removed using an etching cycle, which includes removing the exposed portion of the second insulating structure 208 of the uppermost layer 210 using a first etching action (e.g., a first anisotropic etching action), and then removing the exposed portion of the first insulating structure 206 of the uppermost layer 210 using a second etching action (e.g., a second anisotropic etching action). Subsequently, one or more additional etching cycles similar to the above etching cycle can be used to remove the portion of one or more additional layers 210 of the first initial stacked structure 204 vertically adhering to the photoresist structure 218 (…). Figure 12A and 12B Opening 219 in ) Figure 12B The portion of the horizontal boundary and within the horizontal boundary is used to form the recess 220 to the desired vertical depth within the first preliminary stacking structure 204.

[0094] Next reference Figure 14A It can be in the recess 220 ( Figure 13B Dielectric filling material 222 is formed outside and on the exposed surface of the first preliminary stacked structure 204. Figure 14B Is in Figure 14A The processing stages described in the text revolve around Figure 14A A simplified partial cross-sectional view of the microelectronic device structure 200 of line BB shown. Figure 14A As shown, dielectric filling material 222 may be formed to cover the surface of the first preliminary stacked structure 204 within the memory array region 212 and the stepped region 214 of the microelectronic device structure 200, and extend substantially across said surface (e.g., extend substantially continuously). Figure 14B As shown, dielectric filler 222 can substantially fill the recess 220 that extends vertically into the first preliminary stack structure 204. Figure 13B ); and can cover the recessed part 220 ( Figure 13B The dielectric filler 222 extends at and outside the boundaries (e.g., horizontal or vertical boundaries) of the first preliminary stacked structure 204 and generally across said surfaces. The dielectric filler 222 may at least partially (e.g., generally) conform to the surface morphology defined by the surface (e.g., horizontal or vertical surface) on which the dielectric filler 222 is formed.

[0095] The material composition of dielectric filler 222 can be substantially similar to that of the previous reference. Figure 13A and 13B The dielectric filling material 222 is described in terms of its material composition. In some embodiments, the dielectric filling material 222 is composed of a dielectric oxide material (e.g., SiO2). x The dielectric filler material 222 is formed using a dielectric oxide material (such as SiO2). Additionally, the dielectric filler material 222 can be formed using conventional processes (e.g., conventional material deposition processes) and conventional processing equipment, which are not described in detail herein.

[0096] Next reference Figure 15A and 15B ( Figure 15B For being in Figure 15A The processing stages described in the text revolve around Figure 15A The simplified cross-sectional view of the microelectronic device structure 200 of line BB shown indicates that the dielectric filling material 222 can be removed. Figure 14A and 14B ) in the concave part 220 ( Figure 13B The portion outside the boundary (e.g., horizontal boundary, vertical boundary) of the dielectric filling material 222 is retained. Figure 14A and 14B ) in the concave part 220 ( Figure 13B The additional portion within the boundary of ) to form an inter-stack dielectric structure 224 ( Figure 15B The removal process may expose the uppermost surface of the first preliminary stacked structure 204 within the memory array region 212 and the stepped region 214 of the microelectronic device structure 200. The uppermost boundary (e.g., the uppermost surface) of the inter-stack dielectric structure 224 may be substantially coplanar with the uppermost boundary (e.g., the uppermost surface) of the first preliminary stacked structure 204.

[0097] The dielectric filler material 122 can be removed using conventional processes (e.g., conventional planarization processes). Figure 14A and 14B ) in the concave part 220 ( Figure 13B The portion outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the dielectric material 222 is used to form the inter-stack dielectric structure 224; these processes are not described in detail herein. For example, at least one CMP process can be used to remove the dielectric filler material 222 ( Figure 14A and 14B ) in the concave part 220 ( Figure 13B The portion outside the boundary of the stack is used to form an inter-stack dielectric structure 224.

[0098] Next reference Figure 16A An opening 226 (e.g., a through-hole) may be formed in the memory array region 212 of the microelectronic device structure 200, and a plug structure 228 may be formed at the upper vertical boundary (e.g., in the Z direction) of the opening 226 to substantially plug (e.g., cover) the opening 226. Figure 16B Is in Figure 16A The processing stages described in the text revolve around Figure 16A The simplified cross-sectional view of the microelectronic device structure 200 of line BB shown is illustrated.

[0099] like Figure 16BAs shown, opening 226 may extend vertically (e.g., in the Z direction) through a portion of the first preliminary stack structure 204 within the memory array region 212 of the microelectronic device structure 200. Opening 226 may be horizontally positioned between portions of the inter-stack dielectric structure 224 within the memory array region 212 of the microelectronic device structure 200 (e.g., in the Y direction). Each opening 226 may be at least partially (e.g., substantially) horizontally aligned (e.g., in the X and Y directions) with a contact structure 216 vertically below it. The lower vertical boundary of opening 226 may be defined by a surface (e.g., upper surface) of contact structure 216, and the horizontal boundary of opening 226 may be defined by a surface (e.g., side surface) of the first preliminary stack structure 204 (e.g., the surfaces of the first insulating structure 206 and the second insulating structure 208 of its layers 210). Opening 226 may then be filled with material to form a post structure within the memory array region 212 of the microelectronic device structure 200, as described in further detail below.

[0100] The geometry (e.g., shape, size) and number of openings 226 can be substantially similar to those in the previous reference. Figure 6A and 6B The geometry and number of openings 126 are described. Additionally, openings 226 can be formed using conventional processes (e.g., conventional photolithography patterning processes, conventional etching processes) and conventional processing equipment, which are not described in detail herein.

[0101] Continue to refer to Figure 16B The plug structure 228 may extend vertically (e.g., in the Z direction) into the first preliminary stack structure 204 and may plug the opening 226. The plug structure 228 may be configured and positioned to protect the opening 226 from being filled with material during additional processing actions to form an additional preliminary stack structure over the first preliminary stack structure 204, as described in further detail below. Each plug structure 228 may be at least partially (e.g., substantially) horizontally aligned (e.g., in the X and Y directions) with one opening 226 vertically below it. The lower vertical boundary of the plug structure 228 may be defined by the upper vertical boundary of the remaining unfilled portion of the opening 126 and a horizontally extending surface in the first preliminary stack structure 204 above the lowermost vertical boundary of the inter-stack dielectric structure 224. Figure 16BAs shown, in some embodiments, the lower vertical boundary of the plug structure 228 is substantially coplanar with the lower vertical boundary of the uppermost vertical layer 210 of the first preliminary stack structure 204. In some embodiments, the lower vertical boundary of the plug structure 228 is vertically offset relative to the lower vertical boundary of the uppermost vertical layer 210 of the first preliminary stack structure 204 (e.g., vertically above or below it). The horizontal boundary of the plug structure 228 may be defined by a vertically extending surface (e.g., a side surface) of the first preliminary stack structure 204. The plug structure 228 may be horizontally positioned between portions of the inter-stack dielectric structure 224 located within the memory array region 212 of the microelectronic device structure 200 (e.g., in the Y direction).

[0102] The geometry (e.g., shape, size) and material composition of the plug structure 228 can be substantially similar to those of the previous reference. Figure 6A and 6B The geometry and material composition of the plug structure 128 are described. Additionally, the plug structure 228 can be formed using conventional processes (e.g., conventional material removal processes such as conventional etching and planarization processes; conventional deposition processes such as conventional non-conformal deposition processes) and conventional processing equipment, which are not described in detail herein.

[0103] Next reference Figure 17A A second preliminary stack structure 230 may be formed on or above the first preliminary stack structure 204, the inter-stack dielectric structure 224, and the plug structure 228; then a guide pillar structure 238 may be formed, which extends vertically through the second preliminary stack structure 230, the plug structure 228, and the first preliminary stack structure 204 within the memory array region 212 of the microelectronic device structure 200. Figure 17A As shown, the second preliminary stacking structure 230 can extend horizontally through the memory array region 212 and the step region 214 of the microelectronic device structure 200, and the guide pillar structure 238 can be horizontally confined within the memory array region 212 of the microelectronic device structure 200. Figure 17B Is in Figure 17A The processing stages described in the text revolve around Figure 17A The simplified cross-sectional view of the microelectronic device structure 100 of line BB shown is shown.

[0104] The second preliminary stack structure 230 may be formed as a vertically alternating (e.g., in the Z direction) sequence comprising additional first insulating structures 232 and additional second insulating structures 234 arranged as additional layers 236. The second preliminary stack structure 230 (the additional layer 236 comprising the additional first insulating structures 232 and additional second insulating structures 234) may be substantially similar to the previously referenced Figure 7A and 7BThe second preliminary stacked structure 130 described includes an additional layer 136 comprising an additional first insulating structure 132 and an additional second insulating structure 134. The second preliminary stacked structure 230 can be formed using conventional processes (e.g., conventional material deposition processes) and conventional processing equipment, which are not described in detail herein.

[0105] Within the memory array region 212 of the microelectronic device structure 200, the guide pillar structure 238 may be formed to extend vertically from the upper surface of the second preliminary stack structure 230 to the upper surface of the contact structure 216. The guide pillar structure 238 may be substantially similar to the previously referenced Figure 7A and 7B The guide pillar structure 138 is described. Additionally, the guide pillar structure 238 can be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein.

[0106] Next reference Figure 18A An upper stadium structure 240 may be formed within a portion of the second preliminary stacking structure 230 within the horizontal boundary of the stepped region 214 of the microelectronic device structure 200. Each upper stadium structure 240 may each include opposing stepped structures 244 (e.g., a forward stepped structure 244a and a reverse stepped structure 244b mirroring the forward stepped structure 244a), each opposing stepped structure having a step 246 defined by the horizontal end of the additional layer 236 of the second preliminary stacking structure 230. The boundaries (e.g., vertical boundaries, horizontal boundaries) of trenches 242 (e.g., openings) formed to extend vertically into the second preliminary stacking structure 230 may be at least partially defined by the upper stadium structure 240. Each trench 242 may be horizontally interposed between the opposing stepped structures 244 of one of the upper stadium structures 240. Figure 18B Is in Figure 18A The processing stages described in the text revolve around Figure 18A The simplified cross-sectional view of the microelectronic device structure 200 of line BB shown is illustrated.

[0107] The upper stadium structure 240 (including the relative stepped structure 244 and its steps 246) and the trench 242 can be substantially similar to those in the previous reference. Figure 8A and 8B The superstructure 140 of the stadium (including the relative stepped structure 144 and its steps 146) and the trench 142 are described. The superstructure 240 of the stadium can be formed using conventional processes (e.g., conventional photolithography patterning processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein.

[0108] Next reference Figure 19AThe microelectronic device structure 200 may undergo one or more material removal processes (e.g., one or more cleaving processes) to increase the depth of one or more upper stadium structures 240 relative to one or more others (e.g., in the Z direction) and form at least one lower stadium structure 248. Figure 19A As shown, the lower stadium structure 248 can be configured to be vertically positioned within the first preliminary stacking structure 204, while the upper stadium structure 240 can remain vertically positioned within the second preliminary stacking structure 230. Figure 19B Is in Figure 19A The processing stages described in the text revolve around Figure 19A The simplified cross-sectional view of the microelectronic device structure 200 of line BB shown is illustrated.

[0109] like Figure 19A As shown, each lower stadium structure 248 may include opposing stepped structures 250 (e.g., a forward stepped structure 250a and a reverse stepped structure 250b mirroring the forward stepped structure 250a), each opposing stepped structure having a step 252 defined by the horizontal end of the layer 210 of the first preliminary stacking structure 204. The boundaries (e.g., vertical boundaries, horizontal boundaries) of one or more additional trenches 249 (e.g., additional openings) formed to extend vertically through the second preliminary stacking structure 230 and into the first preliminary stacking structure 204 may be partially defined by the lower stadium structure 248. The additional trenches 249 may each be horizontally interposed between the opposing stepped structures 250 of one of the lower stadium structures 248. Except at the horizontal end of layer 210 of the first preliminary stacked structure 204, the relative stepped structure 250 of the lower stadium structure 248 (including the configuration of its steps 252) can be formed in a manner generally similar to the relative stepped structure 244 of the upper stadium structure 240 used to form the lower stadium structure 248 (including the configuration of its steps 246).

[0110] like Figure 19AAs shown, layer 210 of the first preliminary stack structure 204, located at the same vertical position (e.g., in the Z direction) as a portion of the inter-stack dielectric structure 134, may substantially exclude portions of the lower stadium structure 248 (e.g., steps 152). For example, all steps 252 of the lower stadium structure 248 may be vertically positioned below layer 210 of the first preliminary stack structure 204, located at the same vertical position (e.g., in the Z direction) as a portion of the inter-stack dielectric structure 224. Layer 210 of the first preliminary stack structure 204, located at the same vertical position (e.g., in the Z direction) as a portion of the inter-stack dielectric structure 224, may form a passive (e.g., dummy) region, subsequently forming a stack structure from the first preliminary stack structure 204 and the second preliminary stack structure 230, as described in further detail below. In an additional embodiment, one or more layers 210 of the first initial stacked structure 204, located in the same vertical position (e.g., in the Z direction) as a portion of the inter-stack dielectric structure 224, may include portions of the lower stadium structure 248 (e.g., one or more steps 252).

[0111] The lower stadium structure 248 (including the relative stepped structure 250 and its steps 252) and the additional trench 249 can be generally similar to those in the previous reference. Figure 9A and 9B The process described for forming the lower stadium structure 148 (including the relative stepped structure 150 and its steps 152) and the additional trench 149 is described.

[0112] Next reference Figure 20A It can be found in trench 242 ( Figure 19A ) and additional trench 249 ( Figure 19A An insulating material 254 is formed within the structure, and the microelectronic device structure 200 can undergo a so-called "replacement gate" or "gate persistence" process to at least partially replace the first initial stacked structure 204 with a conductive structure 256. Figure 19A The second insulation structure 208 () Figure 19A ) and the second preliminary stacked structure 230 ( Figure 19A Additional second insulation structure 234 () Figure 19A Some (e.g., less than all) of them are stacked to form structure 260. The insulating material 254 and the conductive structure 256 may be substantially similar to those in the previous reference. Figure 10A and 10B The insulating material 154 and the conductive structure 156 are described. Figure 20B Is in Figure 20A The processing stages described in the text revolve around Figure 20A The simplified cross-sectional view of the microelectronic device structure 200 of line BB shown is illustrated.

[0113] refer to Figure 20BThe stacked structure 260 includes a vertically alternating (e.g., in the Z direction) sequence of conductive structures 256 and insulating structures 257 arranged as layers 258, positioned vertically above and below the inter-stack dielectric structure 224; and also includes layers 210 of a first insulating structure 206 and a second insulating structure 208 located vertically within the vertical boundary of the inter-stack dielectric structure 224. The insulating structure 257 may correspond to a first preliminary stacked structure 204 located vertically outside (e.g., beyond) the vertical boundary of the inter-stack dielectric structure 224. Figure 9A The first insulating structure 206 () Figure 9A ) and the second preliminary stacked structure 230 ( Figure 9A Additional first insulation structure 232 () Figure 9A The remaining portion (e.g., the rest). Each layer 258 of the stacked structure 260 includes at least one of the conductive structures 256 that are vertically adjacent to at least one of the insulating structures 257.

[0114] Continue to refer to Figure 20B To form the stacked structure 260, slits 268 (e.g., gaps, grooves) can be formed, which extend vertically through the second preliminary stacked structure 230. Figure 19A and 19B ), inter-stack dielectric structure 224 and first preliminary stacked structure 204 ( Figure 19A and 19B This forms discrete blocks 270. Each slit 268 may be formed having a width W2 (e.g., a dimension in the Y direction), which is smaller than the width W1 of the inter-stack dielectric structure 224 through which the slit 268 extends vertically. Subsequently, a second preliminary stacked structure 230 ( Figure 19A and 19B Additional second insulation structure 234 () Figure 19A and 19B ) part and the first preliminary stacked structure 204 ( Figure 19A and 19B The second insulation structure 208 () Figure 19A and 19BThe portion of the second insulating structure 208 outside the vertical boundary of the inter-stack dielectric structure 224 can be selectively removed (e.g., selectively etched and mined) through slit 268 and replaced with a conductive material to form conductive structure 256. The remaining portion of the inter-stack dielectric structure 224 can substantially prevent the portion of the second insulating structure 208 within the vertical boundary of the inter-stack dielectric structure 224 from being removed through slit 268 and replaced with a conductive material. Some of these conductive structures 256 can be used as access line structures (e.g., word line structures) of the microelectronic device structure 200, while others can be used as select gate structures of the microelectronic device structure 200. After forming the conductive structure 256, slit 268 can be filled with at least one dielectric filler material 272 and optionally at least one dielectric liner material 274, such as... Figure 20B The dielectric filler material 272 and dielectric liner material 274 (if formed) are respectively substantially similar to those described in the previous reference. Figure 10B The dielectric filler material 172 and dielectric liner material 174 are described.

[0115] Refer again Figure 20AAfter forming the stacked structure 260, the microelectronic device structure 200 may include a lower stack 262, an upper stack 264 vertically overlying the lower stack 262, and an inter-stack section 266 vertically intervening between the lower stack 262 and the upper stack 264. The lower stack 262 may include a layer 258 (including its conductive structure 256 and insulating structure 257) vertically overlying the inter-stack dielectric structure 224 in the stacked structure 260. The upper stack 264 may include a layer 258 (including its conductive structure 256 and insulating structure 257) vertically overlying the inter-stack dielectric structure 224 in the stacked structure 260. The inter-stack section 266 may include the inter-stack dielectric structure 224 and a layer 210 (including its first insulating structure 206 and second insulating structure 208) horizontally adjacent to and within the vertical boundary of the inter-stack dielectric structure 224 in the stacked structure 260. Layer 210 within the inter-stack segment 266 of the stacked structure 260 may include so-called "dummy layers" that do not facilitate electrical connectivity between two or more components (e.g., memory cells, string drivers) of the microelectronic device containing the microelectronic device structure 200. Conversely, at least some of the layers 258 within the lower stack 262 and upper stack 264 of the microelectronic device structure 200 in the stacked structure 260 include so-called "active layers" that facilitate electrical connectivity between two or more components (e.g., memory cells, string drivers) of the microelectronic device containing the microelectronic device structure 200. Optionally, one or more of the layers 258 in the lower stack 262 of the stack structure 260 that are vertically adjacent to (e.g., vertically adjacent to) the inter-stack section 266 may include dummy layers, provided that one or more of the other layers 258 in the lower stack 262 of the stack structure 260 include active layers; and / or one or more of the layers 258 in the upper stack 264 of the stack structure 260 that are vertically adjacent to (e.g., vertically adjacent to) the inter-stack section 266 may include dummy layers, provided that one or more of the other layers 258 in the upper stack 264 of the stack structure 260 include active layers.

[0116] Therefore, according to embodiments of this disclosure, a microelectronic device includes a microelectronic device structure comprising a stacked structure, a stepped structure, and a semiconductive pillar structure. The stacked structure has layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stacked structure includes a lower stack including some of these layers, an upper stack overlying the stack and including other layers, and an inter-stack section between the lower and upper stacks. The inter-stack section includes an inter-stack dielectric structure and additional layers horizontally positioned between the inter-stack dielectric structures. Each of the additional layers includes an additional insulating structure and another insulating structure vertically adjacent to the additional insulating structure. The stepped structure has steps, the steps including the edges of layers within the lower and upper stacks of the stacked structure. The semiconductive pillar structure extends vertically through the stacked structure.

[0117] Furthermore, according to embodiments of this disclosure, a method of forming a microelectronic device includes forming a microelectronic device structure including a first preliminary stacked structure, the first preliminary stacked structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in layers. A dielectric structure is formed to extend vertically into the first preliminary stacked structure. The dielectric structures are horizontally spaced apart from each other in a first direction and extend horizontally in a generally linear manner in a second direction orthogonal to the first direction. A second preliminary stacked structure is formed over the first preliminary stacked structure and the dielectric structures. The second preliminary stacked structure includes a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged as additional layers. A semiconductive pillar structure is formed, the semiconductive pillar structure extending vertically through portions of the second preliminary stacked structure and the first preliminary stacked structure horizontally positioned between the dielectric structures. A stepped structure is formed within the second preliminary stacked structure and the first preliminary stacked structure. Some of these stepped structures have steps at the edges of the layers of the first preliminary stacked structure. Other stepped structures have additional steps at the edges of the additional layers of the second preliminary stacked structure. The additional second insulating structure of the second preliminary stack structure, located outside the vertical boundary of the dielectric structure, and the second insulating structure of the first preliminary stack structure are replaced with conductive structures.

[0118] Figure 21 This is a partially sectional perspective view showing a portion of a microelectronic device 300 (e.g., a memory device, such as a 3D NAND flash memory device) including a microelectronic device structure 302. The microelectronic device structure 302 may be substantially similar to that in the previous reference. Figure 10A and 10B The microelectronic device structure 100 or microelectronic device structure 302 described in the processing stage may be substantially similar to that in the previous reference. Figure 20A and 20B The microelectronic device structure 200 of the described processing stage. In some embodiments, the microelectronic device structure 302 is based on the previously referenced... Figures 1A to 10B The described process is formed. In an additional embodiment, the microelectronic device structure 302 is described in the previous reference. Figures 11A to 20B The process described is formed. For example... Figure 21 As shown, the microelectronic device structure 302 may include: a stacked structure 304 comprising a vertically alternating (e.g., in the Z direction) sequence of conductive structures 306 and insulating structures 308 arranged as layers 310; and a stepped structure 312 having a step 314 defined by an edge of the layer 310 (e.g., a horizontal end in the X direction). In some embodiments, the stacked structure 304, conductive structures 306, insulating structures 308, layers 310, stepped structure 312, and step 314 are each substantially similar to those in the previous reference. Figure 10A and 10B The described stacked structure 160, conductive structure 156, insulating structure 157, layer 158, stepped structures 144 and 150, and steps 146 and 152. In such embodiments, the microelectronic device structure 302 further includes an inter-stack dielectric structure that is generally similar to that described in the previous reference. Figure 10A and 10B The microelectronic device structure 100 depicted in the process stage describes the inter-stack dielectric structure 124. In an additional embodiment, the stack structure 304, conductive structure 306, insulating structure 308, layer 310, step structure 312, and step 314 are respectively substantially similar to those in the previous reference. Figure 20A and 20B The described stacked structures 260, conductive structures 256, insulating structures 257, layers 258, stepped structures 244 and 250, and steps 246 and 252 are described. In such embodiments, the microelectronic device structure 302 further includes inter-stack dielectric structures and additional layers, which are generally similar to those in the previous reference. Figure 20A and 20B The microelectronic device structure 300 depicted in the process phase describes the inter-stack dielectric structure 224 and layer 210 (including its first insulating structure 206 and second insulating structure 208). The microelectronic device 300 also includes additional features (e.g., structures, devices) operatively associated with the microelectronic device structure 302, as described in further detail below.

[0119] The microelectronic device 300 may further include a vertical string 319 of memory cells 320 coupled in series with each other, data lines 322 (e.g., bit lines), source structures 324, access lines 326, a first select gate 328 (e.g., upper select gate, drain select gate (SGD)), select line 330, a second select gate 332 (e.g., lower select gate, source select gate (SGS)), contact structures 318, and additional contact structures 334. The vertical string 319 of the memory cells 320 extends vertically and orthogonally to the conductive lines and layers (e.g., data lines 322, source structures 324, layer 310 of the stacked structure 304, access line 326, first select gate 328, select line 330, and second select gate 332). Contact structure 318 and additional contact structure 334 can electrically couple components to each other, as shown (e.g., electrically couple select line 330 to first select gate 328, and electrically couple access line 326 to layer 310 of stacked structure 304 of microelectronic device structure 302).

[0120] Continue to refer to Figure 21 The microelectronic device 300 may also include a control unit 336 (e.g., a control device) vertically positioned below the vertical string 319 of the memory cell 320, which may include one or more of the following: a string driver circuitry, a pass-through gate, a circuitry for selecting a gate, a circuitry for selecting conductive lines (e.g., access line 326, select line 330, data line 322, additional access line, additional select line, additional data line), a circuitry for amplifying signals, and a circuitry for sensing signals. In some embodiments, the control unit 336 is at least partially (e.g., substantially) positioned within the horizontal boundaries (e.g., in the X and Y directions) of the horizontal region occupied by the vertical string 319 of the memory cell 320. For example, the control unit 336 may be electrically coupled to the data line 322, the source structure 324, the access line 326, and the select line 330. In some embodiments, the control unit 336 includes a complementary metal-oxide-semiconductor (CMOS) circuitry. In such embodiments, the control unit 336 may be characterized as having an “array-controlled CMOS” (“CuA”) configuration.

[0121] Microelectronic device structures according to embodiments of the present disclosure (e.g., previously referenced) Figure 10A and 10B The microelectronic device structure 100 described; previous references Figure 20A and 20B The microelectronic device structure 200 described herein and the microelectronic device (e.g., previously referenced) Figure 21 The described microelectronic device 300 can be used in embodiments of the electronic systems disclosed herein. For example, Figure 22This is a block diagram of an illustrative electronic system 400 according to embodiments of the present disclosure. For example, electronic system 400 may include a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, Wi-Fi, or a cellular-enabled tablet computer (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 400 includes at least one memory device 402. For example, memory device 402 may include one or more embodiments of the microelectronic device architecture and microelectronic devices described earlier herein. Electronic system 400 may further include at least one electronic signal processor device 404 (generally referred to as a “microprocessor”). Optionally, electronic signal processor device 404 may include one or more embodiments of the microelectronic device architecture and microelectronic devices described earlier herein. Although memory device 402 and electronic signal processor device 404 are... Figure 22 While depicted as two (2) separate devices, in additional embodiments, electronic system 400 includes a single (e.g., only one) memory / processor device having the functions of memory device 402 and electronic signal processor device 404. In such embodiments, the memory / processor device may include one or more of the microelectronic device architectures and microelectronic devices described previously herein. Electronic system 400 may further include one or more input devices 406 for a user to input information into electronic system 400, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 400 may further include one or more output devices 408 for outputting information to a user (e.g., visual or audio output), such as one or more of a monitor, display, printer, audio output jack, and speaker. In some embodiments, input device 406 and output device 408 may include a single touchscreen device that can be used both to input information into electronic system 400 and to output visual information to a user. Input device 406 and output device 408 may be electrically connected to one or more of memory device 402 and electronic signal processor device 404.

[0122] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device and including at least one microelectronic device structure having a memory array region and a step region. The at least one microelectronic device structure includes a stacked structure, a step structure, and a semiconductive pillar structure. The stacked structure has layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stacked structure includes a stack comprising some of these layers, an additional stack vertically covering the stack and including other layers, and an inter-stack section vertically located between the stack and the additional stack. The inter-stack section includes at least one dielectric structure located within the horizontal boundary of the memory array region and substantially absent or incompletely extending across the horizontal region of the step region. The step structure is located within the step region and has steps, the steps including edges of layers in the stacked structure located within the stack and the additional stack. The semiconductive pillar structure is located within the memory array region and extends vertically through the stacked structure.

[0123] Compared to conventional structures, devices, and systems, the methods, structures (e.g., microelectronic device structures 100, 200, 302), devices (e.g., microelectronic device 300), and systems (e.g., electronic system 400) of this disclosure advantageously facilitate one or more of the following: improved performance, reliability, and durability; reduced cost; increased component miniaturization; improved pattern quality; and increased package density. The methods and structures of this disclosure can alleviate problems associated with the formation and processing of conventional microelectronic devices (including stacked structures with stepped edges). For example, the methods and structures of this disclosure allow stepped structure configurations formed in one or more relatively vertically taller preliminary stacked structures (e.g., second preliminary stacked structures 130, 230) to be efficiently transferred using a simple cleaving process to one or more relatively vertically shorter preliminary stacked structures (e.g., first preliminary stacked structures 104, 204), thereby avoiding the complex, inefficient, and expensive processes (e.g., separate step-forming processes, each comprising a series of masking and etching actions) traditionally associated with forming stepped structures within different stacks of conventional microelectronic device structures.

[0124] Additional non-limiting example embodiments of this disclosure are described below.

[0125] Example 1: A microelectronic device comprising: a microelectronic device structure having a memory array region and a step region, the microelectronic device structure comprising: a stacked structure having layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure comprising: a stack including a set of the layers; an additional stack vertically covering the stack and including an additional set of the layers; and an inter-stack section vertically located between the stack and the additional stack, the inter-stack section comprising: a dielectric structure horizontally confined within the memory array region; and another set of the layers located within the vertical boundary of the dielectric structure and horizontally confined within the step region; a step structure horizontally confined within the step region and having steps, the steps including edges of the layers in the stack structure located within the stack and the additional stack; and a semiconducting post structure horizontally confined within the memory array region and extending vertically through the stacked structure.

[0126] Example 2: The microelectronic device according to Example 1 further includes a plug structure that is located within a dielectric structure and horizontally surrounds the semiconductive post structure.

[0127] Example 3: A microelectronic device according to one of Examples 1 and 2, wherein the other set of layers in the inter-stack section of the stacked structure includes at least two of the layers of the stacked structure.

[0128] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the dielectric structure and the insulating structure of each layer of the stacked structure comprise at least one dielectric oxide material.

[0129] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the inter-stack section of the stacked structure does not contain any portion of the stepped structure within its vertical boundary.

[0130] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein the stepped structure includes: a first stadium structure, which is located within the stack of the stacked structure and includes: a first stepped structure having a positive slope; and a second stepped structure opposite to the first stepped structure and having a negative slope; and a second stadium structure, which is located within the additional stack of the stacked structure and includes: a third stepped structure having a positive slope; and a fourth stepped structure opposite to the third stepped structure and having a negative slope.

[0131] Example 7: A method of forming a microelectronic device, comprising: forming a microelectronic device structure having a memory array region and a stepped region, the microelectronic device structure being formed to include a first preliminary stack structure, the first preliminary stack structure including a vertically alternating sequence of a first insulating structure and a second insulating structure arranged in layers; forming a dielectric structure located within an upper portion of the first preliminary stack structure and substantially confined within a horizontal boundary of the memory array region; forming a second preliminary stack structure above the first preliminary stack structure and the dielectric structure, the second preliminary stack structure including additional first insulating structures and additional second insulating structures arranged in additional layers. A straight alternating sequence; forming a semiconductive post structure that extends vertically through the second preliminary stack structure, the dielectric structure, and the portion of the first preliminary stack structure located within the memory array region; forming a stepped structure within the portion of the second preliminary stack structure and the first preliminary stack structure located within the stepped region, some of the stepped structures having steps including the horizontal ends of the layers of the first preliminary stack structure, and other stepped structures having additional steps including the horizontal ends of the additional layers of the second preliminary stack structure; and at least partially replacing the second insulating structure and the additional second insulating structure with a conductive structure.

[0132] Example 8: According to the method of Example 7, forming a dielectric structure in the upper portion of the first preliminary stack structure includes: forming a photoresist structure on the portion of the first preliminary stack structure located within the stepped region; selectively removing the upper portion of the first preliminary stack structure using the photoresist structure as a mask to form a recess, the recess being located within the first preliminary stack structure and generally confined within the horizontal boundary of the memory array region; forming a dielectric filler material on the exposed surface of the first preliminary stack structure inside and outside the recess; and removing portions of the dielectric filler material outside the horizontal and vertical boundaries of the recess to form the dielectric structure.

[0133] Example 9: The method according to one of Examples 7 and 8 further includes selecting the first insulating structure of the first preliminary stacked structure, the dielectric structure, and the additional first insulating structure of the second preliminary stacked structure to each comprise a dielectric oxide material.

[0134] Example 10: The method according to any one of Examples 7 to 9, wherein forming a semiconductive post structure includes: forming an opening extending vertically through the dielectric structure and the first preliminary stack structure, lying beneath the lower portion of the dielectric structure; covering the opening with a plug structure extending partially vertically into the opening; forming a second preliminary stack structure above the first preliminary stack structure, the dielectric structure, and the plug structure; forming an additional opening extending vertically through the second preliminary stack structure and the plug structure to the remaining portion of the opening to form a relatively large opening; and filling the relatively large opening with a semiconductive material.

[0135] Example 11: The method according to any one of Examples 7 to 10, wherein forming a stepped structure within the portion of the second preliminary stacking structure and the first preliminary stacking structure located within the stepped area comprises: forming a stadium structure within the second preliminary stacking structure, the stadium structure comprising: a first of the stepped structures having a positive slope; and a second of the stepped structures having a negative slope opposite to the first of the stepped structures; and forming an additional stadium structure within the first preliminary stacking structure, the additional stadium structure comprising: a third of the stepped structures having a positive slope; and a fourth of the stepped structures having a negative slope opposite to the third of the stepped structures.

[0136] Example 12: According to the method of Example 11, forming an additional stadium structure within the first preliminary stacking structure includes subjecting the second preliminary stacking structure to a splitting process to vertically extend an opening defined by another stadium structure formed within the second preliminary stacking structure into the first preliminary stacking structure and form the additional stadium structure.

[0137] Example 13: The method according to any one of Examples 7 to 12, wherein replacing the second insulating structure and the additional second insulating structure with a conductive structure at least partially includes replacing the second insulating structure and the additional second insulating structure with tungsten at least partially.

[0138] Example 14: A microelectronic device comprising: a microelectronic device structure including: a stacked structure having layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure including: a lower stack including some of the layers; an upper stack covering the stack and including other layers; and an inter-stack section between the lower stack and the upper stack, the inter-stack section including: an inter-stack dielectric structure; and additional layers horizontally between the inter-stack dielectric structures, each of the additional layers including an additional insulating structure and another insulating structure vertically adjacent to the additional insulating structure; a stepped structure having steps, the steps including edges of the layers in the stacked structure within the lower stack and the upper stack; and a semiconductive post structure extending vertically through the stacked structure.

[0139] Example 15: The microelectronic device according to Example 14, wherein the semiconducting post structure is horizontally positioned between the inter-stack dielectric structures.

[0140] Example 16: A microelectronic device according to one of Examples 14 and 15, wherein the semiconducting pillar structure extends vertically through a first set of layers in the upper stack of the stacked structure, an additional layer in the stacked structure in the inter-stack section of the stacked structure, and a second set of layers in the lower stack of the stacked structure.

[0141] Example 17: A microelectronic device according to any of Examples 14 to 16, further comprising a filling slit extending vertically through the layers of the stacked structure and the inter-stack dielectric structure, each filling slit being filled with at least one dielectric material.

[0142] Example 18: A microelectronic device according to any of Examples 14 to 17, wherein the inter-stack dielectric structure, the insulating structure of each layer in the lower stack and the upper stack of the stacked structure, and the additional insulating structure of each additional layer in the inter-stack section of the stacked structure comprise at least one dielectric oxide material.

[0143] Example 19: A microelectronic device according to any of Examples 14 to 18, wherein the other insulating structure of each of the additional layers within the inter-stack section of the stacked structure comprises at least one dielectric nitride material.

[0144] Example 20: A microelectronic device according to any one of Examples 14 to 19, wherein the stepped structure includes: a stadium structure located within the upper stack of the stacked structure and including: a first stepped structure having a positive slope; and a second stepped structure mirrored with the first stepped structure and having a negative slope; and an additional stadium structure located within the lower stack of the stacked structure and including: a third stepped structure having a positive slope; and a fourth stepped structure mirrored with the third stepped structure and having a negative slope.

[0145] Example 21: A method of forming a microelectronic device, comprising: forming a microelectronic device structure including a first preliminary stacked structure, the first preliminary stacked structure including a vertically alternating sequence of first insulating structures and second insulating structures arranged in layers; forming a dielectric structure extending vertically into the first preliminary stacked structure, the dielectric structures being horizontally spaced apart from each other in a first direction and extending substantially linearly horizontally in a second direction orthogonal to the first direction; forming a second preliminary stacked structure above the first preliminary stacked structure and the dielectric structures, the second preliminary stacked structure including a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged in additional layers; forming a semi-... A conductive post structure, the semiconductive post structure extending vertically through the portion of the second preliminary stack structure and the first preliminary stack structure horizontally positioned between the dielectric structure; a stepped structure formed within the second preliminary stack structure and the first preliminary stack structure, some of the stepped structures having steps including the edges of the layers of the first preliminary stack structure, and other stepped structures having additional steps including the edges of the additional layers of the second preliminary stack structure; and replacing the additional second insulating structure of the second preliminary stack structure positioned outside the vertical boundary of the dielectric structure and the second insulating structure of the first preliminary stack structure with a conductive structure.

[0146] Example 22: According to the method of Example 21, forming a dielectric structure extending vertically into the first preliminary stack structure includes: forming a photoresist structure on the first preliminary stack structure, the photoresist structure including a photoresist material having an opening extending vertically through it; selectively removing an upper portion of the first preliminary stack structure exposed through the opening in the photoresist material of the photoresist structure and located within the horizontal boundary of the opening to form a recess within the first preliminary stack structure; forming a dielectric filler material on an exposed surface of the first preliminary stack structure inside and outside the recess; and removing a portion of the dielectric filler material outside the boundary of the recess to form the dielectric structure.

[0147] Example 23: The method according to one of Examples 21 and 22 further includes: selecting the first insulating structure of the first preliminary stacked structure, the dielectric structure, and the additional first insulating structure of the second preliminary stacked structure to each include a dielectric oxide material; and selecting the second insulating structure of the first preliminary stacked structure and the additional second insulating structure of the second preliminary stacked structure to each include a dielectric nitride material.

[0148] Example 24: The method according to any one of Examples 21 to 23, wherein forming a semiconductive post structure includes: forming an opening extending vertically through a portion of the first preliminary stack structure horizontally positioned between the dielectric structures; covering the opening with a plug structure extending partially vertically into the opening; forming a second preliminary stack structure above the first preliminary stack structure, the dielectric structures, and the plug structure; forming an additional opening extending vertically through the second preliminary stack structure and the plug structure to the remaining portion of the opening to form a relatively large opening; and filling the relatively large opening with a semiconductive material.

[0149] Example 25: The method according to any one of Examples 21 to 24, wherein forming a stepped structure within the second preliminary stacking structure and the first preliminary stacking structure includes: forming a first stadium structure within the second preliminary stacking structure, the first stadium structure including: a first member of the stepped structure; and a second member of the stepped structure mirroring the first member of the stepped structure; and forming a second stadium structure within the first preliminary stacking structure, the second stadium structure including: a third member of the stepped structure; and a fourth member of the stepped structure mirroring the third member of the stepped structure.

[0150] Example 26: According to the method of Example 25, forming a second stadium structure within the first preliminary stacking structure includes extending an opening defined by a third stadium structure formed within the second preliminary stacking structure vertically into the first preliminary stacking structure to form the second stadium structure.

[0151] Example 27: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure having a memory array region and a step region, the at least one microelectronic device structure including: a stacked structure having layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure including: a stack including some of the layers; an additional stack vertically covering the stack and including other layers; and an inter-stack section vertically between the stack and the additional stack, the inter-stack section including at least one dielectric structure located within a horizontal boundary of the memory array region and substantially not present in or partially extending across the horizontal region of the step region; a step structure located within the step region and having steps including the edges of the layers in the stacked structure located within the stack and the additional stack; and a semiconducting pillar structure located within the memory array region and extending vertically through the stacked structure.

[0152] Specific embodiments have been illustrated by way of example in the accompanying drawings and described in detail herein, but this disclosure is readily subject to various modifications and alternatives. However, this disclosure is not limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the scope of the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: A microelectronic device structure having a memory array region and a step region, the microelectronic device structure comprising: A stacked structure having layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure comprising: A stack comprising a set of the aforementioned layers; An additional stack, which vertically overlies the stack and includes an additional set of the layers; and An inter-stack section, vertically located between the stacked group and the additional stacked group, the inter-stack section comprising: Dielectric structure, the horizontal of which is confined within the memory array region; and Another set of the layers is located within the vertical boundary of the dielectric structure and horizontally confined within the stepped area; A stepped structure, horizontally confined within the stepped area and having steps including the edges of the layers within the stacked group and the additional stacked group in the stacked structure; and A semiconducting post structure, which is horizontally confined within the memory array area and extends vertically through the stacked structure.

2. The microelectronic device of claim 1, further comprising a plug structure, the plug structure being situated within a dielectric structure and horizontally surrounding the semiconductive post structure.

3. The microelectronic device of claim 1, wherein the other set of layers within the inter-stack section of the stacked structure comprises at least two of the layers of the stacked structure.

4. The microelectronic device according to any one of claims 1 to 3, wherein the dielectric structure and the insulating structure of each layer of the stacked structure comprise at least one dielectric oxide material.

5. The microelectronic device according to any one of claims 1 to 3, wherein the inter-stack section of the stacked structure does not contain any portion of the stepped structure within its vertical boundary.

6. The microelectronic device according to any one of claims 1 to 3, wherein the stepped structure comprises: A first stadium structure, which is located within the stack of the stacked structure and includes: The first step structure with a positive slope; and A second step structure with a negative slope, opposite to the first step structure; and A second stadium structure, which is located within the additional stack of the stacked structure and includes: A third-step structure with a positive slope; and A fourth step structure that is opposite to the third step structure and has a negative slope.

7. A method for forming a microelectronic device, comprising: A microelectronic device structure having a memory array region and a stepped region is formed, the microelectronic device structure being formed to include a first preliminary stacking structure, the first preliminary stacking structure including a vertically alternating sequence of a first insulating structure and a second insulating structure arranged in layers; A dielectric structure is formed, which is located in the upper portion of the first preliminary stacked structure and confined within the horizontal boundary of the memory array region; A second preliminary stack structure is formed on top of the first preliminary stack structure and the dielectric structure, the second preliminary stack structure comprising a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged as additional layers; A semiconductive post structure is formed, which extends vertically through the second preliminary stack structure, the dielectric structure, and the portion of the first preliminary stack structure located within the memory array region; A stepped structure is formed within the portion of the stepped area in the second preliminary stacking structure and the first preliminary stacking structure, some of the stepped structures having a step including the horizontal end of the layer of the first preliminary stacking structure, and other stepped structures having an additional step including the horizontal end of the additional layer of the second preliminary stacking structure; and The second insulating structure and the additional second insulating structure are at least partially replaced with conductive structures.

8. The method of claim 7, wherein forming a dielectric structure within the upper portion of the first preliminary stacked structure comprises: A photoresist structure is formed on the portion of the first preliminary stacked structure located within the stepped region; Using the photoresist structure as a mask, the upper portion of the first preliminary stack structure is selectively removed to form a recess, the recess being located within the first preliminary stack structure and confined within the horizontal boundary of the memory array region; Dielectric filling material is formed inside and outside the recess on the exposed surface of the first preliminary stacked structure; and The portion of the dielectric filling material outside the horizontal and vertical boundaries of the recess is removed to form the dielectric structure.

9. The method of claim 7, further comprising selecting the first insulating structure of the first preliminary stacked structure, the dielectric structure, and the additional first insulating structure of the second preliminary stacked structure to each comprise a dielectric oxide material.

10. The method according to any one of claims 7 to 9, wherein forming the semiconductive post structure comprises: Forming an opening that extends vertically through the dielectric structure and the lower portion of the first preliminary stacked structure; The opening is covered by a plug structure that extends vertically into the opening; A second preliminary stack structure is formed on top of the first preliminary stack structure, the dielectric structure, and the plug structure; Additional openings are formed, extending vertically through the second initial stack structure and the plug structure and reaching the remainder of the opening to form other openings; and The other openings are filled with a semiconductive material.

11. The method according to any one of claims 7 to 9, wherein forming the stepped structure within the portion of the second preliminary stacking structure and the first preliminary stacking structure located within the stepped region comprises: A stadium structure is formed within the second preliminary stacking structure, the stadium structure comprising: The first of the stepped structures having a positive slope; and The second of the stepped structures, which is opposite to the first of the stepped structures and has a negative slope; and An additional stadium structure is formed within the first initial stacked structure, the additional stadium structure comprising: A third party in the stepped structure having a positive slope; and The fourth element in the stepped structure that is opposite to the third element in the stepped structure and has a negative slope.

12. The method of claim 11, wherein forming an additional stadium structure within the first preliminary stacked structure comprises subjecting the second preliminary stacked structure to a cleaving process to vertically extend an opening defined by another stadium structure formed within the second preliminary stacked structure into the first preliminary stacked structure and form the additional stadium structure.

13. The method of claim 7, wherein replacing at least partially the second insulating structure and the additional second insulating structure with a conductive structure comprises replacing at least partially the second insulating structure and the additional second insulating structure with tungsten.

14. A microelectronic device comprising: Microelectronic device structure, including: A stacked structure having layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure comprising: The lower stack includes some of the aforementioned layers; Upper stack, which covers the stack and includes the other layers; and The inter-stack section is located between the lower stack and the upper stack, and the inter-stack section includes: Inter-stacking dielectric structure; and An additional layer is horizontally positioned between the inter-staple dielectric structures, each of the additional layers comprising an additional insulating structure and another insulating structure vertically adjacent to the additional insulating structure; A stepped structure having steps, the steps including the edges of the layers located within the lower and upper stacks of the stacked structure; and A semi-conductive post structure extends vertically through the stacked structure.

15. The microelectronic device of claim 14, wherein the semiconducting post structure is horizontally positioned between the inter-stack dielectric structures.

16. The microelectronic device of claim 15, wherein the semiconducting pillar structure extends vertically through a first set of layers in the upper stack of the stacked structure, an additional layer in the stacked structure in the inter-stack section of the stacked structure, and a second set of layers in the lower stack of the stacked structure.

17. The microelectronic device according to any one of claims 14 to 16, further comprising a filling slit extending vertically through the layers and the inter-stack dielectric structure of the stacked structure, each of the filling slits being filled with at least one dielectric material.

18. The microelectronic device according to any one of claims 14 to 16, wherein the inter-stack dielectric structure, the insulating structure of each layer in the lower stack and the upper stack of the stacked structure, and the additional insulating structure of each additional layer in the inter-stack section of the stacked structure comprise at least one dielectric oxide material.

19. The microelectronic device of claim 18, wherein the other insulating structure of each of the additional layers within the inter-stack section of the stacked structure comprises at least one dielectric nitride material.

20. The microelectronic device according to any one of claims 14 to 16, wherein the stepped structure comprises: A stadium structure, situated within the upper stack of the stacked structure, and comprising: The first step structure with a positive slope; and A second step structure that is a mirror image of the first step structure and has a negative slope; and An additional stadium structure, located within the lower stack of the stacked structure, includes: A third-step structure with a positive slope; and A fourth step structure that is a mirror image of the third step structure and has a negative slope.

21. A method of forming a microelectronic device, comprising: A microelectronic device structure is formed including a first preliminary stacked structure, the first preliminary stacked structure including a vertically alternating sequence of a first insulating structure and a second insulating structure arranged in layers; A dielectric structure is formed that extends vertically into the first preliminary stack structure, the dielectric structures being horizontally spaced apart from each other in a first direction and extending linearly horizontally in a second direction orthogonal to the first direction; A second preliminary stack structure is formed on top of the first preliminary stack structure and the dielectric structure, the second preliminary stack structure comprising a vertically alternating sequence of additional first insulating structures and additional second insulating structures arranged as additional layers; A semiconductive post structure is formed, the semiconductive post structure extending vertically through the portion of the second preliminary stack structure and the first preliminary stack structure that is horizontally positioned between the dielectric structures; A stepped structure is formed within the second preliminary stacking structure and the first preliminary stacking structure, some of the stepped structures having steps including the edges of the layers of the first preliminary stacking structure, and other stepped structures having additional steps including the edges of the additional layers of the second preliminary stacking structure; and The additional second insulating structure of the second preliminary stack structure located outside the vertical boundary of the dielectric structure and the second insulating structure of the first preliminary stack structure are replaced with conductive structures.

22. The method of claim 21, wherein forming the dielectric structure extending vertically into the first preliminary stacked structure comprises: A photoresist structure is formed on the first preliminary stacked structure, the photoresist structure comprising a photoresist material having an opening extending vertically through it; Selectively remove the upper portion of the first preliminary stacked structure that is exposed by the opening in the photoresist material of the photoresist structure and is located within the horizontal boundary of the opening, so as to form a recess within the first preliminary stacked structure; Dielectric filling material is formed inside and outside the recess on the exposed surface of the first preliminary stacked structure; and Remove the portion of the dielectric filling material outside the boundary of the recess to form the dielectric structure.

23. The method of claim 21, further comprising: The first insulating structure of the first preliminary stacked structure, the dielectric structure, and the additional first insulating structure of the second preliminary stacked structure are each selected to include a dielectric oxide material; and The second insulating structure of the first preliminary stacked structure and the additional second insulating structure of the second preliminary stacked structure are selected to each include a dielectric nitride material.

24. The method according to any one of claims 21 to 23, wherein forming the semiconductive post structure comprises: Forming openings that extend vertically through the layers of the first preliminary stacked structure and are horizontally positioned between the dielectric structures; The opening is covered by a plug structure that extends vertically into the opening; A second preliminary stack structure is formed on top of the first preliminary stack structure, the dielectric structure, and the plug structure; Additional openings are formed, extending vertically through the second initial stack structure and the plug structure and reaching the remainder of the opening to form other openings; and The other openings are filled with a semiconductive material.

25. The method according to any one of claims 21 to 23, wherein forming a stepped structure within the second preliminary stacking structure and the first preliminary stacking structure comprises: A first stadium structure is formed within the second preliminary stacked structure, the first stadium structure comprising: The first one in the stepped structure; and The second of the stepped structure that is a mirror image of the first of the stepped structures; and A second stadium structure is formed within the first preliminary stacked structure, the second stadium structure comprising: The third party in the stepped structure; and A fourth element in the stepped structure that is a mirror image of the third element in the stepped structure.

26. The method of claim 25, wherein forming the second stadium structure within the first preliminary stacking structure comprises causing an opening defined by the third stadium structure formed within the second preliminary stacking structure to extend vertically into the first preliminary stacking structure to form the second stadium structure.

27. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device and comprising at least one microelectronic device structure having a memory array region and a step region, the at least one microelectronic device structure comprising: A stacked structure having layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure comprising: A stack, which includes some of the said layers; Additional stacks, which vertically overlay the stacks and include the other layers; and A vertical inter-stack section located between the stacked group and the additional stacked group, the inter-stack section comprising: Dielectric structure, which is horizontally confined within the memory array region; and Some other layers of the layer are located within the vertical boundaries of the dielectric structure and are horizontally confined within the stepped region; A stepped structure, situated within the stepped area and having steps including the edges of the layers within the stacked group and the additional stacked group in the stacked structure; and A semiconducting pillar structure is located within the memory array area and extends vertically through the stacked structure.

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