Shielded connector assembly with temperature and alignment control

Abstract

Various connector side plate designs (e.g., 9a, 9b) and / or high speed connectors (e.g., la) and connector assemblies including temperature and alignment control can be employed. The side plates can be configured to receive and hold portions of more than one wafer so that the tail edges of the terminals of the tail portions of the wafers are aligned in the same geometric plane.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. provisional application US 63 / 010061 filed on April 15, 2020 and U.S. provisional application US 63 / 116648 filed on November 20, 2020, both of which are incorporated herein in their entirety by reference thereto. TECHNICAL FIELD

[0003] The present disclosure relates to the field of connector assemblies, and more particularly to connector assemblies and components thereof suitable for high speed data rate applications, such as at least 100 gigabits per second (Gbps). BACKGROUND

[0004] This section provides background information which can be helpful to better understand the various aspects of the application. As such, the statements of this section are not an admission that any of the information provided herein is prior art or relevant to the patentability of the application, that any of the publications referred to herein are prior art merely because it was published before the filing date of this patent application, or that any such publications are prior art only because of their inclusion in the section.

[0005] Heretofore, it has been challenging for high speed data connector assemblies, among other things, to control temperature, for example, generated by electronic circuitry within plug modules connected to the assemblies, while maintaining conductor alignment within the assemblies and reducing potentially harmful electromagnetic interference (EMI). In particular, it has been challenging to control temperatures reached within receptacle cages of an assembly.

[0006] Accordingly, it is desirable to provide solutions to these challenges. SUMMARY

[0007] The present inventors describe various configurations of exemplary compact high speed multi-layer multi-port connector assemblies and components thereof. The assemblies and components of the present invention are configured, among other things, to control temperature and / or alignment while reducing EMI.

[0008] In one embodiment, a high speed multi-layer multi-port connector assembly of the present invention can include a shield cage and a connector within the cage including a base composed of a plastic and configured to enclose an interior of one or more wafers, a first support side plate on one side of the base and a second support side plate on an opposite side of the base, wherein each side plate is configured to receive and hold a tail portion of each of the one or more wafers such that tail edge of a terminal of each tail portion is aligned in a same geometric plane. In various embodiments, for example, the plastic can include a high temperature liquid crystal polymer (LCP) and the one or more wafers can equal 1 to 8 wafers.

[0009] A number of different internal bases are provided. In one embodiment, an internal base of the present invention surrounds a portion of a top port and a portion of a bottom port, while in another embodiment, an internal base surrounds a portion of a top port but does not surround a bottom port. For example, but when the base does not surround a bottom port, such a base can include more than one notch on both sides that contacts a bottom port to support a top port and base. Alternatively, an alternate base can include a top port support structure that is configured to be fixedly disposed between a top port and a bottom port, wherein the top port support structure can include more than one aperture, each aperture configured to receive a respective top port tab to fixedly position the top port support structure.

[0010] The base can be fixed in a number of different ways. In one embodiment, a base can include more than one base lock that fixes the base to a PCB, wherein the more than one base lock can be constructed of a deformable metal or plastic.

[0011] It should be understood that, for example, one or more of the laminae of the connector assembly of the present invention can include a lamina of a top port lamina assembly, while others of the laminae can include a lamina of a bottom port assembly.

[0012] Each lamina of the connector assembly of the present invention can include more than one lamina tab, wherein the first support side plate and the second support side plate can be configured to receive the more than one lamina tab, and, for example, the two side plates can be constructed of a metal, such as stainless steel, or a plastic, such as LCP. In more detail, for example, the first support side plate and the second support side plate can be constructed with more than one aperture that receives the more than one lamina tab, wherein each lamina tab and aperture can be configured such that each tab is biased structurally toward a corner of a respective aperture to control the tail of each lamina such that the tail of the lamina is in the same geometric plane as a PCB that is also connected to the assembly.

[0013] The connector assembly of the present application can also include a top port tail alignment and support structure (e.g., made of a non-conductive material) that includes one or more protrusions, wherein the first support side plate and the second support side plate can be configured to receive the one or more protrusions of the top port tail alignment and support structure. For example, such a top port tail alignment and support structure of the present application can also include one or more attachment structures for attaching the structure to a printed circuit board (PCB), wherein (i) some of the one or more attachment structures can be comprised of a non-conductive plastic that is covered with a glue, and some of the attachment structures can be comprised of a solderable plated non-conductive plastic or a metal, or (ii) one or more of the attachment structures can be comprised of a non-conductive plastic that is covered with a glue, or (iii) one or more of the attachment structures can be comprised of a solderable plated non-conductive plastic or a metal.

[0014] Further, for example, an assembly of the present application can also include a bottom port wafer assembly that can be configured to be connected to a PCB by surface mount technology, grid array, solder carrier, press fit, or by a fiber optic technology. Also, in various embodiments, an assembly of the present application can additionally include a conductive bottom port tail alignment and support structure that is configured to align tail edges of the tails of one or more terminals of the bottom port wafer of the bottom port assembly, and further, the conductive bottom port tail alignment and support structure can be configured as a ground reference plane structure that surrounds the differential high speed terminals of the bottom port wafer and electrically mirrors a ground plane structure formed on the surface of a PCB to which the connector assembly is mated. It should be understood that such a conductive bottom port tail alignment and support structure need not be connected to a PCB, and for example, can be configured to be spaced apart from the surface of a PCB by a non-limiting distance of 0.25-0.50 millimeters. In an embodiment, for example, the conductive bottom port tail alignment and support structure can include a plated plastic or a stainless steel and can be configured as an integral part of a bottom port wafer assembly.

[0015] In an embodiment, a conductive ground plastic shielding element can be configured to cover the wafer of the bottom port wafer assembly, wherein such a conductive ground plastic shielding element can include a plated plastic, a plated ceramic, or a hybrid laminate with dielectric and conductive elements or another conductive material with a dielectric cladding.

[0016] Also, such a conductive ground plastic shielding element can include multiple separate elements.

[0017] In various embodiments, for example, the connector assembly of the present application can include four small form-factor pluggable input / output (I / O) connectors or a quad-dual density small form-factor pluggable I / O connector.

[0018] For example, the terminals of the connector assembly of the present application can include terminals overmolded with a plastic or plated plastic structure, wherein the terminals include differential high-speed terminals, low-speed terminals, power terminals, and ground terminals, and each differential high-speed signal terminal can be configured with another differential high-speed signal terminal on one side and a ground terminal on the other side.

[0019] In various embodiments, for example, each differential high-speed signal terminal can transmit signals at up to at least 100 gigabits per second (Gbps). Also, the portions of each wafer corresponding to the low-speed terminals and the power terminals can electrically isolate a set of differential high-speed terminals adjacent to the low-speed terminals and the power terminals from another set of adjacent differential high-speed terminals in the same wafer from harmful electrical interference.

[0020] The connector assembly of the present application provided by the present inventor can also include a base including one or more clamps on either side of the base configured to secure or lock the top portions of the wafers in place, wherein each clamp can be constructed as part of the base and operable to flex to secure the one or more wafers.

[0021] In addition to the alignment features described above, the connector assembly of the present application can include one or more conductive ground shields that can be configured to cover the terminals of some or all of the one or more wafers. Thus, in some embodiments, wherein each of the one or more wafers supports one or more differential high-speed terminals, one or more low-speed terminals, one or more power terminals, and one or more ground terminals, a conductive ground shield of the present application can be positioned between some of the one or more wafers.

[0022] For example, the one or more electrically conductive ground shields can include two or more independent shields configured to cover differential high speed transmit terminals with a gap therebetween and two or more independent shields covering high speed receive terminals with a gap therebetween to allow for temperature control (i.e., air passing through the gap and over the uncovered low speed terminals and power terminals). In another embodiment, a first of the one or more electrically conductive ground shields can be configured to cover one or more differential high speed terminals of one of the one or more wafers, and a second of the one or more electrically conductive ground shields can be configured to cover another differential high speed terminal of the same wafer. Still further, the first and second electrically conductive ground shields can be constructed with a gap therebetween, the gap sized to correspond to the total number of low speed terminals and power terminals plus one terminal times an area of the terminals times a desired spacing of the terminals. In one embodiment, for example, the gap can include 4.0 millimeters.

[0023] In one embodiment, the one or more electrically conductive ground shields can be configured along a vertical axis (with or without a gap therebetween), or can be configured along an axis other than a vertical axis (with or without a gap therebetween). Regardless of the orientation of the one or more shields, in various embodiments, for example, a ground shield can be configured to cover one or more differential high speed terminals, one or more low speed terminals, one or more power terminals, and one or more ground terminals of a respective wafer.

[0024] As described above and elsewhere herein, one or more differential high speed terminals can be covered by an electrically conductive ground shield. For example, when one set of differential high speed terminals are transmit elements and another set are receive elements, one electrically conductive ground shield (a "first") can cover the transmit terminals and another electrically conductive ground shield (a "second") can cover the receive terminals.

[0025] Still further, wherein each of the one or more wafers supports one or more differential high speed terminals, and the assembly can be further configured to position an electrically conductive ground shield at a first distance proximate one or more of the respective differential high speed terminals of the one or more wafers to create a field affinity between the respective ground shield and the respective differential high speed terminals.

[0026] In addition to the aforementioned gap in a shield, the connector assembly of the present invention provided by the inventor can include additional temperature control. For example, low speed terminals and power terminals in the same row of a wafer can be configured to be offset from low speed terminals and power terminals in another row of another wafer.

[0027] For example, the base described above and elsewhere herein can include one or more gaps to allow air flow through and remove heat generated by at least the low speed terminals and power terminals in the one or more wafer bodies.

[0028] The inventors also provide a connector assembly that includes a combination of the ground conductors and the plastic ground shields of the present invention. For example, in one embodiment, one or more insert molded metal ground conductors (e.g., composed of copper, copper alloy, gold, or platinum) can each be able to be insertably mated to a ground conductive portion, e.g., that is part of a plastic ground shield element, where, for example, the one or more ground conductive portions can include a conductive plastic, a conductive metal, a conductive or plated plastic, or a hybrid laminate having dielectric and conductive elements.

[0029] For example, each of the one or more insert molded metal ground conductors that are mated can include a continuous conductive structure.

[0030] To reduce unwanted voltage gradients in the connector assembly, the inventors provide one or more wafer bodies (of a top and / or bottom wafer assembly) that each can include dual ground paths, where a first path can be formed by a plurality of independent ground conductors and a second ground path can be formed by a plurality of conductive fingers and a conductively plated plastic shield. The inventors believe that the dual ground paths of the present invention significantly reduce a common complex impedance along the length of each path, where the common complex impedance can be less than either impedance of an independent path.

[0031] With respect to the fingers of the present invention just described, for example, each of the plurality of conductive fingers can be electrically and galvanically connected to a contact of one of the plurality of independent ground conductors and can include a conductive ground plate finger. Alternatively, each of the plurality of conductive fingers can include an insert molded finger of a plastic ground shield structure.

[0032] In addition to the connector assemblies of the present invention, the inventors also provide methods of the present invention that are related to the connector assemblies of the present invention.

[0033] In one embodiment, a connector assembly of the present invention can include an inner base having a first side and a second side opposite the first side, and first and second support side plates connected to the first and second sides of the inner base, respectively, each side plate configured to secure the positions of tail portions of a plurality of wafer bodies relative to each other within the inner base and to align tail edges of terminals of each tail portion in a common geometric plane.

[0034] In one embodiment, the side plates can comprise metal side plates and the interior base can comprise a plastic such as a liquid crystal polymer (LCP). Also, for example, each side plate can be configured to receive a tab of a wafer in one or more apertures of each side plate to retain a tail of a terminal and to align tail edges of each tail in a same geometric plane.

[0035] It should be appreciated that the connector assembly of the present invention can also include a plurality of wafers (top port wafers and bottom port wafers) within the interior base, wherein each of the plurality of wafers can include a terminal overmolded with a plastic or a plated plastic.

[0036] The exemplary connector assembly of the present invention can also include a top port tail alignment and support structure comprising one or more tail alignment and support structure tabs and a bottom port tail alignment and support structure comprising one or more bottom port tail alignment and support structure tabs.

[0037] In one embodiment, for example, the top port tail alignment and support structure can be comprised of a non-conductive material and the bottom port tail alignment and support structure can be comprised of a conductive material.

[0038] Further, the exemplary top port tail alignment and support structure can include one or more attachment structures to attach the top port tail alignment and support structure to a printed circuit board (PCB), wherein the one or more attachment structures can comprise (i) a non-conductive plastic covered with a glue, or (ii) a solderable plated non-conductive plastic or a metal solderable to the PCB or (iii) a combination of the non-conductive plastic covered with the glue, the solderable plated non-conductive plastic or a metal solderable to the PCB.

[0039] In an alternative embodiment, for example, each side plate can include one or more inwardly or outwardly curved or configured hook-like tabs to attach to a PCB and can also include one or more integral solder feet to secure each side plate to a PCB.

[0040] Another embodiment of the present invention is directed to a member of a connector assembly, particularly a side plate. In one embodiment, among other things, a side plate of the present invention can connect a side of an interior base, wherein the side plate can be configured to receive a plurality of tabs of a tail alignment and support structure and a plurality of wafer tabs to retain a tail of each of a plurality of wafers and to align tail edges of each tail in a same geometric plane. Such a side plate can also include one or more inwardly or outwardly curved or configured hook-like tabs to attach to a PCB or one or more integral solder feet to secure each side plate to the PCB.

[0041] In addition to the connector assemblies and components of the present application, the present inventors also provide related methods of the present application that are collateral to the connector assemblies and components of the present application. For example, a method for securing the position of a plurality of wafers within a connector assembly can include: securing the position of the plurality of wafers relative to one another within an interior base of the connector assembly using first and second support side panels coupled to first and second sides of the interior base; and aligning and supporting a non-conductive top port tail portion, a conductive bottom port tail portion, and a wafer tail portion within apertures of the first and second side panels to retain the tail of each of the plurality of wafers and align the tail edge of the tail of each of the plurality of wafers within a common geometric plane. BRIEF DESCRIPTION OF DRAWINGS

[0042] The present application is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar parts, and in which:

[0043] FIG. 1A and FIG. 1B shows a view of an exemplary connector assembly of the present application according to an embodiment of the present application.

[0044] FIG. 2 shows an exploded view of an exemplary connector assembly of the present application according to an embodiment of the present application.

[0045] FIG. 3A , FIG. 3B and FIG. 3U shows different views of an exemplary connector of the present application according to embodiments of the present application.

[0046] FIG. 3C and FIG. 3H shows an exemplary wafer of the present application according to embodiments of the present application.

[0047] FIG. 3D , FIG. 3E , FIG. 3V , FIG. 3W and FIG. 3X shows an exemplary alignment control feature of the present application according to embodiments of the present application.

[0048] FIG. 3F , FIG. 3J and FIG. 3K shows an exemplary conductive ground shield of the present application according to embodiments of the present application.

[0049] FIG. 3G shows an enlarged view of an exemplary temperature control feature of the present application according to an embodiment of the present application.

[0050] FIG. 3I Further exemplary temperature control features of the present invention according to embodiments thereof are shown.

[0051] FIG. 3L to FIG. 3N An exemplary grounding terminal stitching of the present invention, according to an embodiment of the present invention, is shown in connection with a conductive grounding shield.

[0052] FIG. 3P to FIG. 3R An exemplary grounding path configuration according to an embodiment of the present invention is shown.

[0053] FIG. 3S Figure 3T and FIG. 3X An exemplary tail alignment and support structure according to an embodiment of the present invention is shown.

[0054] FIG. 4A to FIG. 4H An exemplary feature of the invention is shown in an embodiment of the bottom port sheet body assembly according to the invention.

[0055] FIG. 4I An exemplary tail alignment and support structure for at least one bottom port sheet body assembly is shown according to an embodiment of the present invention.

[0056] FIG. 5A to FIG. 5J A view illustrating exemplary features of an alternative exemplary connector according to an embodiment of the present invention.

[0057] FIG. 6A and FIG. 6B An alternative top port sheet assembly configuration is shown according to an embodiment of the present invention.

[0058] Specific embodiments of the invention are disclosed below with reference to various accompanying drawings and sketches. The specification and illustrations have been prepared to enhance understanding. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements, and well-known elements that are advantageous or even necessary for commercially successful implementation may not be shown, thereby enabling a clearer and less obstructive presentation of the embodiments.

[0059] The brevity and clarity in the illustrations and descriptions are intended to enable those skilled in the art to effectively make, use, and best practice the invention based on what is known in the art. Those skilled in the art will recognize that various modifications and variations can be made to the specific embodiments described herein without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative and exemplary, not restrictive or all-encompassing, and all such modifications to the specific embodiments described herein are intended to be included within the scope of the invention. Detailed Implementation

[0060] The following detailed description describes exemplary embodiments and is not intended to limit the combinations explicitly disclosed. Thus, features disclosed herein can be combined with one another to form additional combinations not otherwise expressly disclosed or suggested, for the sake of brevity.

[0061] The disclosure provided herein illustrates features by way of preferred and exemplary embodiments. Numerous other embodiments, modifications, and substitutions are contemplated by those of ordinary skill in the art having the benefit of this disclosure, within the scope and spirit of the claims appended hereto.

[0062] As used herein and in the appended claims, the terms "comprises," "comprising," or "comprised of" or any other variation thereof, "includes," "including," or "including of" or any other variation thereof, are intended to cover a process, method, article, or apparatus that includes a stated element, but not excluding additional elements. Thus, these terms are not intended to exclude the presence of additional elements.

[0063] As used herein, the term "a" or "an" refers to one or more than one, not to one. As used herein, the term "plurality" refers to two or more. As used herein, the term "another" refers to at least a second.

[0064] Unless otherwise stated herein, the use of relational terms, if any, such as "first" and "second," "top" and "bottom," "left" or "right," and the like are used solely to distinguish one element, component, entity or act from another, without necessarily requiring or implying any actual such relationship, priority, importance or order between such elements, components, entities or acts.

[0065] As used herein, the terms "including," "includes" and / or "include" are defined as including, that is, open language that does not exclude anything, unless specifically indicated otherwise. As used herein, the term "coupled" is defined as connected, although not necessarily directly, and not necessarily mechanically. The use of "or" or "and / or" herein is defined as inclusive, that is, A, B, or C means any one of A, B, or C, or any two or all three of A, B, or C, and not exclusive, unless expressly indicated otherwise. Thus, use of "and / or" in some instances does not imply that "or" in other instances is exclusive. The terms derived from the word "indicating" (e.g., "indicates" and "indication") are intended to encompass all various techniques that can be used to convey or reference the indicated object / information. Some, but not all, examples of techniques that can be used to convey or reference the indicated object / information include conveyance of the indicated object / information, conveyance of an identifier of the indicated object / information, conveyance of information used to generate the indicated object / information, conveyance of some portion or portions of the indicated object / information, conveyance of some derivation of the indicated object / information, and conveyance of some symbol representative of the indicated object / information.

[0066] As used herein, the phrases "high speed," "high speed signal," "high speed data," "high speed data signal," and the like mean synonymous, unless the context or knowledge of one of ordinary skill in the art indicates otherwise. One example of a high speed data signal can be a signal of at least 100 Gbps.

[0067] Similarly, the phrases "low speed," "low speed signal," "low speed data," "low speed data signal," and the like mean synonymous, unless the context or knowledge of one of ordinary skill in the art indicates otherwise. In general, a low speed signal can be considered to be a signal related to control and system maintenance, rather than information transfer. Further, a non-limiting low speed signal can be associated with a data transfer rate of less than 1 Gbps and typically does not require a specialized signal transmission structure, such as a ground supported waveguide. For brevity, a reference to "low speed terminals" can sometimes include power terminals, depending on the context.

[0068] As used herein, the phrases "configured to," "operable to" mean "function to," unless the context or knowledge of one of ordinary skill in the art indicates otherwise.

[0069] As used herein, the phrase "a-n" means the first element "a" and the last element "n". For example, one or more apertures, where "a" is the first aperture and "n" is the last aperture. Further, the letter "n" or "nn" means an exemplary one of a number of similar elements, such as aperture 11n.

[0070] As used herein, the term "exemplary" or "embodiment" means one or more non-limiting examples of the inventive connector assembly, inventive component or element, inventive method, or a portion of the inventive method.

[0071] As used herein, the words "terminal" and "conductor" can be used synonymously, unless the context or knowledge of one of ordinary skill in the art dictates otherwise.

[0072] As used herein, the words "retain" and "secure" can be used synonymously, unless the context or knowledge of one of ordinary skill in the art dictates otherwise.

[0073] Referring now to the drawings FIG. 1A , an exemplary shielded high speed multi-layer multi-port connector assembly of the present invention is shown in a view. As shown, the assembly 1 can include an electromagnetic shield 2 that can be configured to protect a number of different connectors, each of which can have a top port and a bottom port (both hidden in the view) and can be connected to a host electronic printed circuit board 3 (PCB) according to one embodiment of the present invention. Also shown are pluggable module assemblies 4a, 4b that can include PCB subassemblies, one of which 4a can be connected to a top port via a card slot (not shown) in the top port and the other assembly 4b can be connected to a bottom port via a card slot in the bottom port. FIG. 1B The two assemblies 4a, 4b are shown before connection to the top and bottom ports 8a, 8b.

[0074] In more detail, the shield 2 can be positioned over portions of the top and bottom ports 8a, 8b of a connector to provide shielding for at least the connector and other components within the shield 2 from a range of electromagnetic interference (EMI).

[0075] Referring now to the drawings FIG. 2, showing an "exploded" view of exemplary components that can be used to construct an exemplary connector assembly 1. As shown, the cage 2 can include a three-sided (e.g., a top and two sides) conductive cover 2a along with a cage base 2b, a shield backplane 2c, and a front end shield 2d. Each of these components 2a, 2b, 2c, 2d can operate to shield EMI from the components (such as the connector 1a) that they each cover. So positioned, the cage 2 can operate to shield the connector 1a from a range of EMI (e.g., nominally covering 10 MHz to 50 GHz).

[0076] In an embodiment, for example, the components 2a, 2b, 2c, 2d can be constructed of a sufficiently conductive metal or conductively plated plastic, although these are merely two of the conductive materials that can be employed. Also, the construction of these shielded components can include one or more differently configured perforated and / or non-perforated apertures to allow air flow and contribute to controlling the temperature of the components that make up the assembly 1. Such apertures can also be configured to reduce the effects of EMI.

[0077] In more detail, the front end shield 2d can include one or more associated openings, apertures, or vents 5a (collectively "apertures") that operate to allow air to flow into and / or out of the interior of the cage 2 to reduce the temperature of the components (such as the connector 1a) that the cage 2 encloses. Also, the front end shield 2d can further include a plurality of conductive deformable structures or elements 6 that can be formed around a portion or substantially the entire perimeter of the shield 2d. In an embodiment, another device (e.g., a paddle card, see component 7b) having corresponding opposing deformable structures or elements (not shown) can be pushed against and positioned on the elements 6, such that the other device can be said to be "inserted" into the port 8b of the connector 1a via a card slot of the port 8b. The opposing force of the two opposing sets of deformable elements along with one or more retaining members (e.g., as described elsewhere herein, one retaining member is typically located on each side near the front of the cage 2) secure the other device to the port 8b of the connector 1a. Further, in an embodiment, such an "inserted" configuration forms a continuous EMI shielded seal. Also, because the elements 6 are conductive, an electrical ground path can be established.

[0078] Continuing, the assembly 1 can further include a top heat sink 2g and a second fastening retainer 2h and an integral (e.g., one-piece) central base 2j that surrounds the interior of the bottom, top ports 8a, 8b, with a paddle card 7b shown as being inserted into the bottom port 8b.

[0079] Optionally, the assembly 1 can also include a shroud middle portion including an internal heat sink 2e and a fastening clip 2f.

[0080] In an embodiment, a top heat sink 2g can extend substantially the entire length of the shroud 2 while the internal central pedestal 2j is within the shroud 2.

[0081] Although FIG. 2 The assembly 1 is shown including all of the components just described, but it should be understood that other connector assembly embodiments can contemplate including only a subset of these components. Further, for example, additional embodiments can include: (i) FIG. 2 additional components; (2) fewer components (i.e. FIG. 2 a subset of the components shown); and / or (iii) FIG. 2 a subset of the components shown and FIG. 2 additional components not shown.

[0082] Continuing, the first fastening clip 2f can include one or more deformable elements 2ff operable to apply a spring-like force on the internal heat sink 2e within the three sides of the shroud 2. As a result of such force, the heat sink 2e can contact components within the shroud 2, such as a top port. Turning to the second fastening clip 2h, for example, in an embodiment, the clip 2h is operable to apply a force to the top heat sink 2g such that the heat sink 2g contacts components enclosed by the shroud 2 and within the shroud 2, such as opto-electronic (O / E) and / or electro-optic (E / O) conversion circuitry, active devices, and / or re-timing circuitry (not shown).

[0083] In various embodiments of the present invention, the assembly 1 of the present invention can include additional components operable to reduce the temperature of components of the assembly 1 in addition to the front end shield 2d. For example, the shroud 2 and the shield back plate 2c can also each include one or more corresponding associated apertures 5b, 5c, respectively, configured to allow air to flow through the internal shroud 2 to reduce the temperature of components enclosed by the shroud 2 (see FIG. 1A and FIG. 2 ). In an embodiment, for example, when connected, the assembly 1a, the inserted board-type card 7b, and the PCB 3 form a complete functional connection allowing transmission of up to at least 100 Gbps.

[0084] Depending on the embodiment, one or more of each of the above-described apertures can be shaped as a hexagon, alternatively, one or more of each of the above-described apertures can be shaped as a circle, to give only two of the many types of aperture shapes that can be employed, and still allow the apertures to function to reduce the temperature of a component of an inventive assembly. Also, for example, a given set of associated apertures can include a subset of hexagonally shaped apertures and a subset of circularly shaped apertures. In various embodiments, the surface area and / or structure of a component (e.g., component 2a, 2c, 2d) of an inventive assembly can be allowed to include more hexagonally shaped apertures than circularly shaped apertures (i.e., more hexagonally shaped apertures than circularly shaped apertures can be formed in a component) due to the size of the component and the apertures.

[0085] Also, each aperture can be configured to have a width that reduces the effect of EMI on components within the interior of an assembly 1 depending on the frequency or frequencies sought to be attenuated, and each aperture can be configured to have an extruded depth that reduces the effect of EMI on components of the interior depending on the amount of attenuation (e.g., in dB) desired. For example, the smaller the width of an aperture, the higher the upper cutoff frequency that can be attenuated, and the deeper the extruded depth, the more a given signal can be attenuated (i.e., the decibel level of a signal can be reduced) at a given frequency by an aperture. In an embodiment, an aperture used as part of an inventive assembly can have (i.e., the dimensions can be set to) a width and extruded depth that correspond to the amount of attenuation desired.

[0086] Also, in various embodiments, a given size of aperture in a set of apertures can not be repeated periodically to avoid aperture-to-aperture enhancement or "gain" at a given frequency or band of frequencies. Also, exemplary apertures can each have the same width, and thus, can attenuate signals at substantially the same frequency range. However, by varying the extruded depth of a given aperture, such an aperture can attenuate a given signal at a given frequency more than a aperture having a smaller (shallower) extruded depth (i.e., a aperture having a greater extruded depth can reduce the decibel level of a signal more than a aperture having a shallow extruded depth).

[0087] In an embodiment, the thickness and composition of the cover 2a of the enclosure 2 can be set to achieve a desired level of EMI attenuation. For example, a given material that is thinner in thickness can attenuate unwanted frequencies less than the same given material that is thicker in thickness. Also, the cover 2a of the enclosure 2 can be constructed of multiple layers of the same or different attenuating materials (e.g., multiple layers can be constructed of a metallic material and other layers can be constructed of other conductive materials such as plated plastic).

[0088] Referring now to FIG. 3A and FIG. 3U, a view of the connector 1a is shown. In an embodiment, the connector includes a central, inner base 2j that is substantially within the shielded housing 2 and can be constructed of a plastic such as a high temperature liquid crystal polymer (LCP), the base 2j can be configured to surround a portion of the top and bottom ports 8a, 8b and respective one or more wafers (not shown) that are within the connector 1a.

[0089] Also shown in FIG. 3A and FIG. 3U is a first support side plate 9a on a side of the inner base 2j, the first support side plate 9a can be constructed with features that connect to and fix the position of the plurality of wafers within the inner base 2j relative to each other. For example, the side plate 9a (and a second side plate 9b on a second, opposite side of the base 2j that is hidden in the view of FIG. 3A ) can be configured to receive and hold the“tails” of the terminals of each wafer by, for example, receiving one or more posts or tabs 14a-14n (collectively“tabs”) of a top port tail alignment and support structure 14 and wafer tabs or posts 10a-10n (collectively“tabs”) that hold the tails of each wafer such that the tail edges of each tail (see description for FIG. 3C ) are aligned in the same geometric plane (i.e., the geometric plane in which the tail edges terminate in the same plane as the PCB 3). In embodiments, the side plates 9a, 9b can be constructed of a metal such as stainless steel. Because the side plates 9a, 9b are connected to the base 2j, the base 2j can be said to be configured to control the center-to-center positioning between each wafer.

[0090] As shown, in an embodiment, the connector 1a can be constructed as a shielded high-speed multi-level multi-port connector with temperature and alignment control features. In an embodiment, the connector 1a can include an input / output (I / O) connector such as can be used in small form-factor pluggable applications or dual-density small form-factor pluggable applications (e.g., QSFP, SFP, QSFP-DD, SFP-DD, OSFP, CDFP applications). As configured, the assembly 1 including the connector 1a can be referred to as a shielded high-speed multi-port multi-level connector assembly 1 with temperature and alignment control.

[0091] In more detail, referring now to FIG. 3CIn one embodiment, the connector 1a can include a plurality of tabs 15a-15n (e.g., 4 to 8 tabs, although only 4 are shown) within the base 2j on their distal or top ends aligned with a card slot of a port (such as ports 8a, 8b). In one embodiment, each tab 15a-15n can support a set of terminals, where such terminals include terminals overmolded with a plastic or plated plastic structure (e.g., such as differential high speed terminals, low speed terminals, power terminals, and ground terminals, although not shown for clarity) as described in greater detail elsewhere herein. More particularly, unless otherwise noted, the terminals of each tab can include a high speed portion, where the high speed portion includes differential high speed signal terminals and ground terminals extending side-by-side through the tab, with each respective differential high speed signal terminal configured to have another differential high speed signal terminal on one side and a ground terminal on the other side of the respective differential high speed signal terminal (e.g., see FIG. 3K ).

[0092] Also, each terminal can have three portions: a distal, top, or contact portion (collectively "contact portion") that contacts an end of a pluggable card (such as cards 7a, 7b), an opposite tail portion, and a central body portion between the contact portion and the tail portion. As shown in FIG. 3C , the respective tail portions of the terminals of a tab 15a-15n can include a number of tail edges 30a'-30n' (tail edges of ground conductors), 31a'-31n' (tail edges of low speed terminals or power terminals), 32a'-32n' (high speed tail edges) aligned in the same geometric plane.

[0093] As will be seen by the drawings herein, the terminals of each tab can be arranged in more than one row to contact a pluggable card (e.g., see FIG. 3Q and FIG. 3R ).

[0094] In various embodiments, for example, the contact portions of more than one terminal of a tab can be arranged to form a top row of terminals that contact a card slot or a bottom row of terminals that contact a card slot (e.g., see FIG. 3Q and FIG. 3R ).

[0095] The conductive terminals that are part of the tabs 15a-15n can be configured to carry electrical signals. In addition, in an alternative embodiment, the terminals can also be configured to feed electrical signals to or receive electrical signals from an E / O conversion circuit or an O / E conversion circuit, for example. In the latter case, such O / E or E / O conversion circuit can be included in a mating module or card (e.g., member 7b) that is mated to the connector 1a and then connected to the respective conductive tabs of the connector 1a.

[0096] In many cases, the signals passing through the terminals of a wafer or through additional O / E and E / O conversion circuitry can generate a significant amount of heat during operation. As such, as explained herein, the inventors provide solutions of the present invention that control such temperatures.

[0097] Referring to FIG. 3B , an illustrative view of the connector la and its separate components is shown, which can include the base 2j removed from the connector la for ease of explanation, it should be understood that, FIG. 3B the components shown are typically connected to or within the base 2j. Such components include a first support side plate 9a, a second support side plate 9b, a tail alignment and support structure 14, and a top port wafer assembly 10 (a bottom port wafer assembly is not shown, but is indeed within the connector la). In an embodiment, the internal components of the base 2j, the top side plates 9a, 9b, and the alignment and support structure 14 can be constructed of a plastic material, such as a LCP material. In embodiments, the structure 14 can be a non-conductive material that can be fully or partially plated.

[0098] In embodiments of the present invention, the side plates 9a, 9b can be constructed with one or more apertures 11a-11n, where one or more of the one or more apertures can be configured to receive the aforementioned one or more wafer tabs (see FIG. 3C elements 10a-10n) of the respective wafer 15a-15n tabs of the top port wafer assembly 10 at the tail of the terminals of the wafer 15a-15n. As configured, the tabs help control the alignment and positioning of the respective wafer 15a-15n to ensure that the tails of the terminals of the respective wafer 15a-15n are held and the corresponding tail edges are aligned in the same plane (i.e., the tail edges of the respective terminals are coplanar with the plane of the PCB 3). Although FIG. 3B and FIG. 3C only the tabs (e.g., 10a-10n) on one side (i.e., the ingress side plate 9a) of the respective wafer 15a-15n are shown, it should be understood that both sides of the respective wafer can be constructed with tabs that extend into (are received by) the apertures 11a-11n of the respective side plates 9a, 9b. In an embodiment, the tabs can be insert molded tabs.

[0099] Further, the base 2j can include one or more catches 12a-12n on either side of the base 2j (see FIG. 3A and FIG. 3B). In one embodiment, each set of retainers 12a-12n (e.g., at least one on each side) can be configured to substantially fix or lock the top of each wafer 15a-15n in position to prevent the top port wafer assembly 10 from exiting the base 2j (i.e., moving away from the front of the port 8a). While only one retainer is shown on one side of the base 2j, it should be understood that both sides of the base 2j can include such retainers. In one embodiment, each retainer 12a-12n can be configured as an integral part of the base 2j or as a separately attached part that is operable to flex outwardly (e.g.) when the top port wafer assembly 10 including more than one wafer is inserted into the base 2j. As the wafer assembly 10 contacts the retainers 12a-12n, the wafers 15a-15n pass over the retainers 12a-12n and into a certain position within the base 2j that fixes the more than one wafer 15a-15n, the retainers 12a-12n can flex inwardly (e.g.). Alternatively, base posts that fit into additional apertures of the base 2j can replace the retainers 12a-12n.

[0100] For example, FIG. 3D A close-up view of the wafer tab 10n inserted within the aperture 1 In of the side plate 9a (the same would be true for the side plate 9b) is shown. Also shown are the trailing edges 30a'-30n' (of the ground conductors), 31a'-31n' (of the low speed terminals or power terminals), 32a'-32n' (of the high speed terminals) aligned in the same geometric plane.

[0101] FIG. 3E A close-up view of a single exemplary tab 10n is shown, having side surfaces S A -S D The tab 10n is inserted into the aperture 1 In of the side plate 9a having side surfaces S1-S4. In one embodiment, each tab 10a-10n and aperture 1 la-1 In can be configured (i.e., in this case, shaped) such that the distance between side surface S A and side surface S2 is less than the distance between side surface S B and side surface S3 at the lower right corner C2, and the distance between side surface S C and side surface S4. D

[0102] In more detail, side surface S2 is straight to straight (i.e., not overlapping) with side surface S B and side surface S1 is straight to straight (i.e., not overlapping) with side surface S A On the other hand, side surface S3 overlaps side surface S C and side surface S4 overlaps side surface S​D The same is true. In one embodiment, the overlapping side surfaces create an interference / compression fit force that is exerted on the tab 10n and directed toward the upper left corner C1. Thus, the surfaces (e.g., S2 and S B , and S1 and S A ) near C1 will be forced closer to the corner C1, while the surfaces (e.g., S3 and S C , and S4 and dS D ) will be forced away from the corner C2. In an exemplary embodiment, for example, the surface S3 and the surface S C , and the surface S4 and the surface S D may be 0.03 mm further from the corner C2 than the surface S2 and the surface S B , and the surface S1 and the surface S A from the corner C1.

[0103] Thus, for example, it can be said that the tabs 10a-10n are "biased" toward the upper left corner C1. However, it should be understood that the bias toward the upper left corner is exemplary only. In alternative embodiments, the tabs 10n can be biased toward any of the four corners, so long as the overlapping side surfaces are properly configured and achieve the same or similar distance differentials.

[0104] Such exemplary biased tabs, for example, are one of the alignment control features of the present invention discovered by the inventors, as such biased tabs control the planarity and position of the tails of the dies 15a-15n when the dies are connected to the host PCB 3 using surface mount technology (SMT). More particularly, such biased tabs help control the tails of the terminals of the dies 15a-15n to allow the tail edges of the tails of the terminals of one to be aligned in the same plane (i.e., in the same geometric plane as the PCB 3). Without such biasing, the tail height of more than one of the terminals of the dies 15a-15n can vary, and thus, the tail edges can not be coplanar (i.e., can be misaligned).

[0105] Further, FIG. 3B and FIG. 3D additional alignment control features are shown. In FIG. 3B , the non-conductive tail alignment and support structure 14 of the present invention can include one or more tail alignment tabs 14a-14n as shown. In FIG. 3D , in one embodiment, one or more apertures 11a-11n on each of the side plates 9a, 9b can be configured to receive one or more tabs 14a-14n to further secure the tails of the dies 15a-15n to a common datum (i.e., a fixed reference structure) and allow the side plates 9a, 9b to be connected. Although in the exemplary embodiment shown in FIG. 6, the tail alignment tabs 14a-14n are shown as being separate from the side plates 9a, 9b, in alternative embodiments, the tail alignment tabs 14a-14n can be integral with the side plates 9a, 9b.FIG. 3D Only four tabs are shown attached to side panels 9a, 9b, but it should be understood that more than four tabs can be attached to a side panel. For example, eight tabs can be attached to a side panel (see FIG. 3X ).

[0106] In summary, each exemplary side panel 9a, 9b can be configured to receive a tab 14a-14n of tail alignment and support structure 14 and a tab 10a-10n of tabbed structure 10 to hold each of a plurality of tabs 15a-15n such that the tail edge 30a'-30n', 31a'-31n', and / or 32a'-32n' of each tail is aligned in the same geometric plane as a PCB, such as PCB 3.

[0107] FIG. 3V 、 FIG. 3W and FIG. 3X show alternative side panels 9aa, 9ab, 9ac, respectively. While only one side and side panel can be shown, it should be understood that each side of a base can include a similar side panel 9aa, 9ab, 9ac.

[0108] As shown in FIG. 3V and FIG. 3W , side panels 9aa, 9ab can include one or more inwardly or outwardly curved or configured hook-like tabs 19a-19n. In an embodiment, tabs 19a-19n can be attached to a PCB, such as PCB 3, by soldering. In these embodiments, FIG. 3W side panel 9ab of FIG. 3V is shown attached to base 2j, while FIG. 5A to FIG. 5E side panel 9aa of is shown attached to a bottom port 88b (see

[0109] for a bottom port 88b), but these are merely exemplary configurations. FIG. 3X In the series of drawings constituting side panel 9ac is shown attached to base 2j with tabs and apertures as described elsewhere herein. In this embodiment, side panel 9ac can be configured with one or more solder feet 29a-29n integral therewith. As shown, for example, each solder foot 29a-29n can be received in an opening in a PCB 3 to secure side panel 9ac and base 2j to PCB 3. Further, for example, solder feet 29a-29n can be configured to frictionally contact tail alignment and support structure 14, 46 at location 3a to further hold structure 14, 46 in a fixed position.

[0110] Similar to the foregoing, each side plate 9aa, 9ab, 9ac can be configured to receive a tab of a tail alignment and support structure and a tab of a wafer tab to hold or secure each of the plurality of wafer tabs and to align the tail edges of the terminals of each wafer tab in the same geometric plane as the PCB 3.

[0111] For ease of understanding, the present disclosure will now give a discussion of the features of the present disclosure that can be incorporated into a top port wafer assembly (e.g., assembly 10) of an inventive connector assembly (such as assembly 1). Also herein, the present inventor will give a discussion of a bottom port wafer assembly. Even so, it should be understood that more than one feature of a top port wafer assembly of an inventive assembly can be used in a bottom port wafer assembly of an inventive assembly and vice versa.

[0112] In an embodiment, the top port wafer assembly 10 can include one or more independent power conductors, high speed communication signal conductors, and low speed communication signal conductors, as well as ground conductors (sometimes referred to as "terminals") that form part of independent ground paths, power paths, and communication signal paths. In embodiments, each high speed conductor / terminal can be configured to transmit signals of up to at least 100 gigabits per second (Gbps), while in alternative embodiments, more than 100 Gbps can be transmitted by the high speed signal terminals of assembly 10 (as well as the bottom port assembly). In alternative embodiments, up to 160 Gbps of communication signals can be transmitted by the high speed terminals of an assembly.

[0113] In an embodiment, the top port wafer assembly 10 can include respective differential high speed terminals, centrally located low speed / power terminals, and ground terminals. In other words, the differential high speed terminals can be located on the left and right sides of each wafer of the top port connector assembly 10, while the low speed terminals or power terminals can be centrally (i.e., "in the center of") located between the high speed terminals. In an embodiment, this "in the center" portion of the positioning of the corresponding low speed terminals and power terminals of each wafer in assembly 10 can electrically isolate the differential high speed terminals on opposite sides of the low speed terminals and power terminals from harmful electrical interference. In more detail, this portion can act to isolate or "block" a set of high speed terminals configured to transmit communication (data) signals on one side of a low speed terminal and a power terminal from harmful electrical interference caused by communication (data) signals transmitted by a second set of high speed terminals on the opposite side of the same low speed terminal and power terminal. This "blocking" or isolation portion can reduce harmful electrical crosstalk between the differential high speed terminals on opposite sides as well as improve signal to noise performance for the respective high speed data signals transmitted by the high speed terminals.

[0114] Reference will now be made to FIG. 3Fmore than one independent electrically conductive ground shielding element 16a-16n. In one embodiment, with more than one element, one element 16a (a "first element") can be configured to cover more than one differential high speed terminal (covered terminals not shown) of a wafer of a top port wafer assembly 10, while another element 16n (a "second element") can be configured to cover different differential high speed terminals of the same wafer. In one embodiment, elements 16a-16n together can comprise a multi-piece electrically conductive ground shield. It should be understood that each wafer of wafer assembly 10 can have its own electrically conductive ground shielding element (see, e.g., elements 16aa-16an of FIG. 16). FIG. 3H

[0115] Also, as shown, there is no electrically conductive ground shield covering the low speed and power terminals 31a-31n in gap "gl". In other words, in one embodiment, the first and second electrically conductive ground shields 16a, 16n can be configured with a gap gl therebetween, the size of gap gl corresponding to the total number of low speed and power terminals 31a-31n plus one terminal area times a desired spacing of the terminals (length times width) (e.g., if the area of 4 terminals is "X", then the size of gap gl would equal (the area of X plus the area of 1 / 4X) times the terminal spacing). For the benefit of the reader, for example, if an exemplary terminal spacing is 0.8 mm and there are five exemplary low speed and power terminals, then gap gl can be 4.0 mm.

[0116] For example, because the exemplary electrically conductive multi-piece ground shield does not cover all of the terminals of the wafer, heat generated and dissipated by at least the uncovered low speed and power terminals 31a-31n during operation of at least the low speed and power terminals 31a-31n can be cooled by air flowing over the terminals. In other words, for example, air flowing over the terminals can remove heat generated by such terminals. Moreover, for example, in embodiments in which one electrically conductive ground shield 16a is configured to cover high speed transmit / emission terminals and another electrically conductive ground shield 16n is configured to cover high speed receive / accept terminals, the separation of the ground shields can serve to electrically isolate the transmit terminals from the receive terminals to reduce the effects of unwanted electrical interference and / or noise. The separated electrically conductive ground shields 16a-16n are just one of the temperature and electrical control aspects of the present invention discovered by the present inventor. The use of more than one (e.g., two) separated elements 16a, 16n can be referred to herein as a "split electrically conductive ground shield" or simply a "split shield".

[0117] Although FIG. 3F ​The shielding members 16a, 16n are separated into two members 16a, 16n by a gap g1 therebetween, but it is understood that an alternative exemplary shielding member can include additional shielding members (e.g., two or more separate shielding members with a gap therebetween can be configured to cover the high speed transmit terminals, and two or more separate shielding members with a gap therebetween can be configured to cover the high speed receive terminals).

[0118] Further, the two shielding members 16a, 16n can be combined into a single shielding member with an opening, vent, or aperture in a central portion thereof that allows air flow and temperature control. In other words, the conductive ground shielding member(s) can be configured to cover some or all of the differential high speed terminals of a wafer.

[0119] FIG. 3F and FIG. 3G Another feature of the assembly of the present application is also shown. In more detail, one or more low speed / power terminals 31a-31n in a row (i.e., the same row) of a wafer of the top port assembly 10 can be configured to be offset from the low speed / power terminals in another row of another wafer (i.e., offset from a vertical axis "Y"), as shown by the offset 18a-18n.

[0120] FIG. 3G A close-up view of the offset 18a-18n is shown. As can be seen within the gap g1, there can be multiple rows of terminals (e.g., terminals 31a-31n) nested below one another (except for the top row) within the gap g1. For ease of understanding, for example, the multiple rows of terminals can be aligned vertically (i.e., along the vertical axis "Y") in a top row, a middle row, and a bottom row. FIG. 3G Referring to FIG. 1, four wafers are shown within an exemplary top port, labeled 1-4.

[0121] As shown, the low speed / power terminals in row 3 and row 4 can be offset 1 / 2 pitch to the left, and the terminals in row 1 and row 2 can be offset 1 / 2 pitch to the right. In embodiments, the offsets allow the terminals in each of the rows 1-4 to line up and allow air to pass through. In an embodiment, for example, a terminal (e.g., 31a-31n) can be offset a distance of 1 / 2 pitch from the vertical axis "Y".

[0122] Further, by configuring a set of terminals in a row to be offset from a vertical axis "Y", the terminals (e.g., low speed terminals and power terminals) can be more easily aligned.

[0123] Referring now to FIG. 3H Exemplary wafers 15a-15n (i.e., the wafers 1-4 of FIG. 1) are shown. In this example, the wafers 15a-15n are configured to be offset from a vertical axis "Y" by a distance of 1 / 2 pitch. FIG. 3HFigure 2 is another view of the connector assembly of Figure 1, showing the tail edges of the wafer bodies 15a-15n and the contact points. In one embodiment of the application, it is understood that more than one wafer body 15a-15n can support more than one differential high speed terminal, more than one low speed terminal, more than one power terminal, and more than one ground terminal. Also, a conductive ground shield (e.g., a split shield or a unitary shield) as described elsewhere herein can be constructed between some of the more than one wafer bodies to, among other things, reduce harmful crosstalk between the respective conductors making up each wafer body. However, in a particular embodiment, no shield can be constructed between certain wafer bodies. For example, FIG. 3H Figure 2 is another view of the connector assembly of Figure 1, showing the tail edges of the wafer bodies 15a-15n and the contact points. In one embodiment of the application, it is understood that more than one wafer body 15a-15n can support more than one differential high speed terminal, more than one low speed terminal, more than one power terminal, and more than one ground terminal. Also, a conductive ground shield (e.g., a split shield or a unitary shield) as described elsewhere herein can be constructed between some of the more than one wafer bodies to, among other things, reduce harmful crosstalk between the respective conductors making up each wafer body. However, in a particular embodiment, no shield can be constructed between certain wafer bodies. For example,

[0124] In more detail, each of the more than one wafer body 15a-15n supporting more than one differential high speed terminal can have a conductive ground shield located at a first distance proximate its respective differential high speed terminal to create a field affinity between the respective ground shield and differential high speed terminal. In one embodiment, the differential high speed terminals of each wafer body 15a-15n can be configured to communicate a communication data signal at a particular power level. Thus, a corresponding respective ground shield 16aa-16an can act as a conductive ground reference structure located in close proximity to the respective terminals of a given wafer body 15a-15n to create a field affinity. That is, the close proximity of a respective ground shield 16aa-16an to its respective wafer body 15a-15n and included terminals acts to electrically couple signals (e.g., high speed data signals) communicated within the terminals to a respective shield 16aa-16an (referred to as signal or field "affinity").

[0125] To create such a field affinity in a connector assembly of the application, in one embodiment, an exemplary respective shield (e.g., a split shield or a unitary shield) can be constructed between the respective terminals of a given wafer body 15a-15n to create a field affinity between the respective terminals and the respective shield 16aa-16an. In one embodiment, the respective shield 16aa-16an can be constructed to be located at a second distance proximate the respective terminals of a given wafer body 15a-15n to create a field affinity between the respective shield and the respective terminals. In one embodiment, the second distance can be less than the first distance. FIG. 3HShield 16ac) can be located at a first distance h1 from the respective signal terminals of a dielectric (e.g., dielectric 15c) that is less than a second distance h2 from the same terminals of dielectric 15c to the terminals of another dielectric (e.g., dielectric 15b). In other words, shield 16ac can be located at a shorter distance than the positioning of the terminals of dielectric 15b closer to the terminals of dielectric 15c.

[0126] In embodiments, the field affinity can be generated between each dielectric 15a-15n and its respective positioned shield 16aa-16an. Because of the field affinity, no shield is needed between dielectric 15b and dielectric 15c.

[0127] Exemplary non-limiting distances h1 and h2 can be 0.30 mm and 2.40 mm, respectively.

[0128] Further, in an embodiment, first distance h1 should be less than a third distance (e.g., between terminals 30a-30n of a given dielectric) between any two differential signal terminals of a given dielectric. FIG. 3R In an embodiment where third distance h3 represents the distance between adjacent high speed differential signal terminals of the same dielectric, h1 should be less than h3. Also, in embodiments that include a ground terminal between groups of differential signal terminals (e.g., in FIG. 3R In an embodiment where one of terminals 30a-30n is between groups of differential terminals 32a-32n, distance h1 should be much less than a distance represented by h4 between one of the differential signal terminals 32a-32n of a group and the nearest adjacent differential signal terminal 32a-32n of an adjacent second group of differential signal terminals. FIG. 3R In an embodiment where distance h4 is represented by h4.

[0129] Referring to FIG. 3I , an alternate embodiment is shown that also includes temperature control features. The figure shows the back of base 2j. As shown, base 2j can include one or more gaps or openings g 2a-2n In an embodiment, the size (i.e., area) of the central gap g 2a-2n may be at least equal to the size of gap g1 as described elsewhere herein. In an embodiment, for example, by way of openings g 2a-2n included in the back of base 2j, air can flow through and remove heat generated by at least the low speed terminals and power terminals 31a-31n of each dielectric within base 2j. In FIG. 3B , FIG. 3F and FIG. 3I , the conductive split ground shields are split into elements along a vertical axis "Y". Also shown in FIG. 3I are stakes 17a-17n for securing the base to a PCB.

[0130] Referring now to FIG. 3J In an alternative embodiment, for example, an exemplary conductive split ground shield can include two or more separate elements 20a-20n split along an axis other than a vertical or Y axis (e.g., an "X" axis or a "Z" axis) to cover, for example, a portion of the terminals of a wafer 15nn.

[0131] It should be understood that while the above description has described split shields, this is exemplary only. Alternatively, a conductive ground shield of the present application for a wafer (e.g., a top port wafer or a bottom port wafer) will include a single element (i.e., a single piece). Thus, in an alternative embodiment, a conductive ground shield element can be configured to cover one or more differential high speed terminals, one or more low speed terminals, one or more power terminals, and one or more ground terminals of a respective wafer (e.g., one shield per respective wafer).

[0132] Referring now to FIG. 3K for example, a single element conductive ground shield 21 is shown configured to cover all of the terminals (e.g., low speed and power terminals 31a-31n and high speed terminals 32a-32n and ground conductors or terminals 30a-30n) of one or more of the wafers. As shown, each differential high speed terminal 32a-32n can be configured with another differential high speed signal terminal 32a-32n on one side and a ground terminal 30a-30n on the other side.

[0133] In addition to temperature and alignment control features, the present inventors also provide methods and structures of the present application that combine metal ground conductors / terminals with plastic conductive ground shields.

[0134] Referring now to FIG. 3L to 3N for example, by "stitched" is meant that one or more insert molded metal ground conductors 22a-22n can be mated as a part of a plastic ground shield element 16a", 16n" (referred to as "stitched mating") by (typically) applying a force that forces the respective elements together in an interference fit. FIG. 3L and FIG. 3M In these embodiments, for example, the ground conductive portions 23a-23n can include a conductive plastic that is operable as a ground path segment that can connect one conductive metal portion 22a to another metal portion 22n.

[0135] In these embodiments, for example, the ground conductive portions 23a-23n can include a conductive plastic that is operable as a ground path segment that can connect one conductive metal portion 22a to another metal portion 22n.

[0136] Although FIG. 3L The conductive grounding portions 22a-22n of the metal are shown separately from the respective grounding conductor portions 23a-23n of a respective plastic conductive grounding shield, but it should be understood that, for example, FIG. 3L All components may include, as in FIG. 3M The diagram illustrates a single, interlocking mating structure when assembled. In several embodiments, exemplary metal portions 22a-22n may be made of copper, a copper alloy, or another conductive metal (e.g., gold, platinum).

[0137] It should be noted that mating a thin sheet conductor / terminal is one method of connecting conductors. Alternatively, for example, the conductor / terminal may include a support structure for connecting the terminals of a thin sheet to a top port module nose piece.

[0138] The grounding conductive portions 23a-23n of a grounding shielding element 16a”, 16n” can be constructed from a metal, a conductive or plastic-plated composite, or a hybrid laminate such as a PCB portion having dielectric and conductive elements. For example, in FIG. 3M In the middle, the grounding conductive parts 23a-23n are made of a plated plastic. Alternatively, in FIG. 3N In the diagram, the grounding conductive parts 24a-24n can be metallic. Therefore, the electrical grounding path P1-P... N It can be formed into a continuous metallic conductor (e.g., as shown in the image). FIG. 3N (as shown in the image) or some combination of metal and plastic conductive parts (such as...) FIG. 3M (like in the middle).

[0139] It should be noted that, for example, portions 22a-22n can be a continuous conductive structure rather than being divided into multiple parts.

[0140] In addition to providing the temperature and alignment control features of the present application, the connector assemblies of the present application provided by the inventors can also include features that reduce the impedance of a respective ground path and reduce harmful electrical cross-talk. For example, in various embodiments of the present application, the connector assemblies of the present application are provided by the inventors with electrical ground structures that function to maintain substantially the same voltage gradient (i.e., voltage differential) substantially along the length of the ground structure. Although a zero voltage gradient along an entire ground structure is not practically achievable, in various embodiments of the present application, the ground structures discovered and provided by the inventors minimize such gradients substantially along the entire structure at operating temperatures. The ability to minimize such voltage gradients substantially along the entire ground structure provides the connector assemblies of the present application with a high quality ground reference structure that in turn can reduce transmitted cross-talk and even cross-talk between terminals, provide a reduction in shared voltages, and provide an effective ground drain for any induced or coupled voltages due to electrical noise.

[0141] For example, the inventors provide connectors that include configurations that form dual ground path structures. Referring now to FIG. 3P , a dual ground path configuration according to an embodiment of the present application is shown. For ease of explanation, FIG. 3P Any low speed terminals or power terminals are not included.

[0142] As shown, a view of a top port ground path assembly 10" can include a dual ground path, where one ground path can be formed by individual ground conductors 30a-30n, and the other ground path can be formed by the conductive, deflectable, resilient "fingers" or tabs 28a-28n (collectively "fingers") of an insert molded conductive ground plate 28 and a conductive plated plastic shield 21a. In more detail, each of the fingers 28a-28n can be inserted into a groove 36a-36n formed on the shield 21a.

[0143] In an embodiment, each of the ground conductors 30a-30n can function as a first ground path that includes a structure that is connected at one end to a terminal of an input / output module (e.g., card 7b), is positioned in parallel and inline with a respective differential signal conductor, and is connected at an opposite end to a surface of a PCB (e.g., PCB 3).

[0144] When assembled, each of the fingers 28a-28n can be electrically and galvanically connected to (i.e., contact) a respective contact of a ground conductor 30a-30n (i.e., an end of the conductor 30a-30n), thereby functioning to provide a portion of a second ground path. The second ground path can pass from such contact point through a respective finger 28a-28n and the conductive plate 28 and then through the conductive plated plastic 21a.

[0145] While the figures and description herein illustrate the formation of a second ground path for the differential high speed terminals 32a-32n, it should be understood that similar additional ground paths can also be formed for the low speed terminals 31a-31n. In either case (high speed applications and low speed applications), the inventors have found that the formation of dual or multiple ground paths provides a substantial improvement in the integrity of the ground path structure of an assembly. This ensures that the electrical impedance and steady state resistance of the ground structure is controlled along the length of the ground path. For example, the ability to control impedance and resistance also allows the dual ground paths to share a ground associated power terminal / conductor temperature control when such power conductors are passing greater currents (i.e., the smaller the resistance, the less power can be dissipated or consumed).

[0146] As described herein, the shield 21a can be a plated plastic. Alternatively, for example, the shield 21a can be comprised of a plated ceramic (i.e., ceramic with a conductive flashing), plated metal or another conductive material with a dielectric cladding such as a nickel, tin gold or copper cladding. While the conductive flexible fingers are shown as part of a unitary plate, it should be understood that this is merely exemplary. Alternatively, for example, each of the plurality of fingers can be insert molded into a respective plastic ground shield structure.

[0147] It should be noted that in an embodiment including a structure of a discrete finger type, terminals that can be supported by a redundant isolated ground path can have the advantage of lower overall longitudinal resistance along the path to board termination and thereby enjoy the advantage of reduced path resistance and lower heat generation on a power transfer function.

[0148] Other dual ground path structures / configurations can also be included in an inventive assembly. For example, FIG. 3Q and FIG. 3RA configuration is shown that includes electrically conductive, flexible, resilient finger or tab portions 35a-35n (collectively "fingers") that are not part of a conductive plate but can be insert molded as part of a conductive plated plastic shield 21b. In this embodiment, a first ground path can be formed by each of the ground conductors 30a-30n, while a second ground path can be formed by each of the fingers 35a-35n contacting a respective contact portion (i.e., the end or top of the conductors 30a-30n) of a ground conductor 30a-30n, thereby serving to provide a second ground path from such a contact point through a respective finger 35a-35n and the conductive plastic shield 21b. FIG. 3Q An optional gap g for temperature control in the intervening shield of the top port wafer assembly 10 (which is obscured in this view) is also shown 3a-3n .

[0149] In each of the dual ground paths described herein, each path has an associated voltage difference that can be measured between opposite ends of the path (e.g., a path from the end of each finger 28a-28n to a PCB 3 or from the top of each conductor 30a-30n to a PCB 3) due to the impedance of each path. In various embodiments, the presence of the dual ground paths significantly reduces a common composite impedance along the length of each path. For example, if a first path has an impedance of Zl and a second path has an impedance of Z2, the common composite impedance Z3 will be less than Zl or Z2 and can be given by the relationship: Z3 = 1 / [(1 / Z1) + (1 / Z2)].

[0150] Reference is now made to FIG. 3S and FIG. 3T, which shows a view of exemplary tail alignment and support structures 14, 46 in accordance with embodiments of the application. In an embodiment, for example, structure 14 is configured as a non-conductive top port tail alignment and support structure that can be attached at the bottom of a connector assembly to the tail edges 30a'-30n' of the ground terminals 30a-30n, the tail edges 32a'-32n' of the differential high speed terminals 32a-32n, and the tail edges 31a'-31n' of the low speed and power terminals 31a-31n, while structure 46 is configured as a conductive bottom port tail alignment and support structure that can be attached at the bottom of a connector assembly to the tail edges of the ground terminals 43a-43n, the differential high speed terminals 42a-42n, and the low speed and power terminals 49a-49n.

[0151] Structure 14 can include apertures into which a side plate 9a, 9b can be inserted or affixed to a side plate 9a, 9b (see FIG. 3A or FIG. 3D) tail portions of the terminals of the wafer to align the tail edges of the terminals of the wafer. In addition, such exemplary structure 14 can include one or more attachment structures 26a-26n and attachment structures 27a-27n. In one embodiment, structures 26a-26n can be comprised of a non-conductive plastic that can be, for example, covered with a glue to attach structure 14 to a PCB of a PCB 3, and structures 26a-26n can also be combined with one or more structures 27a-27n comprised of a solderable plated non-conductive plastic or a metal that can be soldered to further attach structure 14 to a PCB. Alternatively, for example, all structures 26a-26n and structures 27a-27n can be comprised of a non-conductive plastic that can be covered with a glue or can all be comprised of a solderable plated non-conductive plastic or a metal. FIG. 1A

[0152] The present inventor now turns his attention to a bottom port wafer assembly. Recall that FIG. 1B Assembly 1 shows a top port 8a and a bottom port 8b. Each port has a corresponding wafer assembly that can include a plurality of wafers that in turn can include a plurality of terminals.

[0153] FIG. 4A shows an enlarged view of bottom port 8b, while FIG. 4B shows an enlarged view of an exemplary bottom port wafer assembly 40 within port 8b. It should be understood that some of the features of a top port wafer assembly can be incorporated into a bottom port wafer assembly. For example, a bottom port wafer assembly can include side plates for holding the tail portions of the terminals of the wafers to align the tail edges of the terminals of the wafers, although such plates are not shown in FIG. 4A and FIG. 4B .

[0154] In one embodiment, for example, bottom port wafer assembly 40 can be configured to be connected to PCB 3 using SMT. In alternative embodiments, for example, bottom port wafer assembly 40 can be connected to PCB 3 using a ball grid array, solder charge, press fit, SMT, a fiber optic technology, or a combination of these technologies.

[0155] Similar to the top port wafer assembly, each wafer of bottom port wafer assembly 40 can include one or more independent power conductors / terminals and low speed communication signal conductors / terminals, one or more differential high speed conductors / terminals, and one or more ground conductors. In various embodiments, at least exemplary high speed communication signals of up to and exceeding 100 gigabits per second (Gbps) can be transmitted by the high speed signal conductors of assembly 40. In alternative embodiments, communication signals of up to 160 Gbps can be transmitted by the high speed conductors.​

[0156] In one embodiment, for example, the low-speed terminals / power terminals can be located in the center of a wafer. Also, each differential high-speed terminal can be configured such that another differential high-speed signal terminal is located on one side and a ground terminal is located on the other side.

[0157] In FIG. 4B In one embodiment, the bottom port wafer assembly 40 can include a conductive, grounded plastic shielding element 41 configured to cover the lead frame and its respective wafer. Similar to the top port wafer assembly described above, the shielding 41 can include a plated plastic. Alternatively, for example, the shielding 41 can be constructed of a plated ceramic (i.e., ceramic with a conductive flash), plated metal, such as a hybrid laminate of a dielectric element and a conductive element of a PCB section or another conductive material with a dielectric coating, such as a nickel, tin, gold or copper coating. Although shown as a single, unitary piece, it should be understood that the shielding 41 can include multiple, separate elements (e.g., two elements), where double or multiple paths can be created to have the advantage of overall lower longitudinal resistance and thereby enjoy the advantage of reduced path resistance and lower heat generation on a power transfer function.

[0158] The bottom port wafer assembly can also include a dual ground path configuration similar to those described above. For example, one ground path can be formed by the individual ground conductors 43a-43n, while the other ground path can be formed by the conductive, deflectable "fingers" 45a-45n. In more detail, each of the ground conductors 43a-43n can function as a ground path to a PCB, such as the PCB 3. In one embodiment, when assembled, each of the fingers 45a-45n can be electrically and galvanically connected to a respective contact (i.e., end or top) of a ground conductor 43a-43n, thereby functioning to provide a second ground path from such contact point through a respective finger 45a-45n and then through the conductive plated plastic 41 to a PCB. Also shown are the high-speed terminals 42a-42n with the low-speed and power terminals 49a-49n.

[0159] Other dual ground path configurations can also be employed. For example, rather than providing an insert molded to the fingers 45a-45n of the shielding 41, the fingers can be part of a plate, similar to the plate 28 described above. In each of the multiple dual ground path embodiments, the dual ground path configuration can provide the features described herein.

[0160] Referring to FIG. 4CFigure 6 shows an enlarged view of an exemplary wafer 40a of the assembly 40. As shown, the wafer 40a shows a dual ground path formed by the individual ground conductors 43a-43n and by the conductive, flexible "fingers" 45a-45n and the shield 41.

[0161] FIG. 4D Figure 7 shows an exploded view of the exemplary wafer 40a. In one embodiment, for example, the flexible metal "fingers" 45a-45n can be soldered or otherwise conductively attached to the dielectric guide frame support structures 44a-44n, which also support the main ground conductors 42a-42n (e.g., high speed conductors / terminals).

[0162] FIG. 4E Figure 8 shows an exploded view of the bottom port wafer assembly 40. As shown, the assembly 40 can include a plurality of dielectric guide frame support structures 47a-47n, each for supporting and electrically isolating one or more wafers having one or more conductors (e.g., high speed terminals, low speed terminals, power terminals, and ground conductors). Also shown is a conductive bottom port tail alignment structure 46 for holding the tails of the terminals of each wafer and for helping to align the tail edges of the terminals of the bottom port wafers. In one embodiment, the structure 46 can include a plated plastic or stainless steel (e.g., such as stainless steel SUS 301, copper C70250, etc.).

[0163] Figure 9 shows an enlarged view of the exemplary wafer 40a shown in FIG. 4F and FIG. 4G Figure 10 shows a view from below of the bottom port wafer 40a shown in FIG. 4H To show one exemplary method of connecting the conductive fingers 45a-45n to the guide frame 47a, the green cones show the connection points in FIG. 4F and FIG. 4G It should be understood that such cones are merely illustrative of the connection points and are not physical structures. In one embodiment, for example, an exemplary conductive finger 45a-45n can be soldered to connect with the guide frame 47a at a respective connection point indicated by a green cone.

[0164] Reference is now made to FIG. 4IFIG. 8B shows a bottom view of the bottom port tail alignment and support structure 46 of FIG. 8A. In one embodiment, the structure 46 can be constructed of a conductive material (e.g., metal, plated plastic) unlike the top port wafer assembly tail alignment and support structure 14, as previously described. To provide alignment control, the tail edges 42a'-42n' of the one or more high speed terminals 42a-42n, the tail edges 49a'-49n' of the one or more low speed terminals and power terminals 49a-49n, and the tail edges 43a'-43n' of the one or more ground conductors 43a-43n of the wafer can be connected to the structure 46. Also, the bottom port tail alignment and support structure can include a plurality of tabs (e.g., apertures similar to 11a-11n and tabs similar to 14a-14n) that can be inserted into a side plate.

[0165] In addition to alignment control, the structure 46 can provide control of unwanted electrical interference (e.g., noise). For example, the structure 46 can be configured as a ground reference plane structure that surrounds, for example, the differential high speed terminals 42a-42n and their tail edges 42a'-42n'. Such a ground reference plane structure can be configured to electrically "mirror" (i.e., be configured similar to) a ground plane structure formed on the surface of a mating PCB (e.g., PCB 3). In an embodiment, it should be understood that the "mirrored" conductive ground structures (e.g., structure 46 and the surface of PCB 3) and conductive surfaces need not be in direct galvanic contact with each other to electrically isolate the differential signals carried in the high speed terminals 32a-32n from the differential signals carried by the terminals / conductors on the surface of the PCB, for example. In an embodiment, to provide such electrical isolation, the structure 46 can be spaced apart from the surface of the PCB by 0.25-0.50 mm, to give one non-limiting distance. Although not in direct galvanic contact, the two facing mirrored structures / surfaces can act as a capacitor; i.e., the two conductive structures / surfaces are separated by a dielectric (in this case, generally air).

[0166] In an embodiment, the structure 46 can be an integral part of a bottom port wafer assembly.

[0167] In our earlier description, the assembly 1 includes a central base 2j that surrounds a portion of the two top and bottom ports 8a, 8b. In an embodiment, an alternative base can surround a single port.

[0168] Referring now to FIG. 9, a perspective view of a top port tail alignment and support structure 14 is shown. In one embodiment, the structure 14 can be constructed of a conductive material (e.g., metal, plated plastic). To provide alignment control, the tail edges 42a'-42n' of the one or more high speed terminals 42a-42n, the tail edges 49a'-49n' of the one or more low speed terminals and power terminals 49a-49n, and the tail edges 43a'-43n' of the one or more ground conductors 43a-43n of the wafer can be connected to the structure 14. Also, the top port tail alignment and support structure can include a plurality of tabs (e.g., apertures similar to 11a-11n and tabs similar to 14a-14n) that can be inserted into a side plate. FIG. 5AFIG. 1b shows a connector 1b that can be part of an alternative high-speed shielded multi-layer multi-port connector assembly 100. As shown, the connector 1b can include a central housing 102. Like the housing 2j, the central housing 102 can be within a cage 2 and can be constructed of a plastic (e.g., LCP). Unlike the housing 2j, the housing 102 can be capable of surrounding a portion of a top port 88a but not a bottom port 88b. The housing 102 can be configured to protect one or more conductive wafers (not shown) within the housing 102.

[0169] In an embodiment, among other features, the housing 102, the ports 88a, 88b, the internal wafers and their respective terminals, and additional components within the housing 102 can form a high-speed shielded multi-layer multi-port connector with temperature and alignment control. In one embodiment, the connector 1b can include an input / output (I / O) connector such as those used for quad small form-factor pluggable (QSFP) or quad-double density small form-factor pluggable (CDFP) applications (e.g., QSFP, OSFP, CDFP applications). Thus, the assembly 100 including the housing 102 can be referred to as a high-speed shielded multi-port multi-layer connector assembly with temperature and alignment control, among other features.

[0170] The conductive terminals that are part of the wafers within the connector 1b can be configured to pass electrical signals. Additionally, in an alternative embodiment, for example, the terminals can also be configured to feed electrical signals to or receive electrical signals from E / O or O / E conversion circuitry. In the latter case, for example, such O / E or E / O conversion circuitry can be included and connected to the respective conductive wafers with a cage that interfaces to the active electronic circuitry.

[0171] In many cases, signals passing through the conductive wafers, O / E, E / O conversion circuitry, active devices, and re-timing circuitry can generate a significant amount of heat during operation. As such, as explained herein, the inventors provide solutions of the present invention that control such temperatures.

[0172] The housing 102 can be constructed with one or more notches 101a-101n on both sides that contact the bottom port 88b. Alternatively, posts or trusses can also be employed (see, e.g., FIG. 1c). FIG. 5D), to support the base on the bottom port 88b. For example, in comparison to the base 2j, because the base 102 does not enclose a portion of the bottom port 88b unlike the base 2j that encloses a portion of the bottom port 8b, the base 102 provides increased freedom of movement during assembly (i.e., the upper port 88ah and the lower port 88b are independent of each other and can be freely manipulated without affecting each other).

[0173] FIG. 5B An exploded view of the connector lb is shown. As shown, the base 102 can include a central structure 102a, a first support side plate 102b, and a second support side plate 102c (e.g., two metal side plates) opposite the first support side plate 102b. In embodiments of the present application, each side plate 102b, 102c can be configured to connect and secure the position of the plurality of thin sheet bodies relative to each other (i.e., sheet body to sheet body) within the interior of the base 102. In more detail, the side plates 102b, 102c can be constructed with one or more apertures 104a-104n, each aperture 104a-104n configured to receive a respective first tab 105a-105n of the top port thin sheet body assembly to control the positioning of the terminals of the thin sheet bodies within the top port, such that the thin sheet bodies can be held and the tail edges of the respective terminal tails can be aligned in the same plane. Also, to secure the central structure 102a and each side plate 102b, 102c to a lower side PCB (e.g., PCB 3 in FIG. 1A ), the central structure 102a and each side plate 102b, 102c can be constructed with one or more integral deformable board locks 103a-103n, for example, that can be composed of a deformable metal or plastic.

[0174] FIG. 5B Also shown are dielectric guide frame support structures or hangars 117a-117n (referred to simply as "hangars") that can be composed of a plastic, such as an LCP. In an embodiment, each hangar 117a-117n can be configured to provide physical support and alignment for each upper guide frame. Each hangar 117a-117n can also be constructed with a hot melt post 118a-118n (see FIG. 5C ), where each post can be configured to be received by an alignment opening on each side plate 102b, 102c.

[0175] Reference is now made to FIG. 5D and FIG. 5EFIG. 6 shows an alternative top port support structure 107 that can be fixedly configured between top port 88a and bottom port 88b. In one embodiment, structure 107 can include one or more apertures 108a-108n that are configured to receive a respective top port tab 109a-109n to fixedly position structure 107. As configured, structure 107 can operate to support top port 88a and the wafer within top port 88a. Although shown as an open right angle, it should be understood that this is merely an exemplary shape and structure for top port support structure 107. For example, other shapes and structures can be employed, such as an open or filled in square shaped structure.

[0176] In a further embodiment, for example, top port 88a can be independently connected to PCB 3 using an SMT technique. An exemplary top port assembly of this type is shown in FIG. 7. In addition to the SMT type connection, as previously described, for example, the assembly can be connected to PCB 3 using one or more substrate locks 103a-103n that are inserted into corresponding apertures (e.g., pin-in-paste holes, or compliant pin (press-fit) holes) on PCB 3 to provide alignment control of the wafer and its respective terminals that make up the top port assembly during a reflow soldering operation. FIG. 5F

[0177] FIG. 5G to FIG. 5J FIG. 8 shows a view of connector lb including temperature control.

[0178] In FIG. 9, a back cover 102d of the internal top port base 102 can include one or more openings 110a-110n that allow air to flow over the terminals (e.g., low speed signal terminals and power terminals) within the wafer of connector lb. FIG. 5G Referring now to FIGS. 10 and 11, a view of a top port's guide frame ground shield 111 is shown. Shield 111 can include temperature control features that control the temperature of the conductors / terminals. For example, one or more openings 112a-112n can be constructed on guide frame ground shield 111 to allow air to flow over the low speed signal terminals and power terminals 116a-116n, for example. Also shown are high speed signal terminals 114a-114n (e.g., differential signal pairs) that can be nested between ground conductors 113a-113n. As configured, this configuration provides enhanced shielding. It should be noted that the top port wafer assembly configuration shown in FIGS. 10 and 11 can also incorporate the top port wafer assembly 10 previously described herein.

[0179] FIG. 5H FIG. 5I FIG. 5G FIG. 5H

[0180] For example, FIG. 5H ​​​​​​and FIG. 5I Exemplary dielectric guide frame support structures 115a-115n of a top port assembly are also shown. For example, the guide frame support structures 115a-115n can be configured to align and support a plurality of ground conductors 113a-113n, a plurality of high speed conductors or terminals 114a-114n, and a plurality of low speed conductors or terminals and power conductors or terminals 116a-116n.

[0181] While the terminals of the ground conductors, high speed conductors, low speed conductors, and power conductors are illustrated facing downward, it should be understood that the assembly can also include guide frame structures having terminals facing upward that can be supported by similar guide frame supports and can be covered by a similar ground shield. That is, a top port assembly can include a plurality of guide frame structures.

[0182] In embodiments of the application, for example, as explained previously, the signal and field affinity between the terminals of the guide frame structures of the assembly 115a-115n and their respective ground shields can be sufficient to limit harmful guide frame to guide frame coupling and crosstalk.

[0183] FIG. 5J A view of a connector lb with a top port 88a prior to connection of a bottom port 88b is shown. Also shown, for example, are substrate locks 103a-103n that secure the top port assembly to a PCB (e.g., PCB 3) during a reflow soldering operation.

[0184] Reference is now made to FIG. 6A and FIG. 6b, a view of a top port wafer assembly 13 is shown. As shown, the assembly can include opposing metal side panels (only one shown) of an internal base 102. In an embodiment, the assembly can be aligned and connected to a PCB (such as PCB 3) and substrate locks 103a-103n, for example, using SMT. The assembly 13 can also include one or more gaps g provided in each of the conductive shields (e.g., plated plastic shields) therebetween to allow air to flow over the terminals. 4a-4n .

[0185] As explained herein, the inventors have discovered connector assemblies and related methods of the present application that include multiple alignment controls not only for alignment of a mating device (e.g., a high speed active plug-in module) but also for internal conductors and ground wafers. Also, the temperature control included in the connector assemblies of the present application allows such connectors to control the temperature generated by electronic circuitry within the connected plug-in module (e.g., up to 20 or more watts) that is capable of transmitting communications (data) signals of at least up to 100 Gbps.

[0186] It should be understood that every feature and function described herein with regard to one embodiment or illustrative drawing of the application is merely exemplary. That is, some features and functions can be applicable to and incorporated into many embodiments in addition to the specifically described embodiment or drawing.

[0187] The following is included in the form of a summary of the disclosure only in order to provide a brief

[0188] While benefits, advantages, solutions to problems and any element(s) that facilitates or otherwise supports the herein described benefits, advantages or solutions or causes them to become more pronounced are identified in the above description, it should be understood that such benefits, advantages, solutions and any element(s) that has relative importance thereto should not be deemed critical, required, or essential to any or all the claims, nor should they be interpreted as restricting the scope of the disclosure in any way.

Claims

1. A connector assembly comprising: a housing including a port; a contact-carrying wafer assembly positioned in the port of the housing, the wafer assembly including a row of conductors including a plurality of communication signal conductors and a plurality of ground conductors arranged in the row of conductors, wherein each of the communication signal conductors is positioned alongside one of the ground conductors in the row of conductors; and a ground path assembly, wherein the ground path assembly includes a dual ground path for at least one of the ground conductors, wherein the ground conductors include a contact tip portion and a tail portion; and the ground path assembly includes: a ground shield; and an electrically conductive resilient finger inserted into a groove of the ground shield and contacting a top surface of the ground conductors. the communication signal conductors include a plurality of high speed communication signal conductors and a plurality of low speed communication signal conductors; and 2. The connector assembly of claim 1, wherein, the plurality of low speed communication signal conductors are centrally positioned in the row of conductors, a first pair of the plurality of high speed communication signal conductors are on a first side of the low speed communication signal conductors, and a second pair of the plurality of high speed communication signal conductors are on a second side of the low speed communication signal conductors. the communication signal conductors include a plurality of high speed communication signal conductors and a plurality of low speed communication signal conductors; and 3. The connector assembly of claim 1, wherein, the plurality of low speed communication signal conductors are centrally positioned in the row of conductors, two pairs of the plurality of high speed communication signal conductors are on a first side of the low speed communication signal conductors, and two other pairs of the plurality of high speed communication signal conductors are on a second side of the low speed communication signal conductors. the ground path assembly includes at least one of a metal ground shield and a plated plastic ground shield.

4. The connector assembly of claim 1, wherein, the ground path assembly includes a stack of dielectric metal and conductive metal.

5. The connector assembly of claim 1, wherein, the ground path assembly includes a plated plastic ground shield and a metal ground shield insert that inter-fittingly mates with the plated plastic ground shield.

6. The connector assembly of claim 1, wherein, 7. The connector assembly of claim 1, wherein: the row of conductors includes a row of transmit conductors; the wafer assembly further includes a second row of conductors; and the second row of conductors includes a row of receive conductors.

8. The connector assembly of claim 1, wherein: the wafer assembly further includes a second row of conductors; the second row of conductors includes a plurality of high speed communication signal conductors, a plurality of low speed communication signal conductors, and a plurality of ground conductors arranged in the second row of conductors; and the wafer assembly further includes a ground shield positioned between the row of conductors and the second row of conductors.

9. The connector assembly of claim 8, wherein: the plurality of low speed communication signal conductors in the second row of conductors are centrally positioned in the second row of conductors; and the plurality of low speed communication signal conductors in the second row of conductors are offset from the plurality of low speed communication signal conductors in the row of conductors to form a centrally positioned air gap in the wafer assembly. the wafer assembly further includes a second row of conductors, a third row of conductors, and a fourth row of conductors.

10. The connector assembly of claim 1, wherein, ​ 11. The connector assembly of claim 10, wherein, The wafer assembly further includes: a first ground shield between the row of conductors and the second row of conductors; and a second ground shield between the third row of conductors and the fourth row of conductors.

12. The connector assembly of claim 11, wherein, The second row of conductors faces the third row of conductors without a ground shield between the second row of conductors and the third row of conductors.

13. The connector assembly of claim 10, wherein, The wafer assembly further includes a plurality of dielectric guide frame support structures supporting and electrically isolating the row of conductors, the second row of conductors, the third row of conductors, and the fourth row of conductors.

14. The connector assembly of claim 1, further comprising: a side plate on one side of the base, the side plate including an aperture, wherein, the wafer assembly further includes a tab at one end of the row of conductors; and the tab is inserted into the aperture of the side plate to align the row of conductors.

15. The connector assembly of claim 14, further comprising: a second side plate on another side of the base, the second side plate including an aperture, wherein, the wafer assembly further includes a second tab at another end of the row of conductors; and the second tab is inserted into the aperture of the second side plate to align the row of conductors.

16. The connector assembly of claim 15, wherein, the side plate extends along a first bottom edge of the base on the one side of the base; and the second side plate extends along a second bottom edge of the base on the another side of the base.

17. The connector assembly of claim 1, wherein, the ground path assembly includes a first ground shield and a second ground shield; the communication signal conductors include a plurality of high speed communication signal conductors and a plurality of low speed communication signal conductors; and the plurality of low speed communication signal conductors are centrally located in the row of conductors, a first pair of the plurality of high speed communication signal conductors extend along the first ground shield on a first side of the low speed communication signal conductors, and a second pair of the plurality of high speed communication signal conductors extend along the second ground shield on a second side of the low speed communication signal conductors.

18. The connector assembly of claim 17, wherein, the wafer assembly further includes a gap in the row of conductors between the first ground shield and the second ground shield; and the plurality of low speed communication signal conductors extend between the gap.

Images