Domestic DSP Remote Loading Method, Device and Medium Based on FPGA

Abstract

The present invention discloses a method, device and medium for remote loading of a domestic DSP based on FPGA, which belongs to the application field of domestic chips, and includes: S1, starting and resetting the FT‑M6678 chip; S2, loading the Bootloader program; S3, reading the frequency value; S4, adjusting the main frequency of the FT‑M6678 chip; S5, the FT‑M6678 chip shakes hands with the MSU chip; S6, if the handshake is successful, data is read from the MSU chip, and if the verification is passed, the data is parsed and moved to a specified memory address; S7, if the handshake is unsuccessful or the verification is unsuccessful after receiving the receipt, the current chip operating frequency is recorded, and the MSU chip is notified to reset the FT‑M6678 chip. The present invention solves the technical problem that the correctness and high efficiency of DSP loading cannot be guaranteed at the same time in the FPGA instead of Flash mode, and improves the loading efficiency and reliability.

Description

Technical Field

[0001] The present invention relates to the field of domestic chips, and more specifically, to a domestic DSP remote loading method, device and medium based on FPGA. Background Art

[0002] The characteristics of an integrated electronic system are that most functions in the system are realized by adding different software to general hardware modules. Commonly used embedded processors in general hardware modules include Field Programmable Gate Array (FPGA), Digital Signal Processor (DSP), and General Purpose Processor (GPP). FPGA has rich input and output pins and task parallel execution ability, DSP has high-efficiency data processing ability and a convenient and flexible debugging and development environment, and GPP can effectively support these control-intensive applications that are not digital signal processing types. These three types of embedded processors each have their own advantages and are used to run different programs in an integrated system to process different types of tasks, and their powerful performance is exerted through the programs running in them.

[0003] Currently, an integrated electronic information system mainly includes a General Data Processing Module (DPM), a General Signal Processing Module (SPM), a Network Switching Module (RCM), a System Control Module (SCM), and a High-Speed Mass Storage Module (MMM). In terms of the division and design of functional units of the module, it follows the requirements of the general functional framework of the module. The requirements of the general functional framework of the module are as follows: each module is composed of a Module Support Unit (MSU), a Processing Unit (PU), a Routing Unit (RU), a Network Interface Unit (NIU), a Power Supply Support Component (PSE), a Module Physical Interface (MPI), etc., to achieve the standardized, generalized and integrated design of the module hardware circuit. Among them, MSU is a unit that each hardware module has, and it is usually connected to the system control through a control bus, and is used to receive system control instructions to complete board-level management such as power-on control, reset control, program loading, program update, current acquisition, voltage acquisition, temperature acquisition, and health status reporting.

[0004] In the prior art, Feiteng M6678 (abbreviated as FT-M6678) is a domestically produced DSP fully independently developed by National University of Defense Technology. The single-core floating-point theoretical operation speed reaches 16 GFLOPS, and it has a powerful FFT coprocessor. It is the main DSP chip in the current integrated electronic system and is usually used in the general signal processing hardware module of the integrated electronic system. Feiteng M6678 uses a 28nm process, internally integrates 8 C66x processors, the single-core main frequency is 1 Hz, and it has peripherals such as a DDR3 controller, a DMA controller, an SRIO interface, an EMIF interface, a GPIO interface, a UART interface, and an SPI interface. It requires multiple power supplies such as a kernel, a SERDES kernel, digital I / O, DDR, and SERDES I / O for its operation.

[0005] Compared with the multi-level boot loading of the TI C6678 chip in the prior art, the self-boot mode of the Feiteng M6678 has no limitation that the first loading program must be less than or equal to 1KB. The conventional boot loading mode is to access the external Flash chip through interfaces such as EMIF and SPI, read out the complete code data (unlimited in length) pre-cured in the Flash, parse and move it to the specified memory address, and then run.

[0006] The present invention improves the loading technical solution of the existing Feiteng M6678 chip, aiming to solve the technical problems in terms of loading efficiency and loading reliability. Summary of the Invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art, provide a domestic DSP remote loading method, device and medium based on FPGA, solve the technical problem that it is impossible to ensure the correctness and high efficiency of DSP loading simultaneously in the FPGA replacing Flash mode, and improve the loading efficiency and reliability.

[0008] The purpose of the present invention is achieved through the following solutions:

[0009] A domestic DSP remote loading method based on FPGA includes:

[0010] S1, the FPGA sets the startup mode of the FT-M6678 chip to the BYPASS mode, starts and resets the FT-M6678 chip;

[0011] S2, after the self-loading startup program RBL of the FT-M6678 chip starts up, load the first-level user startup program Bootloader program, and the Bootloader program determines whether it is the first startup. If it is the first startup, go to step S3, otherwise go to S4;

[0012] S3, the current step is the first startup. After raising the main frequency of the FT-M6678 chip to the highest frequency, go to step S5;

[0013] S4, the current step is not the first startup. Read the frequency value X recorded during the previous startup. When X is greater than the set adjustment value, raise the DSP main frequency to (X - adjustment value). When X is less than or equal to the adjustment value, maintain the BYPASS mode and then go to step S5;

[0014] S5, the FT-M6678 chip shakes hands with the MSU chip to confirm whether the data is ready and stably readable. If the handshake is successful, go to step S6, otherwise go to step S7;

[0015] S6. When the FT-M6678 chip successfully shakes hands with the MSU, it starts to read the application program data from the MSU chip. After receiving all the data, it performs a CRC check. If the check passes, it parses and moves the program data to the specified memory address and starts the application program; otherwise, it proceeds to step S7.

[0016] S7. If the FT-M6678 chip fails to shake hands with the MSU chip within the timeout period or the CRC check fails after receiving the data, it records the current chip operating frequency, notifies the MSU chip to reset the FT-M6678 chip, and repeats step S1.

[0017] Furthermore, in the BYPASS mode, the main clock of the FT-M6678 chip is the same as the input clock and is not frequency-multiplied, which is the lowest rate gear that can be set when the FT-M6678 starts.

[0018] Furthermore, the Bootloader program is the user startup program before the user application program executes. It is the first-level user program bootstrapped by the chip's inherent self-startup program, and its function is to initialize the basic peripherals and complete the task of moving the subsequent second-level actual application program to the target memory address and loading it.

[0019] Furthermore, the frequency value X is the system main frequency configured adaptively. The FT-M6678 chip stores it in the register of the MSU chip through the EMIF interface. Each time after a startup failure, it records the system frequency value X used this time and adaptively reduces the clock frequency of the FT-M6678 chip when retrying. If the data stability still cannot be guaranteed after reducing to the adjusted value, it does not perform frequency multiplication and continues to use the BYPASS mode. If the BYPASS mode still cannot load correctly, the FT-M6678 chip notifies the MSU chip through the EMIF to restart the entire module.

[0020] Furthermore, the handshake and notification between the FT-M6678 chip and the MSU chip are both through the EMIF interface. The handshake method is to directly access the EMIF address space identifier. After the MSU prepares the data, it sets the ready identifier to 1, and the DSP waits until the ready identifier is 1 before reading the data.

[0021] Furthermore, the MSU chip is of the 95T model.

[0022] Furthermore, in step S4, the frequency adjustment value is set to 200 MHz each time.

[0023] Furthermore, in step S3, the highest main frequency supported by the chip is 1 GHz.

[0024] A computer device comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method described in any one of the above items is executed.

[0025] A computer-readable storage medium stores a computer program, wherein the computer program is loaded by a processor and executes any of the above methods.

[0026] The beneficial effects of the present invention include:

[0027] The present invention solves the technical problem that the correctness and high efficiency of DSP loading cannot be guaranteed simultaneously in the FPGA replacing Flash mode.

[0028] The present invention adds a first-level user startup program Bootloader program on the basis of the self-boot loader (RBL program) of FT-M6678. The Bootloader is very small in size and can be quickly loaded by the RBL program in BYPASS mode. At the same time, after the Bootloader is started, the main clock frequency will be adaptively reset to a high-speed gear suitable for the current system to ensure the efficiency of subsequent user application loading.

[0029] The present invention replaces the inherent self-loading startup program of the chip by adding a user startup program Bootloader to read, verify and move the application program. After the DSP is started, the RBL program loads the Bootloader at a low speed stably and safely. The Bootloader program will adaptively increase the DSP main clock frequency to the high-speed gear that adapts to the current system according to the system status and the compatibility status between domestic chips. At the same time, the correctness of the data is guaranteed by the handshake when reading the MSU data and the CRC check after reading the complete data, so as to achieve the purpose of ensuring both transmission efficiency and high data reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 It is a schematic diagram of a domestic DSP remote loading method based on FPGA in an embodiment of the present invention;

[0032] Figure 2 It is a structural principle diagram of DSP, MSU and external system in the integrated electronic system of an embodiment of the present invention. Specific embodiments

[0033] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or extended, replaced in any manner.

[0034] In the application of domestic chips, Feiteng M6678 has advantages compared with the existing TI C6678 chips. In the process of the inventors of the present invention improving the domestic DSP loading method by utilizing this advantage, after creative thinking, the following technical problems are found:

[0035] To improve the flexibility and convenience of loading, an FPGA can be used to simulate Flash. After receiving code data from the remote end through a high-speed interface (Srio or Ethernet), the DSP is reset and the data is transmitted to the DSP through interfaces such as EMIF, without the need to pre-solidify the program into Flash in advance. However, in the startup mode of Feiteng M6678 itself, there are only three options for the clock frequency: BYPASS, 800 MHz, and 1 GHz. In the BYPASS mode, the main clock is the same as the input clock, and the operating rate is very slow. In the 800 MHz and 1 GHz gears, the operating rate is very fast. Also, during the process of the FPGA transmitting data to the DSP, due to interference jitter inside and outside the system and compatibility issues between domestic chips, when the DSP reading rate is too fast, the transmitted data is unstable. The RBL program (self-loading startup program) in the Feiteng M6678 chip is solidified in the ROM and cannot be modified to add operations to maintain data correctness. After realizing the above technical problems, the inventors of the present invention further carried out creative thinking and proposed the following technical concept: A method is needed to ensure data correctness and loading efficiency while using the FPGA to replace Flash to provide data.

[0036] In the process of seeking solutions to the above-discovered technical problems, the embodiments of the present invention propose the following implementation solutions:

[0037] As Figure 1 shown, a domestic DSP remote loading method based on FPGA is proposed, including the following steps:

[0038] S1, the FPGA sets the FT-M6678 startup mode to the BYPASS mode, starts and resets the DSP;

[0039] S2, after the RBL of the FT-M6678 chip starts self-booting, it loads the Bootloader program. The Bootloader determines whether it is the first startup. If it is the first startup, step S3 is performed; otherwise, S4 is performed;

[0040] S3. If it is the first startup currently, after increasing the main frequency of the DSP to 1 GHz, proceed to S5;

[0041] S4. If it is not the first startup currently, read the frequency value X (MHz) recorded during the previous startup. When X is greater than 200 MHz, increase the main frequency of the DSP to (X - 200) (MHz). When X is less than or equal to 200 MHz, after maintaining the BYPASS mode, proceed to S5;

[0042] S5. Perform a handshake with the MSU chip to confirm whether the data is ready and stably readable. If the handshake is successful, proceed to step S6; otherwise, proceed to step S7;

[0043] S6. The handshake between the DSP and the MSU is successful. Start reading the application program data from the MSU. After receiving all the data, perform a CRC check. If the check passes, then parse and transfer the program data to the specified memory address and start the application program; otherwise, proceed to step S7;

[0044] S7. If the handshake between the DSP and the MSU is not successful within the timeout period or the CRC check is not successful after receiving the data, then record the current chip operating frequency X (MHz), notify the MSU to reset the DSP, and restart from step S1;

[0045] In an optional implementation, in the BYPASS mode, the main clock is the same as the input clock and is not frequency - doubled. It is the lowest speed gear that can be set when M6678 starts up. If the input clock is 25 MHz, then the main clock frequency of the DSP is 25 MHz.

[0046] In an optional implementation, the Bootloader program is the user startup program before the user application program is executed. It is the first - level user program boot - started by the chip's inherent self - startup program. Its function is to initialize basic peripherals and complete the task of transferring the subsequent second - level actual application program to the target memory address and loading it. It has the characteristics of being small in scale and programmable.

[0047] In an optional implementation, the frequency value X (MHz) is the system main frequency configured adaptively. The DSP stores it in the register of the MSU through the EMIF interface (it still exists after the DSP is powered off and reset). Each time after a startup failure, record the system frequency X used this time, and adaptively reduce the DSP clock frequency during the re - attempt, reducing 200 MHz each time. If reducing to 200 MHz still cannot ensure data stability, then do not perform frequency doubling and continue to use the BYPASS mode. If the BYPASS mode still cannot load correctly, then the DSP notifies the MSU through the EMIF to restart the entire module.

[0048] In an optional implementation, the handshake and notification between the DSP and the MSU are all through the EMIF interface. The handshake method is to directly access the EMIF address space identifier. After the MSU prepares the data, it sets the ready flag to 1. The DSP waits for the ready flag to be 1 before reading the data.

[0049] In an optional implementation, the MSU is a 95T model, the DSP is a FT-M6678 model, and the network switching chip is a NRS1800 chip.

[0050] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0051] High efficiency: the main clock frequency of the self-start loading mode of the FT-M6678 chip has only three gears. When the BYPASS low gear is selected, although the data transmission is stable, the rate is too slow. When the high gear is selected, the system interference jitter and the inconsistency of the compatibility between domestic chips will cause the technical problem of abnormal data read by the DSP. The present invention adds a first-level user loader Bootloader on the basis of the self-start loading program of FT-M6678. The scale of Bootloader is very small, and the program loading can be completed quickly in the BYPASS mode. At the same time, the main clock frequency in the Bootloader will be adaptively reset to a high-speed gear adapted to the current system to ensure the efficiency of subsequent user application loading.

[0052] High reliability: The main clock frequency of the self-starting mode of the FT-M6678 chip has only two gears, high and low, and the RBL self-loading program solidified in the ROM cannot be changed to increase the operation of maintaining data stability, so that the correctness and high efficiency of DSP loading cannot be guaranteed at the same time in the FPGA instead of Flash mode. The embodiment of the present invention replaces the subsequent RBL reading, checking and moving of the application program by adding a user loading program Bootloader. After the DSP is started, the RBL loads the Bootloader at a low speed stably and safely. The Bootloader program will adaptively increase the DSP main clock frequency to a high-speed gear that adapts to the current system according to the system status and the compatibility status between domestic chips. At the same time, the handshake when reading the MSU data and the CRC check after reading the complete data are used to ensure the correctness of the data, so as to achieve the purpose of ensuring both transmission efficiency and high data reliability.

[0053] Example 1

[0054] A domestic DSP remote loading method based on FPGA, comprising:

[0055] S1, FPGA sets the startup mode of the FT-M6678 chip to BYPASS mode, starts and resets the FT-M6678 chip;

[0056] S2. After the self-loading startup program RBL of the FT-M6678 chip starts self-booting, it loads the first-level user startup program, the Bootloader program. The Bootloader program determines whether it is the first startup. If it is the first startup, step S3 is performed; otherwise, S4 is performed.

[0057] S3. The current step is the first startup. After raising the main frequency of the FT-M6678 chip to the highest frequency, step S5 is performed.

[0058] S4. The current step is not the first startup. Read the frequency value X recorded during the previous startup. When X is greater than the set adjustment value, raise the DSP main frequency to (X - adjustment value). When X is less than or equal to the adjustment value, after maintaining the BYPASS mode, step S5 is performed.

[0059] S5. The FT-M6678 chip shakes hands with the MSU chip to confirm whether the data is ready and stably readable. If the handshake is successful, step S6 is performed; otherwise, step S7 is performed.

[0060] S6. The FT-M6678 chip shakes hands successfully with the MSU chip and starts to read the application program data from the MSU chip. After receiving all the data, perform CRC verification. If the verification passes, then parse and move the program data to the specified memory address and start the application program; otherwise, step S7 is performed.

[0061] S7. If the FT-M6678 chip fails to shake hands with the MSU chip within the timeout period or the CRC verification fails after receiving the data, record the current chip operating frequency, notify the MSU chip to reset the FT-M6678 chip, and re-perform step S1.

[0062] Embodiment 2

[0063] Based on Embodiment 1, in the BYPASS mode, the main clock of the FT-M6678 chip is the same as the input clock and there is no frequency multiplication, which is the lowest speed gear that can be set when the FT-M6678 starts up.

[0064] Embodiment 3

[0065] Based on Embodiment 1, the Bootloader program is the user startup program before the user application program is executed. It is the first-level user program boot-started by the chip's inherent self-startup program. Its function is to initialize the basic peripherals and complete the task of moving and loading the subsequent second-level actual application program to the target memory address. It has the characteristics of small scale and programmability.

[0066] Embodiment 4

[0067] Based on Embodiment 1, the frequency value X is the system main frequency configured adaptively. The FT-M6678 chip stores it in the register of the MSU chip through the EMIF interface. Each time the startup fails, the system frequency value X used this time is recorded, and when retrying, the clock frequency of the FT-M6678 chip is adaptively reduced. If the data stability still cannot be guaranteed after reducing to less than or equal to the adjustment value, no frequency doubling is performed, and the BYPASS mode is continued to be used. If the BYPASS mode still cannot be correctly loaded, the FT-M6678 chip notifies the MSU chip through the EMIF to restart the entire module.

[0068] Embodiment 5

[0069] Based on Embodiment 1, the handshake and notification between the FT-M6678 chip and the MSU chip are both through the EMIF interface. The handshake method is to directly access the EMIF address space identifier. After the MSU prepares the data, it sets the ready identifier to 1, and the DSP waits until the ready identifier is 1 before reading the data.

[0070] Embodiment 6

[0071] Based on Embodiment 1, the MSU chip is of the 95T model.

[0072] Embodiment 7

[0073] Based on Embodiment 1, in step S4, the frequency adjustment value is set to 200 MHz.

[0074] Embodiment 8

[0075] Based on Embodiment 1, in step S3, the highest main frequency of the chip is 1 GHz.

[0076] Embodiment 9

[0077] A computer device, the computer device includes a processor and a memory, and a computer program is stored in the memory. When the computer program is loaded and executed by the processor, the method described in any one of Embodiments 1 to 8 is performed.

[0078] Embodiment 10

[0079] A computer-readable storage medium, in which a computer program is stored. The computer program is loaded and executed by the processor to perform the method described in any one of Embodiments 1 to 8.

[0080] The units involved in the embodiments described in the present invention can be implemented in software or in hardware, and the described units can also be provided in the processor. Among them, the names of these units do not constitute a limitation to the unit itself in some cases.

[0081] According to one aspect of the present application, there is provided a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above various alternative implementation manners.

[0082] As another aspect, the present application further provides a computer-readable medium, which may be included in the electronic device described in the above embodiments; or may exist alone without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by an electronic device, the electronic device implements the methods described in the above embodiments.

[0083] Parts not involved in the present invention are the same as the prior art or can be implemented by the prior art.

[0084] The above technical solution is only one implementation manner of the present invention. For those skilled in the art, based on the disclosed application methods and principles of the present invention, it is very easy to make various types of improvements or deformations, not limited to the methods described in the above specific implementation manners of the present invention. Therefore, the above-described manner is only preferred and does not have a restrictive meaning.

[0085] In addition to the above examples, those skilled in the art can obtain inspiration according to the above disclosure or make modifications using the knowledge or technology in related fields to obtain other embodiments. The features of each embodiment can be interchanged or replaced. As long as the modifications and changes made by those skilled in the art do not depart from the spirit and scope of the present invention, they should all be within the protection scope of the claims appended to the present invention.

Claims

1. A domestic DSP remote loading method based on FPGA, characterized in that Including: S1. The FPGA sets the startup mode of the FT-M6678 chip to the BYPASS mode, starts and resets the FT-M6678 chip. S2. After the self-loading startup program RBL of the FT-M6678 chip starts self-starting, it loads the first-level user startup program, the Bootloader program. The Bootloader program determines whether it is the first startup. If it is the first startup, go to step S3; otherwise, go to S4. S3. The current step is the first startup. After raising the main frequency of the FT-M6678 chip to the highest frequency, go to step S5. S4. The current step is not the first startup. Read the frequency value X recorded during the previous startup. When X is greater than the set adjustment value, raise the DSP main frequency to (X - adjustment value). When X is less than or equal to the adjustment value, maintain the BYPASS mode and then go to step S5. S5. The FT-M6678 chip shakes hands with the MSU chip to confirm whether the data is ready and stably readable. If the handshake is successful, go to step S6; otherwise, go to step S7. S6. The handshake between the FT-M6678 chip and the MSU is successful. Start reading the application program data from the MSU chip. After receiving all the data, perform CRC verification. If the verification passes, then parse and transfer the program data to the specified memory address and start the application program; otherwise, go to step S7. S7. If the handshake between the FT-M6678 chip and the MSU chip is not successful within the timeout period or the CRC verification fails after receiving the receipt, record the current chip operating frequency, notify the MSU chip to reset the FT-M6678 chip, and re-perform step S1.

2. The domestic DSP remote loading method based on FPGA according to claim 1, wherein In the BYPASS mode, the main clock of the FT-M6678 chip is the same as the input clock, without frequency multiplication, which is the lowest speed gear that can be set when the FT-M6678 starts up.

3. The domestic DSP remote loading method based on FPGA according to claim 1, wherein The Bootloader program is the user startup program before the user application program is executed. It is the first-level user program boot-started by the chip's inherent self-startup program. Its function is to initialize basic peripherals and complete the task of transferring and loading the subsequent second-level actual application program to the target memory address.

4. The domestic DSP remote loading method based on FPGA according to claim 1, characterized in that, The frequency value X is the system main frequency configured adaptively. The FT-M6678 chip stores it in the register of the MSU chip through the EMIF interface. Each time the startup fails, record the system frequency value X used this time, and adaptively reduce the clock frequency of the FT-M6678 chip when retrying; if it still cannot ensure data stability after reducing to the same as the adjustment value, do not perform frequency multiplication and continue to use the BYPASS mode. If the BYPASS mode still cannot load correctly, the FT-M6678 chip notifies the MSU chip through the EMIF to restart the entire module.

5. The domestic DSP remote loading method based on FPGA according to claim 1, characterized in that, The handshake and notification between the FT-M6678 chip and the MSU chip are both through the EMIF interface. The handshake method is to directly access the EMIF address space identifier. After the MSU prepares the data, it sets the ready identifier to 1, and the DSP waits until the ready identifier is 1 before reading the data.

6. The domestic DSP remote loading method based on FPGA according to claim 1, wherein The MSU chip is of the 95T model.

7. The domestic DSP remote loading method based on FPGA according to claim 1, characterized in that In step S4, the frequency adjustment value each time is set to 200 MHz.

8. The domestic DSP remote loading method based on FPGA according to claim 1, characterized in that In step S3, the highest main frequency supported by the chip is 1 GHz.

9. A computer device, characterized in that, The computer device includes a processor and a memory. A computer program is stored in the memory. When the computer program is loaded and executed by the processor, the method according to any one of claims 1 to 8 is performed.

10. A computer-readable storage medium, characterized in that, A computer program is stored in a readable storage medium. The computer program is loaded and executed by a processor to perform the method according to any one of claims 1 to 8.

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