Method for manufacturing ohmic contact of group iii nitride semiconductor element

Abstract

This invention provides a method for fabricating ohmic contacts with low contact resistance in group III nitride semiconductor devices. The method primarily utilizes fluoride gas plasma for etching and surface treatment, followed by annealing to achieve ultra-low contact resistance ohmic contacts. This manufacturing method does not damage the semiconductor channel surface, has a relatively simple overall process, and produces group III nitride semiconductor devices with excellent reliability, applicable to group III nitride transistors and diodes.

Description

Technical Field

[0001] This invention relates to a group III nitride semiconductor device, and more particularly to a method for manufacturing an ohmic contact of a group III nitride semiconductor device. Background Technology

[0002] In the field of power electronics, the adoption of wide-bandgap semiconductor devices to improve the energy efficiency of equipment and modules and reduce energy consumption is a future trend. Gallium nitride (GaN) high-frequency power devices, in particular, are considered the most promising semiconductor devices to surpass the limits of silicon materials in next-generation high-power and high-frequency devices due to their superior performance. Group III nitride semiconductor devices, such as gallium nitride (GaN) semiconductor high electron mobility transistors (HEMTs), typically form a two-dimensional electron gas (2DEG) to achieve high-frequency operation and high-power output.

[0003] Taking a high electron mobility (HEMT) group III nitride semiconductor device with a metal-insulator-semiconductor (MIS) structure as an example, its turn-on resistance is roughly related to the contact resistance, the resistance between the source and gate of the two-dimensional electron gas, the resistance between the gate and drain of the two-dimensional electron gas, and the channel resistance. Among them, the contact resistance accounts for the largest part of the turn-on resistance. Therefore, in the design, it is necessary to reduce its resistance value to become an ohmic contact in order to achieve high turn-on current, low power loss, low heat generation, and long life cycle.

[0004] There are two known methods for reducing contact resistance when forming ohmic contacts, described below. One method involves etching the contact electrode region of the barrier layer and then regrowing a heavily doped N-type channel layer (e.g., an N+ GaN layer) on both sides of the barrier layer and on top of the channel layer. Subsequently, Ti / Au metal source and drain electrodes are formed to create an ohmic contact on the N-type channel layer. However, this method may have the following drawbacks: low yield; high manufacturing cost; damage to the inner side of the barrier layer after etching, leading to defects and potential leakage; and the need for complex and expensive molecular beam epitaxy (MBE) to regrow the heavily doped N-type channel layer.

[0005] Another approach to reducing contact resistance is to bury the source and gate portions of the Ti / Au metal within a barrier layer. However, this approach has several drawbacks: difficulty in controlling etching depth and sidewall slope accuracy; potential inhomogeneity issues in wafer-scale chip fabrication; potential residue and etching damage; and significant difficulty in achieving HEMT III nitride semiconductor devices with ultra-thin AlN or Al(Ga)N barrier layers (note: due to difficulty in controlling etching depth). Therefore, there remains a pressing need in the industry for methods to manufacture low-complexity, low-cost, and high-yield ohmic contacts with low contact resistance. Summary of the Invention

[0006] According to the present invention, a method for manufacturing an ohmic contact of a group III nitride semiconductor device is provided, wherein the group III nitride semiconductor device includes a transistor and a diode. The method for manufacturing the ohmic contact of this group III nitride semiconductor device includes: providing a group III nitride semiconductor structure without source and drain electrodes; forming a protective layer on a barrier layer of the group III nitride semiconductor structure; forming a patterned mask layer (e.g., a photoresist layer or other material layer resistant to corrosion by fluoride gas plasma) on the protective layer to define the locations of the source and drain electrodes; etching the protective layer of the group III nitride semiconductor structure using fluoride gas plasma, wherein portions of the protective layer corresponding to the locations of the source and drain electrodes are etched at least to the surface of the barrier layer; surface treating the exposed barrier layer of the group III nitride semiconductor structure using fluoride gas plasma; removing the mask layer and performing an annealing process; after the annealing process, implanting metal at the locations of the source and drain electrodes to form the source and drain electrodes; and performing a rapid annealing process on the group III nitride semiconductor structure with the source and drain electrodes formed.

[0007] According to the present invention, a semi-finished group III nitride semiconductor device is provided, which is manufactured using the aforementioned method for manufacturing ohmic contacts of group III nitride semiconductor devices, comprising: a group III nitride semiconductor structure; and a protective layer, a source electrode, and a drain electrode, formed on the barrier layer of the group III nitride semiconductor structure.

[0008] According to the present invention, a group III nitride semiconductor device is provided, comprising another group III nitride semiconductor device semi-finished product formed by removing part of the protective layer of the above-mentioned group III nitride semiconductor device semi-finished product and a gate, wherein the gate is formed on the barrier layer and is located between the source and the drain in the horizontal direction.

[0009] In summary, compared with prior art, the method for manufacturing ohmic contacts of group III nitride semiconductor devices provided by the embodiments of the present invention has the technical advantages of low manufacturing cost, high production yield and simple process. Attached Figure Description

[0010] The accompanying drawings of this invention are merely illustrative to those skilled in the art, and their dimensions and arrangements are not intended to limit the invention. A brief description of each drawing follows:

[0011] Figure 1 This is a flowchart of a method for manufacturing the ohmic contact resistance of a group III nitride semiconductor device according to an embodiment of the present invention;

[0012] Figures 2A to 2H This is a cross-sectional schematic diagram of the steps in the manufacturing method of the ohmic contact resistance of a group III nitride semiconductor device according to an embodiment of the present invention.

[0013] Figure 3A This is a schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment of the present invention;

[0014] Figure 3B This is a cross-sectional schematic diagram of a group III nitride semiconductor device according to another embodiment of the present invention;

[0015] Figure 3C This is a cross-sectional schematic diagram of a group III nitride semiconductor device according to another embodiment of the present invention.

[0016] The reference numerals in the attached figures are explained as follows:

[0017] 1: Group III nitride semiconductor device semi-finished products

[0018] 3-5: Group III nitride semiconductor devices

[0019] 11: Group III nitride semiconductor structure

[0020] 111: Substrate

[0021] 112: Nucleation layer

[0022] 113: Buffer layer

[0023] 114: Channel Layer

[0024] 115: Barrier Layer

[0025] 12: Source

[0026] 13: Drain

[0027] 14, 14': Protective layer

[0028] 15: Gate

[0029] 88: Dielectric layer

[0030] 17: Masking layer

[0031] S31~S38: Steps

[0032] RI: Quarantine Zone

[0033] 1141: Two-dimensional electron gas layer Detailed Implementation

[0034] To facilitate understanding of the technical features, content, advantages, and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and embodiments. The drawings used are for illustrative purposes only and to assist in the description. They may not represent the actual proportions and precise configurations of the present invention after implementation. Therefore, the proportions and configurations of the accompanying drawings should not be used to interpret or limit the scope of the present invention in actual implementation.

[0035] To address the low yield and high manufacturing cost of ohmic contacts in prior art group III nitride semiconductor devices, this invention proposes a novel and feasible method for manufacturing ohmic contacts that reduces contact resistance in group III nitride semiconductor devices. This method does not cause damage to the semiconductor channel surface, has a relatively simple overall process, and produces group III nitride semiconductor devices with excellent reliability. Furthermore, the resistivity of the contact resistance can be as low as 0.1 ohm·mm. Specifically, the method for manufacturing ohmic contacts with reduced contact resistance in group III nitride semiconductor devices involves forming a protective layer on a barrier layer in the group III nitride semiconductor structure before the source and drain electrodes are formed. Next, a pattern is defined using a masking material (e.g., photoresist). Then, fluoride gas plasma is used to etch and surface-treat the protective layer not covered by the masking material. After removing the photoresist and performing annealing, metal is implanted to form the source and gate electrodes. Finally, rapid annealing is performed to achieve ultra-low contact resistance.

[0036] In the method for fabricating the ohmic contact of a group III nitride semiconductor device according to the present invention, since a protective layer is present, fluoride gas plasma treatment will not damage the channel layer surface, and by controlling the power and processing time, fluoride ions will not penetrate into the channel layer. Furthermore, annealing can remove residual fluoride ions. Accordingly, the ohmic contact manufacturing method for reducing the contact resistance of a group III nitride semiconductor device according to embodiments of the present invention has technical advantages such as low manufacturing cost, high production yield, and simple process. In addition, embodiments of the present invention also provide a group III nitride semiconductor device and a semi-finished product manufactured using the above-described method for manufacturing the ohmic contact of a group III nitride semiconductor device.

[0037] Please refer to Figure 2H A cross-sectional schematic diagram of a group III nitride semiconductor device semi-finished product according to an embodiment of the present invention is shown below. Figure 2H The group III nitride semiconductor structure 11 includes a group III nitride semiconductor structure 11 without a source 12 and a drain 13, a source 12, a drain 13, and a protective layer 14. The source 12, drain 13, and protective layer 14 are located on the surface of the barrier layer 115 of the group III nitride semiconductor structure 11, and in the horizontal direction, a portion of the protective layer 14 is located between the sidewalls of the source 12 and the sidewalls of the drain 13. Due to etching and surface treatment by fluoride gas plasma, and vacuum annealing and rapid annealing, the resistivity of the contact resistance of the source 12 and drain 13 relative to the barrier layer 115 can reach 0.1 to 0.2 ohm-mm (inclusive).

[0038] In this embodiment of the invention, the protective layer 14 is a dielectric material, and may be SiN. x The protective layer 14 can be a layer, a SiO2 layer, or a Si layer, where x represents any number greater than 0. The thickness of the protective layer 14 can generally be selected between 5 and 100 nanometers (inclusive), preferably between 5 and 40 nanometers (inclusive). Furthermore, the selection of the thickness of the protective layer 14 is related to the material, the power of the fluoride gas plasma, and the processing time, and its main purpose is to protect the two-dimensional electron gas (2DEG) layer 1141 from damage during fluoride gas plasma processing. Each of the source electrode 12 and the drain electrode 13 can be a metal stack structure comprising a first structural layer and a second structural layer arranged from bottom to top. The first structural layer can be a Ti / Al bilayer structure, and the second structural layer can be a Ni / Au bilayer structure, a Ti / Ta bilayer structure, a Ti layer, a TiN layer, a Cu layer, or a W layer, and the invention is not limited thereto.

[0039] At Figure 1 and Figures 2A to 2HIn one embodiment, the group III nitride semiconductor structure 11 is a HEMT semiconductor structure, and the final group III nitride semiconductor device semi-finished product 1 does not have a gate, so it can be used as a HEMT diode. However, this invention is not limited thereto. In other embodiments, the group III nitride semiconductor device semi-finished product 1 can have a gate formed, and in the horizontal direction, the gate is located between the sidewall of the source 12 and the sidewall of the drain 13. The group III nitride semiconductor structure 11 includes a substrate 111, a nucleation layer 112, a buffer layer 113, a channel layer 114, and a barrier layer 115. The nucleation layer 112 is formed on the surface of the substrate 111, the buffer layer 113 is formed on the surface of the nucleation layer 112, the channel layer 114 is formed on the surface of the buffer layer 113, and the barrier layer 115 is formed on the surface of the channel layer 114. In the group III nitride semiconductor structure 11, a two-dimensional electron gas layer 1141 is formed in the interface between the channel layer 114 and the barrier layer 115.

[0040] The substrate 111 may be, for example, silicon, silicon-on-insulator (SOI), silicon carbide (SiC), sapphire substrate, or other substrates capable of epitaxially representing group III nitride semiconductors, and this invention is not limited thereto. The nucleation layer 112 may be, for example, a low-temperature GaN layer, a low-temperature AlN layer, a high-temperature GaN layer, or a high-temperature AlN layer, and this invention is not limited thereto. The buffer layer 113 may be, for example, an AlN layer, an AlGaN layer, an InGaN layer, a superlattice AlN / GaN layer, a superlattice AlGaN / GaN layer, a superlattice AlN / AlGaN layer, a carbon-doped GaN layer, an iron-doped GaN layer, or an undoped GaN layer, and this invention is not limited thereto. When the buffer layer 113 is an AlGaN layer, the chemical formula of AlGaN is Al y Ga 1-y N, 5% <= y. Channel layer 114 can be, for example, a GaN layer, an AlGaN layer, an InN layer, or an InGaN layer, and the present invention is not limited thereto. Barrier layer 115 can be, for example, an AlGaN layer, an InAlGaN layer, an InGaN layer, or an AlN layer, and the present invention is not limited thereto. When an AlGaN layer is selected as the barrier layer 115, the chemical formula of AlGaN is Al x Ga 1-x N, 0 <= x <= 40%, for example, x can be 20%, the thickness of the barrier layer 115 is 20 nanometers, and at this time the sheet resistance of the two-dimensional electron gas layer 1141 is <450 ohms / □.

[0041] Please refer to the following: Figure 1 , Figures 2A to 2H , Figure 1This is a flowchart of a method for manufacturing a group III nitride semiconductor device to reduce ohmic contacts according to an embodiment of the present invention, and... Figures 2A to 2H This is a cross-sectional schematic diagram of the finished product of each step in the manufacturing method of the ohmic contact of a group III nitride semiconductor device according to an embodiment of the present invention.

[0042] First, in step S31, a method such as... Figure 2A The group III nitride semiconductor structure 11, which does not form source 12 and drain 13 and has a two-dimensional electron gas, is structurally similar to Figure 2A The group III nitride semiconductor structure 11. Next, in step S32, a protective layer 14' is formed on the barrier layer 115 of the group III nitride semiconductor structure 11, such as... Figure 2B As shown, the protective layer 14' is formed, for example, by plasma-enhanced chemical vapor deposition (PECVD). The material of the protective layer 14' is as described above, and its thickness is selected from below 40 nanometers, for example, 10, 20, or 40 nanometers. Alternatively, the protective layer 14' can be deposited using in-situ metal-organic vapor deposition (MOCVD), any type of chemical vapor deposition (CVD), any type of physical vapor deposition (PVD), or any type of atomic layer deposition (ALD). Then, in step S33, a patterned masking layer 17 is formed on the protective layer 14' to define the positions of the source 12 and the drain 13, as shown... Figure 2C .

[0043] Next, in step S34, the protective layer 14' of the group III nitride semiconductor structure 11 is etched using a fluoride gas plasma in a dry etching manner, such as... Figure 2D As shown; in step S35, surface treatment is performed using fluoride gas plasma, such as... Figure 2EAs shown. Etching and surface treatment can be performed, for example, by generating CF4 plasma using an inductively coupled plasma (ICP) system, where the portion of the protective layer 14 corresponding to the positions of the source 12 and drain 13 is etched onto the surface of the barrier layer 115 to form the protective layer 14 and achieve ohmic region treatment. The power of the fluoride gas plasma is selected from 50 to 300 watts (inclusive), and the processing time is selected from 5 to 300 seconds (inclusive), preferably from 5 to 50 seconds (inclusive). When the thickness of the protective layer 14' is between 10 and 40 nanometers, the processing time can be 50 seconds, and the optimal thickness of the protective layer 14' is 30 nanometers. In addition to CF4 plasma, SF6, CHF3, or C4F8 plasma can also be used, and Ar plasma can be selectively mixed in. Furthermore, in addition to using an inductively coupled plasma system, reactive ion etching (RIE) or inductively coupled plasma-reactive ion etching (ICP-RIE) systems can also be used. When the protective layer is 14', approximately 20 nanometers, treatment with fluoride gas plasma for about 30 and 50 seconds can reduce the resistivity of the original contact resistance from 0.8 to 0.44 and 0.2 ohm-mm, respectively. Incidentally, the type, power, and treatment time of the fluoride gas plasma used for etching and surface treatment can be the same or different.

[0044] Next, in step S36, the masking layer 17 is removed, and a surface heat treatment, such as vacuum annealing, is performed to remove fluoride ion bonds. Figure 2F As shown. The annealing process here can be a multi-step annealing process or a single-step annealing process. For example, the number of steps in the annealing process is preferably 1 to 4 (inclusive). Then, after the annealing process, in step S37, the metal is implanted, as shown. Figure 2G The metal implantation method can be, for example, electron beam deposition to form the source 12 and drain 13. Annealing can be performed in a vacuum chamber or in an Ar environment, and other gases can be introduced in an Ar environment. Annealing can be rapid annealing or other types of annealing, with the annealing temperature generally between 450 and 650 degrees Celsius (inclusive), and the total annealing time approximately between 30 and 240 seconds (inclusive). If multi-step annealing is performed, each step takes between 15 and 60 seconds (inclusive).

[0045] Then, in step S38, a rapid annealing process is performed to achieve ultra-low contact resistance, such as... Figure 2HThe rapid annealing process is carried out at a temperature of 750 to 850 degrees Celsius (inclusive), and the total time for rapid annealing is approximately between 10 and 60 seconds (inclusive, preferably 30 seconds). Furthermore, the resistivity of the contact resistance can be reduced to 0.1 to 0.15 ohm-mm.

[0046] Please refer to Figure 3A , Figure 3A This is a schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment of the present invention. Figure 3A In this context, group III nitride semiconductor device 3 is a group III nitride semiconductor device for HEMT. The implementation of group III nitride semiconductor device 3 is as follows. First, [the following steps are taken]... Figure 2H After mesa etching is performed on the group III nitride semiconductor device semi-finished product 1 to define the isolation region RI, the portion of the protective layer 14 between the source 12 and the drain 13 in the horizontal direction is removed to define the gate region. Then, a gate 15 is formed on top of the barrier layer 115 in the gate region.

[0047] Please refer to Figure 3B , Figure 3B This is a schematic cross-sectional view of a group III nitride semiconductor device according to another embodiment of the present invention. Different from... Figure 3A In one embodiment, after removing part of the protective layer 14, a dielectric layer 88 with a thickness of approximately 1 to 10 nanometers (including the two endpoints of 1 and 10 nanometers) is deposited on the protective layer 14 and the barrier layer 115 at the gate region of the group III nitride semiconductor device 4. Then, the gate 15 is formed on the dielectric layer 88 at the gate region.

[0048] Please refer to Figure 3C , Figure 3C This is a schematic cross-sectional view of a group III nitride semiconductor device according to another embodiment of the present invention. Unlike... Figure 3B In one embodiment, when a portion of the protective layer 14 is removed from the group III nitride semiconductor device 5, a portion of the barrier layer 115 is also removed, so the gate 15 is located above the recess of the barrier layer 115.

[0049] Specifically, the ohmic contact manufacturing method for reducing the contact resistance of group III nitride semiconductor devices according to embodiments of the present invention uses fluoride gas plasma treatment with a protective layer and annealing treatment to reduce the contact resistance twice, thus effectively reducing the resistivity of the contact resistance. Furthermore, compared to prior art, the ohmic contact manufacturing method for group III nitride semiconductor devices according to embodiments of the present invention has the technical advantages of low manufacturing cost, high production yield, and simple process.

[0050] In summary, it is clear that the present invention has indeed achieved the desired improved effects by breaking through the previous technology, and these effects are not easily conceived by those skilled in the art.

[0051] The embodiments described above are merely for illustrating the technical ideas and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the patent scope of the present invention. That is, all equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered within the patent scope of the present invention.

Claims

1. A method for manufacturing an ohmic contact for a group III nitride semiconductor device, comprising: A group III nitride semiconductor structure (11') without a source (12) and a drain (13) is provided; A protective layer (14') is formed on a barrier layer (115) of the group III nitride semiconductor structure (11); A patterned mask layer (17) is formed on the protective layer (14') to define the positions of the source (12) and the drain (13); The protective layer (14') of the group III nitride semiconductor structure (11') is etched using fluoride gas plasma, wherein a portion of the protective layer (14') corresponding to the positions of the source (12) and the drain (13) is etched to at least the surface of the barrier layer (115). The barrier layer (115) exposed in the group III nitride semiconductor structure (11) was surface treated using a fluoride gas plasma. Remove the mask layer (17) and perform an annealing process at a temperature between 450 and 650 degrees Celsius for a total time between 30 and 240 seconds. After the annealing process, metal is implanted at the positions of the source electrode (12) and the drain electrode (13) to form the source electrode (12) and the drain electrode (13); and A rapid annealing process is performed on the group III nitride semiconductor structure (11) on which the source (12) and the drain (13) are formed, wherein the temperature of the rapid annealing process is between 750 degrees Celsius and 850 degrees Celsius, and the total time of the rapid annealing process is between 10 and 60 seconds. The protective layer (14') is SiN x The protective layer (14') is a layer or SiO2 layer, and the thickness of the protective layer (14') is between 5 and 100 nanometers. The fluoride gas plasma is CF4, SF6 or C4F8 plasma, the power of the fluoride gas plasma is between 50 and 300 watts, and the processing time of the fluoride gas plasma is between 5 and 300 seconds.

2. The method for manufacturing an ohmic contact of a group III nitride semiconductor device as described in claim 1, wherein the barrier layer (115) is an AlGaN layer with the chemical formula AlxGa1-xN, 0<=x<=40%, or the barrier layer (115) is an AlN layer.

3. A semi-finished group III nitride semiconductor device, manufactured using a method for manufacturing an ohmic contact of a group III nitride semiconductor device as described in any one of claims 1 to 2, comprising: The group III nitride semiconductor structure (11); as well as The protective layer (14), the source electrode (12), and the drain electrode (13) are formed on the barrier layer (115) of the group III nitride semiconductor structure (11).

4. The group III nitride semiconductor device semi-finished product as claimed in claim 3, wherein the resistivity of the contact resistance of the group III nitride semiconductor device is between 0.1 and 0.2 ohm·mm.

5. A group III nitride semiconductor device, comprising: Another group III nitride semiconductor device semi-finished product (1) is formed by removing a portion of the protective layer (14) of a group III nitride semiconductor device semi-finished product (1) as described in claim 3; and A gate (15) is formed on the barrier layer (115) and is located horizontally between the source (12) and the drain (13).

6. The group III nitride semiconductor device of claim 5, further comprising: A dielectric layer (88) is located below the gate (15) and above the barrier layer (115), and above the protective layer (14).

7. The group III nitride semiconductor device as claimed in claim 5, wherein a portion of the barrier layer (115) of the group III nitride semiconductor device semi-finished product (1) is further removed to form another group III nitride semiconductor device semi-finished product (1) having a groove in the barrier layer (115), and the gate (15) is located on the groove.

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