Package substrate and semiconductor device including the same

Abstract

This embodiment relates to a package substrate and a semiconductor device. The semiconductor device comprises: an element portion including a semiconductor element; and a package substrate electrically connected to the element portion. By using a glass substrate as a core for the package substrate, the semiconductor element and the motherboard are more closely connected, allowing electrical signals to be transmitted over the shortest possible distance. This significantly improves electrical characteristics such as signal transmission speed, substantially prevents the generation of parasitic elements, further simplifies the insulating film processing process, and provides a package substrate suitable for high-speed circuits.

Description

[0001] This case is a divisional application with application number 2020800112829, application date March 12, 2020, and invention name “Packaging substrate and semiconductor device including the same”. Technical Field

[0002] The present embodiment relates to a package substrate having a cavity structure and a semiconductor device including the same. Background Art

[0003] When manufacturing electronic components, realizing circuits on semiconductor chips is called the front-end (FE) process, and assembling the chips into a state that can be used in actual products is called the back-end (BE) process, which includes the packaging process.

[0004] The four core technologies of the semiconductor industry that have enabled the recent rapid growth of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is advancing in various forms, such as line widths in the nanometer unit below micrometers, cells exceeding 10 million, high-speed operation, and the generation of large amounts of heat. However, the technology to fully package these semiconductors is still lacking. Therefore, the electrical performance of semiconductors sometimes depends on the packaging technology and corresponding electrical connections, rather than the performance of the semiconductor technology itself.

[0005] Package substrates are made of ceramic or resin. Ceramic substrates, due to their high resistance and dielectric constant, make it difficult to mount high-performance, high-frequency semiconductor components. Resin substrates can mount relatively high-performance, high-frequency semiconductor components, but they have limitations in reducing wiring pitch.

[0006] Recently, research is underway to use silicon or glass as substrates for high-end packaging. By forming through-holes in silicon or glass substrates and applying conductive materials to these through-holes, the wiring length between components and the motherboard can be shortened, achieving excellent electrical characteristics.

[0007] Furthermore, semiconductor packages generate heat during operation and sometimes additionally include a heat sink for releasing the heat.

[0008] Related prior art documents include Korean Patent Publication No. 10-2019-0008103, Korean Patent Publication No. 10-2016-0114710, and Korean Patent Authorization No. 10-1468680. Summary of the Invention

[0009] Problems to be solved by the invention

[0010] The purpose of this embodiment is to provide a more integrated semiconductor device by manufacturing a package substrate having a cavity structure using a glass substrate.

[0011] Means used to solve problems

[0012] In order to achieve the above-mentioned purpose, according to one embodiment, a packaging substrate includes a core layer and an upper layer located on the above-mentioned core layer, the above-mentioned core layer includes a glass substrate and a core through-hole, the above-mentioned glass substrate includes a first surface and a second surface facing each other, the above-mentioned glass substrate includes: a first region having a first thickness; and a second region adjacent to the above-mentioned first region and having a second thickness, the thickness of the above-mentioned second thickness is thinner than the thickness of the above-mentioned first thickness, the above-mentioned core through-hole penetrates the above-mentioned glass substrate in the thickness direction, and the above-mentioned core through-hole is arranged in plurality, the above-mentioned core layer includes a core distribution layer located on the surface of the above-mentioned glass substrate or the core through-hole, at least a portion of the above-mentioned core distribution layer electrically connects the conductive layer on the above-mentioned first surface and the conductive layer on the above-mentioned second surface through the above-mentioned core through-hole, the above-mentioned upper layer includes a conductive layer located on the above-mentioned first surface and electrically connecting the above-mentioned core distribution layer and the external semiconductor element part, the above-mentioned packaging substrate also includes a cavity portion located above or below the above-mentioned second region, the above-mentioned cavity portion includes an internal space, and the cavity distribution layer and the cavity element electrically connected to the above-mentioned core distribution layer can be located in the above-mentioned internal space.

[0013] In one embodiment, the cavity may further include a support portion protruding toward the internal space on at least one side of the cavity.

[0014] In one embodiment, the support portion may have an arc shape connecting one end and the other end of a side surface of the cavity portion.

[0015] In one embodiment, at least a portion of the support portion may be connected to one surface in the thickness direction of the first region, and another portion of the support portion may protrude into the inner space to fix the position of the inserted cavity element.

[0016] In one embodiment, the support portion may include the same material as the glass substrate.

[0017] In one embodiment, one side surface of the cavity portion may be a first side surface of the cavity, and another side surface different from the first side surface of the cavity may be a second side surface of the cavity. Support portions may be arranged on the first side surface of the cavity and the second side surface of the cavity, respectively.

[0018] In one embodiment, the cavity distribution layer may include: a cavity distribution pattern, which is a conductive layer electrically connected to the cavity element and the core distribution layer, and at least a portion of the cavity element is located in the internal space; and a cavity insulation layer, which is an insulation layer surrounding the cavity distribution pattern.

[0019] In one embodiment, the encapsulation substrate may further include a heat dissipation portion located between the core layer and the cavity portion. The heat dissipation portion may be located on a surface where the first region of the glass substrate and the inner space of the cavity portion meet.

[0020] In one embodiment, at least a portion of the heat dissipation portion may be connected to the core distribution layer.

[0021] In order to achieve the above-mentioned purpose, according to one embodiment, a semiconductor device may include: a semiconductor element portion, in which one or more semiconductor elements are located; a packaging substrate, electrically connected to the above-mentioned semiconductor elements; and a motherboard, electrically connected to the above-mentioned packaging substrate, transmitting external electrical signals to the above-mentioned semiconductor elements and connecting the above-mentioned semiconductor elements and the external electrical signals.

[0022] Effects of the Invention

[0023] The package substrate and the semiconductor device including the same of this embodiment transmit electrical signals over the shortest possible distance by connecting the semiconductor element and the motherboard more closely, thereby significantly improving electrical characteristics such as signal transmission speed.

[0024] In addition, since the glass substrate used as the core of the substrate itself is an insulator, there is almost no possibility of parasitic elements being generated compared to the existing silicon core, so the insulating film processing process can be further simplified and it can be applied to high-speed circuits.

[0025] Furthermore, compared to the manufacture of silicon circular wafers, since glass substrates are manufactured in the form of large panels, mass production is relatively easy and economic efficiency can be further improved.

[0026] In addition, by locating components such as transistors in the package substrate, the transmitted electrical signals can be transmitted over a shorter distance, and excellent performance can be achieved through a thinner substrate.

[0027] Furthermore, the cavity element can be fixed at a more precise position by the support portion in the cavity portion, further improving workability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram illustrating a cross-sectional structure of a semiconductor device according to one embodiment.

[0029] Figure 2FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment.

[0030] Figure 3A and Figure 3B Each of them is a schematic diagram illustrating a portion of a package substrate according to the present embodiment in cross section.

[0031] Figure 4A and Figure 4B Each of them is a schematic diagram illustrating a portion of a package substrate according to the present embodiment in cross section.

[0032] Figure 5 Detailed schematic diagram illustrating a portion of a cross section of a package substrate according to the present embodiment (circles indicate shapes viewed from the top or bottom).

[0033] Figure 6 Detailed schematic diagram illustrating a portion of a cross section of a package substrate according to the present embodiment (circles indicate shapes viewed from the top or bottom).

[0034] FIG. 7 is a schematic diagram illustrating in cross section the shape of a core through-hole formed on a glass substrate according to the present embodiment.

[0035] Figure 8 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment.

[0036] Figure 9A and Figure 9B Each of them is a schematic diagram illustrating a portion of a package substrate according to another embodiment in cross section.

[0037] Figure 10A and Figure 10B Each of them is a schematic diagram illustrating a portion of a package substrate according to another embodiment in cross section.

[0038] FIG. 11 is a schematic diagram illustrating the shape of a cavity element fixed on a glass substrate having a cavity portion applicable to a support portion according to the present embodiment.

[0039] Figure 12 This is a schematic diagram illustrating the shape of a glass substrate having a cavity portion to which a support portion is applied according to the present embodiment when viewed from the top.

[0040] Figure 13A and Figure 13B Schematic diagram illustrating a cross-section of a cavity glass substrate and a core distribution pattern to which a support portion is applied according to this embodiment. Figure 13A It is a cross section observed along the line a-a' in FIG11 , Figure 13B For Figure 13A A cross section having a core distribution pattern is formed therein.

[0041] Figure 14Schematic diagram illustrating in cross section the core portion and the cavity portion of a package substrate to which the support portion is applied according to the present embodiment.

[0042] Figure 15 Schematic diagram illustrating a cross section of a package substrate to which a support portion is applied according to the present embodiment. DETAILED DESCRIPTION

[0043] Below, embodiments of the present invention are described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in a variety of different embodiments and is not limited to the embodiments described in this specification. Throughout the text, the same reference numerals represent the same components.

[0044] In this specification, the term "combination thereof" included in the Markush-type description refers to a mixture or combination of one or more components selected from the group consisting of multiple components of the Markush-type description, thereby indicating that one or more components selected from the group consisting of the above multiple components are included.

[0045] In this specification, unless otherwise specified, terms such as "first," "second," or "A," "B," etc. are used to distinguish the same terms from each other. Also, a singular expression may include a plural expression unless the meaning is completely different from the context.

[0046] In the present specification, the “~” group may mean that a compound equivalent to “~” or a derivative of “~” is included in the compound.

[0047] In this specification, "B is located on A" means that B is located on A in direct contact with A, or that B is located on A with another layer sandwiched between A and B, and is not limited to the meaning that B is located on A in contact with the surface of A.

[0048] In this specification, the meaning of A being connected to B means that A and B are directly connected or connected through other constituent elements between A and B, and unless otherwise specified, the interpretation is not limited to A and B being directly connected.

[0049] In this specification, unless otherwise specified, an expression in the singular may be construed as including a meaning in the singular or plural as read from the context.

[0050] While developing a more integrated semiconductor device capable of exhibiting high performance at a thinner thickness, the inventors realized that the packaging of the components themselves is also an important factor in improving performance. Through research into this issue, they confirmed that, unlike conventional interposers and organic substrates that use a core with two or more layers as a packaging substrate on a motherboard, by using a glass core as a single layer and employing a cavity structure, the packaging substrate can be made thinner and contribute to improving the electrical characteristics of the semiconductor device, thereby completing the present invention.

[0051] Furthermore, the inventors have confirmed that applying a method such as a heat sink that can transfer heat generated by internal components to the outside can contribute to improving the electrical characteristics of a semiconductor device using a thinner package substrate, thereby completing the present invention.

[0052] Furthermore, it was confirmed that when the components are set in the above-mentioned cavity structure, the performance of the semiconductor device can only be further improved if the above-mentioned components are set in the pre-set correct position and maintain their position. Therefore, by further applying the position of the guiding component and the supporting part of the supporting component in the cavity space, the workability of the substrate manufacturing and the performance of the packaging substrate can be further improved, thereby completing the present invention.

[0053] Figure 1 Schematic diagram illustrating a cross-sectional structure of a semiconductor device according to one embodiment. Figure 2 FIG2 is a schematic diagram illustrating a structure of a package substrate according to another embodiment in cross section. Figure 3A and Figure 3B Each of them is a schematic diagram illustrating a portion of a package substrate according to the present embodiment in cross section. Figure 4A and Figure 4B are schematic diagrams illustrating a portion of a package substrate according to the present embodiment in cross section, Figure 5 Detailed schematic diagram illustrating a portion of a cross section of a package substrate according to this embodiment (circles indicate shapes viewed from the top or bottom), Figure 6 FIG. 7 is a schematic diagram illustrating a cross section of a portion of a package substrate according to the present embodiment (circles indicate the shape when viewed from the top or bottom). FIG. 8 is a schematic diagram illustrating a cross section of a core through hole formed on a glass substrate according to the present embodiment. Figure 8 FIG2 is a schematic diagram illustrating a structure of a package substrate according to another embodiment in cross section. Figure 9A and Figure 9B Each of them is a schematic diagram illustrating a portion of a package substrate according to another embodiment in cross section. Figure 10A and Figure 10B11 is a schematic diagram illustrating the shape of a cavity element fixed on a glass substrate having a cavity portion suitable for a support portion according to this embodiment. Figure 12 Schematic diagram illustrating the shape of the glass substrate having the cavity portion applicable to the support portion according to the present embodiment when viewed from the top, Figure 13A and Figure 13B Schematic diagram illustrating a cross-section of a cavity glass substrate and a core distribution pattern to which a support portion is applied according to this embodiment. Figure 13A It is a cross section observed along the line a-a' in FIG11 , Figure 13B For Figure 13A A cross section having a core distribution pattern is formed therein. Figure 14 This is a schematic diagram illustrating a cross section of a core portion and a cavity portion in a package substrate to which a support portion is applied according to this embodiment. Figure 15 The present invention will be described in more detail below with reference to the accompanying drawings.

[0054] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to this embodiment includes: a semiconductor element portion 30, which is provided with one or more semiconductor elements 32, 34, and 36; a packaging substrate 20, which is electrically connected to the above-mentioned semiconductor elements; and a motherboard 10, which is electrically connected to the above-mentioned packaging substrate, transmits external electrical signals to the above-mentioned semiconductor elements and connects the above-mentioned semiconductor elements and the external electrical signals.

[0055] According to another embodiment, a package substrate 20 includes: a core layer 22 ; an upper layer 26 located on one side of the core layer; and a cavity portion 28 for arranging a cavity element 40 .

[0056] The package substrate further includes: a heat dissipation portion H located between the core layer and the cavity portion; and / or a support portion 285 protruding toward the internal space on at least one side of the cavity portion.

[0057] The semiconductor element portion 30 is a component mounted on a semiconductor device and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, as the semiconductor element portion 30, computing elements such as a CPU and a GPU (first element: 32, second element: 34), and storage elements such as a memory chip (third element: 36) can be applied, but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0058] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0059] The package substrate 20 may optionally further include a lower layer 29 located below the core layer.

[0060] The core layer 22 includes a glass substrate 21 including a first region 211 and a second region 222, wherein the second region 222 is adjacent to the first region 221 having the first thickness 211 and has a second thickness 212 thinner than the first thickness; a plurality of core through holes 23 penetrating the glass substrate in the thickness direction; and a core distribution layer 24 located on the surface of the glass substrate or the core through holes, and electrically connecting the first surface 213 of the glass substrate and the second surface 214 facing the first surface through the core through holes.

[0061] The core layer 22 includes a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 thinner than the first thickness. The second region may function as a cavity structure.

[0062] In the same region, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other. The two surfaces are substantially parallel to each other, so that the glass substrate as a whole has a certain thickness.

[0063] The glass substrate 21 has a first surface 213 and a second surface 214 facing each other. A characteristic of the glass substrate 21 is that the first region (first thickness 211) is thicker than the second region (second thickness 212). Consequently, at the junction of the first and second regions, excluding the core through-hole, the sidewall of one side of the first region in the thickness direction is exposed. Furthermore, the internal space 281 formed by the thickness difference between the first and second regions serves to house part or all of the cavity element.

[0064] A support portion 285 protruding into the interior space 281 of the cavity may be provided on one side in the thickness direction of the first region that exposes the side wall. At least a portion of the support portion 285 is connected to one side in the thickness direction of the first region, and another portion of the support portion 285 protrudes into the interior space 281 to secure the position of the inserted cavity element 40.

[0065] The glass substrate 21, in which the first and second regions of different thicknesses are adjacent, can be manufactured by stacking or combining glass substrates of different sizes. Considering durability and manufacturing efficiency, it is preferably manufactured in such a manner that the difference between the first and second thicknesses is removed from the glass substrate. In this case, a method for removing the difference between the first and second thicknesses can be employed, such as by applying a mechanical force to the weakened portion of the bonding strength through an etching process performed simultaneously with or separately from the process for forming the core through-hole described later, but the present invention is not limited thereto.

[0066] The support portion 285 can be formed simultaneously with the removal in the glass substrate 21. Specifically, after forming a defect in the glass substrate 21 by laser irradiation or the like, etching with a strong acid such as hydrofluoric acid to form a through hole or cavity can be performed. By adjusting the interval and intensity of laser irradiation, the support portion can be formed on the side of the cavity. However, the method for manufacturing the support portion is not limited to the above method.

[0067] The glass substrate 21 may have core through holes 23 penetrating the first surface and the second surface. The core through holes 23 may be formed in both the first region and the second region, and may be formed at desired intervals and patterns.

[0068] Traditionally, semiconductor device packaging substrates have used stacked silicon and organic substrates. Due to the properties of semiconductors, silicon substrates can generate parasitic elements when used in high-speed circuits, leading to relatively high power loss. Furthermore, organic substrates require larger areas to form more complex distribution patterns, but this is inconsistent with the trend toward ultra-miniaturized electronic devices. Forming complex distribution patterns within a predetermined size requires substantial pattern miniaturization, but this is limited by the properties of materials such as polymers used for organic substrates.

[0069] In this embodiment, as a method for solving the above-mentioned problems, a glass substrate 21 is used as a support for the core layer 22. In addition, a core through hole 23 formed through the glass substrate is also used, thereby providing a package substrate 20 with a shorter current length, a smaller size, a faster response, and lower loss characteristics.

[0070] The glass substrate 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0071] The thickness 211 (first thickness) of the glass substrate 21 measured in the first region can be 1,500 μm or less, or can be 300 μm to 1,200 μm, or can be 350 μm to 900 μm, or can be 350 μm to 700 μm. A thinner package substrate can be advantageous in terms of more efficient electrical signal transmission. However, since the package substrate also needs to serve as a support, a glass substrate 21 having the above-mentioned thickness is preferably used.

[0072] The thickness 212 (second thickness) of the second portion of the glass substrate 21 can be 80% or less of the first thickness, or can be 20% to 80%, or can be 30% to 70%. Specifically, the thickness 212 (second thickness) of the glass substrate 21 measured in the second region can be 1,000 μm or less, or can be 700 μm or less, or can be 500 μm or less. Furthermore, the second thickness 212 can be 100 μm to 500 μm, or can be 100 μm to 350 μm. Furthermore, the difference in thickness between the first region and the second region can be greater than the thickness of the cavity element. When a glass substrate having a second portion having such a thickness is used, a cavity structure can be formed more efficiently and stably.

[0073] Here, the thickness of the glass substrate refers to the thickness of the glass substrate itself minus the thickness of the conductive layer located on the glass substrate.

[0074] The difference between the second thickness of the glass substrate 21 and the first thickness can be smaller or larger than the thickness of the cavity element. If the difference is smaller than the thickness of the cavity element, the entire cavity element may be difficult to place within the internal space, and in this case, the structure of the package substrate may become more complex. Therefore, to simplify the structure of the package substrate, the difference is preferably larger than the thickness of the cavity element.

[0075] The height of the inner space may be 50 μm to 500 μm, or 150 μm to 450 μm, or 250 μm to 400 μm.

[0076] The core through hole 23 penetrates the glass substrate 21. The core through hole may be formed by removing a predetermined region of the glass substrate 21, and more specifically, may be formed by etching a plate glass using a physical and / or chemical method.

[0077] Specifically, when forming the core through hole 23 , a method of forming a defect (stain) on the surface of the glass substrate by laser or the like and then performing chemical etching or laser etching may be used, but the present invention is not limited thereto.

[0078] The core through hole 23 includes a first opening 233 connected to the first surface, a second opening 234 connected to the second surface, and a minimum inner diameter portion 235, which is the area with the narrowest inner diameter in the entire core through hole connecting the first opening and the second opening.

[0079] The diameter of the first opening, ie, the first opening diameter CV1, and the diameter of the second opening, ie, the second opening diameter CV2, may be substantially different, or the first opening diameter and the second opening diameter may be substantially the same.

[0080] In the latter case of having substantially the same diameter, the shape of the core through hole 23 as viewed from the cross section is substantially quadrilateral, and may be a core through hole having an overall cylindrical shape, or may be a core through hole having an overall barrel shape with the inner diameter of the core through hole slightly narrowing in the center portion based on the thickness of the glass substrate (see Figure 7B ).

[0081] In the case of the former having substantially different diameters, the core through hole may be a through hole having a substantially trapezoidal truncated cone cross section (see FIG. Figure 7A ).

[0082] The first opening diameter CV1 and the second opening diameter CV2 may each be 150 μm or less, or may be 40 μm to 200 μm, or may be 70 μm to 120 μm.

[0083] The minimum inner diameter portion may be located at the first opening or the second opening, in which case the core through hole may be a cylindrical or (trimmed) triangular pyramidal core through hole. In this case, the diameter CV3 of the minimum inner diameter portion corresponds to the smaller diameter of the first opening or the second opening.

[0084] The minimum inner diameter portion may be located between the first opening and the second opening. In this case, the core through hole may be a barrel-shaped core through hole. In this case, the diameter CV3 of the minimum inner diameter portion may be smaller than the larger diameter of the first opening or the second opening.

[0085] When the core through-hole 23 has a narrowed region at least partially, the diameter CV3 of the narrowed minimum inner diameter portion can be 50% to 99% of the larger of the first opening diameter CV1 and the second opening diameter CV2, or 70% to 95%. When the inner diameter is narrowed within the above range, a conductive layer and the like can be formed more smoothly.

[0086] Specifically, the average diameter of the minimum inner diameter portion may be 50 μm to 95 μm.

[0087] The minimum inner diameter portion may satisfy the following condition of Formula 1.

[0088] [Formula 1]

[0089] 0.83×D 90 ≤D 50 ≤1.25×D 10

[0090] In the above formula 1, D 50 D is the value corresponding to 50% of the diameter distribution in the smallest inner diameter part. 90D is the value corresponding to 90% of the diameter distribution at the minimum inner diameter part. 10 This is a value corresponding to 10% in the diameter distribution at the minimum inner diameter portion.

[0091] The average diameter of the minimum inner diameter portion may be 55 μm to 85 μm, or 60 μm to 70 μm.

[0092] More specifically, the minimum inner diameter portion may satisfy the following condition of Formula 1-1.

[0093] [Formula 1-1]

[0094] 0.88×D 90 ≤D 50 ≤1.18×D 10

[0095] In the above formula 1-1, D 50 D is the value corresponding to 50% of the diameter distribution in the smallest inner diameter part. 90 D is the value corresponding to 90% of the diameter distribution at the minimum inner diameter part. 10 This is a value corresponding to 10% in the diameter distribution at the minimum inner diameter portion.

[0096] Specifically, the average diameter of the target openings, which is the larger diameter between the first opening diameter and the second opening diameter, may be 70 μm to 120 μm.

[0097] Specifically, the opening having the larger diameter between the first opening diameter and the second opening diameter may satisfy the following condition of Formula 2.

[0098] [Formula 2]

[0099] 0.9×D 90 ≤D 50 ≤1.1×D 10

[0100] In the above formula 2, D 50 D is the value corresponding to 50% of the diameter distribution of the target opening. 90 D is the value corresponding to 90% of the diameter distribution of the target opening. 10 This is a value corresponding to 10% in the diameter distribution of the target openings.

[0101] Specifically, the average diameter of the openings, which is the larger of the first opening diameter and the second opening diameter, may be 80 μm to 105 μm.

[0102] Specifically, the opening that is the larger of the first opening diameter and the second opening diameter may satisfy the condition of the following formula 2-1.

[0103] [Formula 2-1]

[0104] 0.92×D 90 ≤D 50 ≤1.08×D 10

[0105] In the above formula 2-1, D 50 D is the value corresponding to 50% of the diameter distribution of the target opening. 90 D is the value corresponding to 90% of the diameter distribution of the target opening. 10 This is a value corresponding to 10% in the diameter distribution of the target openings.

[0106] In the core through hole, the average diameter of the target opening, which is the larger of the diameter of the opening in contact with the first surface, i.e., the first opening diameter, and the diameter of the opening in contact with the second surface, i.e., the second opening diameter, may be greater than the value D corresponding to 50% of the diameter distribution of the target openings. 50 Larger value.

[0107] As for the diameter distribution described above, the prepared sample was divided into 9 areas (3×3), and samples were taken from 5 areas: upper left, lower left, center, upper right and lower right. The sample was cut and the cross section was observed under a microscope to measure the diameter, and the above diameter distribution was evaluated based on this diameter.

[0108] When the total length of the core through hole is defined as 100%, the minimum inner diameter portion can be located between 40% and 60% of the reference, or between 45% and 55% of the reference, based on the first opening. As described above, when the minimum inner diameter portion is located at the above position based on the total length of the core through hole, the conductive layer design and conductive layer formation process of the package substrate can be more easily implemented.

[0109] The thickness of the conductive layer measured at the larger diameter of the first opening diameter CV1 and the second opening diameter CV2 may be equal to or greater than the thickness of the conductive layer formed at the portion having the smallest inner diameter in the core through hole and the diameter CV3 of the smallest inner diameter portion.

[0110] Based on the unit area (1 cm×1 cm) of the glass substrate 21, 100 to 3000 core through holes 23 may be provided, or 100 to 2500 core through holes 23 may be provided, or 225 to 1024 core through holes 23 may be provided. When the above spacing conditions are met, it is more conducive to forming a conductive layer, etc., and the performance of the package substrate can be improved.

[0111] The core through holes 23 may be provided at a pitch of 1.2 mm or less, or at a pitch of 0.12 mm to 1.2 mm, or at a pitch of 0.3 mm to 0.9 mm on the glass substrate 21. In this case, it is advantageous to form a conductive layer, etc. while maintaining the mechanical properties of the glass substrate at a predetermined level or higher.

[0112] In the above-mentioned glass substrate 21, stress is measured on a blank line which is a straight line connecting positions where the above-mentioned core through hole 23 is not formed on the first surface 213 of the above-mentioned glass substrate 21, and stress is measured on a through-hole line which is a straight line connecting positions where the above-mentioned core through hole 23 is formed. Let P be the stress difference value measured on the same glass substrate, then the stress difference value P is a value based on the following formula (1), and the above-mentioned glass substrate 21 can satisfy the condition that the stress difference value P is less than 1.5 MPa.

[0113] Formula (1) P = Vp - Np

[0114] In the formula (1), Vp is the difference between the maximum and minimum stress values measured on the through-hole line, and Np is the difference between the maximum and minimum stress values measured on the blank line.

[0115] The P value may be 1.35 MPa or less, 1.2 MPa or less, or 1.1 MPa or less, or 0.01 MPa or more, or 0.1 MPa or more.

[0116] When the glass substrate having the core through hole formed therein and having the stress difference value P within the above range is applied to a semiconductor package substrate, a package substrate having more stable mechanical and physical properties can be manufactured.

[0117] The Vp value may be 2.5 MPa or less, or 2.3 MPa or less, 2.0 MPa or less, or 1.8 MPa or less, or 0.2 MPa or more, or 0.4 MPa or more.

[0118] When the difference Vp between the maximum and minimum stress values measured on the through-hole line is within the above range, a package substrate having more stable mechanical and physical properties can be manufactured when the glass substrate having the core through-hole formed therein is used as a semiconductor package substrate.

[0119] The Np value may be 1.0 MPa or less, 0.9 MPa or less, or 0.8 MPa or less, or 0.1 MPa or more, or 0.2 MPa or more.

[0120] When the difference Np between the maximum and minimum stress values measured on the blank line is within the above range, a semiconductor package substrate having more stable mechanical properties can be manufactured when the glass substrate having the core through hole is used as a semiconductor package substrate.

[0121] Let K be the stress difference ratio measured on the same surface of the same glass substrate. The stress difference ratio K is a value based on the following formula (2). The condition that the stress difference ratio K is 6 or less can be satisfied on the glass substrate.

[0122] Formula (2): K = Lp / La

[0123] In formula (2), the above-mentioned Lp is the difference between the maximum and minimum values of the stress measured on the object line selected from the blank line as a straight line connecting the positions where the core through hole is not formed or the through-hole line as a straight line connecting the positions where the core through hole is formed, and the above-mentioned La is the average value of the stress measured on the above-mentioned object line.

[0124] Specifically, the K value may be 5 or less, 4.5 or less, or 4 or less. When the K value is within this range, when the glass substrate having the core through hole is applied to a semiconductor package substrate, a package substrate having more stable mechanical and physical properties can be manufactured.

[0125] The stress difference ratio K is measured on the blank line and may have a value of 2 or less. Specifically, the stress difference ratio Kn of the blank line may be 1.8 or less, or greater than 0.3, or greater than 0.5.

[0126] The stress difference ratio K is measured on the through-hole line and may have a value of 6 or less, or a value of 5 or less. The stress difference ratio Kv of the through-hole line may be 4.5 or less, or 3 or less. Furthermore, the stress difference ratio Kv of the through-hole line may be 0.5 or more, or 1.0 or more, or 1.5 or more.

[0127] When the glass substrate having the stress difference ratio K is applied to a semiconductor package substrate, a package substrate having more stable mechanical and physical properties can be manufactured.

[0128] The stress is analyzed by applying a birefringence two-dimensional evaluation device. Specifically, as a birefringence two-dimensional distribution evaluation device, the WPA-200 device of NPM (Nippon Pulse Korea Co., LTD) can be applied. Specifically, when the probe is used along Figure 2When reading data from a glass substrate using the stress measurement path shown in the figure, measured values such as birefringence are input to the device. Then, through a predetermined calculation process, the stress along the measurement path is expressed in pressure units (e.g., MPa). Stress can be measured by inputting the photoelastic coefficient and the thickness of the object being measured. In this case, a photoelastic coefficient of 2.4 is used.

[0129] Provide specific measurement examples.

[0130] The stress (Stress) of the blank lines and through-hole lines of four glass substrate samples was measured using the above-described settings by varying the position four or more times. The average values of the stresses were used to obtain the Vp, Np, and P values shown in Table 1 below. The glass substrate samples had an average opening diameter of 100 μm, an average minimum inner diameter of 75 μm, and an average thickness of approximately 300 μm.

[0131] Table 1

[0132]

[0133] The core distribution layer 24 includes a core distribution pattern 241, a conductive layer that electrically connects the first and second surfaces of the glass substrate via core vias, and a core insulation layer 223 surrounding the core distribution pattern. A conductive layer is formed within the core layer 22 through the core vias, serving as an electrical path across the glass substrate 21. This connects the upper and lower portions of the glass substrate over a relatively short distance, enabling faster electrical signal transmission and low loss.

[0134] The core distribution pattern 241 is a pattern that electrically connects the first surface 213 and the second surface 214 of the glass substrate via the core through-holes 23. Specifically, it includes a first surface distribution pattern 241a, which is a conductive layer located on at least a portion of the first surface 213; a second surface distribution pattern 241c, which is a conductive layer located on at least a portion of the second surface 214; and a core through-hole distribution pattern 241b, which is a conductive layer that electrically connects the first surface distribution pattern and the second surface distribution pattern via the core through-holes 23. For example, the conductive layer may be a copper plating layer, but the present invention is not limited thereto.

[0135] The glass substrate 21 serves as an intermediate or mediating function for connecting the semiconductor element of the semiconductor element portion 30 and the motherboard 10 to the upper and lower portions, respectively. The core through-hole 23 serves as a path for transmitting electrical signals therebetween, thereby achieving smooth signal transmission.

[0136] The thickness of the conductive layer measured at the larger diameter of the first opening diameter and the second opening diameter may be equal to or greater than the thickness of the conductive layer formed at a portion having the smallest inner diameter in the core through-hole.

[0137] The core distribution layer 24 is a conductive layer formed on a glass substrate. Its adhesion value according to the ASTM D3359 Cross Cut Adhesion Test (cross cut adhesion test) can meet 4B or higher, specifically, 5B or higher. Furthermore, the conductive layer serving as the core distribution layer 24 can have an adhesion to the glass substrate of 3 N / cm or higher, or 4.5 N / cm or higher. When this adhesion level is achieved, sufficient adhesion between the substrate and the conductive layer is achieved for use as a packaging substrate.

[0138] The upper layer 26 is located on the first surface 213 .

[0139] The upper layer 26 includes an upper distribution layer 25 and an upper connection layer 27 located on the upper distribution layer. The uppermost layer 26 may be protected by a cover layer 60 having an opening formed therein for direct contact of the connection electrodes of the semiconductor element.

[0140] The upper distribution layer 25 includes an upper insulating layer 253 on the first surface and an upper distribution pattern 251 which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24. The upper distribution pattern 251 is embedded in the upper insulating layer.

[0141] The upper insulating layer 253 may be any insulating layer suitable for use with a semiconductor element or a package substrate. For example, epoxy resin containing a filler may be used, but the present invention is not limited thereto.

[0142] The above-mentioned insulator layer can be formed by forming a coating and curing it, or can be formed by laminating an insulator film formed in an uncured or semi-cured state on the above-mentioned core layer and curing it. At this time, if a reduced pressure lamination method or the like is adopted, the above-mentioned insulator is embedded in the space inside the core through-hole, so that the process can be carried out efficiently. In addition, even if multiple insulator layers are stacked for application, it may be substantially difficult to distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 can be made of the same insulating material, in which case their boundaries may be substantially indistinguishable.

[0143] The upper distribution pattern 251 is a conductive layer located within the upper insulating layer 253 in a predetermined shape. It can be formed, for example, by a build-up layer method. Specifically, after forming an insulating layer, unnecessary portions of the insulating layer are removed, and then a conductive layer is formed by a method such as copper plating. Unnecessary portions of the conductive layer are selectively removed, and then an insulating layer is formed again on the conductive layer. Unnecessary portions are again removed, and then a conductive layer is formed by plating or other methods. This process is repeated to form the upper distribution pattern 251 having a conductive layer formed in a desired pattern in the vertical or horizontal direction.

[0144] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30 and is therefore formed to include a fine pattern in at least a portion thereof to facilitate smooth transmission of electrical signals between the core layer 22 and the semiconductor element portion 30 and to fully accommodate the required complex pattern. In this case, the fine pattern refers to a pattern having a width and spacing of less than 4 μm, or a pattern having a width and spacing of less than 3.5 μm, or a pattern having a width and spacing of less than 3 μm, or a pattern having a width and spacing of less than 2.5 μm, or a pattern having a width and spacing of 1 μm to 2.3 μm (the same applies to the following description of the fine pattern).

[0145] In order to form the upper distribution pattern 251 including a fine pattern, at least two or more methods are applied in this embodiment.

[0146] As one method, a glass substrate 21 is used as the encapsulation substrate. The glass substrate 21 can have a relatively flat surface with a surface roughness Ra of 10 angstroms or less, thereby minimizing the influence of the surface morphology of the support substrate on the formation of fine patterns.

[0147] Another method lies in the characteristics of the above-mentioned insulator. The above-mentioned insulator is usually applied with a filler component together with a resin, and the above-mentioned filler can be inorganic particles such as silica particles. When inorganic particles are applied as fillers to the insulator, the size of the inorganic particles may affect whether a fine pattern can be formed. In this embodiment, the insulator applicable is a granular filler with an average diameter of less than 150nm, specifically, including a granular filler with an average diameter of 1nm to 100nm. The above-mentioned characteristics keep the physical properties required by the insulator above the specified level, and minimize the influence of the insulator itself on the formation of a conductive layer with a width of microns, and also help to form a fine pattern with excellent adhesion on its surface with a fine surface morphology.

[0148] The upper connection layer 27 includes an upper connection pattern 272, at least a portion of which is electrically connected to the upper distribution pattern 251 and is located on the upper insulating layer 253; and an upper connection electrode 271, which electrically connects the semiconductor element portion 30 to the upper connection pattern 272. The upper connection pattern 272 may be located on one side of the upper insulating layer 253, or may be embedded in such a manner that at least a portion of the upper connection pattern is exposed in the upper insulating layer. For example, if the upper connection pattern is located on one side of the upper insulating layer, the upper insulating layer may be formed by plating or other methods. If the upper connection pattern is embedded in such a manner that a portion of the upper connection pattern is exposed in the upper insulating layer, after forming a copper plating layer or the like, a portion of the insulating layer or conductive layer may be removed by surface polishing, surface etching, or other methods.

[0149] Similar to the upper distribution pattern 251 described above, at least a portion of the upper connection pattern 272 may include a fine pattern. The upper connection pattern 272 including the fine pattern as described above allows for electrical connection of more components even in a narrow area, thereby facilitating smoother electrical signal connections between components or with the outside world and enabling a more integrated package.

[0150] The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 through a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball or the like.

[0151] The cavity portion 28 includes an inner space 281 , which is located above and / or below the second region. A cavity distribution layer 282 electrically connected to the core distribution layer and a cavity element 40 are disposed in the inner space 281 .

[0152] Specifically, the second region of the glass substrate is thinner than the first region, and the cavity element 40 can be disposed in the internal space 281 formed by the difference in thickness. Furthermore, the core through-holes and core distribution layer formed in the glass substrate function as electrical connection structures connecting the cavity element to external elements.

[0153] The cavity portion 28 is generally in the shape of a circle, triangle, quadrilateral, hexagon, octagon, or cross. The shape is not limited, but in the present invention, a quadrilateral is used as an example for description.

[0154] A side surface of the cavity portion 28 may further include a support portion 285 protruding toward the internal space.

[0155] When one side surface of the cavity portion 28 is referred to as a cavity first side surface 281a and the other side different from the cavity first side surface is referred to as a cavity second side surface 281b, the support portion 285 may be located at at least one of the cavity first side surface 281a and the cavity second side surface 281b.

[0156] Furthermore, the first side surface supporting portion 285 a and the second side surface supporting portion 285 b may be disposed on the adjacent first side surface 281 a and the second side surface 281 b of the cavity, respectively.

[0157] The first side support portion 285a and the second side support portion 285b support and fix the position of the cavity element 40. Compared with the case of using only one support portion, when two or more adjacent support portions are used, the position of the cavity element can be fixed more firmly.

[0158] The above-mentioned support part 285 can be an elastic component such as a spring. Specifically, the above-mentioned support part 285 can be a glass spring support part, which is formed of the same material as the above-mentioned glass substrate 21 and has elasticity in a direction opposite to the direction of the force applied to the above-mentioned support part by the above-mentioned cavity element 40.

[0159] The shape of the cavity element 40 can be cylindrical, rectangular or polygonal.

[0160] The angle at which the first cavity side surface 281a and the second cavity side surface 281b meet can be 45 to 135 degrees, or 75 to 105 degrees, or substantially 90 degrees. By providing side support portions on the first cavity side surface 281a and the second cavity side surface 281b, the cavity element 40 can be stably supported even if the angle at which the first cavity side surface 281a and the second cavity side surface 281b meet is any angle within the above range.

[0161] The angle between the first and second connecting lines (first connecting lines) where the curved first side support portion 285a meets the cavity element and the second connecting line (second connecting line) where the curved second side support portion 285b meets the cavity element (the junction between the first and second connecting lines) can be 45 to 135 degrees, or 75 to 105 degrees, or substantially 90 degrees. In this case, it is more convenient to fix the position of the cavity element when the shape of the cavity element is angular or when the shape of the cavity element is not angular.

[0162] When the cavity second side surface length C2 is set to 100%, the length to the maximum protrusion of the first side surface support portion 285a, i.e., the first side surface support portion length CS1, can be 15% or less, or 10% or less. Furthermore, when the cavity second side surface length C2 is set to 100%, the first side surface support portion length CS1 can be 1% or more, or 3% or more.

[0163] When the first side length C1 of the cavity is set to 100%, the length to the maximum protrusion of the second side support portion 285b, that is, the second side support portion length CS2, can be 15% or less, or 10% or less. Furthermore, when the first side length C1 of the cavity is set to 100%, the second side support portion length CS2 can be 1% or more, or 3% or more.

[0164] The support portion 285 may be directly connected to the glass substrate 21 to form an integral body. In this case, the support portion 285 may be formed by etching the glass substrate, thereby simplifying the manufacturing process of the glass substrate. The elastic support portion has substantially similar physical properties to the glass substrate, thus facilitating better control of the physical properties of the package substrate.

[0165] The support portion 285 only needs to protrude from the side of the cavity portion to support the inserted cavity element. Specifically, it can have an arc shape connecting one point to another on the side of the cavity portion, or it can have an arc shape connecting one end to the other end of the side. When the support portion has an arc shape, the support portion lengths CS1 and CS2 can be measured at the middle portion of the arc-shaped support portion.

[0166] The length from the most protruding position of the first side support portion 285a to the side surface of the cavity portion, and the length from the most protruding position of the second side support portion 285b to the side surface of the cavity portion, respectively, can be the same as the length of the corresponding position of the cavity element inserted into the cavity portion, or within 10% greater than the length of the corresponding position, preferably 0.1% to 8% greater than the length of the corresponding position. In this case, the support portion is more conducive to stably fixing the cavity element.

[0167] The cavity portion 28 may include a cavity distribution pattern 283 as a conductive layer electrically connecting the cavity element 40 and the core distribution layer 24. The cavity distribution pattern 283 may include a sidewall pattern 283a of the conductive layer located on the thickness direction surface of the glass substrate 21 at the boundary between the first region and the second region. However, the sidewall pattern is preferably formed on a surface other than the side surface where the support portion is formed.

[0168] In addition to the function of transmitting electrical signals, the side wall pattern 283 a may also function as a heat dissipation layer that transfers heat generated by the cavity components and the like in the cavity portion 28 to the outside.

[0169] Specifically, the cavity distribution layer 282 may include: a cavity distribution pattern 283, which serves as a conductive layer electrically connected to the cavity element 40 and the core distribution layer, at least a portion of which is located in the internal space; and / or a cavity insulation layer 284, which serves as an insulation layer surrounding the sidewall pattern 283a.

[0170] The cavity allocation pattern may be formed on the package substrate, or may be provided in the form of a terminal such as the electrode 42 (connection electrode) of the cavity element 40 .

[0171] The cavity element 40 may include a transistor. If a device such as a transistor is used as the cavity element 40 to convert the electrical signal between the motherboard and the semiconductor device to an appropriate level, and the transistor is used as a path of the package substrate 20, a semiconductor device 100 with higher efficiency and higher speed can be provided.

[0172] The cavity element 40 can be formed by inserting a passive component such as a capacitor alone, or it can be formed by being embedded between insulator layers (cavity element insulating layer 46) so that the electrodes of a component group including multiple passive components are exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the package substrate can be improved more smoothly, and the insulating layer can be more effectively and reliably provided in the space between the complex components.

[0173] Furthermore, the second-region core via 232, which interfaces with the electrodes of the aforementioned cavity element 40, can have a core distribution pattern formed as a filled via 283c. For example, the core via distribution pattern 241b, which serves as the core distribution pattern formed on the first-region core via 231, can have an interior filled with a core insulating layer, forming a space when viewed from the side of a conductive layer such as a metal layer. In contrast, the core via connected to the aforementioned cavity element 40 can have a filled via 283c with an interior filled with a conductive layer. In this case, power transmission in the cavity element, such as a capacitor, can be smoother, and the characteristics of the package substrate can be further improved.

[0174] Specifically, the cavity element 40 may be provided in the cavity portion 28 located below the second region 222. Furthermore, the cavity element may be electrically connected to the motherboard 10 directly or via a lower layer via a connection electrode formed thereunder.

[0175] Specifically, the cavity element 40 may be provided in the cavity portion 28 located above the second region 222. Furthermore, the cavity element may be electrically connected to the semiconductor element portion 30 directly or via an upper layer via a connection electrode formed thereon.

[0176] As described above, when the cavity portion is arranged above or below the second region, at least one of the connection electrodes present on both sides of the cavity element can be directly connected to the upper layer or lower layer of the glass substrate, or directly connected to the semiconductor element or motherboard, thereby providing a semiconductor device with a simpler structure.

[0177] The heat dissipation portion H may be located on a surface where the first region 221 of the glass substrate and the inner space 281 of the cavity portion meet.

[0178] The heat dissipation portion H may be located between the first region 221 and the second region 222 of the glass substrate, and may be located between the first region 221 of the glass substrate and the inner space 281 of the cavity.

[0179] At least a portion of the heat dissipation portion H may be connected to the core distribution layer 24. Specifically, when the inner space 281 is located above the second region, the heat dissipation portion H may be connected to at least a portion of the first surface distribution pattern 241a of the second region. Specifically, when the inner space 281 is located below the second region, the heat dissipation portion H may be connected to at least a portion of the second surface core pattern 241b of the second region.

[0180] The heat dissipation portion H can transfer the heat generated in the cavity portion 28 to the outside of the package substrate. Furthermore, the heat dissipation portion H connected to the core pattern layer can be connected to the core distribution layer or to the conductive layer, heat dissipation layer, etc. of the upper and / or lower layers, thereby dissipating the heat generated by the connected components, etc. to the outside of the semiconductor package.

[0181] The heat dissipation portion H and the cavity distribution layer 282 may be electrically insulated from each other by a cavity insulation layer 284 which is an insulation layer surrounding the cavity distribution layer.

[0182] The heat dissipation portion may be formed from a separate heat dissipation material or a metal layer having both electrical conductivity and heat dissipation properties. In this case, insulation treatment is required except for predetermined areas to ensure connection with the distribution layer, particularly with the cavity distribution layer that is likely to be adjacent. This insulation treatment can be performed similarly to the method for forming the insulation layer described above.

[0183] As described above, the cavity portion 28 may include a cavity distribution pattern 283 as a conductive layer electrically connecting the cavity element 40 and the core distribution layer 24. The cavity distribution pattern 283 may include a sidewall pattern (not shown). The sidewall pattern is a conductive layer located on the thickness-direction surface of the glass substrate 21 at the boundary between the first region and the second region. The sidewall pattern may function as the heat sink H. In particular, when the sidewall pattern is a conductive layer having relatively high thermal conductivity, it may function as both a sidewall pattern and a heat sink.

[0184] The heat dissipation portion H may have a thermal conductivity of 300 W / mK to 450 W / mK.

[0185] The heat dissipation portion H may be formed of the same material as the conductive layer.

[0186] When the conductive layer is formed, the heat dissipation portion H may be formed together.

[0187] The heat dissipation portion H may be a conductive metal layer having a thickness of 4 μm or more.

[0188] The heat dissipation portion H is a thermally conductive layer formed on a glass substrate. Its adhesion value according to the ASTM D3359 Cross Cut Adhesion Test (cross-cut adhesion test) can meet 4B or higher, specifically, 5B or higher. Furthermore, the heat dissipation portion H can have an adhesion to the glass substrate of 3 N / cm or higher, or 4.5 N / cm or higher. When these adhesion levels are met, sufficient adhesion between the substrate and the heat dissipation portion exists for use as a packaging substrate.

[0189] The package substrate 20 may further include a lower layer 29 located below the core layer 22 .

[0190] The lower layer 29 may include a lower distribution layer 291 electrically connected to the core distribution layer and a lower connection layer 292 providing a lower connection electrode 292a connected to an external motherboard.

[0191] Specifically, the cavity portion 28 acts as a channel for transmitting electrical signals and a channel for heat transfer through the side wall pattern 283a as a conductive layer. The package substrate needs to have a heat dissipation function that releases heat generated inside the package or generated from external components and transferred to the package substrate to the outside. When the side wall surface of the cavity portion is a conductive layer formed of a material with excellent thermal conductivity such as copper or other metals, both heat dissipation and electrical signal transmission can be achieved at the same time. In addition, since the side wall pattern can be formed together in the process of forming the core distribution pattern, the efficiency of the manufacturing process is also excellent.

[0192] The package substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution layer, namely the second surface distribution pattern 241c, located on at least a portion of the second surface 214 of the core layer 22. The motherboard 10 can be electrically connected via board connection portions such as solder balls. Furthermore, the second surface distribution pattern 241c can be connected to the motherboard 10 via a lower layer 29 located below the core layer 22.

[0193] The lower layer 29 includes a lower distribution layer 291 and a lower connection layer 292 .

[0194] The lower distribution layer 291 includes: i) a lower insulating layer 291b, at least a portion of which is connected to the above-mentioned second surface 214; and ii) a lower distribution pattern 291a, embedded (buried) in the above-mentioned lower insulating layer, having a predetermined pattern, and at least a portion of the above-mentioned lower distribution pattern 291a is electrically connected to the above-mentioned core distribution layer.

[0195] The lower connection layer 292 may also include: i) a lower connection electrode 292a, electrically connected to the above-mentioned lower connection pattern; and ii) a lower connection pattern 292b, at least a portion of which is electrically connected to the above-mentioned lower distribution pattern, and at least a portion of the lower connection pattern 292b is exposed on one side of the above-mentioned lower insulating layer.

[0196] The lower connection pattern 292 b is connected to the motherboard 10 . Unlike the upper connection pattern 272 , the lower connection pattern 292 b may be formed as a non-fine pattern having a width greater than that of a fine pattern to more effectively transmit electrical signals.

[0197] One of the features of the present invention is that, except for the glass substrate 21 , substantially no additional substrate is used in the package substrate 20 located between the semiconductor device portion 30 and the motherboard 10 .

[0198] Conventionally, an interposer and an organic substrate were stacked together to connect the component and the motherboard. This multi-stage approach is adopted for at least two reasons: one is the dimensional issues that arise when directly bonding the component's fine pattern to the motherboard, and another is the potential for wiring damage during the bonding process or while the semiconductor device is operating due to differences in thermal expansion coefficients. In this embodiment, a glass substrate with a thermal expansion coefficient similar to that of the semiconductor element is used, and a fine pattern with dimensions sufficiently fine for component mounting is formed on the first surface and upper layers of the glass substrate, thereby resolving these issues.

[0199] In this embodiment, when the distance from the inner diameter surface of the core through-hole 23 to the surface of the core distribution pattern 241 is defined as the overall distance, the thickness of the conductive layer constituting the core distribution pattern 241 can be 90% or greater, 93% to 100%, or 95% to 100%. Furthermore, when the distance from the inner diameter surface of the core through-hole 23 to the surface of the core distribution pattern 241 is defined as the overall distance, the thickness of the conductive layer constituting the core distribution pattern 241 can be 97% to 100%, or 96% to 100%.

[0200] The distance between the surface of the core through hole pattern close to the inner diameter surface of the core through hole and the inner diameter surface of the core through hole can be 1 μm or less, and an adhesive layer having a thickness of more than 1 μm is not substantially formed between the inner diameter surface and the conductive layer.

[0201] Specifically, when the distance from the inner diameter surface of the above-mentioned core through hole 23 to the surface of the above-mentioned core distribution pattern 241 in the larger diameter opening of the first opening diameter CV1 and the second opening diameter CV2 is defined as 100% as a whole, the thickness of the above-mentioned conductive layer can be more than 90%, or can be 93% to 100%, or can be 95% to 100%, or can be 98% to 99.9%.

[0202] Specifically, at the position of the diameter CV3 of the minimum inner diameter portion, when the distance from the inner diameter surface of the above-mentioned core through hole 23 to the surface of the above-mentioned core distribution pattern 241 is defined as 100% as a whole, the thickness of the above-mentioned conductive layer can be more than 90%, or can be 93% to 100%, or can be 95% to 100%, or can be 95.5% to 99%.

[0203] As described above, when the core distribution pattern 241 is formed in a manner close to the inner diameter surface of the above-mentioned core through hole 23, and is essentially formed directly on the above-mentioned inner diameter surface, by further simplifying the processing process, not only can the process efficiency be improved, but also, compared with the size of the core through hole, the core through hole pattern as the conductive layer can be thicker, thereby further improving the space efficiency and further improving the electrical characteristics of the packaging substrate within a predetermined space.

[0204] In this embodiment, the thickness of the thin conductive layer in the conductive layers of the core distribution layer 24 may be equal to or greater than the thickness Tus of the thin conductive layer in the conductive layers of the upper layer 26. When the thickness of the thin conductive layer in the conductive layers of the core distribution layer 24 is equal to or greater than the thickness of the thin conductive layer in the conductive layers of the upper layer 26 as described above, electrical signals can be more efficiently transmitted between the component and the motherboard.

[0205] The thickness of the conductive layer at the minimum inner diameter of the core through-hole 23 may be equal to or greater than the thickness of the thin conductive layer in the conductive layer of the upper layer 26. When the thickness of the conductive layer at the minimum inner diameter of the core through-hole is equal to or greater than the thickness of the thin conductive layer in the conductive layer of the upper layer, electrical signals can be more efficiently transmitted between the component and the motherboard.

[0206] In this embodiment, the average thickness Tcv of the core distribution pattern 241 can be 0.7 to 12 times, or 1.0 to 10 times, the thickness Tus of the thinnest portion of the upper connection pattern 272. Furthermore, the core distribution pattern 241 can have a thickness Tcv of 1.1 to 8 times, 1.1 to 6 times, or 1.1 to 3 times the thickness Tus of the thinnest portion of the upper connection pattern 272. The core distribution pattern 241 having such a thickness ratio can more efficiently connect electrical signals from highly integrated components to a motherboard.

[0207] As shown in the figure, the core distribution pattern 241 can be formed by forming a conductive layer with a predetermined thickness on the inner diameter of the core through-hole and filling the remaining portion with an insulating layer. If necessary, the space in the core through-hole can be filled with the conductive layer without any excess space. When the space in the core through-hole is filled with the conductive layer as described above, the width of the core through-hole pattern is the distance from the side of the core through-hole pattern close to the inner diameter surface to the center of the conductive layer (the same applies hereinafter).

[0208] In this embodiment, the thick thickness of the second-surface distribution pattern 241c can have a wiring thickness Tsc of 0.7 to 20 times, or 0.7 to 15 times, the thin thickness Tus of the upper connection pattern 272. Furthermore, the second-surface distribution pattern 241c can have a wiring thickness Tsc of 1 to 12 times, or 1.1 to 5 times, the thin thickness Tus of the upper connection pattern 272. When the second-surface distribution pattern 241c has such a wiring thickness, the process of connecting electrical signals from highly integrated components to a motherboard can be more efficient.

[0209] In this embodiment, at least a portion of the lower connection pattern 292b may have a thickness Tds of 0.7 to 30 times, 1 to 25 times, or 1.5 to 20 times the thickness Tus of the upper connection pattern 272. When the lower connection electrode 292a having such a ratio is used, the process of connecting electrical signals from highly integrated components to the motherboard can be more efficiently achieved.

[0210] The semiconductor device 100 has a relatively thin package substrate 20, which can reduce the overall thickness of the semiconductor device and, by applying fine patterns, can arrange the intended electrical connection pattern even in a narrower area. Specifically, the thickness of the package substrate 20 can be 2000 μm or less, 1800 μm or less, or 1500 μm. Furthermore, the thickness of the package substrate 20 can be 350 μm or more, or can be 550 μm or more. Through the features described above, even with a relatively thin thickness, the package substrate can stably connect the components and the motherboard electrically and structurally, and can further contribute to the miniaturization and thin filmization of semiconductor devices.

[0211] The method for preparing a packaging substrate of the present embodiment includes the following steps to prepare the packaging substrate as described above: a preparation step of forming defects at predetermined positions on the first surface and the second surface of a glass substrate; an etching step of applying an etching liquid to the glass substrate on which the defects are formed to prepare a glass substrate having a core through-hole; a core layer preparation step of forming a core distribution layer as a conductive layer by plating the surface of the glass substrate having the core through-hole formed to prepare a core layer; and an upper layer preparation step of forming an upper distribution layer as a conductive layer surrounded by an insulating layer on one side of the core layer.

[0212] The core layer preparation step may include: a pretreatment process of forming an organic-inorganic composite primer layer including nanoparticles having an amine group on the surface of the glass substrate having the core through-hole formed thereon to prepare a pretreated glass substrate; and a plating process of plating a metal layer on the pretreated glass substrate.

[0213] The core layer preparation step may include: a pretreatment process of preparing a pretreated glass substrate by forming a metal-containing primer layer on the surface of the glass substrate having the core through hole formed thereon by sputtering; and a plating process of plating a metal layer on the pretreated glass substrate.

[0214] An insulating layer forming step may be further included between the core layer preparing step and the upper layer preparing step.

[0215] The insulating layer forming step may be a step of providing an insulating film on the core layer and then performing reduced pressure lamination to form the core insulating layer.

[0216] The method of preparing the package substrate will be described in more detail.

[0217] 1) Preparation step (glass defect formation process): prepare a glass substrate having a flat first surface and a second surface, and form a defect (groove) at a predetermined position on the glass surface in order to form a core through hole. The above-mentioned glass can be a glass substrate suitable for a substrate of an electronic device, for example, it can be an alkali-free glass substrate, a borosilicate glass, etc., but the present invention is not limited to this. As a commercial product, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. At this time, a glass substrate having a cavity portion formed by removing a portion of the glass substrate can be used, or a glass substrate having a cavity portion by bonding a flat glass substrate can be used, or the defects described below are formed in the cavity portion on the flat glass substrate to simultaneously prepare the core through hole and the cavity portion. In addition, the support portion can be formed simultaneously with or independently of the preparation of the above-mentioned cavity portion. The above-mentioned defect (groove) can be formed by mechanical etching, laser irradiation, etc.

[0218] 2-1) Etching Step (Core Through-Hole Forming Step): A glass substrate having a defect (groove) formed therein is subjected to a physical or chemical etching process to form a core through-hole. During the etching process, the core through-hole is formed in the defective portion of the glass substrate while simultaneously etching the surface of the glass substrate. To prevent this etching of the glass surface, a masking film or the like may be applied. However, given the complexity of applying and removing the masking film, the defective glass substrate itself may be etched. In this case, the thickness of the glass substrate having the core through-hole may be slightly thinner than the original glass substrate.

[0219] Chemical etching can be performed by placing the grooved glass substrate in a bath containing hydrofluoric acid and / or nitric acid and applying ultrasonic treatment. In this case, the hydrofluoric acid concentration can be 0.5M or more, or 1.1M or more. The hydrofluoric acid concentration can be 3M or less, or 2M or less. The nitric acid concentration can be 0.5M or more, or 1M or more. The nitric acid concentration can be 2M or less. The ultrasonic treatment can be performed at a frequency of 40 Hz to 120 Hz, or 60 Hz to 100 Hz.

[0220] 2-2) Cavity Forming Step: The cavity is formed by removing a portion of the glass substrate simultaneously with or separately from the etching process. Specifically, a defect for forming the cavity is formed separately from the defect for forming the core through-hole. Thereafter, a glass substrate having a second region thinner than the first region is prepared by etching simultaneously with or separately from the etching for forming the core through-hole. Furthermore, by setting the laser beam so that the irradiated laser does not remove a portion of the interior of the cavity, the support portion can be formed simultaneously with the formation of the core through-hole and the cavity during the etching process.

[0221] 3-1) Core layer preparation step: forming a conductive layer on a glass substrate. Typically, the conductive layer may be a metal layer including copper metal, but the present invention is not limited thereto.

[0222] The glass surface (including the surface of the glass substrate and the surface of the core through-hole) and the copper metal surface have different properties, so the adhesion is poor. In this embodiment, the adhesion between the glass surface and the metal is improved by two methods: dry method and wet method.

[0223] The dry method utilizes sputtering, forming a seed layer on the glass surface and the inner diameter of the core through-hole by sputtering a metal. This seed layer can be formed by sputtering dissimilar metals such as titanium, chromium, and nickel along with copper. This is believed to improve glass-metal adhesion through the interaction of the glass surface morphology and the anchoring effect of the metal particles.

[0224] Wet method is the method for carrying out primer treatment, is by carrying out pre-treatment with the compound with the functional group such as amine etc. and forms the method for primer layer.According to required adhesion degree, after carrying out pre-treatment with silane coupling agent, can carry out primer treatment with compound or particle with amine functional group.As mentioned above, the support substrate of present embodiment needs to have the high performance of the degree that is enough to form fine pattern, even after primer treatment, also need to keep this state.Therefore, when this primer comprises nanoparticle, preferably being suitable for mean diameter is the nanoparticle below 150nm, for example, has the particle of amino group and is preferably used as nanoparticle.For example, above-mentioned primer layer can be formed by being suitable for the adhesion improver made by the CZ series etc. of MEC company.

[0225] In the seed layer / primer layer, the conductive layer can be selectively formed into a metal layer, with or without portions where a conductive layer is not required. Furthermore, the seed layer / primer layer 21c can be selectively treated to activate or deactivate portions of the conductive layer for metal plating, allowing subsequent steps to proceed. For example, the activation or deactivation treatment can be performed using light irradiation with a laser of a predetermined wavelength, or chemical treatment. The metal layer can be formed using a copper plating method suitable for semiconductor device manufacturing, but the present invention is not limited thereto.

[0226] During the metal plating, the thickness of the conductive layer formed can be controlled by adjusting various variables such as the concentration of the plating solution, the plating time, the type of applicable additives, etc.

[0227] When a portion of the core distribution layer is not needed, it can be removed, or the seed layer can be partially removed or inactivated before metal plating to form a conductive layer in a predetermined pattern, thereby forming an etched layer of the core distribution layer.

[0228] Simultaneously with the formation of the core distribution layer, a heat dissipation portion is formed by applying a conductive layer made of, for example, copper, which has excellent thermal conductivity. The heat dissipation portion can be formed separately from the core distribution layer, but the core distribution layer and the heat dissipation portion can also be formed simultaneously through a plating process, for example, to improve process efficiency.

[0229] During the process of forming the core distribution layer, it may be adjusted to form or not form an additional conductive layer on the support portion.

[0230] Furthermore, for more efficient power transmission, etc., at least a portion of the core through hole (second region core through hole 232) connected to the electrode of the above-mentioned cavity element can be made into a form having a filled through hole 283c. By performing a filled through hole forming step simultaneously with or separately from the above-mentioned plating forming step, the above-mentioned second region core through hole is filled with a metal such as copper that forms a conductive layer, thereby forming a filled through hole that can more efficiently transmit signals.

[0231] Alternatively, the above-mentioned cavity member may be inserted before the subsequent step of forming the insulating layer.

[0232] 3-2) Insulation Layer Formation Step: After forming the core distribution layer, which serves as the conductive layer, the core through-holes may be subjected to an insulation layer formation step in which the empty spaces are filled with an insulation layer. In this case, the insulation layer may be a thin film, for example, applied by a method such as vacuum lamination of a thin film. This vacuum lamination method allows the insulation layer to be fully embedded in the empty spaces within the core through-holes, forming a core insulation layer free of voids.

[0233] 4) Upper layer preparation step: This step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming an insulating layer or stacking insulating films. Simply put, it is preferred to stack insulating films. The stacking of insulating films can be performed by laminating insulating films and curing them. At this time, if a reduced pressure lamination method is adopted, the insulating resin can be fully embedded in the layer where no conductive layer is formed inside the core through hole, etc. At least a portion of the above-mentioned upper insulating layer is also in direct contact with the glass substrate, so a layer with sufficient adhesion is suitable. Specifically, the above-mentioned glass substrate and the above-mentioned upper insulating layer preferably have a characteristic of satisfying 4B or above in the adhesion test value according to ASTMD3359.

[0234] The upper distribution pattern can be formed by repeatedly forming the above-mentioned insulating layer, forming a conductive layer in a predetermined pattern, and etching unnecessary portions to form an etching layer of the conductive layer. The conductive layer is formed adjacent to the insulating layer, and then a plating process is performed. The blind holes can be formed by dry etching methods such as laser etching and plasma etching, or wet etching methods using a mask layer and an etching solution.

[0235] 5) Upper connection layer and cover layer formation step: The upper connection pattern and upper connection electrode can also be formed through a process similar to the process of forming the upper distribution layer. Specifically, they can be formed by forming an etching layer of the insulating layer on the insulating layer, forming a conductive layer thereon, and then forming an etching layer of the conductive layer. However, they can also be formed by selectively forming only the conductive layer without etching. The cover layer can be formed with an opening formed at a position corresponding to the upper connection electrode, so that the upper connection electrode is exposed and directly connected to the component connection part or terminal, etc.

[0236] 6) Lower connection layer and cover layer forming step: The lower distribution layer and / or lower connection layer may be formed by a method similar to the above-described upper connection layer and cover layer forming step, and the cover layer may be selectively formed.

[0237] As described above, although the preferred embodiments of the present invention have been described in detail, it should be understood that the scope of the present invention is not limited to the above embodiments, but various changes or modifications made by those skilled in the art using the basic concepts of the present invention defined in the claims fall within the scope of the present invention.

[0238] Description of Reference Numerals

[0239] 100: Semiconductor device 10: Motherboard

[0240] 30: Semiconductor element portion 32: First semiconductor element

[0241] 34: Second semiconductor element 36: Third semiconductor element

[0242] 20: Package substrate 22: Core layer

[0243] 223: core insulating layer 21, 21a: glass substrate

[0244] 213: First surface 214: Second surface

[0245] 23: Core through hole 233: First opening

[0246] 234: Second opening 235: Minimum inner diameter portion

[0247] 24: Core distribution layer 241: Core distribution pattern

[0248] 241a: First surface distribution pattern 241b: Core through hole distribution pattern

[0249] 241c: Second surface distribution pattern 26: Upper layer

[0250] 25: Upper distribution layer 251: Upper distribution pattern

[0251] 252: Blind hole 253: Upper insulation layer

[0252] 27: Upper connection layer 271: Upper connection electrode

[0253] 272: Upper connection pattern 28: Cavity

[0254] 281a: First side of the cavity 281b: Second side of the cavity

[0255] 282: Cavity distribution layer 283: Cavity distribution pattern

[0256] 283a: Sidewall pattern

[0257] 282b: Core cavity connection pattern or cavity element connection electrode

[0258] 283c: Filled via 284: Cavity insulation layer

[0259] 285: Support part 29: Lower layer

[0260] 291: Lower distribution layer 291a: Lower distribution pattern

[0261] 291b: Lower insulation layer 292: Lower connection layer

[0262] 292a: bottom connection electrode 292b: bottom connection pattern

[0263] 40: Cavity element 42: Cavity element electrode

[0264] 46: Cavity element insulation layer 50: Connecting part

[0265] 51: Component connection part 52: Board connection part

[0266] 60: Cover layer H: Heat dissipation part

Claims

1. A packaging substrate, characterized in that: comprising a core layer and an upper layer located on the core layer, The core layer includes a glass substrate and a core through hole, and the core through hole is provided in a plurality. The glass substrate includes a first surface and a second surface facing each other. The glass substrate includes a first region having a first thickness and a second region having a second thickness, wherein the second region is adjacent to the first region, and the second thickness is thinner than the first thickness. The core through hole penetrates the first region and the second region of the glass substrate in the thickness direction. The core layer includes a core distribution layer located on the surface of the glass substrate or the core through hole. At least a portion of the core distribution layer electrically connects the conductive layer on the first surface and the conductive layer on the second surface through the core through-hole. The upper layer includes a conductive layer located on the first surface and electrically connecting the core distribution layer and the external semiconductor element portion. The package substrate further includes a cavity portion located above or below the second region. The cavity portion includes an internal space for accommodating components for converting electrical signals between the motherboard and the semiconductor components. The cavity distribution layer and the cavity element electrically connected to the core distribution layer are located in the internal space. The cavity distribution layer includes a cavity distribution pattern for electrically connecting the cavity element and the core distribution layer. The cavity distribution pattern includes a sidewall pattern, and a boundary between the first region and the second region is located on a surface in a thickness direction of the glass substrate.

2. The packaging substrate according to claim 1, wherein: The cavity distribution layer further includes a cavity insulation layer, which is an insulation layer surrounding the cavity distribution pattern.

3. The packaging substrate according to claim 1, wherein: The cavity element includes a connecting electrode, The core through hole in the second region is in the form of a filled through hole, and the core through hole is in contact with the connection electrode of the cavity element.

4. The packaging substrate according to claim 1, wherein: The thermal conductivity of the sidewall pattern is 300 W / mK to 450 W / mK.

5. The packaging substrate according to claim 1, wherein: The side wall pattern and the glass substrate have an adhesive force of 3 N / cm or more.

6. The packaging substrate according to claim 1, wherein: The side wall pattern has a thickness of 4 μm or more.

7. The packaging substrate according to claim 1, wherein: The core through hole includes: a first opening connected to the first surface; The second opening is in contact with the second surface; and The minimum inner diameter portion is a region with the narrowest inner diameter in the entire core through hole connecting the first opening portion and the second opening portion.

8. The packaging substrate according to claim 7, wherein: The diameter of the first opening and the diameter of the second opening are respectively 40 μm to 200 μm.

9. A semiconductor device, characterized in that: include: a semiconductor element portion in which one or more semiconductor elements are located, a packaging substrate electrically connected to the semiconductor element, and a motherboard electrically connected to the package substrate, transmitting external electrical signals to the semiconductor element and connecting the semiconductor element to the external electrical signals; The package substrate is the package substrate according to claim 1.

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