Semiconductor device and method of forming the same

Abstract

Embodiments of the invention relate to semiconductor devices and methods of forming the same. A semiconductor device includes a substrate; and a cell region having a first side and a second side opposite with respect to a first direction, the cell region including active regions formed in the substrate extending in the first direction; a first plurality of the active regions having a first end aligned with respect to an imaginary first reference line in a second direction perpendicular to the first direction, the first side being parallel to and proximate to the first reference line; a second plurality of the active regions having a second end aligned with respect to an imaginary second reference line in the second direction, the second side being parallel to and proximate to the second reference line; and gate structures respectively located on first active regions and second active regions among the active regions; and wherein a first end of a selected gate structure among the gate structures is contiguous to an intermediate region located between the first active region and the second active region with respect to the second direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to solve problems in many different fields. Advances in semiconductor process technology nodes have gradually reduced component size and narrowed spacing, resulting in a gradual increase in transistor density. ICs are becoming smaller.

[0003] In the semiconductor device manufacturing environment, design rules are geometric constraints imposed on circuit board, semiconductor device, and IC designers to ensure their designs function correctly, reliably, and are manufactured with acceptable yields. Production design rules are developed by process engineers based on the relevant semiconductor process technology nodes. Electronic Design Automation (EDA) is used to ensure designers do not violate design rules; this is called a Design Rule Check (DRC). DRC is a step during the physical verification and approval process of a design, which also involves LVS (Landing and Schematic) checks, XOR (Logic) checks, Electrical Rule Checks (ERC), antenna checks (collecting charge from electromagnetic fields), etc. Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor device is provided, comprising: a substrate; and a cell region having a first side and a second side opposite to a first direction, the cell region including an active region formed in the substrate extending in the first direction; a first majority of the active region having a first end aligned with the first reference line relative to an imaginary first reference line in a second direction perpendicular to the first direction, the first side being parallel to and close to the first reference line; a second majority of the active region having a second end aligned with the second reference line relative to an imaginary second reference line in the second direction, the second side being parallel to and close to the second reference line; and a gate structure correspondingly located on the first active region and the second active region in the active region; and wherein, relative to the second direction, a first end of a selected gate structure in the gate structure is adjacent to an intermediate region located between the first active region and the second active region.

[0005] According to another aspect of the present invention, a semiconductor device is provided, comprising: a cell region including an active region extending in a first direction; the cell region being arranged such that the central reference line is located at the center of the cell region relative to the first direction, relative to an imaginary center reference line extending in a second direction perpendicular to the first direction; first end portions of two or more active regions extending a maximum distance from the center reference line to the first reference line in the first direction relative to an imaginary first reference line extending in the second direction, and a first edge of the cell region being parallel to and close to the first reference line; second end portions of two or more active regions extending a maximum distance from the center reference line to the second reference line relative to an imaginary second reference line extending in the second direction, and a second edge of the cell region being parallel to and close to the second reference line, the second edge being located on an opposite side of the cell region relative to the first edge; and a first active region and a second active region having corresponding major axes in the first direction, the major axes being collinear with the first direction, and the first active region and the second active region being separated by a first intermediate region.

[0006] According to one aspect of the present invention, a method for forming a semiconductor device is provided, the method comprising: forming an active region in a substrate, the active region extending correspondingly in a first direction, the forming of the active region comprising: forming a first majority of active regions having a first end aligned with the first reference line relative to an imaginary first reference line in a second direction perpendicular to the first direction, a first side of a cell region being parallel to and close to the first reference line, the cell region including the active region; forming a second majority of active regions having a second end aligned with the second reference line relative to an imaginary second reference line in the second direction, the second side of the cell region being parallel to and close to the second reference line; forming gate structures correspondingly located on the first active region and the second active region in the active region; and converting a selected gate structure in the gate structure into a corresponding isolation pseudo-gate structure such that no gate structure occupies the intermediate region between the first active region and the second active region. Attached Figure Description

[0007] One or more embodiments are shown in the accompanying drawings by way of example and not limitation, wherein elements having the same reference numerals denote the same elements throughout. Unless otherwise stated, the drawings are not drawn to scale.

[0008] Figure 1A-Figure 1B This is a corresponding block diagram of an integrated circuit (IC) according to some embodiments.

[0009] Figure 2A It is a layout diagram of a semiconductor device according to some embodiments.

[0010] Figure 2B It is a plan view of a semiconductor device according to some embodiments.

[0011] Figure 3A It is a layout diagram of a semiconductor device according to some embodiments.

[0012] Figure 3B It is a plan view of a semiconductor device according to some embodiments.

[0013] Figures 3C-3D According to some embodiments Figure 3B The corresponding cross-sectional view of the semiconductor device.

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E It is a plan view of a semiconductor device according to some embodiments.

[0015] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E It is a plan view of a semiconductor device according to some embodiments.

[0016] Figure 6A , Figure 6B and Figure 6C It is a plan view of a semiconductor device according to some embodiments.

[0017] Figure 7A and Figure 7B It is a plan view of a semiconductor device according to some embodiments.

[0018] Figure 8A and Figure 8B It is a plan view of a semiconductor device according to some embodiments.

[0019] Figure 9A and Figure 9B It is a plan view of a semiconductor device according to some embodiments.

[0020] Figure 10A and Figure 10B It is a plan view of a semiconductor device according to some embodiments.

[0021] Figure 11A and Figure 11B It is a plan view of a semiconductor device according to some embodiments.

[0022] Figure 12A and Figure 12B It is a plan view of a semiconductor device according to some embodiments.

[0023] Figure 13 It is a plan view of a semiconductor device according to some embodiments.

[0024] Figure 14 It is a plan view of a semiconductor device according to some embodiments.

[0025] Figure 15A , Figure 15B and Figure 15C It is a plan view of a semiconductor device according to some embodiments.

[0026] Figure 16A This is a flowchart of a method for generating a layout diagram according to some embodiments.

[0027] Figure 16B This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0028] Figure 17A and Figure 17B This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0029] Figure 18 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0030] Figure 19 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0031] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, operations, arrangements, etc., may be considered. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0032] Furthermore, for ease of description, spacing relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to include different orientations of the device during use or operation. Devices may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein can be interpreted accordingly. In some embodiments, the term “standard cell structure” refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from the library of standard cell structures and used as components in layout diagrams representing circuits.

[0033] In some embodiments, one or more semiconductor devices within an IC include a substrate and one or more cell regions. The cell regions have opposing first and second sides relative to a first direction (e.g., the X-axis). Each cell region includes an active region formed in the substrate, extending parallel to the X-axis. In some embodiments, a first majority of the active regions includes a first end aligned with a hypothetical first reference line in a vertical second direction (e.g., the Y-axis). In some embodiments, the first side is parallel to and close to the first reference line. In some embodiments, a second majority of the active regions includes a second end aligned with a hypothetical second reference line parallel to the Y-axis. In some embodiments, the second side is parallel to and close to the second reference line. Gate structures are correspondingly located on the first and second active regions of the active regions. The first and second active regions are separated by an intermediate region relative to the X-axis. Relative to the Y-axis, a first end of a selected gate structure is adjacent to the intermediate region between the first and second active regions. In some embodiments, each of the gate structures is not present in the intermediate region between the first and second active regions. In some embodiments, the intermediate region between the first and second active regions does not overlap with the gate structure.

[0034] In some embodiments, an isolation dummy gate (IDG) occupies the middle region. In some embodiments, the semiconductor device includes a low-leakage (LL) portion. In some embodiments, the semiconductor device includes a high-leakage (HL) portion. In some embodiments: a first active region is substantially located within the LL portion; and, relative to the Y-axis, the first active region is configured to have a height that contributes to current leakage below a predetermined threshold. In some embodiments: a second active region is substantially located within the high-leakage portion; and, relative to the Y-axis, the second active region is configured to have a height greater than that of the first active region that contributes to higher performance (e.g., switching speed at or above a predetermined threshold). In some embodiments, a second isolation dummy gate divides one or more first active regions into a first portion and a second portion. In some embodiments, a third isolation dummy gate separates one or more second active regions into a first portion and a second portion. An isolation dummy gate is a dielectric structure comprising one or more dielectric materials and used as an electrical isolation structure. Therefore, an isolation dummy gate is not a conductive structure and cannot be used as a gate electrode such as an active transistor.

[0035] According to another method, all active regions (ARs) within the substrate are rectangular and fully projected. According to other methods, active regions extending continuously from one side of a cell region to the other (e.g., from left to right) are considered fully projected. According to other methods, full projection of all ARs within a cell region wastes cell region space, for example, because there is only one active region on a given horizontal track (reference line) within the cell region, and therefore only one transistor on that given horizontal track. In contrast, in some embodiments, for a given horizontal track, one or more isolation dummy gates are used to divide what would otherwise be a single, fully projected active region according to other methods into multiple active regions on the same horizontal track within the cell region, and therefore into multiple transistors on the same given horizontal track within the cell region. Thus, in some embodiments, less cell region space is wasted compared to other methods, and therefore transistor density (e.g., the ratio of the number of transistors in a cell region to the area of ​​the cell region) is increased compared to other methods.

[0036] Figure 1A-Figure 1B This is a corresponding block diagram of IC 100 according to some embodiments.

[0037] IC 100 includes a semiconductor device 102 having a cell region 104. Cell region 104 is configured with cell portions 106 and 108. Cell portion 106 is a high-performance portion and therefore a high-leakage (HL) portion. Cell portion 108 is a low-leakage (LL) portion and therefore a low-performance portion. Figure 1A In the middle, HL part 106 is adjacent to LL part 108. Figure 1BIn this context, HL portion 106 is surrounded by LL portion 108. In some embodiments, relative to... Figure 1B Multiple instances of HL portion 106 are surrounded by LL portion 108. In some embodiments, one or more ARs within cell region 104 are not fully projected (see...). Figure 2A The FC pattern (where FC is an acronym for future conversion to isolation dummy gates) and the spacing between ARs relative to each other are varied relative to the X and Y axes. In some embodiments, one or more ARs within cell region 104 are split or separated by isolation dummy gates, which accordingly occupy the middle region, compared to other methods. In some embodiments, the width (relative to the X-axis) and height (relative to the Y-axis) of the ARs within cell region 104 are configured to vary based on desired performance or desired current leakage. In some embodiments, isolation dummy gates limit current leakage between adjacent ARs. In some embodiments, isolation dummy gates are configured to allow adjacent ARs to be placed closer to each other than previously allowed by design rules according to other methods. In some embodiments, cell region performance is increased by increasing AR size without sacrificing increased current leakage. In some embodiments, placing adjacent ARs between isolation dummy gates improves cell area ratio, as well as cell area efficiency, AR density, and semiconductor yield. In some embodiments, the configuration of isolation dummy gates for separated ARs within the cell region reduces the distance between ARs of different sizes and maintains design rule check (DRC) compliance.

[0038] IC 100 is referred to as a chip or microchip, and is a collection of electronic circuits or semiconductor devices (e.g., on a piece of semiconductor material, such as a wafer, chip, or substrate). Figures 3C-3D The substrate 314B is typically silicon or other suitable material, which is within the scope of this disclosure. IC 100 supports one or more metal-oxide-semiconductor field-effect transistors (MOSFETs), such as semiconductor device 102, integrated into the chip; however, other suitable transistors and electronic components are within the scope of this disclosure. IC 100 is electrically coupled to, incorporated into, or accommodates one or more semiconductor devices 102.

[0039] Semiconductor device 102 is an electronic component or group of electronic components configured to perform its function using the electronic properties of semiconductor materials (such as silicon, germanium, or gallium arsenide, as well as organic semiconductors or other suitable materials within the intended scope of this disclosure).

[0040] In some embodiments, cell region 104 is a single cell region. In some embodiments, a cell region in an EDA environment is an abstract representation of a component in a schematic diagram or layout of an electronic circuit in software. Cell-based design is a technique that helps designers analyze chip designs at varying levels of abstraction. For example, one designer may focus on logic functionality (high level) while another focuses on physical implementation (low level).

[0041] In some embodiments, the cell region 104 is such as along... Figure 1A The cell region 104 is a combination of two cell regions adjacent to each other along a vertical axis (such as HL portion 106 and LL portion 108). In some embodiments, cell region 104 is a combination of two cell regions adjacent to each other along a horizontal axis. In some embodiments, cell region 104 is a combination of four cell regions adjacent to each other along a vertical axis. In some embodiments, cell region 104 is a combination of four cell regions, wherein two cell regions are adjacent to each other along a horizontal axis and two other cell regions are adjacent to each other along a vertical axis. Other applicable cell region orientations are within the scope of this disclosure.

[0042] Each of the HL 106 and LL 108 portions includes one or more ARs, which are configured such that they are not fully projected. In some embodiments, one or more ARs within each of HL 106 and LL 108 are separated by one or more isolation dummy gates occupying a respective intermediate region. An isolation dummy gate is a dielectric structure comprising one or more dielectric materials and used as an electrical isolation structure. Therefore, an isolation dummy gate is not a conductive structure and therefore cannot be used as, for example, a gate electrode of an active transistor. In some embodiments, the isolation dummy gate is referred to as a dielectric gate structure. In some embodiments, the isolation dummy gate is an example of a structure included in a CPODE layout scheme. In some embodiments, CPODE is an acronym for continuous poly on diffusion edge. In some embodiments, CPODE is an acronym for continuous poly on oxide definition edge. In some embodiments, the isolation dummy gate is based on a gate structure as a precursor. In some embodiments, a dielectric gate is formed by first forming a gate structure (e.g., a dummy gate), sacrificing / removing (e.g., etching) the dummy gate to form a trench, (optionally) removing a portion of the substrate previously below the dummy gate to deepen the trench, and then filling the trench with one or more dielectric materials, such that the physical dimensions of the resulting electrically isolated structure (i.e., the isolated dummy gate) are similar to the dimensions of the sacrificed precursor (i.e., the gate structure or a combination of the gate structure and a portion of the substrate).

[0043] Cell region 104 is configured with an HL portion 106, which is configured for performance, such as improved switching speed. In some embodiments, the HL portion 106 includes substantially all cell area of ​​cell region 104. In some embodiments, the HL portion 106 includes half of cell region 104. In some embodiments, the HL portion 106 includes a single AR, multiple ARs, or other suitable HL portion 106 arrangements within the scope of this disclosure.

[0044] Cell region 104 is further configured with an LL portion 108, which is configured to exhibit low leakage current. In some embodiments, the LL portion 108 includes substantially all cell area of ​​cell region 104. In some embodiments, the LL portion 108 includes up to half of cell region 104. In some embodiments, the LL portion 108 includes one AR, multiple ARs, or other suitable LL portions 108 arranged within the scope of this disclosure.

[0045] In some embodiments, cell region 104 is configured with one or more HL portions 106 and one or more LL portions 108, with one or more HL cell portions 106 inserted into one or more LL portions 108. In some embodiments, the distance between HL portions 106 and LL portions 108 is less than 3δ, where δ is the distance between the centers of adjacent gate structures (also referred to as the contact polysilicon pitch CPP), and δ varies depending on the corresponding semiconductor process technology node. In some embodiments, the distance between HL portions 106 and LL portions 108 is less than 2δ. In some embodiments, the distance between HL portions 106 and LL portions 108 separated by isolation dummy gate material is 1δ. In some embodiments, the distance between HL portions 106 and LL portions 108 is approximately the width of the isolation dummy gate occupying the middle region. In some embodiments, placing HL portions 106 and LL portions 108 closer to each other improves cell area efficiency, AR density, and cell region yield.

[0046] Figure 2A This is a layout diagram 202A of a semiconductor device according to some embodiments.

[0047] For the purpose of discussing layout 202A, the shapes and patterns within layout 202A are discussed using reference numerals in the form 2XXA or 2XX_A. This corresponds to semiconductor device 202B ( Figure 2B The layout diagram 202A shows the shape and pattern structure in... Figure 2B The reference numbers in the form of 2XXB or 2XX_B are used for discussion.

[0048] because Figure 2A The FC pattern 224A (discussed below) generates the corresponding Figure 2B AR correspondence Figure 2B The internal isolation dummy gate is not fully projected (discussed below). Compared with other methods, Figure 2B One or more benefits of all AR incomplete projections include reduced cell area space waste, increased AR density, etc.

[0049] In some embodiments, layout diagram 202A is a layout diagram of a semiconductor device, such as semiconductor device 102. In some embodiments, layout diagram 202A is configured for manufacturing a semiconductor device included within an IC (e.g., IC 100), such as semiconductor device 202B. Figure 2B In some embodiments, cell region 204A is an example of cell region 104. In some embodiments, cell regions 204_AA, 204_AB, 204_AC, 204_AD, 204_AE, 204_AF, 204_AG, and 204_AH are in Figure 2A Within cell region 204A, and used for manufacturing semiconductor cells, such as those used in ICs (such as IC 100). Figure 2B The corresponding cell regions 204_BA, 204_BB, 204_BC, 204_BD, 204_BE, 204_BF, 204_BG, and 204_BH in cell region 204B of semiconductor device 202B. In some embodiments, HL portion 206A is an example of HL portion 106. In some embodiments, HL portion 206A is configured for manufacturing HL portions, such as HL portion 206B ( Figure 2B ) and HL portion 106. In some embodiments, LL portion 208A is an example of LL portion 108. In some embodiments, LL portion 208A is configured for manufacturing a similar unit portion 208B ( Figure 2B ) and the LL part of 108.

[0050] Layout diagram 202A includes cell region 204A, which is a single cell region. In some embodiments, cell region 204A is considered as a larger cell region that includes smaller cell regions (such as cell regions 204_AA, 204_AB, 204_AC, 204_AD, 204_AE, 204_AF, 204_AG, and 204_AH).

[0051] In some embodiments, cell region 204A is considered a larger cell region comprising two medium-sized cell regions separated relative to the X-axis by an imaginary center vertical reference line 219A. In some embodiments, each of the two medium-sized cell regions is considered a “larger” cell region comprising the smaller cell region. For example, the intermediate cell region to the left of reference line 219A comprises cell regions 204_AA, 204_AB, 204_AC, and 204_AD, and the intermediate cell region to the right of reference line 219A comprises cell regions 204_AE, 204_AF, 204_AG, and 204_AH.

[0052] In some embodiments, cell region 204A is considered a larger cell region comprising two medium-sized cell regions separated relative to the Y-axis by an imaginary central horizontal reference line 201B. In some embodiments, each of the two medium-sized cell regions is considered a “larger” cell region comprising the smaller cell region. For example, the medium-sized cell regions above reference line 201B include cell regions 204_AA, 204_AB, 204_AE, and 204_AF, and the medium-sized cell regions below reference line 201B include cell regions 204_AC, 204_AD, 204_AG, and 204_AH.

[0053] In some embodiments, cell region 204A is considered a larger cell region comprising four medium-sized cell regions separated relative to the Y-axis by imaginary horizontal reference lines 201A, 201B, and 201C. In some embodiments, each of the four medium cell regions is considered a “larger” cell region that includes smaller cell regions; for example: the medium cell region above reference line 201A includes cell regions 204_AA and 204_AE; the intermediate cell region between reference lines 201A and 201B includes cell regions 204_AB and 204_AF; the intermediate cell region between reference lines 201B and 201C includes cell regions 204_AC and 204_AG; and the medium cell region below reference line 201C includes cell regions 204_AD and 204_AH.

[0054] In some embodiments, cell region 204A is considered a larger cell region comprising four medium-sized cell regions separated relative to the X-axis by reference line 219A and relative to the Y-axis by reference line 201B. In some embodiments, each of the four medium-sized cell regions is considered a “larger” cell region that includes smaller cell regions; for example: the medium-sized cell region to the left of reference line 219A and above reference line 201B includes cell regions 204_AA and 204_AB; the middle cell region to the left of reference line 219A and below reference line 201B includes cell regions 204_AC and 204_AD; the middle cell region to the right of reference line 219A and above reference line 201B includes cell regions 204_AE and 204_AF; and the middle cell region to the right of reference line 219A and below reference line 201B includes cell regions 204_AG and 204_AH. Other applicable cell region orientations are within the scope of this disclosure.

[0055] Layout 202A also includes an n-well pattern 212A within the substrate. In some embodiments, the n-well pattern 212A and the substrate are in the first layer 340 ( Figures 3C-3D (e.g., within substrate 390). The N-well pattern 212A is configured to have a width extending along a first direction and a height extending along a direction perpendicular to a second direction. Figure 2A In this context, the first and second directions correspond to the X-axis and Y-axis, respectively. In some embodiments, the first and second directions correspond to other than the X-axis and Y-axis. The N-well pattern 212A is separated from each other along the Y-axis and along the X-axis; however, other directions are considered in this disclosure.

[0056] Layout 202A also includes opposing sides 210AR and 210AL relative to the X-axis. In some embodiments, opposing sides 210AR and 210AL correspond to cell boundaries. Cell region 204A includes AR pattern groups 216A_1 and 216A_2, which include a width (Xδ, e.g., 9δ, 10δ) along the X-axis and a height (H_X, e.g., H_1, H_2) along the Y-axis. In some embodiments, the AR region is bounded by oxide and is referred to as an oxide size (OD) region or oxide diffusion (OD) region. In some embodiments, AR pattern groups 216A_1 and 216A_2 are located in the first layer 340 of layout 202A. Figures 3C-3D Within. During the fabrication of semiconductor devices based on layout diagram 202A, AR pattern groups 216A_1 and 216A_2 generate AR groups 216B_1 and 216B_2 ( Figure 2B The corresponding AR in )

[0057] Layout diagram 202A also includes imaginary reference lines 201A, 201B, 201C, 218A, 219A, 220A, 232AT, and 232AB. In some embodiments, the imaginary reference lines are orientation lines / tracks for placing the shapes and patterns of layout diagram 202A. In some embodiments, imaginary reference lines 201A, 201B, 201C, 218A, 219A, 220A, 232AT, and 232AB are cell area boundaries. Reference line 218A extends parallel to the Y-axis. AR pattern group 216A_2 includes an end aligned with reference line 218A relative to the X-axis. In some embodiments, a first side 210AR is parallel to and close to reference line 218A. Reference line 220A extends parallel to the Y-axis. AR pattern group 216A_1 includes an end aligned with reference line 220A relative to the X-axis. In some embodiments, the second side 210AL is parallel to and close to reference line 220A. In some embodiments, reference line 219A represents a cell boundary. In some embodiments, center line 219A represents the boundary between HL portion 206A and LL portion 208A. In some embodiments, reference line 219A is the vertical center reference line of cell region 204A. In some embodiments, reference line 219A is the cell boundary between cell regions 204_AA and 204_AE, 204_AB and 204_AF, 204_AC and 204_AG, and 204_AD and 204_AH. In some embodiments, the first side 210AR and the second side 210AL represent cell region boundaries.

[0058] Layout 202A also includes group 222A of gate patterns 215. The gate patterns of group 222A correspondingly cover AR pattern groups 216A_1 and 216A_2. In some embodiments, the gate patterns of group 222A are in the second layer 342 ( Figures 3C-3D (For example, gate layer 396) Figures 3C-3D In some embodiments, the second layer 342 is above the first layer 340. In some embodiments, the gate layer 396 is in a third layer located above a metal diffusion layer (not shown) in the second layer 342. In some embodiments, the gate pattern of group 222A corresponds to the gate structure of group 222B. Figure 2B ).

[0059] like Figure 2AAs shown, one of the gate patterns in group 222A is collinear with reference line 218A. Relative to the X-axis, all AR patterns in group 216A_2 extend from reference line 219A to reference line 218A, such that the rightmost end of each AR in group 216A_2 is aligned with reference line 218A. Reference line 218A is parallel to and close to the first side 210AR of cell region 204A. In some embodiments, the rightmost end of not all, but still the majority, AR patterns in group 216A_2 is aligned with reference line 218A.

[0060] Figure 2A It also includes an imaginary reference line 217A extending parallel to the Y-axis. Figure 2A In this configuration, one of the gate patterns in group 222A is collinear with reference line 217A. Relative to the X-axis, all AR patterns in group 216A_2 extend from reference line 218A to reference line 219A, such that the leftmost end of each AR in group 216A_2 is aligned with reference line 217A. In some embodiments, not all, but the second majority, of the AR patterns in group 216A_2 have their leftmost ends aligned with reference line 217A. In some embodiments, the first majority of the AR patterns in group 216A_2 is the same as the second majority of the AR patterns in group 216A_2.

[0061] like Figure 2A As shown, one of the gate patterns in group 222A is collinear with reference line 220A. Relative to the X-axis, all AR patterns in group 216A_1 extend from reference line 219A to reference line 220A, such that the leftmost end of each AR in group 216A_1 is aligned with reference line 220A. Reference line 220A is parallel to and close to the second side 210AL of cell region 204A. In some embodiments, not all, but a first majority, of the AR patterns in group 216A_1 have their leftmost ends aligned with reference line 220A.

[0062] Figure 2A It also includes an imaginary reference line 221A extending parallel to the Y-axis. Figure 2A In this configuration, one of the gate patterns in group 222A is collinear with reference line 221A. Relative to the X-axis, all AR patterns in group 216A_1 extend from reference line 220A to reference line 219A, such that the rightmost end of each AR in group 216A_1 is aligned with reference line 221A. In some embodiments, the rightmost end of not all, but the second majority, AR patterns in group 216A_1 are aligned with reference line 221A. In some embodiments, the first majority of AR patterns in group 216A_1 is the same as the second majority of AR patterns in group 216A_1.

[0063] In some embodiments, a first subgroup 223A_1 of the gate pattern is located between reference line 218A and a first side 210AR, and a second subgroup 223A_2 of the gate pattern is located between reference line 220A and a second side 210AL. In some embodiments, a third subgroup 222A_3 is located between AR pattern group 216A_2 and center reference line 219A. In some embodiments, a fourth subgroup 222A_4 is located between AR pattern group 216A_1 and center reference line 219A. In some embodiments, the gate patterns of subgroups 223A_1, 223A_2, 223A_3, and / or 223A_4 are dummy gate patterns. In some embodiments, the dummy gate patterns are configured to isolate one cell region from another. In some embodiments, the dummy gate is not part of a transistor. In some embodiments, one or more dummy gate patterns are arranged at the edges of cell regions (e.g., cell region 204A or cell regions 204_AA, 204_AB, 204_AC, 204_AD, 204_AE, 204_AF, 204_AG, and 204_AH). In some embodiments, the first side 210AR and the second side 210AL represent portions of cell boundaries. In some embodiments, reference lines 218A and 220A represent portions of cell boundaries. In some embodiments, the center reference line 219A represents a portion of the corresponding cell boundary. In some embodiments, reference lines 201A, 201B, and 201C represent portions of the corresponding cell boundaries. In some embodiments, a subgroup 223A_1 of the gate pattern corresponds to a cell boundary. In some embodiments, subgroups 223A_1, 223A_2, 223A_3, and 223A_4 of the gate pattern 222AA represent portions of the corresponding cell boundaries.

[0064] exist Figure 2A The arrangement of the n-well pattern 212A is envisioned. In some embodiments, relative to the X-axis: the left end of an instance of the n-well pattern 212A below the AR pattern in group 216A_1 extends between the two gate patterns of subgroup 223A_2; the right end of an instance of the n-well pattern 212A below the AR pattern in group 216A_1 extends between the two gate patterns of subgroup 223A_4; the left end of an instance of the n-well pattern 212A below the AR pattern in group 216A_2 extends between the two gate patterns of subgroup 223A_3; and the right end of an instance of the n-well pattern 212A below the AR pattern in group 216A_2 extends between the two gate patterns of subgroup 223A_1.

[0065] In some embodiments, relative to the X-axis: the left end of an instance of n-well pattern 212A below the corresponding AR pattern in group 216A_1 extends beyond reference line 220A, but is not located below any gate pattern in group 223A_2; the right end of an instance of n-well pattern 212A below the corresponding AR pattern in group 216A_1 extends beyond the gate pattern above the right end of the AR pattern in group 216A_1, but is not located below any gate pattern in subgroup 223A_4; the left end of an instance of n-well pattern 212A below the corresponding AR pattern in group 216A_2 extends beyond the gate pattern above the left end of the AR pattern in group 216A_2, but is not located below any gate pattern in subgroup 223A_3; the right end of an instance of n-well pattern 212A below the corresponding AR pattern in group 216A_2 extends beyond reference line 218A, but is not located below any gate pattern in subgroup 223A_2.

[0066] Layout 202A further includes an FC pattern 224A that will be converted into an isolated dummy gate in the future, the FC pattern 224A extending relative to the Y-axis. Based on Figure 2A Layout diagram 202A for manufacturing semiconductor devices Figure 2B The semiconductor device 202B, more specifically, based on Figure 2A The manufacture of semiconductor devices with FC pattern 224A Figure 2B An isolated dummy gate 244B. A given FC pattern 224A covers a given portion of the corresponding gate pattern, and a given portion of the gate pattern covers a portion of the corresponding AR pattern; the given portions of the gate pattern and the AR pattern represent the intermediate region 226A.

[0067] In some embodiments, relative to the Y-axis, since the given region 226A lies between the upper and lower portions of the corresponding gate pattern, Figure 2A The given region 226A is therefore considered to be between the corresponding gate pattern and the corresponding FC pattern 224A. The upper portion of the corresponding gate pattern is not below the corresponding FC pattern 224A, i.e., it is not covered by the corresponding FC pattern 224A. The lower portion of the corresponding gate pattern is not below the corresponding FC pattern 224A, i.e., it is not covered by the corresponding FC pattern 224A. Therefore, it can be said that the given region 226A is between the uncovered upper and lower portions of the corresponding gate pattern. In some embodiments, the size of the given region 226A relative to the Y-axis is smaller than that of the corresponding FC pattern 224A. In some embodiments, the size of the given region 226A relative to the Y-axis is approximately the same as that of the corresponding FC pattern 224A.

[0068] Should recall Figure 2A The corresponding in Figure 2BThe middle region 226B is the middle region of the middle region. Similarly, in some embodiments, relative to the Y-axis, because the given region 226B is between the upper gate and the lower gate, Figure 2B The given region 226B is considered to be between the corresponding gate and the upper gate. The given region 226B is occupied by a corresponding isolation dummy gate 244B, which separates the upper gate from the lower gate relative to the Y-axis. In some embodiments, the size of the given region 226B relative to the Y-axis is smaller than that of the corresponding isolation dummy gate 244B. In some embodiments, the size of the given region 226B relative to the Y-axis is approximately the same as that of the corresponding isolation dummy gate 244B.

[0069] In some embodiments, relative to the X-axis, since the given region 226A lies between the left and right portions of the corresponding AR pattern, therefore Figure 2A The given region 226A is considered to be between the corresponding AR pattern and the corresponding FC pattern 224A. The left portion of the corresponding AR pattern is not below the corresponding FC pattern 224A, i.e., it is not covered by the corresponding FC pattern 224A. The right portion of the corresponding AR pattern is not below the corresponding FC pattern 224A, i.e., it is not covered by the corresponding FC pattern 224A. Therefore, the given region 226A is referred to as being between the uncovered left and right portions of the corresponding AR pattern. In some embodiments, the size of the given region 226A relative to the X-axis is approximately the same as that of the corresponding FC pattern 224A. In some embodiments, the size of the given region 226A relative to the Y-axis is smaller than that of the corresponding FC pattern 224A.

[0070] Should recall Figure 2A The corresponding in Figure 2B The middle region 226B in the middle region. Similarly, in some embodiments, relative to the X-axis, because given region 226B is between the left AR and the right AR, therefore Figure 2BA given region 226B is considered to be located between the corresponding ARs. The given region 226B is occupied by a corresponding isolation dummy gate 244B, which separates the left AR from the right AR relative to the Y-axis. In some embodiments, instances of isolation dummy gates 244B found between the left and right ARs relative to the X-axis are referred to as inner isolation dummy gates 244B. Conversely, in such embodiments, instances of isolation dummy gates 244B not located between corresponding left and right ARs in the same cell region are referred to as outer isolation dummy gates 244B. In such embodiments, the outer isolation dummy gate 244B is located at or near the boundary of the corresponding cell region relative to the X-axis and is adjacent to either the left or right AR, but not adjacent to both the left and right ARs in the same cell region. In some embodiments, the size of the given region 226B is approximately the same as the corresponding isolation dummy gate 244B relative to the X-axis. In some embodiments, the size of the given region 226B is smaller than the corresponding isolation dummy gate 244B relative to the X-axis.

[0071] In some embodiments, the FC pattern 224A extends upward on a third direction perpendicular to each of the first and second directions. Figure 2A In the middle, the third direction is parallel to the Z-axis ( Figure 2A (Not shown in the image). More specifically, in some embodiments, the FC pattern 224A extends from the bottom of the first layer 340 to the top of the second layer 342. In some embodiments, the FC pattern 224A extends from the first layer 340 to a third layer. In some embodiments, the FC pattern 224A extends from the substrate layer 390 (…). Figure 3C ) Extends through n-well layer 392, through AR layer 394 ( Figures 3C-3D And through gate layer 396. Other FC pattern configurations, arrangements or numbers of other layout levels of FC pattern 224A are within the scope of this disclosure.

[0072] In some embodiments, each FC pattern 224A specifies a future separation or disconnection between AR patterns and, in other cases, between gate patterns of a fully projected cell region. In some embodiments, each FC pattern 224A is a precursor to a corresponding internal isolation dummy gate 244B. In some embodiments, one or more FC patterns 224A are configured to be located on each of the majority AR patterns in each of groups 216A_1 and 216A2. In some embodiments, the corresponding portion of the FC pattern 224A is located at least 2δ from the nearest end of the corresponding AR pattern relative to the X-axis. In some embodiments, the width of the AR pattern is at least 2δ. In some embodiments, the width of the AR pattern is at least 3δ (see...). Figure 15C In some embodiments, some of the AR patterns are as narrow as 1δ (see...). Figure 15C ).

[0073] Layout 202A includes a low-leakage portion 208A and a high-leakage portion 206A. The AR patterns of group 216A_2 are substantially within the low-leakage (LL) portion 208A. The AR patterns of group 216A_1 are substantially within the high-leakage (HL) portion 206A. The AR patterns of group 216A_2 are configured with a height H_1 relative to the Y-axis, which helps to keep current leakage below a predetermined threshold. The height H_2 of the AR patterns of group 216A_1 is greater than the height of AR pattern group 216A_2 relative to the Y-axis and supports switching speeds within a predetermined threshold. In some embodiments, each AR pattern with a height H_2 is an HL portion. In some embodiments, each AR pattern with a height H_1 is an LL portion. In some embodiments, AR patterns larger than other AR patterns within the cell area are configured as a set of HL portions. In some embodiments, AR patterns smaller than other AR patterns within the cell area are configured as a set of LL portions. In some embodiments, the AR patterns in group 216A_1 are twice the size of the AR patterns in group 216A_2 relative to the Y-axis.

[0074] Relative to the X-axis, one or more AR patterns in each of groups 216A_1 and 216A_2 are covered by one or more corresponding FC patterns 224A. The major axis of the FC pattern 224A extends relative to the Y-axis. In some embodiments, the major axis of one or more FC patterns 224A extends relative to the Y-axis from a first end of the gate pattern 222A to a second end of the gate pattern 222A. The AR patterns in group 216A_2 are separated from each other by corresponding gaps 228A having a distance S_1. The AR patterns in group 216A_1 are separated from each other by corresponding gaps 230A having a distance S_1. In some embodiments, gaps 228A and 230A are configured to have the same height. In some embodiments, gaps 228A and 230A are configured to have different heights. In some embodiments, the distance S_1 is determined by the design rules of the corresponding semiconductor process technology node. In some embodiments, the distance S_1 is the minimum height allowed between AR patterns according to the design rules of the corresponding semiconductor process technology node. For the purpose of describing embodiments of this disclosure, the gap height is labeled in the form S_X, where X is a non-negative integer or fraction. For the purpose of describing embodiments of this disclosure, the AR height is labeled in the form H_X, where X is a non-negative integer.

[0075] The topmost and bottommost AR patterns in group 216A_1 are separated from the corresponding reference lines 232AT and 232AB by a distance of S_1 / 2. In some embodiments, reference lines 232AT and 232AR are cell boundaries. The topmost and bottommost AR patterns in group 216A_2 are separated from the corresponding reference lines 232AT and 232AB by a distance of S_1 / 2. The dimensions of the AR patterns in group 216A_2 are different from those in group 216A_1, for example, having corresponding heights H_1 and H_2. In some embodiments, AR pattern groups 216A_1 and 216A_2 within the n-well pattern 212A are configured as p-type diffused material and support p-channel metal-oxide-semiconductor (PMOS). In some embodiments, AR pattern groups 216A_1 and 216A_2 outside the n-well pattern 212A are configured as n-type diffused material and support n-channel metal-oxide-semiconductor (NMOS).

[0076] In some embodiments, each cell region 204_AE, 204_AF, 204_AG, and 204_AH is configured according to the following design rule (1). In some embodiments, each cell region 204_AA, 204_AB, 204_AC, and 204_AD is represented by the following design rule (2). In some embodiments, cell region 204A is represented by the following design rule (3).

[0077] Unit height = 2·S_1 + 2·H_1 Rule (1)

[0078] Unit height = 1.5·S_1 + 1.5·H_2 Rule (2)

[0079] Figure 2B This is a plan view of a semiconductor device 202B according to some embodiments.

[0080] Semiconductor device 202B is an example of semiconductor device 102. In some embodiments, semiconductor device 202B is configured for use within IC 100. In some embodiments, cell region 204B is an example of cell region 104. Figure 2B Cell regions 204B, 204_BA, 204_BB, 204_BC, 204_BD, 204_BE, 204_BF, 204_BG, and 204_BH correspond to cell regions 204A, 204_AA, 204_AB, 204_AC, 204_AD, 204_AE, 204_AF, 204_AG, and 204_AH. In some embodiments, HL portion 206B is an example of HL portion 106. In some embodiments, HL portion 106 is configured for use in cell region 104. In some embodiments, LL portion 208B is an example of LL portion 108. In some embodiments, LL portion 208B is configured for use in cell region 104.

[0081] Cell region 204B is configured with an isolation dummy gate 244B and an intermediate region 226B. More specifically, the isolation dummy gate 244B occupies the corresponding intermediate region 226B. In some embodiments, at least a selected portion of the gate electrodes correspondingly aligned with reference lines 217B, 218B, 220B, and 221B is replaced by the corresponding isolation dummy gate, wherein, among other things, the selected portion will cover the corresponding end of the corresponding AR. In such embodiments, within the context of cell region 204B, the isolation dummy gate 244B is referred to as the inner isolation dummy gate, while the isolation dummy gate replacing the selected portion of the selected gate structure is referred to as the outer isolation dummy gate. In some embodiments, not only the selected portion but also all of the selected gate electrodes correspondingly aligned with reference lines 217B, 218B, 220B, and 221B are replaced by the corresponding isolation dummy gate.

[0082] Semiconductor device 202B includes cell region 204B, which includes ARs in groups 216B_1 and 216B_2 extending parallel to the X-axis. Group 216B_1 includes instances of AR213B_1 and AR213B_2. Group 216B_1 also includes instances of AR213B_1, AR213B_2, and AR213B_3. Each instance of AR213B_1 and AR213B_2 is an example of a non-fully projected AR. Each instance of AR213B_3 is an instance of a fully projected AR. Cell region 204B is arranged such that the center reference line 219B is centered on cell region 204B relative to the X-axis, with respect to an imaginary center reference line 219B extending parallel to the Y-axis. Relative to an imaginary first reference line 218B extending parallel to the Y-axis, the first ends of two or more ARs in group 216B_2 extend a distance from the center reference line 219B to the first reference line 218B relative to the X-axis. The first edge 210BR of cell region 204B is parallel to and close to the first reference line 218B. Relative to an imaginary second reference line 220B extending parallel to the Y-axis, the second ends of two or more active regions 216B_1 extend a distance from the center reference line 219B to the second reference line 220B. The second edge 210BL of cell region 204B is parallel to and close to the second reference line 220B. The second edge 210BL is on the opposite side of cell region 204B relative to the first edge 210BR. Corresponding instances of left AR 213B_1 and right AR 213B_2 include corresponding major axes that are parallel to and collinear with the X-axis. In some embodiments, the instances of AR 213B_1 on the left and the corresponding instances of AR 213B_2 on the right are separated by the corresponding instances of the intermediate region 226B. In some embodiments, the first set of AR 213B_1 instances and the second set of AR 213B_2 instances are separated by the instances of the intermediate region 226B.

[0083] exist Figure 2B In some embodiments, the rightmost end of not all, but a first majority, of the ARs in group 216B_2 is aligned with reference line 218B. Relative to the X-axis, all ARs in group 216B_2 extend from reference line 218B to reference line 219B, such that the leftmost end of each AR in group 216B_2 is aligned with reference line 217B. In some embodiments, the leftmost end of not all, but a second majority, of the ARs in group 216B_2 is aligned with reference line 217B. In some embodiments, the first majority of ARs in group 216B_2 is the same as the second majority of ARs in group 216B_2.

[0084] exist Figure 2B In some embodiments, the leftmost ends of not all, but a first majority, of the ARs in group 216B_1 are aligned with reference line 220B. Relative to the X-axis, all ARs in group 216B_1 extend from reference line 220B to reference line 219B, such that the rightmost end of each AR in group 216B_1 is aligned with reference line 221B. In some embodiments, the rightmost ends of not all, but a second majority, of the ARs in group 216B_1 are aligned with reference line 221B. In some embodiments, the first majority of ARs in group 216B_1 is the same as the second majority of ARs in group 216B_1.

[0085] refer to Figure 2B Compared to other methods, the intermediate region 226B now occupied by the corresponding isolation dummy gate 224B is located at different positions in the AR of groups 216B_1 and 216B_2. In some embodiments, the removal of a portion of the gate structure 222B and the corresponding portion of the AR in groups 216B_1 and 216B_2 is implemented in FinFET technology, nanosheet FET technology, all-around gate technology, etc.

[0086] Semiconductor device 202B is configured with an isolation dummy gate 244B, which occupies a corresponding intermediate region 226B. Not all AR instances in groups 216B_1 and 216B_2 are collinear with another AR instance. Relative to the X-axis, not all internal instances of the isolation dummy gate 244B must be collinear with another internal instance of the isolation dummy gate 244B. Relative to the X-axis, the individual instances of the isolation dummy gate 244B are located at different positions from one AR to the next. Relative to the Y-axis, each AR in group 216B_1 has a height H_2, and each AR in group 216B_2 has a height H_1, where H1 < H2.

[0087] Figure 3A This is a layout diagram 302A of a semiconductor device according to some embodiments.

[0088] For the purpose of discussing layout 302A, the shapes and patterns within layout 302A are discussed using reference numerals of the form 3XXA or 3XX_A. This corresponds to semiconductor device 302B ( Figure 3B The layout diagram 302A shows the shape and pattern structure in... Figure 3B The reference numbers in the form of 3XXB or 3XX_B are used for discussion.

[0089] because Figure 3A The FC pattern 324A (discussed below) generates the corresponding Figure 3B The internal isolation dummy gate of the AR is not fully projected (discussed below). Compared with other methods, Figure 3B The benefits of all AR incomplete projections include reduced wasted unit area space and increased AR density.

[0090] In some embodiments, layout 302A is a layout diagram of a semiconductor device, such as semiconductor device 102. In some embodiments, layout 302A is configured for manufacturing a semiconductor device included within an IC (e.g., IC 100), such as semiconductor device 302B. Figure 3B In some embodiments, cell region 304A is an example of cell region 104. In some embodiments, cell regions 304_AA, 304_AB, 304_AC, 304_AD, 304_AE, 304_AF, 304_AG, and 304_AH are in Figure 3A Within cell region 304A, and used for manufacturing semiconductor cells, such as those used in ICs (such as IC 100). Figure 3B The corresponding cell regions 304_BA, 304_BB, 304_BC, 304_BD, 304_BE, 304_BF, 304_BG, and 304_BH in the cell region 304B of the semiconductor device 302B. In some embodiments, the HL portion (e.g., HL portion 106) is represented by a group of AR patterns 316A_1, each AR pattern 316_A having a height H_3 relative to the Y-axis. In some embodiments, the LL portion (e.g., LL portion 108) is represented by a group of AR patterns 316A_2 and 316A_3, each of AR patterns 316A_2 and 316A_3 having a height H_1.

[0091] exist Figure 3A In this context, instances of AR patterns 316A_3, 316A_2, and 316A_1 are not fully projected relative to the X-axis. In some embodiments, the distance between an instance of AR pattern 316A_2 and an instance of AR pattern 316A_1 is less than or equal to 1δ, or less than the width of FC pattern 324A, or less than the width of gate pattern 322A.

[0092] Layout diagram 302A includes cell region 304A, which is a single cell region. In some embodiments, cell region 304A is considered as a larger cell region that includes smaller cell regions (such as cell regions 304_AA, 304_AB, 304_AC, 304_AD, 304_AE, 304_AF, 304_AG, and 304_AH).

[0093] In some embodiments, cell region 304A is considered a larger cell region, which comprises two medium-sized cell regions separated relative to the X-axis by an imaginary center vertical reference line 319A. In some embodiments, each of the two medium-sized cell regions is considered a "larger" cell region that includes the smaller cell region. For example, the intermediate cell region to the left of reference line 319A includes cell regions 304_AA, 304_AB, 304_AC, and 304_AD, and the intermediate cell region to the right of reference line 319A includes cell regions 304_AE, 304_AF, 304_AG, and 304_AH.

[0094] In some embodiments, cell region 204A is considered a larger cell region, which includes two intermediate-sized cell regions separated relative to the Y-axis by an imaginary central horizontal line 301B. In some embodiments, each of the two intermediate cell regions is considered a “larger” cell region that includes the smaller cell region. For example, the intermediate cell regions above reference line 301B include cell regions 304_AA, 304_AB, 304_AE, and 304_AF, and the intermediate cell regions below reference line 301B include cell regions 304_AC, 304_AD, 304_AG, and 304_AH.

[0095] In some embodiments, cell region 304A is considered a larger cell region, which includes four medium-sized cell regions separated relative to the Y-axis by imaginary horizontal reference lines 301A, 301B, and 301C. In some embodiments, each of the four medium cell regions is considered a “larger” cell region that includes smaller cell regions; for example: the medium cell region above reference line 301A includes cell regions 304_AA and 304_AE; the intermediate cell region between reference lines 301A and 301B includes cell regions 304_AB and 304_AF; the intermediate cell region between reference lines 301B and 301C includes cell regions 304_AC and 304_AG; and the intermediate cell region below reference line 301C includes cell regions 304_AD and 304_AH.

[0096] In some embodiments, cell region 304A is considered a larger cell region, which includes four medium-sized cell regions separated relative to the X-axis by reference line 319A and relative to the Y-axis by reference line 301B. In some embodiments, each of the four medium-sized cell regions is considered a “larger” cell region that includes smaller cell regions; for example: the medium-sized cell region to the left of reference line 319A and above reference line 301B includes cell regions 304_AA and 304_AB; the middle cell region to the left of reference line 319A and below reference line 301B includes cell regions 304_AC and 304_AD; the middle cell region to the right of reference line 319A and above reference line 301B includes cell regions 304_AE and 304_AF; and the middle cell region to the right of reference line 319A and below reference line 301B includes cell regions 304_AG and 304_AH. Other applicable cell region orientations are within the scope of this disclosure.

[0097] Layout 302A also includes an n-well pattern 312A within the substrate. In some embodiments, the n-well pattern 312A and the substrate are in the first layer 340 ( Figures 3C-3D Within, for example, substrate layer 390 ( Figures 3C-3D The N-well pattern 312A is configured to have a width extending along the X-axis and a height extending along the Y-axis. Figure 3A In this context, the first and second directions correspond to the X-axis and Y-axis, respectively. In some embodiments, the first and second directions correspond to other directions different from the X-axis and Y-axis. The N-well pattern 312A is separated from each other relative to the X-axis; however, other orientations are considered in this disclosure. Variations in the arrangement of the n-well pattern 312A, similar to variations in the n-well pattern 212A, are contemplated.

[0098] Layout 302A also includes opposing sides 310AR and 310AL relative to the X-axis. In some embodiments, opposing sides 310AR and 310AL correspond to cell boundaries. Cell region 304A includes AR patterns 316A_2, 316A_3, and 316A_1, each having a width that is a corresponding multiple of δ (Xδ) relative to the X-axis and a height (H_X) relative to the Y-axis, where X is a non-negative integer. In some embodiments, the AR region is bounded by oxide and is referred to as an oxide size (OD) region or oxide diffusion (OD) region. In some embodiments, AR patterns 316A_2, 316A_3, and 316A_1 are located in the first layer 340 of layout 302A. Figures 3C-3D Within. During the fabrication of semiconductor devices based on layout diagram 302A, instances of AR patterns 316A_2, 316A_3, and 316A_1 generate corresponding instances of AR316B_2, 316B_3, and 316B_1. Figure 3B ).

[0099] Layout diagram 302A also includes imaginary reference lines 301A, 301B, 301C, 318A, 319A, 320A, 332AT, and 332AB. In some embodiments, the imaginary reference lines are orientation lines / tracks on which the shape and pattern of layout diagram 302A lie. Reference line 318A extends parallel to the Y-axis. AR pattern 316A_2 includes an end aligned with reference line 318A relative to the X-axis. In some embodiments, a first side 310AR extends parallel to and close to reference line 318A and parallel to the Y-axis relative to reference line 320A. Instances of AR pattern 316A_3 and selected instances of AR pattern 316A_2 include an end aligned with reference line 320A relative to the X-axis. A second side 310AL is parallel to and close to reference line 320A. In some embodiments, reference line 319A is the vertical center reference line of cell region 304A. In some embodiments, reference line 319A is the cell boundary between cell regions 304_AA and 304_AE, 304_AB and 304_AF, 304_AC and 304_AG, and 304_AD and 304_AH. In some embodiments, AR pattern 316A_3 extends from reference line 318A to 320A. In some embodiments, AR pattern 316A_3 is correspondingly located at the uppermost and lowermost parts of cell region 304A. An example of AR pattern 316A_3 is a distance S_1 / 2 from the corresponding reference lines 332AT and 332AB.

[0100] Layout 302A also includes group 322A of gate patterns 315. The gate patterns of group 322A correspondingly cover AR patterns 316A_2, 316A_3, and 316A_1. In some embodiments, the gate patterns of group 322A are in the second layer 342 ( Figures 3C-3D In, for example, gate layer 396 ( Figures 3C-3D In some embodiments, the second layer 342 is on top of the first layer 340. In some embodiments, the gate layer 396 is in a third layer located on top of a metal diffusion layer (not shown) in the second layer 340. In some embodiments, group 322A of the gate pattern corresponds to group 322B of the gate structure. Figure 3B ).

[0101] like Figure 3A As shown, one of the gate patterns in group 322A is collinear with reference line 318A. Relative to the X-axis, all AR patterns in group 316A_2 extend from reference line 319A to reference line 318A, such that the rightmost end of each AR in group 316A_2 is aligned with reference line 318A. Reference line 318A is parallel to and close to the first side 310AR of cell region 304A. In some embodiments, not all, but a first majority, of AR patterns 316A_2 have their rightmost ends aligned with reference line 318A.

[0102] Figure 3A It also includes an imaginary reference line 317A extending parallel to the Y-axis. Figure 3A In this configuration, one of the gate patterns in group 322A is collinear with reference line 317A. Relative to the X-axis, all AR patterns 316A_2 extend from reference line 318A to reference line 319A, such that the leftmost end of each AR 316A_2 is aligned with reference line 317A. In some embodiments, not all, but a second majority, of the AR patterns 316A_2 are aligned with reference line 317A. In some embodiments, a first majority and a second majority of the AR patterns 316A_2 are identical.

[0103] exist Figure 3A In this configuration, one of the gate patterns in group 322A is collinear with reference line 320A. All AR patterns 316A_1 extend from reference line 319A to reference line 320A relative to the X-axis, such that the leftmost end of each AR 316A_1 is aligned with reference line 320A. Reference line 320A is parallel to and close to the second side 310AL of cell region 304A. In some embodiments, not all, but a first majority, of the leftmost ends of AR patterns 316A_1 are aligned with reference line 320A.

[0104] Figure 3A It also includes an imaginary reference line 321A extending parallel to the Y-axis. Figure 3A In this configuration, one of the gate patterns in group 322A is collinear with reference line 321A. Relative to the X-axis, all AR patterns 316A_1 extend from reference line 320A to reference line 319A, such that the rightmost end of each AR 316A_1 is aligned with reference line 321A. In some embodiments, not all, but a second majority, of the rightmost ends of AR patterns 316A_1 are aligned with reference line 321A. In some embodiments, a first majority of AR patterns 316A_1 is identical to a second majority of AR patterns 316A_1.

[0105] In some embodiments, a first subgroup 323A_1 of the gate pattern is located between reference line 318A and a first side 310AR, and a second subgroup 323A_2 of the gate pattern is located between reference line 320A and a second side 310AL. In some embodiments, the first side 310AR and the second side 310AL represent portions of a cell boundary. In some embodiments, reference lines 318A and 320A represent portions of a cell boundary. In some embodiments, a center reference line 319A represents a portion of a corresponding cell boundary. In some embodiments, the gate pattern 323A_1 corresponds to a cell boundary. In some embodiments, one of the gate patterns 323A_1 corresponds to a cell boundary.

[0106] exist Figure 3A In this work, variations in the arrangement of the n-well pattern 312A are envisioned. In some embodiments, relative to the X-axis: the left end of an instance of the n-well pattern 312A below corresponding AR patterns 316A_1 and 316A_2 extends between the two gate patterns of subgroup 323A_2; the right end of an instance of the n-well pattern 312A below corresponding AR patterns 316A_1 and 316A_2 extends between the two gate patterns of subgroup 323A_1.

[0107] In some embodiments, relative to the X-axis: the left end of an instance of n-well pattern 312A below corresponding AR patterns 316A_1 and 316A_2 extends beyond reference line 320A, but not below any gate pattern of subgroup 323A_2; the right end of an instance of n-well pattern 312A below corresponding AR patterns 316A_1 and 316A_2 extends beyond the gate pattern covering the right end of AR patterns 316A_1 and 316A_2, but not below any gate pattern of subgroup 323A_1.

[0108] Layout diagram 302A also includes an FC pattern 324A extending relative to the Y-axis. Based on Figure 3A The manufacturing of the semiconductor device in layout diagram 302A Figure 3B The semiconductor device 302B, and more specifically, based on Figure 3A The manufacture of the FC pattern 324A semiconductor device Figure 3B An isolated dummy gate 344B. A given FC pattern 224A covers a given portion of the corresponding gate pattern, and a given portion of the gate pattern covers a portion of the corresponding AR pattern; the given portions of the gate pattern and the AR pattern represent the intermediate region 326A.

[0109] In some embodiments, relative to the Y-axis, since the given region 326A is located between the upper and lower portions of the corresponding gate pattern, therefore Figure 3A The given region 326A is considered to be positioned between the corresponding gate pattern and the corresponding FC pattern 324A. The upper portion of the corresponding gate pattern is not located below the corresponding FC pattern 324A, i.e., it is not covered by the corresponding FC pattern 324A. Similarly, the lower portion of the corresponding gate pattern is not located below the corresponding FC pattern 324A, i.e., it is not covered by the corresponding FC pattern 324A. Therefore, the given region 326A is described as interposed between the uncovered upper and lower portions of the corresponding gate pattern. In some embodiments, the size of the given region 326A relative to the Y-axis is smaller than that of the corresponding FC pattern 324A. In some embodiments, the size of the given region 326A relative to the Y-axis is approximately the same as that of the corresponding FC pattern 324A.

[0110] One should recall the corresponding Figure 3B The middle area 326B Figure 3AThe middle region in the middle. Similarly, in some embodiments, relative to the Y-axis, since the given region 326B is between the upper gate and the lower gate, therefore Figure 3B The given region 326B is considered to be between the corresponding gate and the given region 326B. The given region 326B is occupied by a corresponding isolation dummy gate 344B, which separates the upper gate from the lower gate relative to the Y-axis. In some embodiments, the size of the given region 326B relative to the Y-axis is smaller than that of the corresponding isolation dummy gate 344B. In some embodiments, the size of the given region 326B relative to the Y-axis is approximately the same as that of the corresponding isolation dummy gate 344B.

[0111] In some embodiments, relative to the X-axis, since the given region 326A lies between the left and right portions of the corresponding AR pattern, therefore Figure 3A The given region 326A is considered to be positioned between the corresponding AR pattern and the corresponding FC pattern 324A. The left portion of the corresponding AR pattern is not below the corresponding FC pattern 324A, i.e., it is not covered by the corresponding FC pattern 324A. The right portion of the corresponding AR pattern is not below the corresponding FC pattern 324A, i.e., it is not covered by the corresponding FC pattern 324A. Therefore, the given region 326A is described as intervening between the uncovered left and right portions of the corresponding AR pattern. In some embodiments, the size of the given region 326A relative to the X-axis is approximately the same as that of the corresponding FC pattern 324A. In some embodiments, the size of the given region 326A relative to the Y-axis is smaller than that of the corresponding FC pattern 324A.

[0112] One should recall the corresponding Figure 3B The middle area 326B Figure 3A The middle region in. Similarly, in some embodiments, relative to the X-axis, since given region 326B is between the left AR and the right AR, therefore Figure 3BA given region 326B is considered to be located between the corresponding ARs. The given region 326B is occupied by a corresponding isolation dummy gate 344B, which separates the left AR from the right AR relative to the Y-axis. Therefore, such a left AR and right AR are examples of ARs with incomplete projection. In some embodiments, instances of isolation dummy gates 344B found between the left AR and right AR relative to the X-axis are referred to as internal isolation dummy gates 344B. In contrast, in such embodiments, instances of isolation dummy gates 344B not located between corresponding left ARs and right ARs in the same cell region are referred to as external isolation dummy gates 344B. In such embodiments, external isolation dummy gates 344B are located at or near the boundary of the corresponding cell region and are adjacent to either the left AR or the right AR, but not adjacent to both the left AR and right AR of the same cell region, relative to the X-axis. In some embodiments, the size of the given region 326B is approximately the same as the corresponding isolation dummy gate 344B relative to the X-axis. In some embodiments, the size of the given region 326B is smaller than the corresponding isolation dummy gate 344B relative to the X-axis.

[0113] In some embodiments, the FC pattern 324A extends upward on a third direction perpendicular to each of the first and second directions. Figure 3A In the middle, the third direction is parallel to the Z-axis ( Figure 3A (Not shown in the image). More specifically, in some embodiments, the FC pattern 324A extends from the first layer 340 to the second layer 342. In some embodiments, the FC pattern 324A extends from the first layer 340 to the third layer. In some embodiments, the FC pattern 324 extends from the substrate layer 390 through the n-well layer 392 (…). Figures 3C-3D (), through AR layer 394 and through gate layer 396. Other FC pattern configurations, arrangements on other layout levels, or the number thereof are within the scope of this disclosure.

[0114] In some embodiments, each FC pattern 324A specifies a future separation or disconnection between the corresponding AR patterns 316A_2 and 316A_1 and one or more gate patterns in group 322A. In some embodiments, each FC pattern 324A is a precursor to a corresponding internal isolation dummy gate 344B. The FC pattern 324A is located between each of the AR patterns 316A_2 and 316A_1. In some embodiments, the width of the FC pattern 324A relative to the X-axis is less than 1δ. The FC pattern 324A covers one or more gate patterns in group 322A located at the junction of AR regions 316A_2 and 316A_1.

[0115] In some embodiments, layout diagram 302A includes an LL portion, which is AR patterns 316A_2 and 316A_3. In some embodiments, the HL portion is AR pattern 316A_1. In some embodiments, AR patterns 316A_2 and 316A_3 are configured to have a height H_1 that contributes to current leakage below a predetermined threshold. In some embodiments, AR pattern 316A_1 is configured to have a height greater than that of AR pattern 316A_2 and support switching speeds within a predetermined threshold. In some embodiments, AR pattern 316A_1 is considered as an HL portion alone. In some embodiments, AR patterns 316A_2 and 316A_3 are each considered as LL portions. In some embodiments, AR pattern 316A_1 is three times the size of AR patterns 316A_2 and 316A_3 relative to the Y-axis.

[0116] Relative to the X-axis, AR 316A_1 and the selected AR pattern 316A_2 are covered by the corresponding FC pattern 324A. The major axis of the FC pattern 324A extends relative to the Y-axis from a first end of the gate pattern 322A to the other or second end of the same gate pattern 322A. The corresponding AR patterns 316A_2 and 316A_3 are separated from each other by corresponding gaps 328A having a distance S_1. AR pattern 316A_1 is separated from each other by corresponding gaps 330A having a height S_3. AR pattern 316A_2 is separated from AR pattern 316A_1 by corresponding gaps 329A having a height S_2. In some embodiments, gaps 328A, 329A, and 330A are configured to have the same height. In some embodiments, gaps 328A, 329A, and 330A are configured to have different heights. In some embodiments, distances S_1, S_2, and S_3 are determined by the design rules of the corresponding semiconductor process technology node. In some embodiments, S_1≤S_2≤S_3.

[0117] The topmost and bottommost AR patterns 316A_3 are separated from the corresponding reference lines 332AT and 332AB by a distance of S_1 / 2. In some embodiments, the AR patterns 316A_2 and 316A_1 within the n-well pattern 312A are configured as p-type diffused materials and support p-channel metal-oxide-semiconductor (PMOS). In some embodiments, the AR patterns 316A_2, 316A_3, and 316A_1 outside the n-well pattern 312A are configured as n-type diffused materials and support n-channel metal-oxide-semiconductor (NMOS).

[0118] Because of each of the FC pattern 324A, Figure 3CEach of the AR patterns 316A_1 and 316A_23C is an incomplete projection. Since no instance of FC pattern 324A is associated with any instance of AR pattern 316A_3, each instance of AR 316A_3 has a complete projection, that is, a complete projection between the left side 310AL and the right side 310AR of cell region 304A.

[0119] Figure 3B This is a plan view of semiconductor device 302B according to some embodiments.

[0120] Semiconductor device 302B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, semiconductor device 302B is manufactured using a photolithography process based on layout diagram 302A. In some embodiments, cell region 304B is an example of cell region 104. Figure 3B Cell regions 304_BA, 304_BB, 304_BC, 304_BD, 304_BE, 304_BF, 304_BG, and 304_BH correspond to cell regions 304A, 304_AA, 304_AB, 304_AC, 304_AD, 304_AE, 304_AF, 304_AG, and 304_AH. In some embodiments, AR 316B_1 is an HL portion, such as HL portion 106.

[0121] In some embodiments, AR 316B_2 and 316B_3 are LL portions, such as LL portion 108.

[0122] Cell region 304B is configured with an isolation dummy gate 344B and an intermediate region 326B. More specifically, the isolation dummy gate 344B occupies the corresponding intermediate region 326B. In some embodiments, at least a selected portion of the gate electrodes correspondingly aligned with reference lines 318B and 320B is replaced by the corresponding isolation dummy gate, wherein, among other things, the selected portion will cover the corresponding end of the corresponding AR. In such embodiments, within the context of cell region 304B, the isolation dummy gate 344B is referred to as the inner isolation dummy gate, while the isolation dummy gate replacing the selected portion of the selected gate structure is referred to as the outer isolation dummy gate. In some embodiments, not only the selected portion but also all of the selected gate electrodes correspondingly aligned with reference lines 218B and 220B are replaced by the corresponding isolation dummy gate.

[0123] Semiconductor device 302B includes cell region 304B, which includes AR 316B_2, 316B_3, and 316B_1 extending parallel to the X-axis. Cell region 304B is arranged such that the center reference line 319B is located at the center of cell region 304B relative to the X-axis, with respect to an imaginary center reference line 319B extending parallel to the Y-axis. Two or more of AR 316B_2 and 316B_3 have first ends extending a distance from the center reference line 319B to the first reference line 318B along the X-axis, with respect to an imaginary first reference line 318B extending parallel to the Y-axis. A first edge 310BR of cell region 304B is parallel to and close to the first reference line 318B. Two or more of active regions 316B_2 and 316B_3 have second ends extending a distance from the center reference line 319B to the second reference line 320B, with respect to an imaginary second reference line 320B extending parallel to the Y-axis. The second edge 310BL of cell region 304B is parallel to and close to the second reference line 320B. The second edge 310BL is on the opposite side of cell region 304B relative to the first edge 310BR. Corresponding instances of AR 316B_2 and AR 316B_1 have corresponding major axes that are parallel to and collinear with the X-axis. Corresponding instances of AR316B_2 and 316B_1 are separated by corresponding instances of intermediate region 326B.

[0124] about Figure 3B In some embodiments, regarding instances of AR 316B_2 extending to the right of reference line 319B, not all, but the rightmost end of the first majority, is aligned with reference line 318B. In some embodiments, regarding instances of AR 316B_2 extending to the left of reference line 319B, not all, but the leftmost end of the second majority, is aligned with reference line 320B. In some embodiments, the first majority and the second majority are the same.

[0125] exist Figure 3B In this context, all instances of AR 316B_2 are incompletely projected, and all instances of AR 316B_1 are also incompletely projected. In some embodiments, not all, but most, instances of AR 316B_2 are incompletely projected. In some embodiments, not all, but most, instances of AR 316B_1 are incompletely projected. Similarly, in... Figure 3B In this model, all instances of AR 316B_3 are fully projective. Regarding... Figure 3BIn the intermediate region 326B occupied by corresponding instances of the isolated dummy gate 344B, some (but not all) are positioned such that they are aligned with other instances of the isolated dummy gate 344B relative to the X-axis. In some embodiments, the removal of portions of the corresponding gate structures 322B in group 322B and corresponding portions of ARs 316B_1 and 316B_2 (to achieve an AR smaller than the full projection) is applied to FinFET, nanosheet FET, all-around gate, etc. Therefore, cell region 304B does not have a set of ARs with full projection.

[0126] Semiconductor device 302B is configured with an isolation dummy gate 344B occupying a corresponding intermediate region 326B. The height of each instance of AR 316B_2 and AR316B_3 is H_1, and the height of each instance of AR 316B_2 relative to the Y-axis is H_3. In some embodiments, selected instances of AR 316B_1 have corresponding major axes parallel to and collinear with the X-axis. Selected instances of AR 316B_2 and corresponding instances of AR 316B_1 are separated by corresponding instances of the isolation dummy gate 344B occupying the corresponding instances of the intermediate region 326B. Due to each of the isolation dummy gates 344B, Figure 3B Each of AR 316B_1 and 316B_2 is not fully projected. Since no instance of the isolated dummy gate 344B is associated with any instance of AR 316B_3, each instance of AR 316B_3 has a full projection, that is, a full projection between the left and right sides of cell region 304B.

[0127] Figures 3C-3D According to some embodiments Figure 3B The corresponding cross section of semiconductor device 302B.

[0128] Figure 3C The cross-sectional view corresponds to Figure 3B The cross-section line is 3C-3C'. Figure 3C The cross-sectional view corresponds to Figure 3B The section line 3C-3C' in the middle. In other structures, Figures 3C-3D Each of the figures shows a substrate layer 390 including a substrate 314B. The width of a given instance of the intermediate region 326B relative to the X-axis depends on the structure in which the given instance of the intermediate region 326B is located (i.e., in the middle).

[0129] exist Figure 3C In this context, there are two instances of intermediate region 326B between the corresponding instances of AR 316B_2. Therefore, Figure 3C Each of the two instances of the intermediate region 326B can be wider than a single instance of the isolated dummy gate 344B. More specifically, Figure 3CEach of the two instances of the intermediate region 326B is wider than the two instances of the isolation dummy gate 344B. Figure 3C Each of the two instances of the intermediate region 326B is partially occupied by the two instances of the corresponding isolation dummy gate 344B. More specifically, Figure 3C Each of the two instances of the middle region 326B has a width equal to or greater than approximately 3δ.

[0130] exist Figure 3D In this context, there are two instances of intermediate region 326B between the corresponding instances of AR 316B_2 and AR 316B_1. Therefore, Figure 3D Each of the two instances of the intermediate region 326B is substantially the same width as a single instance of the isolation dummy gate 344B. Figure 3D Each of the two instances of the intermediate region 326B is substantially completely occupied by a single instance of the corresponding isolation dummy gate 344B.

[0131] Figure 4A This is a plan view of a semiconductor device 402B according to some embodiments.

[0132] Semiconductor device 402B is an example of semiconductor device 102. In some embodiments, semiconductor device 402B is configured for use within IC 100. Semiconductor device 402B is Figure 3B This is a variant of semiconductor device 302B. In some embodiments, cell region 404B is an example of cell region 104. In some embodiments, AR 416B_1 is included in the HL portion, such as HL portion 106. In some embodiments, AR 416B_2 and 416B_3 are included in corresponding LL portions, such as LL portion 108. For clarity and brevity, references to n-wells within the cell region are omitted. However, it should be understood that in some embodiments, the cell region includes an n-well structure.

[0133] exist Figure 4A In this context, cell region 404B includes cell regions 404_BA and 404_BB. Cell region 404B includes portions of AR 416B_2 and 416B_3, as well as AR 416B_1. Instances of AR 416B_2 and corresponding portions of AR 416B_1 are separated by corresponding portions of corresponding isolation dummy gates 444B. At least some intermediate regions 426B are occupied by corresponding portions of isolation dummy gates 444B. Cell region 404B includes upper AR 416B_3 and lower AR 416B_3 correspondingly extending from a first imaginary reference line 418B to a second imaginary line 420B. In some embodiments, upper AR 416B_3 and lower AR 416B_3 have different heights (see...). Figure 13Each of AR 416B_2 and 416B_3 has a height H_1, while AR 416B_1 has a height H_3, and where H_1 <H_3。

[0134] Instances of AR416B_1 and AR416B_2 are grouped into AR set 446. In some embodiments, AR set 446 is an I-shape or I-bracket, wherein two or more upper AR 416B_2 form the upper horizontal portion of the I-bracket, an AR 416B_1 located at the center forms the vertical portion of the I-bracket, and two or more lower AR 416B_2 form the lower horizontal portion of the I-bracket. In some embodiments, this I-bracket structure is generic for AR sets (such as AR set 446).

[0135] Relative to the Y-axis, the upper portion 450 of AR 416B_1 extends upward and aligns with the middle portion of the upper AR 416B_2, but lies within the range R_1 of the uppermost edge 451 of the upper AR 416B_2. For the purposes of this disclosure, the range is referred to as R_X, where X is a non-negative integer. The upper portion 450 extends above the lower edge of AR 416B_2, but not above the upper edge 451 of AR416B_2.

[0136] about Figure 4A When the viewer is parallel to the X-axis from Figure 4A During left-to-right scanning, the upper edge 451 of upper AR416B_2 and the upper edge 450 of AR 416B_1 form a first contour. As the observer's focus moves from left to right parallel to the X-axis, the position of the first contour relative to the Y-axis changes. Relative to the Y-axis and viewed from the center region of AR 416B_1, the first contour is described as concave towards the center position in cell region 402B, with the upper edge 450 of AR 416B_1 concave below the upper edge 451 of upper AR 416B_2. Therefore, the AR set 446 is described as a concave arrangement of ARs with incomplete projection.

[0137] Also about Figure 4B When the observer is Figure 4AWhen scanning from left to right parallel to the X-axis, the lower edge 451A of lower AR 416B_2 and the lower edge 450A of AR 416B_1 form a second contour. As the observer's focus moves from left to right parallel to the X-axis, the position of the second contour relative to the Y-axis changes. Viewed relative to the Y-axis and from the perspective of the central region of AR 416B_1, the second contour is described as concave towards the center position in cell region 402B, with the lower edge 450A of AR 416B_1 concave above the lower edge 451A of upper AR 416B_2. Therefore, the AR set 446 is described as a concave arrangement of ARs with incomplete projection.

[0138] exist Figure 4A In this embodiment, the first distance between the upper edge 450 of AR 416B_1 and the upper edge 451 of AR 416B_2 in set 446 is substantially the same as the second distance between the lower edge 450A of AR 416B_1 and the lower edge 451A of AR 416B_2 in set 446. In some embodiments, the first distance between the upper edge 450 of AR 416B_1 and the upper edge 451 of AR 416B_2 in set 446 is different from the second distance between the lower edge 450A of AR 416B_1 and the lower edge 451A of AR 416B_2 in set 446.

[0139] Configure cell area 404B according to design rules (3) and (4) to meet DRC requirements.

[0140] Rule (3) is: S_1≤H_3≤S_1+2·H_1

[0141] Rule (4) is S_1≤S_2≤S_1+H_1

[0142] exist Figure 4A In this context, S_1 represents the distance between two instances of AR 416B_2 and the distance between an instance of AR_416B and its corresponding instance of AR416B_2. Figure 4A In this context, S_1 is less than or equal to the height H_3 of AR 416B_1. Height H_3 is less than or equal to height H_1 plus twice the distance S_1. Figure 4A In this embodiment, relative to the X-axis, the width of AR 416B_2 is equal to or greater than about 3δ, while the width of AR 416B_1 is equal to or greater than about 3δ. In some embodiments, other applicable heights and widths of AR 416B_2, 416B_3, and 416B_1 are within the scope of this disclosure.

[0143] Figures 4B-4E This is a plan view of semiconductor devices 402BA, 402BB, 402BC and 402BD according to some embodiments.

[0144] Correspondingly Figures 4B-4E The semiconductor devices 402BA, 402BB, 402BC and 402BD are Figure 4A A variant of the 402B semiconductor device. For the sake of simplicity, conciseness, and reduced repetition, Figures 4B-4E The differences between semiconductor device 402B and semiconductor devices 402BA, 402BB, 402BC, and 402BD are limited. Similar components retain their reference numbers, while new or different components are designated with different reference numbers.

[0145] exist Figure 4B In this context, cell region 404BA comprises two AR sets 446. Cell region 404BA includes cell regions 404_BA, 404_BB, and 404_BC. Each of cell regions 404_BA and 404_BC includes AR 416B_2 and 416B_3, as well as a portion of AR 416B_1. Cell region 404_BB includes portions of AR 416B_2 and AR 416B_1. An instance of AR 416B_1 extends from cell region 404_BB to cell region 404_BA. Another instance of AR 416B_1 extends from cell region 404_BB to cell region 404_BC.

[0146] Unit area 404BA is configured according to the above design rules (3), (4) and (5) to meet DRC.

[0147] Rule (5) is: S_1≤S_3≤S_1+2·H_1

[0148] In some embodiments, the height of each cell region in cell regions 404_BA, 404_BB, and 404_BC is defined by design rule (6) or (7) or (8).

[0149] Rule (6) is 2·S1+2·H_1

[0150] Rule (7) is 1 / 2S_1 + S_2 + H1 + 1 / 2H_3

[0151] S_3+H_3 rule (8)

[0152] exist Figure 4C In this context, cell region 404_BB comprises N AR sets 446 (where N is a non-negative integer). Figure 4C In this context, each AR set 446 includes one instance of AR 416B_1 and four corresponding instances of AR 416B_2. Figure 4C In this case, N≥3.

[0153] Figure 4D Similar to Figure 4B .exist Figure 4DIn this embodiment, cell region 404BC includes two AR sets 446, wherein instances of AR 416B_1 are configured with different widths (e.g., the lower AR 416B_1 is configured with a width of approximately 4δ and the upper AR 416B_1 is configured with a width of approximately 3δ). In some embodiments, other suitable positions for the various instances of AR 416B_1 are within the scope of this disclosure. AR 416B_1 overlaps with the X-axis by a distance Δ1. In some embodiments, Δ1 is a distance greater than zero and up to and including the minimum width of any instance of AR 416B_1.

[0154] Figure 4E Similar to Figure 4B .exist Figure 4E In this configuration, AR 416B_1 are offset from each other by a distance Δ2 relative to the X-axis, and therefore do not overlap with each other relative to the X-axis. In some embodiments, Δ2 is greater than zero and less than the width of AR 416B_3 minus the sum of the widths of the two AR 416B_1 (e.g., ≥7δ).

[0155] Figure 5A This is a plan view of semiconductor device 502B according to some embodiments.

[0156] Semiconductor device 502B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 504B is an example of cell region 104. In some embodiments, AR 516B_1 is an HL portion, such as HL portion 106. In some embodiments, AR 416B_2 and 416B_3 are LL portions, such as LL portion 108.

[0157] Semiconductor devices 502B, 502BA, 502BB, 502BC, and 502BD are Figure 4A A variant of the 402B semiconductor device. For the sake of simplicity, conciseness, and reduced repetition, Figures 5A-5E The discussion is limited to semiconductor device 402B and Figures 5A-5E The differences between semiconductor devices 502B, 502BA, 502BB, 502BC, and 502BD. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0158] exist Figure 5Ain, the cell region 504B includes cell regions 504_BA and 504_BB. Each of cell regions 504_BA and 504_BB includes portions of AR 416B_2 and 416B_3, and AR 516B_1. Cell region 504B includes upper AR 416B_3 and lower AR 416B_3, each AR extending from a first hypothetical reference line 418A to a second hypothetical line 420A. Each of AR 416B_2 and 416B_3 has a height of H_1, AR 516B_1 has a height of H_4, and wherein H_1 < H_4. In some embodiments, H_3( Figures 4A-4E ) is less than H_4, i.e., H_3 < H_4.

[0159] In Figure 5A , AR 416B_2 and AR 516B_1 are grouped into an AR set 546. In some embodiments, the AR set 546 forms an I-shape or an I-support, the I-support having two or more upper AR 416B_2 forming the upper horizontal portion of the I-support, AR 516B_1 forming the vertical portion of the I-support, and two or more lower AR 416B_2 forming the lower horizontal portion of the I-support.

[0160] In Figure 5A , relative to the Y-axis, the upper edge 550 of AR 516B_1 extends upward to align with the middle portion of upper AR 416B_2 and is within the range R_2 of the upper edge 551 of upper AR 416B_2. Relative to the Y-axis, the lower edge 550A of AR 516B_1 extends downward to align with the middle portion of lower AR 416B_2 and is within the range R_2 of the lower edge 551A of lower AR 416B_2. In Figure 5A , the AR set 546 is a concave arrangement of ARs along upper edge 550 and upper edge 551, and is a concave arrangement of ARs along lower edge 550A and lower edge 551A. In some embodiments, the concave AR set 546 is an AR arrangement where all ARs are not fully projected. The cell region 504B has all ARs not fully projected. In Figure 5A , relative to the Y-axis, AR 516B_1 is arranged symmetrically with respect to AR 416B_2. In some embodiments, relative to the Y-axis, AR 516B_1 is arranged asymmetrically with respect to AR 416B_2 (e.g. Figures 7A-7B , Figures 8A-8B , Figures 9A-9B , Figures 10A-10B , Figures 11A-11B , Figures 12A-12B , Figure 13 , Figure 14 etc.).

[0161] Cell region 504B is configured according to design rules (9) and (10) to meet DRC.

[0162] 2·S_1+H_1≤H_4≤2·S_1+3·H_1 Rule (9)

[0163] Rule (10) is: S_1≤S_2≤S_1+H_1

[0164] Twice the distance S_1 between AR 416B_2 plus the height H_1 of AR416B_2 is less than or equal to the height H_4 of AR516B_1, and the height H_4 of AR516B_1 is less than or equal to three times the height H_1 of AR416B_2 plus twice the distance S_1 between AR416B_2. In some embodiments, the combination of twice and a half times the height H_1 and twice and a half times the distance S_1 corresponds to the height of a cell region (e.g., cell region 504_BA). In some embodiments, the height of a cell region is greater than or equal to the maximum AR in the cell (e.g., AR 516B_1), and the maximum AR is greater than or equal to the distance between the minimum ARs in cell region 504B (e.g., AR 416B_2 and 416B_3) or the minimum distance in cell region 504B (i.e., S_1). In some embodiments, S_1 is the minimum distance between AR 416B_2 and 416B_3 in cell region 504B. Figure 5A In this embodiment, AR 416B_2 has a width of 4δ relative to the X-axis, while AR 516B_1 has a width of 3δ. In some embodiments, AR 516B_1 has a width greater than 3δ. In some embodiments, other applicable heights and widths of AR 416B_2, 416B_3, and 516B_1 are within the scope of this disclosure.

[0165] Figures 5B-5E This is a plan view of semiconductor devices 502BA, 502BB, 502BC and 502BD according to some embodiments.

[0166] Correspondingly Figures 5B-5E The semiconductor devices 502BA, 502BB, 502BC and 502BD are Figure 5A A variant of the 502B semiconductor device. For the sake of simplicity and to reduce repetition, Figures 5B-5E Due to the differences between semiconductor device 502B and semiconductor devices 502BA, 502BB, 502BC, and 502BD, identical components retain their reference numbers, while new or different components are designated with different reference numbers.

[0167] exist Figure 5BIn this context, cell region 504BA comprises two AR sets 546. Cell region 504BA includes cell regions 504_BA, 504_BB, and 504_BC. Each of cell regions 504_BA and 504_BC includes two complete AR 416, two half AR416B_2, one AR 416B_3, and one half AR 516B_1. Cell region 504_BB includes four complete AR 416B_2, four half AR 516B_1, and two half AR 516B_1. Upper instances of AR 516B_1 extend from cell region 504_BB to cell region 504_BA. Lower instances of AR 516B_1 extend from cell region 504_BB to cell region 504_BC.

[0168] Configure unit area 504BA according to design rules (9), (10) and (11) to meet DRC.

[0169] Rule (11) is: S_1≤S_3≤S_1+2·H_1

[0170] In some embodiments, the height of each of the cell regions 504_BA, 504_BB and 504_BC is defined by design rule (12) or (13) or (14).

[0171] 2 1 / 2·S1+2 1 / 2·H_1 Rule (12)

[0172] Rule (13) is 1 / 2S_1 + S_2 + H1 + 1 / 2H_4

[0173] S_3+H_3 rule (14)

[0174] exist Figure 5C In the context, cell region 504BB includes N AR sets 546 (where N is a non-negative integer). Figure 5C In this context, each AR set 546 includes one AR 516B_1 instance and six corresponding AR 416B_2 instances. Figure 5C In this case, N≥3.

[0175] exist Figure 5D In this embodiment, cell region 504BC includes two AR sets 546, wherein instances of AR 516B_1 are configured with different widths (e.g., the lower AR 516B_1 is configured with a width of approximately 4δ and the upper AR 516B_1 is configured with a width of approximately 3δ). In some embodiments, other suitable positions of the various instances of AR 516B_1 are within the scope of this disclosure. AR 516B_1 overlaps with a distance Δ3 relative to the X-axis. In some embodiments, Δ3 is a distance greater than zero and up to and including the minimum width of any instance of AR 516B_1.

[0176] Figure 5E similar to Figure 5D . In Figure 5E , the ARs 516B_1 are offset from each other by a distance Δ4. In some embodiments, Δ4 is greater than zero and less than the sum of the width of AR 416B_3 minus the widths of the two ARs 516B_1 (e.g., ≥7δ).

[0177] Figure 6A is a plan view of a semiconductor device 602B in accordance with some embodiments.

[0178] Semiconductor device 602B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 604B is an example of cell region 104. In some embodiments, ARs 416B_2 and 416B_3 are LL portions, such as LL portion 108. In some embodiments, AR 616B_1 is an HL portion, such as HL portion 106.

[0179] corresponding Figures 6A-6C semiconductor devices 602B, 602BA and 602BB are Figure 4A variants of semiconductor device 402B. For brevity, conciseness and reduced redundancy, Figures 6A-6C the discussion is limited to the differences between semiconductor device 402B and Figures 6A-6C semiconductor devices 602B, 602BA and 602BB. Furthermore, for the sake of brevity and conciseness, and to reduce redundancy, references to intermediate cell regions within larger cell regions (e.g., cell region 604B) are omitted. However, embodiments of the present disclosure contemplate multiple intermediate cell regions within a larger cell region. Identical elements retain their reference numerals, while new or different elements are referred to by different reference numerals.

[0180] Cell region 604B includes ARs 416B_2, 416B_3 and AR 616B_1. Cell region 604B includes an upper AR 416B_3 and a lower AR 416B_3, each AR extending from first imaginary reference line 418B to second imaginary line 420B, where imaginary lines 418B and 420B are parallel to the Y-axis. Each of ARs 416B_2 and 416B_3 has a height H_1. AR 616B_1 has a height H_5, where H_1<H_5. In some embodiments, H_4( Figures 5A-5E)is less than H_5, that is, H_4<H_5. AR 416B_2 and 616B_1 are grouped into an AR set 646. In some embodiments, the AR set 646 forms an I-shape or an I-frame, where the I-frame has two or more upper ARs 416B_2 forming the upper horizontal portion of the I-frame, the AR 616B_1 forming the central vertical portion of the I-frame, and two or more lower ARs 416B_2 forming the lower horizontal portion of the I-frame.

[0181] In Figure 6A , relative to the Y-axis, the top edge 650 of AR 616B_1 extends upward to align with the bottom edge 653 of the topmost AR 616B_2 and is within the range R_3 of the bottom edge 653 of AR 416B_2. That is, the top edge 650 does not extend above the bottom edge 653 of the topmost AR 416B_2, but is flush with the bottom edge 653 of AR 416B_2. In some embodiments, the top edge 650 of AR 616B_1 is lower than the bottom edge 653 of the topmost AR 416B_2. Relative to the Y-axis, the bottom edge 650A of AR 606_B extends downward to align with the top edge 653A of the bottommost AR 416B_2. In some embodiments, the bottom edge 650A of AR 616B_1 is above the top edge 653A of the bottommost AR 416B_2. In some embodiments, R_3 is equal to H_1. In some embodiments, R_3 is greater than or less than H_1.

[0182] The height of a higher AR (e.g., AR 616B_1) relative to the Y-axis is H_5. The cell region 604B is configured to satisfy DRC in accordance with design rules (15) and (16). More specifically, design rule (15) configures the height H_5 in the form of a positive integer N, where N represents the number of instances of AR 416B_2 that are substantially completely overlapped by AR 616B_1 relative to the Y-axis.

[0183] N·S_1+(N-1)·H_1≤H_5≤N·S_1+(N+1)·H_1 Rule (15)

[0184] S_1≤S_2≤S_1+H_1 Rule (16)

[0185] Figure 6B is a plan view of a semiconductor device 602BA in accordance with some embodiments.

[0186] Figure 6B The semiconductor device 602BA of Figure 6A is a variant of the semiconductor 602A, and a discussion of the differences between semiconductor 602BA and semiconductor 602A is included. Similarities between the two semiconductor devices are omitted to eliminate redundancy and provide clarity.

[0187] The lower edge 650A of AR616B_1 is aligned with the lower edge 651A of the lowest AR 416B_2. The upper edge 650 of AR 616B_1 is aligned with the upper edge 651 of the highest AR 416B_2. Furthermore, compared to semiconductor device 602B in which AR 616B_1 and its corresponding AR 416B_3 are separated by a distance S_2, AR 616B_1 and its corresponding AR 416B_3 are separated by a distance S_1.

[0188] Figure 6C This is a plan view of semiconductor device 602BB according to some embodiments.

[0189] Figure 6C The semiconductor device 602BB is Figure 6A Variations of semiconductor 602B are described, and a discussion of the differences between semiconductor 602BB and semiconductor 602A is included. Similarities between the two semiconductor devices are omitted to avoid redundancy and provide clarity.

[0190] Figure 6C Cell region 604BB includes two AR 606B_1 instances and two AR sets 646. Cell region 604BB is configured to meet DRC requirements according to design rules (15), (16) and (17).

[0191] Rule (17) is: S_1≤S_3≤S_1+2·H_1

[0192] Figure 7A This is a plan view of a semiconductor device 702B according to some embodiments.

[0193] Semiconductor device 702B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 704B is an example of cell region 104. In some embodiments, AR 716B_1 is an HL portion, such as HL portion 106. In some embodiments, AR 416B_2 and 416B_3 are LL portions, such as LL portion 108.

[0194] Correspondingly Figures 7A-7B The semiconductor devices 702B and 702BA are Figure 4A A variant of the 402B semiconductor device. For the sake of simplicity, conciseness, and reduced repetition, Figures 7A-7B The discussion is limited to semiconductor device 402B and Figures 7A-7B The difference between semiconductor devices 702B and 702BA. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0195] exist Figure 7AIn this context, AR 416B_2 and 716B_1 are grouped into AR set 746. Figure 7A Similar to Figure 4A For example, each includes an instance of an I-bracket. Figure 7A In the image, when an observer scans from left to right parallel to the X-axis, there are two contours: a first contour and a second contour. Relative to the Y-axis, the first contour is located at the top of the I-bracket, and the second contour is located at the bottom of the I-bracket. The first contour is formed by the upper edge 751 of upper AR 416B_2 and the upper edge 750 of AR 76B_1, and is... Figure 4A The concave first contour is the same as that in the middle. Figure 7A The second contour is different Figure 4A The second contour. When the observer is at Figure 7A When scanning from left to right parallel to the X-axis, the second contour is formed by the lower edge 751A of AR 416B_2 and the lower edge 750A of AR 716B_1. Figure 7A In the middle, the lower edge 751A of AR 416B_2 and the lower edge 750A of AR 716B_1 are basically collinear, making the second profile a straight line. Figure 4A The second contour is concave because the lower edge 450A of AR 716B_1 is recessed above the lower edge 451A of the upper AR 416B_2. Figure 7A In the image, AR 716B_1 is arranged asymmetrically relative to AR 416B_2 with respect to the Y-axis. The upper portion 750 of AR 716B_1 extends upward and is within the range R_4 of the uppermost edge 751 of the upper AR 416B_2. The cell region 704B is not fully projected. More specifically, each of the recessed first profile and the straight second profile is the result of the corresponding AR incomplete projection. The first profile has a recess depth or offset R_4.

[0196] Relative to the Y-axis: AR 716B_1 is separated from the upper AR 416B_3 and the lower AR 416B_3 by a distance S_4; AR 416B_2 is separated from each other by a distance S_1; AR 416B_2 is separated from the corresponding AR 416B_3 by a distance S_1; AR 416B_2 and 416B_3 have a height H_1; AR 716B_1 has a height H_6. The cell area 704B is configured to meet DRC requirements according to design rules (18), (19), and (20).

[0197] 0≤R_4≤S_1+H_1 Rule (18)

[0198] Rule (19) is H_1≤H_6≤S_1+2H_1

[0199] S_4=S_1+R_4 Rule (20)

[0200] Relative to the Y-axis, the distance R_4 between the upper edges 750 and 751 is greater than or equal to 0 and less than or equal to the height H_1 plus the distance S_1. The height H_1 of AR 416B_2 is less than or equal to the height H_6 of AR 716B_1, and the height H_6 is less than or equal to the distance S_1 plus twice the height H_1. In some embodiments, the widths of AR 416B_2 and 416B_3 relative to the X-axis are at least 3δ. In some embodiments, the width of AR 716B_1 is less than 3δ. In some embodiments, other applicable heights and widths of AR 416B_2, 416B_3, and 716B_1 are within the scope of this disclosure.

[0201] Figure 7B This is a plan view of a semiconductor device 702BA according to some embodiments.

[0202] Figure 7B The semiconductor device 702BA is Figure 7A A variant of the 702B semiconductor device. For the sake of simplicity, conciseness, and reduced repetition, Figure 7B The discussion is limited to the differences between semiconductor device 702B and semiconductor device 702BA. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0203] Figure 7B Includes two AR sets, 746. Figure 7B Similar to Figure 4B For example, each includes an upper I-bracket and a lower I-bracket. Figure 7B The upper I-bracket in the middle is similar to Figure 7A The I-stent in the middle. Relative to Figure 7B The axis of symmetry between the upper I-bracket and the lower I-bracket is such that the lower I-bracket is mirror-symmetrical with respect to the upper I-bracket.

[0204] exist Figure 7B In this configuration, relative to the Y-axis, the first contour of the lower I-shaped bracket is above the second contour of the lower I-shaped bracket. More specifically, the first / upper contour of the lower I-shaped bracket corresponds to the second / lower contour of the upper I-shaped bracket, and the second / lower contour of the lower I-shaped bracket corresponds to the first / upper contour of the upper I-shaped bracket. Each of the first / upper contour of the upper I-shaped bracket and the second / lower contour of the lower I-shaped bracket is concave. Each of the second / lower contour of the upper I-shaped bracket and the first / upper contour of the lower I-shaped bracket is a straight line.

[0205] Figure 8A This is a plan view of a semiconductor device 802B according to some embodiments.

[0206] Figure 8A Similar to Figure 7A For example, each includes an instance of an I-bracket. Figure 8A In the image, when an observer scans from left to right parallel to the X-axis, there are two contours: a first contour and a second contour. Relative to the Y-axis, the first contour is located at the top of the I-bracket, and the second contour is located at the bottom of the I-bracket. The first contour is formed by the upper edge 851 of AR 416B_2 and the upper edge 850 of AR 86B_1, and is... Figure 7A The concave first contour is the same as that in the middle. Figure 8A The second contour is different Figure 7A The second contour. When the observer is at Figure 8A When scanning from left to right parallel to the X-axis, the second contour is formed by the lower edge 851A of AR 416B_2 and the lower edge 850A of AR 816B_1. Figure 8A In the middle, relative to the Y-axis, the lower edge 850A of AR 816B_1 extends below the lower edge 851A of the lower AR 416B_2, making the second profile convex because the lower edge 850A of AR 816B_1 protrudes below the lower edge 851A of the lower AR 416B_2. Figure 7A The second contour in the image is a straight line, while... Figure 4A The second contour in the image is convex. Figure 8A In the diagram, AR 816B_1 is arranged asymmetrically relative to AR 416B_2 with respect to the Y-axis. The upper part 850 of AR 816B_1 extends upward and is within the range R_4 of the uppermost edge 851 of the upper AR 416B_2. The cell region 804B is not fully projected.

[0207] Semiconductor device 802B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 804B is an example of cell region 104. In some embodiments, AR 816B_1 is an HL portion, such as HL portion 106. In some embodiments, AR 416B_2 and 416B_3 are LL portions, such as LL portion 108.

[0208] Correspondingly Figures 8A-8B The semiconductor devices 802B and 802BA are Figure 4A A variant of the 402B semiconductor device. For the sake of simplicity, conciseness, and reduced repetition, Figures 8A-8B The discussion is limited to semiconductor device 402B and Figures 8A-8B The difference between semiconductor devices 802B and 802BA. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0209] AR416B_2 and 816B_1 are grouped into AR set 846. Relative to the Y-axis, the upper edge 850 of AR 816B_1 extends upwards and is within the range R_5 of the upper edge 851 of the upper AR 416B_2. The lower edge 850A of AR 816B_1 extends a distance R_6 below the lower edge 851A of the lower AR 416B_2. Furthermore, relative to the Y-axis, AR 816B_1 is asymmetrically located between the upper AR 416B_2 and the lower AR 416B_2. Cell region 804B is an incomplete projection. More specifically, each of the concave first contour and the convex second contour is the result of a corresponding incomplete AR projection. The first and second contours have corresponding depths or offsets R_5 and R_6.

[0210] Relative to the Y-axis: the distance between AR 816B_1 and the upper AR 416B_3 is S_4; the distance between AR 816B_1 and the lower AR416B_3 is S_5; AR 416B_2 and AR 416B_3 have a height H_1; AR 816B_1 has a height H_7. The cell area 804B is configured to meet DRC requirements according to design rules (21), (22), (23), (24), and (25).

[0211] 0≤R_5≤S_1+H_1 Rule (21)

[0212] 0≤R_6≤S_1 Rule (22)

[0213] H_1≤H_7≤S1+2H_1+R_6 Rule (23)

[0214] S_4=S_1+R_5 Rule (24)

[0215] S_5 = S_1 - R_6 Rule (25)

[0216] The distance R_5 between the upper edges 850 and 851 is greater than or equal to 0 and less than or equal to H_1 plus S_1. The distance R_6 between the lower edges 850A and 851A is greater than or equal to 0 and less than or equal to S_1. The height H_1 is less than or equal to the height H_7, and H_7 is less than or equal to S_1 plus twice H_1 plus R_6. In some embodiments, the width of AR 416B_2 and 416B_3 relative to the X-axis is at least 3δ. In some embodiments, AR 816B_1 is less than 3δ. In some embodiments, other applicable heights and widths of AR 416B_2, 416B_3, and 816B_1 are within the scope of this disclosure. In some embodiments, the distance between the lower AR 416B_3 and AR 816B_1 is S_5, where S_5 represents the minimum distance allowed by DRC.

[0217] Figure 8B This is a plan view of a semiconductor device 802BA according to some embodiments.

[0218] Figure 8B The semiconductor device 802BA is Figure 8A A variant of the 802B semiconductor device. For simplicity, conciseness, and to reduce repetition, Figure 8B The discussion is limited to the differences between semiconductor device 802B and semiconductor device 802BA. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0219] exist Figure 8B In the middle, unit area 804BA includes two AR sets 846. Figure 8B Similar to Figure 7B For example, each includes an upper I-bracket and a lower I-bracket. Figure 8B The upper I-bracket in the middle is similar to Figure 8A The I-stent in the middle. Relative to Figure 8B The axis of symmetry between the upper I-bracket and the lower I-bracket is such that the lower I-bracket is mirror-symmetrical with respect to the upper I-bracket.

[0220] exist Figure 8B In this configuration, relative to the Y-axis, the first contour of the lower I-shaped bracket is above the second contour of the lower I-shaped bracket. More specifically, the first / upper contour of the lower I-shaped bracket corresponds to the second / lower contour of the upper I-shaped bracket, and the second / lower contour of the lower I-shaped bracket corresponds to the first / upper contour of the upper I-shaped bracket. Each of the first / upper contour of the upper I-shaped bracket and the second / lower contour of the lower I-shaped bracket is concave. Each of the second / lower contour of the upper I-shaped bracket and the first / upper contour of the lower I-shaped bracket is convex.

[0221] The AR 816B_1 is spaced S_6 relative to the Y-axis. The cell area 804BA is configured to meet DRC according to design rules (21), (22), (23), (24) and (25) (see above) and according to design rule (26).

[0222] S6 = S_1 - 2R_6 Rule (26)

[0223] The distance S_6 is equal to S_1 minus twice R_6, where R_6 is as follows. Relative to the Y-axis: the lower edge 850A of the upper AR 816B_1 extends a distance R_6 below the lower edge 851A of the corresponding AR 416B_2 of the upper I bracket; and the upper edge 850 of the lower AR 816B_1 extends a distance R_6 above the upper edge 851 of the corresponding AR 416B_2 of the upper I bracket.

[0224] Figure 9A This is a plan view of a semiconductor device 902B according to some embodiments.

[0225] Semiconductor device 902B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 904B is an example of cell region 104. In some embodiments, AR 916B_1 and 916B_2 are HL portions, such as HL portion 106. In some embodiments, AR 416B_2 is an LL portion, such as LL portion 108.

[0226] Correspondingly Figure 9A and Figure 9B The semiconductor devices 902B and 902BA are Figure 4C A variant of the 402BB semiconductor device. For the sake of simplicity, conciseness, and reduced repetition, Figures 9A-9B The discussion is limited to Figure 4C Semiconductor device 402BB and Figures 9A-9B The difference between semiconductor devices 902B and 902BA. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0227] Cell region 904B includes AR set 947 and corresponding upper and lower sets 946 for AR. Set 947 is similar to... Figure 4B Each of set 446, such as set 947, forms the I-bracket. Each set 946 is different from... Figure 4B The sets 446 differ in that, for example, each set 946 forms a T-shape or T-bracket. Relative to the Y-axis, the upper set 946 has a face-up orientation or T-bracket, while the lower set 946 has an inverted T-bracket orientation. In some embodiments, relative to the Y-axis, the upper set 946 is sufficiently close to set 947 such that the upper set 946 is considered to share an upper instance of AR 416B_2 of set 947, thus the upper set 946 is considered to form an I-bracket. In some embodiments, relative to the Y-axis, the lower set 946 is sufficiently close to set 947 such that the lower set 946 is considered to share a lower instance of AR 416B_2 of set 947, thus the lower set 946 is considered to form an I-bracket.

[0228] AR 416B_2, AR 916B_1, and AR916B_1. Relative to the X-axis, AR 916B_1 is separated from its counterparts AR 416B_2 and 416B_1 by a corresponding isolation dummy gate 944B, which occupies the corresponding intermediate region 926B. The isolation dummy gate 944B extends from reference line 932BT to 932BB. Due to each of the isolation dummy gates 944B, AR 416B_2 and... Figure 9A Each of the 916B_1 values ​​is an incomplete projection.

[0229] Relative to the Y-axis and viewed from the center position in cell region 902B, each of the upper and lower contours of set 947 is concave. Relative to the center position in cell region 902B, the upper contour of upper set 946 includes the outer edge 960 of the corresponding uppermost AR 416B_2 and the outer edge 963 of upper AR 916B_1. The upper contour of upper set 946 is a straight line. Relative to the center position in cell region 902B, the lower contour of lower set 946 includes the outer edge 960 of the corresponding lowermost AR 416B_2 and the outer edge 963 of lower AR 916B_1. The lower contour of lower set 946 is a straight line.

[0230] Relative to the center position in cell region 902B, the lower contour of upper set 946 includes the inner edge 962 of uppermost AR 416B_2 and the inner edge 961 of upper AR 916B_1. Relative to the Y-axis and viewed from the center position in cell region 902B, the lower contour of upper set 946 is convex. Relative to the center position in cell region 902B, the upper contour of lower set 946 includes the inner edge 962 of lowermost AR 416B_2 and the inner edge 961 of lower AR 916B_1. Relative to the Y-axis and viewed from the center position in cell region 902B, the lower contour of lower set 946 is convex.

[0231] Relative to the Y-axis: AR 916B_1 of set 947 is separated from AR 916B_1 of the corresponding upper set 946 and lower set 946 by a distance S_7; AR 416B_2 is separated from each other by a distance S_1; AR 416B_2 has a height H_1; AR 916B_1 of the upper set 946 and lower set 946 has a height H_8; and AR916B_1 of set 947 has a height H_9. Unit area 904B is configured to meet DRC according to design rules (27), (28), (29), (30), and (31).

[0232] 0≤R_7≤S_1 Rule (27)

[0233] H_8 = H_1 + R_7 Rule (28)

[0234] Rule (29) is S_1≤H_9≤S1+2H_1

[0235] Rule (30) is: S_1≤S_7≤S_1+H_1

[0236] Rule (31) is: S_1≤S_8≤S_1+2H_1

[0237] Relative to the Y-axis, distance R_7 lies between inner edges 962 and 961 and is greater than or equal to 0 but less than or equal to S_1. Relative to the Y-axis, the height H_8 of AR 916B_1 in set 947 is equal to R_7 plus H_1. Relative to the Y-axis, the height H_9 of AR 916B_1 in each set 946 is greater than or equal to S_1 but less than or equal to H_1 plus twice S_1. Relative to the Y-axis, distance S_7 lies between AR 916B_1 in set 947 and each AR 916B_1 in set 946 and is greater than or equal to S_1 but less than or equal to H_1 plus S_1. In some embodiments, each AR 916B_1 is less than 3δ relative to the X-axis. In some embodiments, AR 416B_2 is greater than 3δ relative to the X-axis. In some embodiments, other applicable heights and widths of AR 416B_2, 916B_1, and 916C are within the scope of this disclosure.

[0238] Figure 9B This is a plan view of a semiconductor device 902BA according to some embodiments.

[0239] Figure 9B The 902BA semiconductor device's cell region 904BA is similar to Figure 9A The cell region 904B of the semiconductor device 902B, however, with Figure 9A In comparison, cell region 904BA includes an additional AR set 947. The AR 916B_1 separation distance S_8 between the corresponding upper and lower sets 947 relative to the Y-axis is greater than or equal to S_1 but less than or equal to S_1 plus twice H_1.

[0240] Figure 10A This is a plan view of a semiconductor device 1002B according to some embodiments.

[0241] Semiconductor device 1002B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 1004B is an example of cell region 104. In some embodiments, AR 1016B_1 is an HL portion, such as HL portion 106. In some embodiments, AR 416B_2 is an LL portion, such as LL portion 108.

[0242] Correspondingly Figure 10A and Figure 10B The semiconductor devices 1002B and 1002BA are Figure 9A A variant of the 902B semiconductor device. For the sake of simplicity, conciseness, and reduced repetition, Figures 10A-10B The discussion is limited to semiconductor devices 902B and Figures 10A-10BThe difference between semiconductor devices 1002B and 1002BA. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0243] Cell region 1004B includes AR 416B_2 and AR 1016B_1. AR 416B_2 and AR 1016B_1 are separated by corresponding isolation dummy gates 1044B occupying the respective intermediate region 1026B. The isolation dummy gates 1044B extend from reference line 1032BT to 1032BB. Due to each of the isolation dummy gates 1044B, Figure 10A Each of AR 416B_2 and 1016B_1 is an incomplete projection.

[0244] exist Figure 10A In the middle, unit region 1004B includes AR set 1047 and corresponding upper set 1046 and lower set 1046. Figure 10A Similar to Figure 9A Each set of 1046 is similar to Figure 9A Each set of 946, similar to, for example, each set of 1046 forming a T-bracket, Figure 10A The arrangement of the upper set 1046 is similar to Figure 9A The upper set 946, Figure 10A The arrangement of the lower set 946 is similar to Figure 9A The lower set is 946. Relative to the Y-axis, the lower edge of AR 1016B_1 in the upper set 1046 extends a distance R_8 below the lower edge of AR 416B_2 in the upper set 1046. Relative to the Y-axis, the upper edge of AR 1016B_1 in the lower set 1046 extends a distance R_8 above the lower edge of AR 416B_2 in the lower set 1046.

[0245] exist Figure 10A In the middle, set 1047 is similar to Figure 9A The set 947 is similar in that, for example, set 1047 forms an I-bracket. Nevertheless, Figure 10A The arrangement of set 1047 can still be different. Figure 9A The arrangement of set 947. For example, relative to the upper edge of the Y-axis, Figure 9A The upper edge of AR 916B_1 in set 947 lies between the upper edges of AR 416B_2 in set 947, and Figure 10A The upper edge of AR 1016B_1 of set 1047 does not overlap with the lower edge of upper AR 416B_2 of set 1047, but remains below the lower edge of upper AR 416B_2 of set 1047 by a distance R_9. Furthermore, for example, relative to the Y-axis, Figure 9AThe lower edge of AR 916B_1 in set 947 lies between the upper edge of the lower AR 416B_2 in set 947, and Figure 10A The lower edge of AR 1016B_1 of set 1047 does not overlap with the upper edge of the lower AR 416B_2 of set 1047, but remains above the upper edge of the lower AR 416B_2 of set 1047 by a distance R_9.

[0246] Relative to the Y-axis: AR 416B_2 are separated from each other by a distance S_1; AR 1016B_1 of set 1047 is separated from the corresponding AR 1016B_1 of upper set 1046 and lower set 1046 by a distance S_9; AR 416B_2 has a height H_1; AR 1016B_1 of upper set 1046 and lower set 1046 has a height H_10; and AR 1016B_1 of set 1047 has a height H_11. Unit area 1004B is configured to meet DRC according to design rules (32), (33), (34), (35), and (36).

[0247] 0≤R_8≤S_1 Rule (32)

[0248] 0≤R_9≤S_1 / 2 Rule (33)

[0249] H_10=H_1+R_8 Rule (34)

[0250] Rule (35) H_1≤H_11≤S_1

[0251] S_9=S_1+H_1+R_9 Rule (36)

[0252] Figure 10B This is a plan view of a semiconductor device 1002BA according to some embodiments.

[0253] The cell region 1004BA of semiconductor device 1002BA is an example of cell region 904B of semiconductor device 902B; however, compared with... Figure 10A In contrast, cell region 104BB includes an additional AR set 1047. The AR 1016B_1 separation distance S_10 between the corresponding upper set 1047 and lower set 1047 is equal to distance S_1 plus twice H_1 plus twice S_9.

[0254] S_10=S_1+2H_1+2R_9 Rule (37)

[0255] Figure 11A This is a plan view of semiconductor device 1102B according to some embodiments.

[0256] Semiconductor device 1102B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 1104B is an example of cell region 104. In some embodiments, AR 1116B_1 is an HL portion, such as HL portion 106. In some embodiments, AR 416B_2 is an LL portion, such as LL portion 108.

[0257] Correspondingly Figure 11A and Figure 11B The semiconductor devices 1102B and 1102BA are corresponding Figure 9A and Figure 9B Variants of the 902B and 902BA semiconductor devices. For the sake of simplicity, conciseness, and reducing redundancy, Figures 11A-11B The discussion is limited to Figure 9A and Figure 9B The semiconductor devices 902B and 902BA in Figures 11A-11B The differences between semiconductor devices 1102B and 1102BA. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0258] Cell region 1104B includes AR 416B_2 and AR 1116B_1. AR 416B_2 and AR 1016B_1 are separated by corresponding isolation dummy gates 1144B occupying the respective intermediate region 1126B. The isolation dummy gates 1144B extend from reference line 1132BT to 1132BB. Due to each of the isolation dummy gates 1144B, AR 416B_2 and Figure 11A Each of the 1116B_1 values ​​is an incomplete projection.

[0259] Unit region 1104B includes AR set 1147 and corresponding upper set 1146 and lower set 1146. Figure 11A Similar to Figure 9A Each of sets 946, for example, forms an I-bracket. Examples of differences between sets 1147 and 947 include: relative to the Y-axis, the upper edge of AR1116B_1 in set 1147 extends above the upper edge of upper AR416B_2 in set 1147, while the upper edge of AR916B-1 in set 947 extends between the upper and lower edges of upper AR416B_2 in set 947; and, relative to the Y-axis, the lower edge of AR1116B_1 in set 1147 extends below the lower edge of lower AR416B_2 in set 1147, while the lower edge of AR916B-1 in set 947 extends between the upper and lower edges of lower AR416B_2 in set 947.

[0260] exist Figure 11AIn the middle, the upper set 1146 and the lower set 1146 are similar to Figure 9A The corresponding upper set 946 and lower set 946. Examples of differences between upper set 1146 and upper set 946 include: upper set 1146 forms a U-shape or U-bracket, while upper set 946 forms a T-shape; relative to the Y-axis, the lower edge of AR 1160B_1 of upper set 1146 lies between the upper and lower edges of AR 416B_2 of upper set 1146, while... Figure 9A The lower edge of AR 916B_1 in the upper set 946 is at Figure 9A The lower edge of AR 916B_2 in the upper set 946 extends below the lower edge; viewed from the center of cell region 1102B / 902B, the lower contour of the upper set 1146 is concave relative to the Y-axis, while the lower contour of the upper set 946 is convex. Examples of differences between the lower sets 1146 and 946 include: the lower set 1146 forms a U-shaped support, while the lower set 946 forms a T-shaped support; and relative to the Y-axis, the upper edge of AR 1160B_1 in the lower set 1146 lies between the upper and lower edges of AR 416B_2 in the lower set 1146, while... Figure 9A The upper edge of AR 916B_1 in the lower set 946 is at Figure 9A The upper edge of AR 416B_2 of the lower set 946 extends above it; viewed from the center of cell region 1102B / 902B, the upper contour of the lower set 1146 is concave relative to the Y-axis, while the upper contour of the lower set 946 is convex.

[0261] Relative to the Y-axis, the lower edge of AR1116B_1 in the upper set 1146 is recessed by a distance R_10 above the lower edge of AR416B_2 in the upper set 1146. Relative to the Y-axis, the upper edge of AR1116B_1 in the lower set 1146 is recessed by a distance R_10 below the upper edge of AR416B_2 in the lower set 1146. Relative to the Y-axis, the upper edge of AR1116B_1 in set 1147 extends by a distance R_11 above the upper edge of AR416B_2 in set 1147. Relative to the Y-axis, the lower edge of AR1116B_1 in set 1147 extends by a distance R_11 below the lower edge of AR416B_2 in set 1147.

[0262] Relative to the Y-axis: AR 1116B_1 of set 1147 is separated from AR1116B_1 of the corresponding upper set 1146 and lower set 1146 by a distance S_1; AR 3416B_2 is separated from each other by a distance S_1; AR 416B_1 has a height H_1; AR 1116B_1 of the upper and lower sets 1146 has a height H_12; and AR1116B_1 of set 1147 has a height H_13. Unit area 1104B is configured to satisfy DRC according to design rules (38), (39), (40), (41), and (42).

[0263] 0≤R_10≤H_1 Rule (38)

[0264] 0≤R_11≤S_1 Rule (39)

[0265] H_12 = H_1 - R_10 Rule (40)

[0266] H_13=S_1+2H_1+2R_11 Rule (41)

[0267] S_11=S_1+R_10 Rule (42)

[0268] Figure 11B This is a plan view of a semiconductor device 1102BA according to some embodiments.

[0269] The cell region 1104BA of semiconductor device 1102BA is an example of cell region 1104B of semiconductor device 1102B; however, compared with... Figure 11A In comparison, cell region 1104BA includes an additional AR set 947. The AR 1116B_1 separation distance S_12 between the corresponding upper set 1147 and lower set 1147 relative to the Y-axis is S_12. Distance S_12 is equal to distance S_1 minus twice R_11.

[0270] S_12=S_1-2R_11 Rule(43)

[0271] Figure 12A This is a plan view of a semiconductor device 1202B according to some embodiments.

[0272] Cell region 1204B includes AR 416B_2 and AR 1216B_1. AR 416B_2 and AR 1216B_1 are separated by corresponding isolation dummy gates 1244B occupying the respective intermediate region 1226B. The isolation dummy gates 1244B extend from reference line 1232BT to 1232BB. Due to each of the isolation dummy gates 1244B, Figure 12A Each of AR 416B_2 and 1216B_1 is an incomplete projection.

[0273] Semiconductor device 1202B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 1204B is an example of cell region 104. In some embodiments, AR 1216B_1 is an HL portion, such as HL portion 106. In some embodiments, AR 416B_2 is an LL portion, such as LL portions 416B_2 and 108.

[0274] Cell region 1204B includes AR set 1247 and corresponding upper set 1246 and lower set 1246 of AR. Figure 12A In the middle, cell region 1204B is similar to Figure 9A Unit area 904B. Figure 12A The upper set 1246 and the lower set 1246 are similar to Figure 9A The upper set 946 and the lower set 946. Figure 12A The set 1247 is similar to Figure 9A The set is 947. For the sake of brevity, simplicity, and reducing redundancy, Figures 12A-12B The discussion is limited to semiconductor devices 902B and Figures 12A-12B The difference between semiconductor devices 1202B and 1202BA. Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0275] Cell region 1204B includes AR 416B_2 and AR 1216B_1. Relative to the X-axis, AR 1216B_2 is separated from AR 1216B_1 by a corresponding isolation dummy gate 1244B, which occupies the corresponding intermediate region 1226B. The isolation dummy gate 1244B extends from reference line 1232BT to 1232BB. Due to each of the isolation dummy gates 1144B, Figure 12A Each of AR 416B_2 and 1216B_1 is an incomplete projection.

[0276] Relative to the Y-axis: AR 1216B_1 of set 1247 is separated from its corresponding AR1216B_1 of upper set 1246 and lower set 1246 by a distance S_13; AR 416B_2 of set 1247 is separated from each other by a distance S_15; AR 416B_2 of set 1247 is separated from its corresponding AR 416B_1 of upper set 1246 and lower set 1246 by a distance S_16; AR416B_2 of upper set 1246 and lower set 1246 has a height H_14; AR416B_2 of set 1247 has a height H_15; AR1216B_1 of upper set 1246 and lower set 1246 has a height H_16; and AR1216B_1 of set 1247 has a height H_17.

[0277] Relative to the Y-axis and viewed from the center position in cell 1204B: the lower edge of AR 1216B_1 of upper set 1246 extends below the lower edge of AR 416B_1 of upper set 1246; the upper edge of AR 1216B_1 of lower set 1246 extends above the upper edge of AR 416B_1 of lower set 1246.

[0278] Figure 12B This is a plan view of a semiconductor device 1202BA according to some embodiments.

[0279] Figure 12B The cell region 1204BA of the semiconductor device 1202BA is similar to the cell region 1204B of the semiconductor device 1202B; however, it is different from... Figure 12A In comparison, cell region 1204BA includes an additional AR set 1247. The AR 1216B_1 separation distance S_14 between the corresponding upper and lower sets 1247 relative to the Y-axis is greater than or equal to S_16, but less than or equal to S_16 plus twice H_15.

[0280] Units 1204B and 1204BA are configured as follows, according to the design rules related to the first, second, third, or fourth scenario:

[0281] In the first scenario where H_14=H_15 and S_15=S_16, then:

[0282] Rule (44) H_14≤H_16≤H_14+S_15

[0283] Rule (45) is: S_15≤H_17≤S_15+2H_14

[0284] Rule (46) is S_15≤S_13≤S_15+H_14

[0285] Rule (47) is S_15≤S_14≤S_15+2H_14

[0286] In the second scenario where H_14≠H_15 and S_15=S_16, then:

[0287] Rule (48) is: S_15≤H_17≤S_15+2H_15

[0288] Rule (49) is S_15≤S_13≤S_15+H_15

[0289] Rule (50) is: S_15≤S_14≤S_15+2H_15

[0290] In the third scenario where H_14=H_15 and S_15≠S_16, then:

[0291] Rule (51) H_14≤H_16≤H_14+S_16

[0292] Rule (52) is S_16≤S_13≤S_16+H_14

[0293] Rule (53) is S_16≤S_14≤S_16+2H_14

[0294] In the fourth scenario where H_14≠H_15 and S_15≠S_16, then:

[0295] Rule (54) is: S_15≤H_17≤S_15+2H_15

[0296] Rule (55) is: S_16≤S_13≤S_16+H_15

[0297] Rule (56) is S_16≤S_14≤S_16+2H_15

[0298] Figure 13 This is a plan view of semiconductor device 1302B according to some embodiments.

[0299] Figure 13 Similar to Figure 12A The main difference lies in the fifth scene. Figure 13 The design rules are different, and Figure 12A and Figure 12B The design rules involve the first scenario, the second scenario, the third scenario, and the fourth scenario.

[0300] Cell region 1304B includes AR 416B_2 and AR 1316B_1. AR 416B_2 and AR 1316B_1 are separated by corresponding isolation dummy gates 1344B occupying the respective intermediate region 1326B. The isolation dummy gates 1344B extend from reference line 1332BT to 1332BB. Due to each of the isolation dummy gates 1344B, Figure 13 Each of AR 416B_2 and 1316B_1 is an incomplete projection.

[0301] Semiconductor device 1302B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 1304B is an example of cell region 104. In some embodiments, AR 1316B_1, 1316B_3, and 1316_D are HL portions, such as HL portion 106. In some embodiments, AR 1316B_2 is an LL portion, such as LL portions 416B_2 and 108.

[0302] Cell region 1304B includes AR set 1347 and corresponding upper set 1346 and lower set 1346. In Figure 13 In the middle, cell region 1304B is similar to Figure 9A Unit area 904B. Figure 13 The upper set 1346 and the lower set 1346 are similar to Figure 9A The upper set 947 and the lower set 947. Figure 13 The set 1347 is similar to Figure 9A The set is 947. For the sake of brevity and to reduce repetition, Figure 13 The discussion is limited to (1) corresponding to Figure 12A and Figure 12B Semiconductor devices 1202B and 1202BA(2) Figure 12B The differences between semiconductor devices 1202B are as follows: Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0303] Cell region 1304B includes AR 416B_2 and AR 1316B_1. Relative to the X-axis, AR 1316B_1 is separated from AR 416B_2 by a corresponding isolation dummy gate 1344B, which occupies the corresponding intermediate region 1326B. The isolation dummy gate 1344B extends from reference line 1332BT to 1332BB.

[0304] Relative to the Y-axis: AR 1316B_1 of set 1347 is separated from its corresponding AR1316B_1 of upper set 1346 and lower set 1346 by a distance of S_22; AR 416B_2 of set 1347 is separated from each other by a distance of S_19; AR 416B_2 of set 1347 is separated from its corresponding AR 416B_2 of upper set 1346 and lower set 1346 by a distance of S_18; AR416B_2 of upper set 1346 and lower set 1346 has a height of H_18; AR416B_2 of set 1347 has a height of H_19; AR1316B_1 of upper set 1346 and lower set 1346 has a height of H_22; and AR1316B_1 of set 1347 has a height of H_23.

[0305] Relative to the Y-axis and viewed from the center position in cell 1304B: the lower edge of AR 1316B_1 of upper set 1346 extends below the lower edge of AR 416B_1 of upper set 1346; and the upper edge of AR 1316B_1 of lower set 1346 extends above the upper edge of AR 416B_1 of lower set 1346.

[0306] Unit 1304B is configured according to the design rules related to the fifth scenario, and the corresponding Figure 12A and Figure 12B Unit areas 1204B and 1204BA are configured according to the first, second, third, and fourth scenarios. In the fifth scenario, i.e., when H_18≠H_19≠H_20≠H_21 and S_17≠S_18≠S_19≠S_20≠S_21, then:

[0307] Rule (57) is: H_18≤H_22≤H_18+S_18

[0308] Rule (58) is: S_19≤H_23≤S_19+H_19+H_20

[0309] Rule (59) H_21≤H_24≤H_21+S_20

[0310] Rule (60) is S_18≤S_22≤S_18+H_19

[0311] Rule (61) is: S_20≤S_23≤S_20+H_20

[0312] Figure 14 This is a plan view of semiconductor device 1402B according to some embodiments.

[0313] Semiconductor device 1402B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, cell region 1404B is an example of cell region 104. In some embodiments, AR 1416B_1 is an HL portion, such as HL portion 106. In some embodiments, AR 416B_2 is an LL portion, such as LL portions 416B_2 and 108.

[0314] Cell region 1404B includes AR upper set 1447, AR lower set 1448, AR upper set 1446, and AR lower set 1449. Figure 14 In the middle, cell region 1404B is similar to Figure 9A Unit area 904B. Figure 14 The upper set 1446 is similar to Figure 9A The upper set is 946. Figure 14 The lower set 1449 is similar to Figure 9A The upper set is 946. Figure 14 The upper set 1447 is similar to Figure 9A The upper set is 947. Figure 14 The lower set 1448 is similar to Figure 9A The lower set is 947. For the sake of brevity and to reduce repetition, Figure 14 The discussion is limited to Figure 9A902B semiconductor devices and Figure 14 The differences between semiconductor devices 1402B are as follows: Similar components retain their reference numbers, while new or different components are labeled with different reference numbers.

[0315] Cell region 1404B includes AR 416B_2 and AR 1416B_1. AR 416B_2 is separated from AR corresponding to AR 1416B_1 by a corresponding isolation dummy gate 1444B occupying the corresponding intermediate region 1426B. The isolation dummy gate extends from reference line 1432BT to 1432BB. Due to each of the isolation dummy gates 1444B, AR 416B_2 and Figure 14 Each of the 1416B_1 values ​​is an incomplete projection.

[0316] Relative to the Y-axis: The separation distance between AR 1416B_1 of set 1446 and AR 1416B_1 of set 1447 is S_31; the separation distance between AR1416B_1 of set 1447 and AR1416B_1 of set 1448 is S_32; the separation distance between AR1416B_1 of set 1448 and AR1416B_1 of set 1449 is S_33; the separation distance between AR 416B_2 of set 1446 and its corresponding upper AR 416B2 of set 1447 is S_25; the separation distance between AR 416B_2 of set 1447 and each other is S_26; the separation distance between the lower AR 416B_2 of set 1447 and its corresponding upper AR 416B2 of set 1448 is S_27; the separation distance between AR 416B_2 of set 1448 and each other is S_28; the separation distance between the lower AR of set 1448... The separation distance between AR 416B_2 and the corresponding upper AR 416B2 in set 1449 is S_29; AR 416B_2 in set 1446 has a height H_25; the upper AR 416B_2 in set 1447 has a height H_26; the lower AR 416B_2 in set 1447 has a height H_27; the upper AR 416B_2 in set 1448 has a height H_28; the lower AR 416B_2 in set 1448 has a height H_29; and AR 416B_2 in set 1449 has a height H_30.

[0317] When H_25≠H_26≠H_27≠H_28≠H_29≠H_30 and S_24≠S_25≠S_26≠S_27≠S_28≠S_29≠S_30, then:

[0318] H_25≤H_31≤H_25+S_25 Rule (62)

[0319] S_26≤H_32≤S_26+H_26+H_27 Rule (63)

[0320] S_28≤H_33≤S_28+H_28+H_29 Rule (64)

[0321] H_30≤H_34≤H_30+S_29 Rule (65)

[0322] Rule (66) is: S_25≤S_31≤S_25+H_26

[0323] Rule (67) is: S_27≤S_32≤S_27+H_27+H_28

[0324] Rule (68) is S_29≤S_33≤S_29+H_29

[0325] Figure 15A This is a plan view of semiconductor device 1502B according to some embodiments.

[0326] Semiconductor device 1502B is an example of semiconductor device 102 and is configured for use within IC 100. In some embodiments, semiconductor device 1502B is a variant of semiconductor device 302B. In some embodiments, cell region 1504B is an example of cell region 104. In some embodiments, AR 1516B_1 is an HL portion, such as HL portion 106. In some embodiments, AR 416B_2 and 416B_3 are LL portions, such as LL portion 108.

[0327] exist Figure 15A In the middle, cell region 1504B includes AR 416B_2, 416B_3, and AR 1516B_1. AR 416B_2 is separated from AR 1516B_1 by its corresponding isolation dummy gate 1544B, which occupies the corresponding middle region 1526B. The upper left AR 1516B_1 and the lower left AR 1516B_1 share the left isolation dummy gate 1544B. The upper left AR 1516B_1, the lower left AR 1516B_1, and the middle right AR 1516B_1 share the middle isolation dummy gate 1544B.

[0328] The right-center AR1516B_1 is associated with the right isolation dummy gate 1544B, meaning that the right-center AR1516B does not share the right isolation dummy gate 1544B with another instance of AR1516B_1.

[0329] Cell area 1504B includes an uppermost AR 416B_3 and a lowermost AR 416B_3 extending from imaginary reference line 418A to imaginary line 420A. In some embodiments, the uppermost AR 416B_3 and the lowermost AR 416B_3 have different heights (see...). Figure 13Each of AR 416B_2 and 416B_3 has a height H_1 that is less than the height H_3 of AR 1516B_1. Figure 15A Each of the AR416B_3 displays as a full projection.

[0330] In some embodiments, the positions of AR 1516B_1 differ. In some embodiments, AR1516B_1 do not overlap relative to the X-axis. Figure 15A In the middle, relative to the Y-axis: AR 416B3 is separated from its corresponding AR 416B_2 by a distance S_1; AR 416B_2 is separated from each other by a distance S_1; AR 1516B_1 is separated from its corresponding AR 416B_2 and 416B_3 by a distance S_2; AR 1516B_1 is separated from each other by a distance S_3; AR 416B_1 has a height H_1; AR 1016B_1 of the upper set 1046 and the lower set 1046 has a height H_10; and AR 1016B_1 of the set 1047 has a height H_11. The cell area 1504B is configured to meet DRC according to design rules (3), (4) and (5).

[0331] Figure 15B This is a plan view of a semiconductor device 1502BA according to some embodiments.

[0332] Figure 15B The unit area 1504BA is similar to Figure 15A Unit area 1503B. In Figure 15B In the middle, one or more shorter (relative to the Y-axis) instances of AR 1516B_1 are formed between two taller (relative to the Y-axis) AR1516B_1 instances on the left and one taller AR 1516B_1 instance on the right, such that... Figure 15A compared to, Figure 15B Additional examples include the 1544B isolated dummy gate. Figure 15B Including the leftmost, left-middle, right-middle, and rightmost isolated dummy gates 1544B, among which... Figure 15A In comparison, the right-center isolation dummy gate 1544B is an additional instance of the isolation dummy gate 1544B. The shorter instance of AR 1516B_1 has a width of N*δ, where N is an integer and N≥1.

[0333] Figure 15C This is a plan view of semiconductor device 1502BB according to some embodiments.

[0334] Figure 15C Cell 1504BB is similar to Figure 15B Unit area 1504BA. Figure 15B Includes an instance of the isolation pseudo-gate 1544B to the left of each of the top-left and bottom-left AR1516B_1. Figure 15C Includes M isolated pseudo-gate 1544B instances to the left of each of the top-left and bottom-left AR1516B_1 instances, where M is an integer and M≥2. Figure 15C In this case, M = 4. Figure 15B Includes two isolated pseudo-gate 1544B instances to the right of each of the top-left and bottom-left AR 1516B_1 and to the right of the middle-right AR 1516B_1. Figure 15C Includes N isolated pseudo-gate 1544B instances to the right of each of the top-left and bottom-left AR 1516B_1 and to the left of the right-middle AR1516B_1, where N is an integer and N≥2. Figure 15C In this case, N = 4. Figure 15B Including an example of the isolation dummy gate 1544B to the right of AR 1516B_1 in the middle right corner. Figure 15C This includes Q instances of isolated pseudo-gate 1544B to the right of AR 1516B_1 in the right-middle region, where Q is an integer and Q≥2. Figure 15C In this case, Q = 4. In some cases, limitations of the etching technique ultimately resulted in AR 1516B_1, 1516B_2, and 1516B_3 having shapes similar to biconcave (or two concave) lenses (e.g., Figure 15C (as shown in the exploded diagram 1505C), instead of Figure 15C The rectangular shape shown; AR416B_2 and AR 416B_2 have hexagonal shapes instead of rectangular shapes. Figure 15C The rectangle shown. In this case (see...) Figure 15C In the exploded view 1505C, the sharp corners of the biconcave instances of AR 1516B_1, 1516B_2, and 1516B_3 are aligned with the tip of the hexagonal instance of AR 416B_2, resulting in increased leakage flow. In some embodiments with this configuration (see...),... Figure 15C The exploded view (1505C) shows that an additional example of the isolated dummy gate 1544B has the advantage of reducing leakage current.

[0335] Figure 16A This is a flowchart of a method 1600 for generating a layout diagram according to some embodiments.

[0336] exist Figure 16A Box 1602 generates an active region pattern on a substrate that extends along a first direction. An example of the first direction is the X-axis. Examples of active region patterns include... Figure 2A AR patterns in AR pattern groups 216A_1 and 216A_2 Figure 3A The AR patterns are 316A_1, 316A_2, and 316A_1, etc. From box 1602, the process proceeds to box 1606.

[0337] In frame 1604, a first majority of AR patterns is arranged such that the first ends of the first majority of the AR patterns are aligned with an imaginary first reference line extending parallel to the Y-axis. The first reference line is parallel to and close to a first side of the cell region. Examples of such a first majority of AR patterns include... Figure 2A From group 216A_2 Figure 2A The imaginary center reference line 219A extends accordingly. Figure 2A Reference line 219A in AR, AR pattern 316A_3 and from Figure 3A The imaginary center reference line 319A extends to Figure 3A The first imaginary reference line 318A is the selected AR pattern 316A_2, etc. Continuing this example, the first imaginary lines 218A and 318A are close to and parallel to the corresponding first sides 210AR and 310AR of the corresponding unit areas 204A and 304A. From box 1604, the process proceeds to box 1606.

[0338] In frame 1606, a second majority of the AR pattern is arranged such that the second ends of the second majority of the AR pattern are aligned with an imaginary second reference line extending parallel to the Y-axis. The second reference line is parallel to and close to the second side of the cell region. Examples of such a second majority of the AR pattern include... Figure 2A From group 216A_1 Figure 2A The imaginary center reference line 219A is extended accordingly. Figure 2A The second hypothetical reference line 220A in the AR pattern, AR pattern 316A_3 and from Figure 3A The pseudo-center reference line 319A extends to Figure 3A The selected AR pattern 316A_2, etc., of the second imaginary reference line 320A. Continuing the example, the second imaginary lines 220A and 320A are close to and parallel to the second sides 210AL and 310AL of the corresponding cell regions 204A and 304A. In some embodiments, the second majority is different from the first majority. In some embodiments, the second majority is the same as the first majority. From block 1606, the process proceeds to block 1608.

[0339] In box 1608, a gate pattern is generated. The gate patterns are substantially parallel to each other and extend parallel to the Y-axis. The gate pattern overlays the active region pattern. An example of such a gate pattern is shown below. Figure 2A and Figure 3A Examples of gate patterns 222A and 322A, etc. From block 1608, the process proceeds to block 1610.

[0340] In box 1610, generate a Future Transition (FC) pattern. An example of this FC pattern is the corresponding... Figure 2A and Figure 3AExamples of FC patterns 224A and 324A, etc. From box 1610, the process proceeds to box 1612.

[0341] In box 1612, the FC pattern is arranged to partially overlap with one or more gate patterns and one or more AR patterns in the corresponding intermediate region. An example of such an intermediate region is provided. Figure 2A and Figure 3A Examples of intermediate regions 226A and 326A.

[0342] Figure 16B This is a flowchart of a method 1614 for manufacturing a semiconductor device according to some embodiments.

[0343] According to some embodiments, such as method 1614, it is possible to implement using EDA system 1800 ( Figure 18 (discussed below) and integrated circuits (ICs), manufacturing systems 1900 ( Figure 19 (Discussed below). Examples of semiconductor devices that can be manufactured according to method 1614 include corresponding... Figure 2B , Figure 3B , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13 , Figure 14 and Figure 15A Semiconductor devices 202B, 302B, 402B, 502B, 602B, 702B, 802B, 902B, 1002B, 1102B, 1202B, 1302B, 1402B and 1502B, which correspond to various layout diagrams disclosed herein.

[0344] like Figure 16B As shown, method 1614 includes boxes 1616-1618. At box 1616, a layout diagram is generated, including one or more layout diagrams disclosed herein, such as those derived from... Figure 16A The layout diagram generated by method 1600 corresponds to the layout diagram of the corresponding method. Figure 2B , Figure 3B , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13 , Figure 14 and Figure 15A Semiconductor devices such as 202B, 302B, 402B, 502B, 602B, 702B, 802B, 902B, 1002B, 1102B, 1202B, 1302B, 1402B, and 1502B. According to some embodiments, for example, an EDA system 1800 is used. Figure 18 (Discussed below), box 1616 is feasible.

[0345] More specifically, block 1616 includes generating a shape corresponding to the structure to be represented in the semiconductor diagram. For example, if the generated layout corresponds to cell region 204A, block 1616 includes generating a shape corresponding to the structure shown in cell region 204B; if the generated layout corresponds to cell region 304A, block 1616 includes generating a shape corresponding to the structure shown in cell region 304B, and so on. From block 1616, the process proceeds to block 1618.

[0346] In box 1618, based on the layout diagram, at least one of the following is fabricated in the layer of the semiconductor device: (A) performing one or more photolithographic exposures; (b) fabricating one or more semiconductor masks; or (C) one or more components. See below for more details. Figure 19 Discussion of IC manufacturing systems in 1900.

[0347] Figures 17A-17B This is a corresponding flowchart of a method 1700 for manufacturing a semiconductor device according to some embodiments.

[0348] Method 1700 includes blocks 1702-1714. At block 1702, an active region is formed in a substrate, wherein the active region extends along a first direction. An example of the first direction is the X-axis. Examples of AR patterns in a layout corresponding to the active region in the substrate extending in the first direction include... Figure 2A and Figure 3A AR patterns, etc. Examples of active regions corresponding to active regions in a substrate extending in the first direction include... Figure 2A and Figure 3B AR area, etc. Box 1702 includes boxes 1704 and 1706.

[0349] At frame 1704, a first majority of active regions is formed with a first end, the first end being aligned with an imaginary first reference line extending along a second direction perpendicular to the first direction. An example of the second direction is the Y-axis. A first side of the cell region is parallel to and close to the first reference line. Examples of such a first majority of active regions include... Figure 2B From group 216B_2 Figure 2B The imaginary center reference line 219B extends accordingly. Figure 2B The first hypothetical reference line in the diagram is 218B, AR. Figure 2BIn the middle, active region 316B_3 and the selected active region 316B_2 are from Figure 3B The imaginary center reference line 319B extends to Figure 3B The first imaginary reference line 318B, etc. Continuing this example, the first imaginary lines 218B and 318B are close to and parallel to the corresponding first sides 210BR and 310BR of the corresponding cell regions 204B and 304B. From box 1704, the process proceeds to box 1706.

[0350] At frame 1706, a second majority of the active region is formed with a second end, the second end being aligned with an imaginary second reference line extending along a second direction. A second side of the cell region is parallel to and close to the second reference line. Examples of such a second majority of the active region include... Figure 2B From group 216B_1 Figure 2B The imaginary center reference line 219B is extended accordingly. Figure 2B The AR pattern of the second imaginary reference line 220B in the middle, from Figure 2B The imaginary center reference line 319B extends to Figure 3B The second hypothetical reference line 320B in Figure 3B The active region 316B_3 and the selected active region 316B_2, etc. Continuing this example, the second imaginary lines 220B and 320B are close to and parallel to the second sides 210BL and 310BL of the corresponding cell regions 204B and 304B. In some embodiments, the second majority is different from the first majority. In some embodiments, the second majority is the same as the first majority. From block 1706, the process proceeds to block 1708.

[0351] At block 1708, a gate structure is formed on the first AR and the second AR of the AR. An example of a gate structure corresponding to the gate pattern corresponds to... Figure 2A and Figure 3A Gate structures with gate patterns 222A and 322A, etc. Examples of gate patterns corresponding to the gate structures are shown. Figure 2A and Figure 3A Gate patterns 222B and 322B are used. From block 1708, the process proceeds to block 1710.

[0352] At block 1710, the gate structure of the selected active region is converted into a corresponding isolation dummy gate, such that no gate structure occupies the intermediate region between the first and second active regions. In some embodiments, the simultaneous formation of the isolation dummy gate includes multiple steps, including: sacrificing / removing (e.g., etching) each sacrificial portion of the selected gate structure representing the intermediate region to form a gate structure under the trench of the removed gate structure and AR. Examples of FC patterns (based on which isolation dummy gates are formed) and corresponding intermediate regions include occupying the corresponding Figure 2A and Figure 3AThe corresponding intermediate regions 226A and 326A have FC patterns 224A and 324A. Examples of isolating the dummy gate and the corresponding intermediate region include occupying the corresponding Figure 2B and Figure 3B The corresponding isolation pseudo-gates 244B and 344B of the intermediate regions 226B and 326B, respectively. From block 1710, the process proceeds to block 1712.

[0353] exist Figure 17B In this context, block 1710 includes blocks 1712 and 1714. At block 1712, a sacrificial portion of the selected gate structure is removed, thereby creating a corresponding void. Relative to a first direction, the sacrificial portion of the selected gate structure overlaps with the first and second active regions at corresponding adjacent regions of the intermediate regions adjacent to the first and second active regions. The void has a first depth relative to a third direction perpendicular to each of the first and second directions, such as the Z-axis. Removing a portion of the selected gate structure exposes the sacrificial portions of the first and second active regions, which are correspondingly located below the sacrificial portions of the selected gate structure. In some embodiments, the sacrificial portions of the first and second active regions are removed, thereby corresponding to a second depth-deepened void greater than the first depth. Examples of such voids include... Figures 3C-3D The gap AR layer 394 in the middle is filled by corresponding isolation dummy gates 344B, etc. From block 1712, the process proceeds to block 1714.

[0354] At box 1714, the gap is filled with insulating material. The gap is filled with insulating material to a second depth. Examples of insulating materials include those that constitute… Figures 3C-3D The insulating material of the isolation dummy gate 344B in the example. The isolation dummy gate divides one or more active areas into a first part and a second part. The first part and the second part are separated by the isolation dummy gate structure.

[0355] Figure 18 This is a block diagram of an electronic design automation (EDA) system 1800 according to some embodiments.

[0356] In some embodiments, the EDA system 1800 includes an APR system. Figure 17A The method described in flowchart 1700. For example, according to some embodiments, it is implemented using EDA system 1800. Figure 17A This is to generate instances of incomplete projection unit structures 204B, 304B, 404B, 504B, 604B, 704B, 804B, 904B, 1004B, 1104B, 1204B, 1304B, 1404B, or 1504B, or other suitable structures within the scope of this disclosure.

[0357] In some embodiments, the EDA system 1800 is a general-purpose computing device including a hardware processor 1802 and a non-transitory computer-readable storage medium 1804. The storage medium 1804 is encoded (i.e., stores) computer program code 1806 (i.e., a set of executable instructions) among other things. The execution of the instructions 1806 by the hardware processor 1802 represents (at least partially) an EDA tool, the implementation of which is, for example… Figure 16A , Figure 16B , Figure 17A and Figure 17B The method according to one or more embodiments (hereinafter, the processes and / or methods mentioned) is partially or completely represented. Storage medium 1804 stores, in particular, layout diagram 1816 including layout diagrams 202A and 302A, as well as similar layout diagrams within the scope of this disclosure.

[0358] Processor 1802 is electrically coupled to computer-readable storage medium 1804 via bus 1808. Processor 1802 is further electrically coupled to I / O interface 1810 via bus 1808. Network interface 1812 is further electrically connected to processor 1802 via bus 1808. Network interface 1812 is connected to network 1814, enabling processor 1802 and computer-readable storage medium 1804 to be connected to external components via network 1814. Processor 1802 is configured to execute computer program code 1806 encoded in computer-readable storage medium 1804, so that system 1800 can be used to perform some or all of the described processes and / or methods. In one or more embodiments, processor 1802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0359] In one or more embodiments, the computer-readable storage medium 1804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1804 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1804 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0360] In one or more embodiments, storage medium 1804 stores computer program code 1806 configured to enable system 1800 to perform some or all of the said processes and / or methods (where such execution (at least in part) represents an EDA tool). In one or more embodiments, storage medium 1804 also stores information that facilitates the execution of some or all of the said processes and / or methods. In one or more embodiments, storage medium 1804 stores a library 1820 of standard units, including those standard units as disclosed herein.

[0361] EDA system 1800 includes I / O interface 1810. I / O interface 1810 is coupled to external circuitry. In one or more embodiments, I / O interface 1810 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1802.

[0362] EDA system 1800 also includes a network interface 1812 coupled to processor 1802. Network interface 1812 allows system 1800 to communicate with a network 1814 to which one or more other computer systems are connected. Network interface 1812 includes: a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 1800.

[0363] System 1800 is configured to receive information via I / O interface 1810. The information received via I / O interface 1810 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1802. The information is transmitted to processor 1802 via bus 1808. EDA system 1800 is configured to receive UI-related information via I / O interface 1810. This information is stored as a user interface (UI) 1818 in computer-readable medium 1804.

[0364] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by an EDA system 1800. In some embodiments, available VIRTUOSO, such as from CADENCE DESIGNSYSTEMS, Inc., is used. @ Tools or other applicable layout generation tools can be used to generate layouts that include standard cells.

[0365] In some embodiments, processing is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), etc.

[0366] Figure 19 This is a block diagram of an integrated circuit (IC) manufacturing system 1900 and its associated IC manufacturing process according to some embodiments.

[0367] exist Figure 16B Following frame 1616, based on the layout, manufacturing system 1900 is used to fabricate at least one of the following in the layers of an early semiconductor integrated circuit: (A) one or more semiconductor masks or (B) at least one component. In some embodiments, in Figure 17A Following frame 1702, based on the layout, at least one of the following is manufactured in the layer of an early semiconductor integrated circuit: (A) one or more semiconductor masks or (B) at least one component.

[0368] exist Figure 19In this IC manufacturing system 1900, entities interact with each other throughout the design, development, and manufacturing cycles, such as design room 1920, mask room 1930, and IC manufacturer / fabricator (“FAB”) 1940 and / or services related to the manufacture of IC devices 1960. The entities in system 1900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1920, mask room 1930, and IC FAB 1940 are owned by a single, larger company. In some embodiments, two or more of design room 1920, mask room 1930, and IC FAB 1940 coexist in a shared facility and use shared resources.

[0369] Design studio (or design team) 1920 generates IC design layout 1922. IC design layout 1922 includes various geometric patterns designed for IC device 1960. The geometric patterns correspond to the manufacturing patterns of the metal, oxide, or semiconductor layers that constitute various components of IC device 1960. The layers are combined to form various IC components. For example, a portion of IC design layout 1922 includes various IC components to be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnection, and openings for bonding pads. Design studio 1920 implements appropriate design procedures to form IC design layout 1922. Design procedures include one or more of logic design, physical design, or place-and-route. IC design layout 1922 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1922 is represented in GDSII file format or DFII file format.

[0370] Mask room 1930 includes data preparation 1932 and mask fabrication 1934. Mask room 1930 uses IC design layout 1922 to fabricate one or more masks to manufacture the various layers of IC device 1960 according to IC design layout 1922. Mask room 1930 performs mask data preparation 1932, where IC design layout 1922 is translated into a representational data file (“RDF”). Mask data preparation 1932 provides the RDF to mask fabrication 1934. Mask fabrication 1934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask plate) or semiconductor wafer. The design layout is manipulated by mask data preparation 1932 to conform to the specific characteristics of the mask writer and / or the requirements of IC FAB 1940. Figure 19In this embodiment, mask data preparation 1932, mask manufacturing 1934, and mask 1945 are shown as separate elements. In some embodiments, mask data preparation 1932 and mask manufacturing 1934 are collectively referred to as mask data preparation.

[0371] In some embodiments, mask data preparation 1932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1922. In some embodiments, mask data preparation 1932 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other applicable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is further used, which treats OPC as an inverse imaging problem.

[0372] In some embodiments, mask data preparation 1932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout already processed in the OPC. These mask creation rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 1934, which can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0373] In some embodiments, mask data preparation 1932 includes a lithography process check (LPC), which simulates the process to be implemented by IC FAB 1940 to manufacture IC device 1960. The LPC simulates this process based on IC design layout 1922 to manufacture the simulated manufacturing process. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other applicable factors, or combinations thereof. In some embodiments, after manufacturing the device via LPC simulation, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1922.

[0374] It should be understood that, for clarity, the above description of mask data preparation 1932 has been simplified. In some embodiments, data preparation 1932 includes additional features, such as logic operations (LOPs), to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1922 during data preparation 1932 can be performed in various different sequences.

[0375] Following mask data preparation 1932 and during mask fabrication 1934, a mask 1945 or mask set is fabricated based on a modified IC design layout. In some embodiments, a mechanism of electron beam (e-beam) or multiple electron beams is used to form a pattern on the mask (photomask or mask stencil) based on the modified IC design layout. The mask is formed using various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer is blocked by the opaque areas and passes through the transparent areas. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the mask. In another example, a phase-shifting technique is used to form the mask. In a phase-shifting mask (PSM), various components in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shifting mask is a decaying PSM or an alternating PSM. Masks produced by Mask Fabrication 1934 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes, and / or in other applicable processes to form various etched regions in semiconductor wafers.

[0376] IC FAB 1940 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC FAB 1940 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide a portion of the IC products for back-end manufacturing (back-end process (BEOL) manufacturing) for interconnection and packaging, and a third manufacturing plant may provide other services for the foundry business.

[0377] IC manufacturing plant 1940 uses a mask (or multiple masks) manufactured by mask chamber 1930 and manufacturing tools 1952 to manufacture IC device 1960. Therefore, IC FAB 1940 uses IC design layout 1922 at least indirectly to manufacture IC device 1960. In some embodiments, semiconductor wafer 1942 is manufactured by IC FAB 1940 using a mask (or multiple masks) to form IC device 1960. Semiconductor wafer 1942 includes a silicon substrate or other suitable substrate on which a material layer is formed. The semiconductor wafer further includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0378] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 19Details of the system 1900 and the associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0379] For example, in U.S. Patent No. 9,256,709, an IC design layout is generated in a design room (or design team). The IC design layout includes various geometric patterns designed for an IC device. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device to be manufactured. The various layers combine to form various IC functions. For example, portions of the IC design layout include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for forming pads in the semiconductor. These openings will be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room performs appropriate design processes to form the IC design layout. These design processes may include logic design, physical design, and / or placement and routing. The IC design layout is presented in one or more data files containing geometric pattern information. A mask room uses the IC design layout to fabricate one or more masks, which are used to fabricate the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer. The design layout prepared by mask data preparation is modified to conform to a specific mask manufacturer and / or mask vendor before fabrication. In this embodiment, mask data preparation and mask fabrication are illustrated as separate elements; however, they can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has already been processed in the OPC. These mask creation rules may include some geometric and connectivity constraints to ensure sufficient margin.

[0380] For example, in U.S. Patent Publication No. 20150278429, in one embodiment, the IC manufacturing system may employ maskless lithography techniques, such as electron beam lithography or optical maskless lithography. In such a system, mask fabrication is bypassed, and the IC design layout is modified through data preparation suitable for wafer processing using a specific maskless lithography technique. The data preparation modifies the design layout to suit subsequent operations within the IC manufacturing system. The result of the data preparation is represented by one or more data files, such as files in GDSII or DFII file formats. The one or more data files include information on geometric patterns, such as polygons representing the primary design pattern and / or auxiliary components. In this embodiment, the one or more data files also include auxiliary data generated by the data preparation. This auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask fabrication performed in the mask chamber and wafer exposure performed by the IC manufacturer.

[0381] For example, in Pre-License No. 20140040838, the IC design layout is presented in one or more data files containing geometric pattern information. In one example, the IC design layout is represented in the “GDS” format known in the art. In alternative embodiments, the IC design layout may be transferred between components in an IC manufacturing system in alternative file formats such as DFII, CIF, OASIS, or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include primary IC components such as active regions, gate electrodes, source and drain electrodes, metal lines, interlayer interconnect vias, and openings for forming pads in the semiconductor, which will be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include auxiliary components, such as those for imaging effects, processing enhancement and / or mask recognition information.

[0382] For example, in U.S. Patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; and a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on equipment data, material data, and the mask inspection results. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs post-etch or post-stripping inspections and obtains post-etch or post-stripping inspection results, respectively. The controller provides operation-to-operation control for the processing tool, including feedforward and feedback control. The controller receives post-etch or post-stripping inspection results from the metrology tool and retrieves device and material data from the database. The controller, connected to the manufacturing execution system, generates a manufacturing model of the processing tool and calibrates the manufacturing model based on equipment data, material data, and the mask inspection results. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

[0383] In some embodiments, the semiconductor device includes: a substrate; and a cell region having a first side and a second side opposite to a first direction, the cell region including an active region formed in the substrate extending in the first direction; a first majority of the active region having a first end aligned with the first reference line relative to an imaginary first reference line in a second direction perpendicular to the first direction, the first side being parallel to and close to the first reference line; a second majority of the active region having a second end aligned with the second reference line relative to an imaginary second reference line in the second direction, the second side being parallel to and close to the second reference line; and a gate structure correspondingly located on the first active region and the second active region in the active region; and wherein, relative to the second direction, a first end of a selected gate structure in the gate structure is adjacent to an intermediate region located between the first active region and the second active region.

[0384] In some embodiments, the semiconductor device further includes a first isolation dummy gate formed in an intermediate region. In some embodiments, the semiconductor device further includes: a low-leakage portion of the semiconductor device, comprising each active region in the semiconductor device having a first height relative to a second direction; a high-leakage portion of the semiconductor device, wherein each active region in the semiconductor device has a second height relative to the second direction, the second height being greater than the first height; and wherein the first active region is included in the low-leakage portion; and each active region having the first height exhibits current leakage equal to or below a predetermined threshold. In some embodiments, the semiconductor device further includes a high-leakage region of the semiconductor device, wherein a second active region is substantially located within the high-leakage portion, and the second active region is configured to have a height greater than the height of the first active region and support switching speeds within a predetermined threshold. In some embodiments, the first active region and the second active region are separated by an intermediate region relative to the first direction. In some embodiments, the long axis of the first isolation dummy gate extends in the second direction. In some embodiments, the first active region is one of a plurality of first active regions; the semiconductor device further includes: a low-leakage portion of the semiconductor device, wherein each active region included in the semiconductor device has a first height relative to a second direction; a high-leakage portion of the semiconductor device, wherein each active region included in the semiconductor device has a second height relative to the second direction, the second height being greater than the first height; the low-leakage portion includes a majority of the plurality of first active regions; members of the plurality of first active regions are separated from each other by corresponding gaps having a size S_1. In some embodiments, the second active region is one of a plurality of second active regions; the high-leakage portion includes a majority of the plurality of second active regions relative to the first direction; the plurality of first active regions have a first size and the plurality of second active regions have a second size relative to the first direction, the second size being greater than the first size. Members of the plurality of second active regions are separated from each other by corresponding gaps having a size S_1. In some embodiments, a second isolation dummy gate separates one or more of the plurality of first active regions into a first portion and a second portion of one or more first active regions, wherein the first portion and the second portion are separated by the second isolation dummy gate. In some embodiments, the semiconductor device further includes: a third isolation dummy gate that separates one or more of the plurality of second active regions into a first portion and a second portion of the one or more second active regions, wherein the first portion and the second portion of the one or more second active regions are separated by the third isolation dummy gate.

[0385] In some embodiments, the semiconductor device includes: a cell region including an active region extending in a first direction; the cell region is arranged such that the central reference line is located at the center of the cell region relative to the first direction, relative to an imaginary center reference line extending in a second direction perpendicular to the first direction; first end portions of two or more active regions extend a maximum distance from the center reference line to the first reference line in the first direction relative to an imaginary first reference line extending in the second direction, and a first edge of the cell region is parallel to and close to the first reference line; second end portions of two or more active regions extend a maximum distance from the center reference line to the second reference line relative to an imaginary second reference line extending in the second direction, and a second edge of the cell region is parallel to and close to the second reference line, the second edge being located on an opposite side of the cell region relative to the first edge; the first active region and the second active region in the active region have corresponding major axes in the first direction, the major axes being collinear with the first direction, and the first active region and the second active region are separated by a first intermediate region.

[0386] In some embodiments, the semiconductor device further includes an isolation dummy gate located in a first intermediate region. In some embodiments, each of the first and second active regions has a first height in a second direction; and the cell region further includes: a third and a fourth active region having corresponding major axes in the first direction, the major axes being collinear with the first direction, the third and fourth active regions being separated by a second intermediate region, and each of the third and fourth active regions having a first height in the second direction; and a fifth active region located between the first and second active regions relative to each of the first and second directions, and between the third and fourth active regions relative to each of the first and second directions. In some embodiments, the fifth active region does not overlap with any of the first, second, third, or fourth active regions relative to the first direction. In some embodiments, the semiconductor device further includes: a first isolation dummy gate located between the fifth active region and the first active region relative to a first direction; or a second isolation dummy gate located between the fifth active region and the second active region relative to a first direction; or a third isolation dummy gate located between the fifth active region and the third active region relative to a first direction; or a fourth isolation dummy gate located between the fifth active region and the fourth active region relative to a first direction. In some embodiments, the fifth active region at least partially overlaps with each of the first active region and the second active region relative to a second direction; or, the fifth active region at least partially overlaps with each of the third active region and the fourth active region relative to a second direction. In some embodiments, the first end portions of the first active region and the third active region extend a maximum distance from the center reference line to the first reference line in the first direction; the second end portions of the third and fourth active regions extend a maximum distance from the center reference line to the second reference line.

[0387] In some embodiments, a method of forming a semiconductor device includes forming an active region in a substrate, the active region extending correspondingly in a first direction, the forming of the active region comprising: forming a first majority of active regions having first ends aligned with the first reference line relative to an imaginary first reference line in a second direction perpendicular to the first direction, a first side of a cell region being parallel to and close to the first reference line, the cell region including the active region; forming a second majority of active regions having second ends aligned with a second reference line relative to an imaginary second reference line in the second direction, the second side of the cell region being parallel to and close to the second reference line; forming gate structures correspondingly located on the first and second active regions in the active region; and converting a selected gate structure in the gate structure into a corresponding isolated pseudo-gate structure such that no gate structure occupies the intermediate region between the first and second active regions.

[0388] In some embodiments, relative to the first direction, a sacrificial portion of the selected gate structure in the gate structure overlaps with the first and second active regions at a corresponding adjacent region in the intermediate region between the first and second active regions; and the transition includes: relative to the second direction, removing the sacrificial portion of the selected gate structure to create a corresponding gap; and filling the gap with an insulating material. In some embodiments, the gap has a first depth relative to a third direction perpendicular to each of the first and second directions; the removed portion of the selected gate structure exposes the sacrificial portions of the first and second active regions correspondingly located below the sacrificial portion of the selected gate structure; the transition further includes removing the sacrificial portions of the first and second active regions to deepen the gap to a second depth greater than the first depth; and filling the gap with an insulating material to the second depth.

[0389] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to influence various modifications, substitutions of equivalents, and various other embodiments widely disclosed herein. Therefore, the protection granted herein is intended to be limited only to the definitions contained in the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: Substrate; as well as A cell region having a first side and a second side opposite to a first direction, the cell region including an active region formed in the substrate extending in the first direction; Relative to an imaginary first reference line in a second direction perpendicular to the first direction, a first majority of the active region has a first end aligned with the first reference line, and the first side is parallel to and close to the first reference line. Relative to an imaginary second reference line in the second direction, the second majority of the active region has a second end aligned with the second reference line, and the second side is parallel to and close to the second reference line; as well as The gate structure is correspondingly located on a plurality of first active regions and a plurality of second active regions in the active region; and Wherein, relative to the second direction, a first end of one of the gate structures in the gate structure is adjacent to the intermediate region located between the first active region and the second active region; The high leakage region of the semiconductor device, wherein the plurality of second active regions are located within the high leakage region, and each second active region is configured to have a height greater than that of each first active region, and to support switching speeds within a predetermined threshold.

2. The semiconductor device according to claim 1, further comprising: A first isolation dummy gate is formed in the intermediate region.

3. The semiconductor device according to claim 1, further comprising: The low-leakage portion of the semiconductor device, wherein each active region included in the low-leakage portion has a first height relative to the second direction; and Each second active region included in the high-leakage portion has a second height relative to the second direction, the second height being greater than the first height; and in: The first active region is included in the low-leakage portion; and Each active region with the first height exhibits current leakage equal to or below a predetermined threshold.

4. The semiconductor device according to claim 2, wherein: The first isolation dummy gate is a dielectric structure of dielectric material.

5. The semiconductor device according to claim 1, wherein: Relative to the first direction, the first active region and the second active region are separated by the intermediate region.

6. The semiconductor device according to claim 2, wherein: The long axis of the first isolation dummy gate extends in the second direction.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further includes: The low-leakage portion of the semiconductor device, wherein each active region included in the low-leakage portion has a first height relative to a second direction; Each second active region within the high-leakage portion has a second height relative to the second direction, the second height being greater than the first height; and The low-leakage portion includes the plurality of first active regions; and The members in the plurality of first active regions are separated from each other by corresponding gaps of size S_1.

8. The semiconductor device according to claim 7, wherein: Relative to the first direction, the plurality of first active regions have a first size and the plurality of second active regions have a second size, the second size being larger than the first size; and The members of the plurality of second active regions are separated from each other by corresponding gaps having the size S_1.

9. The semiconductor device according to claim 2, wherein: The second isolation dummy gate separates one or more of the plurality of first active regions into a first portion and a second portion of the one or more first active regions, wherein the first portion and the second portion are separated by the second isolation dummy gate.

10. The semiconductor device according to claim 9, further comprising: A third isolation dummy gate separates one or more of the plurality of second active regions into a first portion and a second portion of the one or more second active regions, wherein the first portion and the second portion of the one or more second active regions are separated by the third isolation dummy gate.

11. A semiconductor device, comprising: A cell region, the cell region including an active region extending in a first direction; The cell region is arranged such that the center reference line is located at the center of the cell region relative to the first direction, relative to an imaginary center reference line extending in a second direction perpendicular to the first direction. Relative to an imaginary first reference line extending in the second direction, the first end portions of two or more of the active regions extend a maximum distance from the center reference line to the first reference line in the first direction, and the first edge of the cell region is parallel to and close to the first reference line; Relative to an imaginary second reference line extending in the second direction, the second end portions of two or more of the active regions extend a maximum distance from the center reference line to the second reference line, the second edge of the cell region is parallel to and close to the second reference line, and the second edge is located on the opposite side of the cell region relative to the first edge; and The first active region and the second active region in the active region have corresponding major axes in a first direction, the major axes being collinear with the first direction, and the first active region and the second active region are separated by a first intermediate region; The high leakage region of the semiconductor device, wherein the second active region is located within the high leakage region, and each of the second active regions is configured to have a height greater than that of each of the first active regions and to support switching speeds within a predetermined threshold.

12. The semiconductor device according to claim 11, further comprising: An isolation dummy gate is located in the first intermediate region.

13. The semiconductor device according to claim 11, wherein: The unit region also includes: The third and fourth active regions of the active region have corresponding major axes in the first direction, the major axes being collinear with the first direction, and the third and fourth active regions are separated by a second intermediate region; and The fifth active region in the active region is located between the first active region and the second active region relative to each of the first direction and the second direction, and between the third active region and the fourth active region relative to each of the first direction and the second direction.

14. The semiconductor device according to claim 13, wherein: Relative to the first direction, the fifth active region does not overlap with any of the first active region, the second active region, the third active region, or the fourth active region.

15. The semiconductor device according to claim 13, further comprising: The first isolation dummy gate is located between the fifth active region and the first active region relative to the first direction; or The second isolation dummy gate is located between the fifth active region and the second active region relative to the first direction; or The third isolation dummy gate is located between the fifth active region and the third active region relative to the first direction; or The fourth isolation dummy gate is located between the fifth active region and the fourth active region relative to the first direction.

16. The semiconductor device according to claim 13, wherein: Relative to the second direction, the fifth active region at least partially overlaps with each of the first active region and the second active region; or Relative to the second direction, the fifth active region at least partially overlaps with each of the third and fourth active regions.

17. The semiconductor device according to claim 13, wherein: The first end portions of the first active region and the third active region extend the maximum distance from the center reference line to the first reference line in the first direction; or The second end portions of the third active region and the fourth active region extend the maximum distance from the center reference line to the second reference line.

18. A method of forming a semiconductor device, the method comprising: An active region is formed in a substrate, the active region extending correspondingly in a first direction, the formation of the active region comprising: A first majority of active regions are formed relative to an imaginary first reference line in a second direction perpendicular to the first direction, having a first end aligned with the first reference line. A first side of the cell region is parallel to and close to the first reference line. The cell region includes the active region. A second majority of active regions are formed relative to an imaginary second reference line in the second direction, having a second end aligned with the second reference line, and the second side of the cell region is parallel to and close to the second reference line. A gate structure is formed correspondingly on the first and second active regions in the active regions, wherein a second majority of the active regions is located within a high-leakage portion of the semiconductor device, and each of the second majority of the active regions is configured to have a height greater than that of each of the first majority of the active regions, and supports switching speeds within a predetermined threshold; and Some of the gate structures in the gate structure are converted into corresponding isolated pseudo-gate structures, so that no gate structure occupies the intermediate region between the first active region and the second active region.

19. The method of claim 18, wherein: Relative to the first direction, the sacrificial portion of a portion of the gate structure in the gate structure overlaps with the first active region and the second active region at the corresponding adjacent regions of the first active region and the second active region adjacent to the intermediate region; as well as The conversion includes: Relative to the second direction, the sacrificial portion of the partial gate structure is removed to create a corresponding gap; and The gaps are filled with insulating material.

20. The method of claim 19, wherein: The gap has a first depth relative to a third direction perpendicular to each of the first and second directions; The partial removal of the partial gate structure exposes corresponding sacrificial portions of the first and second active regions located below the sacrificial portions of the partial gate structure; The conversion also includes: The sacrificed portions of the first active region and the second active region are removed, thereby deepening the gap to a second depth greater than the first depth; as well as The gap is filled with the insulating material to a second depth.

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