Semiconductor device and method of forming the same

Abstract

The device includes a substrate including an active region, a gate stack over the active region, and a hard mask over the gate stack. The hard mask includes a cap layer, a support layer extending along sidewalls and a bottom of the cap layer, and a liner layer extending along sidewalls and a bottom of the support layer. The support layer includes a metal oxide material or a metal nitride material. Embodiments of the invention also provide methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is constantly improving the integration density of individual electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device comprising: a substrate including an active region; a gate stack located above the active region; and a hard mask located above the gate stack, the hard mask comprising: a capping layer; a support layer extending along the sidewalls and bottom of the capping layer, wherein the support layer comprises a metal oxide material or a metal nitride material; and a pad layer extending along the sidewalls and bottom of the support layer.

[0005] Other embodiments of the present invention provide a semiconductor device comprising: a substrate including an active region; a first spacer structure and a second spacer structure located above the active region, wherein a first sidewall of the first spacer structure faces a second sidewall of the second spacer structure; a gate stack located above the active region and between the first spacer structure and the second spacer structure, wherein a top surface of the gate stack is lower than the top surface of the first spacer structure and the top surface of the second spacer structure; and a hard mask located above the gate stack and between the first spacer structure and the second spacer structure, the hard mask comprising: a pad. A layer extending along the top surface of the gate stack, the first sidewall of the first spacer structure, and the second sidewall of the second spacer structure, the pad layer comprising a first nitride material; a support layer located above the pad layer, the support layer comprising a second nitride material or a first oxide material; and a cover layer located above the support layer, the cover layer comprising a third nitride material; an epitaxial source / drain region embedded in an active region adjacent to the first spacer structure; and a source / drain contact located above the epitaxial source / drain region and adjacent to the first spacer structure, the top surface of the source / drain contact being flush with the top surface of the hard mask.

[0006] Some embodiments of the present invention provide a method for forming a semiconductor device, comprising: forming a dummy gate structure over an active region of a substrate, the dummy gate structure having a first sidewall and a second sidewall opposite to the first sidewall; forming a first spacer structure on the first sidewall of the dummy gate structure; forming a second spacer structure on the second sidewall of the dummy gate structure; replacing the dummy gate structure with a replacement gate structure; recessing the replacement gate structure to form a groove embedded between the first spacer structure and the second spacer structure; and forming a hard mask in the groove, wherein forming the hard mask comprises: forming a pad layer along the sidewall and bottom of the groove; forming a support layer over the pad layer in the groove, the support layer comprising a metal nitride material or a metal oxide material; and forming a capping layer over the support layer in the groove.

[0007] Some embodiments of the present invention provide a self-aligned contact hard mask structure for semiconductor devices and a method for forming the same. Attached Figure Description

[0008] When read in conjunction with the accompanying drawings, aspects of the invention will be best understood from the following detailed description. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figures 1 to 13 , Figures 15 to 17 as well as Figures 21 to 26 This is a cross-sectional view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments.

[0010] Figure 14 This is a table showing the various possible materials for the various layers of a self-aligned contact hard mask according to some embodiments.

[0011] Figure 18 This is a flowchart illustrating an atomic layer etching process according to some embodiments.

[0012] Figure 19 and Figure 20 This is a cross-sectional view of an intermediate stage during the execution of an atomic layer etching process, according to some embodiments.

[0013] Figure 27 This is a cross-sectional view of a semiconductor device according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples of various components for implementing the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include instances where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] Embodiments will be described with reference to a specific context: self-aligned contact (SAC) hard masks for semiconductor devices and methods thereof. The various embodiments presented herein are discussed in the context of planar field-effect transistor (FET) devices formed using a post-gate process. In other embodiments, a gate-first process may be used. However, the various embodiments can be applied to dies including other types of transistors (e.g., FinFETs, gate-all-around (GAA) transistors (e.g., nanoFETs), etc.) instead of or in combination with planar FETs. The various embodiments discussed herein allow the formation of SAC hard masks including a support layer and having improved etch resistance, thereby reducing corner losses of the SAC hard mask and maintaining good insulation between adjacent source / drain contacts during the etching process that forms openings for the source / drain contacts.

[0017] Figures 1 to 13 , Figures 15 to 17 and Figures 21 to 26 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor device 100 according to some embodiments. Figure 1A substrate 102 is provided. The substrate 102 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 102 can be a wafer such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer provided on the substrate is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 102 can include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0018] Substrate 102 has region 100N and region 100P. Region 100N can be used to form n-type devices, such as n-type transistors. Region 100P can be used to form p-type devices, such as p-type transistors. Region 100N can be physically separated from region 100P (as shown by separator 104), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 100N and region 100P.

[0019] Substrate 102 includes an active region 106. In some embodiments, when the semiconductor device 100 is a planar FET device, the active region 106 includes an upper planar portion of the substrate 102. In other embodiments, when the semiconductor device 100 is a planar FET device, the active region 106 is a semiconductor layer formed above the substrate 102, such that the semiconductor layer and the substrate 102 comprise different semiconductor materials. In some embodiments, when the semiconductor device 100 is a FinFET device, the active region 106 includes one or more semiconductor strips. Semiconductor strips may also be referred to as fins. In some embodiments, the semiconductor strips and the substrate 102 comprise the same semiconductor material. In other embodiments, the semiconductor strips and the substrate 102 comprise different semiconductor materials. The semiconductor strips can be separated and isolated from each other by isolation regions. In some embodiments, when the semiconductor device 100 is a GAA device such as a nanoFET device, the active region 106 includes one or more nanostructures. Nanostructures may include nanosheets, nanowires, etc. In some embodiments, the nanostructures and the substrate 102 comprise the same semiconductor material. In other embodiments, the nanostructures and the substrate 102 comprise different semiconductor materials.

[0020] Further in Figure 1In this process, suitable wells (not shown) can be formed in the active region 106 of the substrate 102. In some embodiments, a P-well can be formed in region 100N and an N-well can be formed in region 100P. In some embodiments, either a P-well or an N-well is formed in both regions 100N and 100P. In embodiments with different well types, different implantation steps for regions 100N and 100P can be implemented using photoresist or other masks (not shown). For example, a first photoresist can be formed over the active region 106 of the substrate 102 in both regions 100N and 100P. The first photoresist is patterned to expose region 100P. The first photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the first photoresist is patterned, n-type dopant implantation is performed in region 100P, while the remainder of the first photoresist acts as a mask to substantially prevent n-type dopant from being implanted into region 100N. The n-type dopant can be phosphorus, arsenic, antimony, combinations thereof, etc. After implantation, for example, the first photoresist is removed by a wet cleaning process followed by an acceptable ashing process.

[0021] Following implantation in region 100P, a second photoresist is formed over the active region 106 of substrate 102 in both regions 100P and 100N. The second photoresist is patterned to expose region 100N. The second photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the second photoresist is patterned, p-type dopant implantation can be performed in region 100N, while the remaining portion of the second photoresist acts as a mask to substantially prevent p-type dopant implantation into region 100P. The p-type dopant can be boron, BF2, indium, combinations thereof, etc. After implantation, the second photoresist can be removed, for example, by an acceptable ashing process followed by a wet cleaning process. After implantation in regions 100N and 100P, an annealing process can be performed to activate the implanted p-type and / or n-type dopant.

[0022] exist Figure 2 In this process, a dummy dielectric layer 108 is formed over the active region 106 of the substrate 102. The dummy dielectric layer 108 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. Subsequently, a dummy gate layer 110 is formed over the dummy dielectric layer 108, and a mask layer 112 is formed over the dummy gate layer 110.

[0023] A dummy gate layer 110 can be deposited over the dummy dielectric layer 108, and then planarized using a process such as chemical mechanical polishing (CMP). The dummy gate layer 110 can be a conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 110 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, or other techniques known in the art for depositing conductive materials.

[0024] A mask layer 112 may be deposited over the dummy gate layer 110. The mask layer 112 may include, for example, one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the mask layer 112 may include a silicon nitride layer and a silicon oxide layer located above the silicon nitride layer.

[0025] In some embodiments, a single dummy dielectric layer 108, a single dummy gate layer 110, and a single mask layer 112 are formed over both regions 100N and 100P. In other embodiments, a first dummy dielectric layer, a first dummy gate layer, and a first mask layer are formed in region 100N, and a second dummy dielectric layer, a second dummy gate layer, and a second mask layer are formed in region 100P, such that the first dummy dielectric layer and the second dummy dielectric layer comprise different materials, the first dummy gate layer and the second dummy gate layer comprise different materials, and the first mask layer and the second mask layer comprise different materials.

[0026] Figures 3 to 13 , Figures 15 to 17 and Figures 21 to 26 Various additional steps for manufacturing the semiconductor device 100 according to some embodiments are shown. Figures 3 to 13 , Figures 15 to 17 and Figures 21 to 26 Components in either region 100N or region 100P are shown. For example, components can be... Figures 3 to 13 , Figures 15 to 17 and Figures 21 to 26 The structures shown apply to both regions 100N and 100P. The differences in the structures for regions 100N and 100P are described (if any) in the accompanying text for each figure.

[0027] exist Figure 3 In this process, acceptable photolithography and etching techniques can be used to pattern the mask layer 112 (see...). Figure 2 To form mask 116. In some embodiments, the etching technique may include one or more anisotropic etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), combinations thereof, etc. Subsequently, the pattern of mask 116 can be transferred to dummy gate layer 110 (see Figure 2To form the dummy gate 114. In some embodiments, the pattern of the mask 116 can also be transferred to the dummy dielectric layer 108 by an acceptable etching technique. As described in more detail below, the dummy gate 114 is a sacrificial gate and is subsequently replaced by a replacement gate. Thus, the dummy gate 114 can also be referred to as a sacrificial gate. In other embodiments, some dummy gates 114 are not replaced and remain in the final structure of the semiconductor device 100.

[0028] Further in Figure 3 In this process, a gate sealing spacer 118 can be formed on the sidewalls of the dummy gate 114 and the corresponding mask 116. Thermal oxidation or deposition followed by anisotropic etching can form the gate sealing spacer 118. The gate sealing spacer 118 may include silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiOC, SiOCN, combinations thereof, etc.

[0029] After the gate sealing spacer 118 is formed, implantation for the lightly doped source / drain (LDD) region (not explicitly shown) can be performed. In embodiments with different device types, similar to the above... Figure 1 The implantation discussed herein can involve forming a mask, such as a photoresist, over region 100N, while exposing region 100P, and implanting an appropriate type of dopant (e.g., p-type) into the active region 106 of the substrate 102 in region 100P. The mask can then be removed. The n-type dopant can be any n-type dopant discussed previously, and the p-type dopant can be any p-type dopant discussed previously. Annealing can be used to activate the implanted dopant.

[0030] exist Figure 4 In this embodiment, a gate spacer 120 is formed on a gate sealing spacer 118 along the sidewalls of the dummy gate 114 and the mask 116. The gate spacer 120 can be formed by blanket or conformal deposition of an insulating material followed by anisotropic etching of the insulating material. The insulating material of the gate spacer 120 may include silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiOC, SiOCN, or combinations thereof. In some embodiments, each of the gate spacers 120 may include multiple layers (not shown) such that these layers comprise different materials.

[0031] It is worth noting that the above disclosure provides a general description of the processes for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and steps in different sequences can be employed (e.g., the gate sealing spacer 118 may not be etched before the gate spacer 120 is formed, resulting in an "L-shaped" gate sealing spacer; spacers can be formed and removed; and / or similar steps). Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region of the n-type device in region 100N can be formed before the gate sealing spacer 118 is formed, while the LDD region of the p-type device in region 100P can be formed after the gate sealing spacer 118 is formed.

[0032] exist Figure 5 In the active region 106, epitaxial source / drain regions 122 are formed to apply stress in the corresponding channel regions, thereby improving device performance. The epitaxial source / drain regions 122 are formed in the active region 106 such that each dummy gate 114 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 122. In some embodiments, the epitaxial source / drain regions 122 may extend into and penetrate the active region 106. In some embodiments, gate spacers 120 are used to separate the epitaxial source / drain regions 122 from the dummy gates 114 by an appropriate lateral distance, such that the epitaxial source / drain regions 122 do not short-circuit the gate of the subsequently formed semiconductor device 100.

[0033] An epitaxial source / drain region 122 in region 100N can be formed by masking the exposed portion of the active region 106 in active region 106 and etching the exposed portion in active region 100N. The epitaxial source / drain region 122 in region 100N is then epitaxially grown in the groove. The epitaxial source / drain region 122 can comprise any acceptable material suitable for n-type transistors. For example, if active region 106 is made of silicon, the epitaxial source / drain region 122 in region 100N can comprise a material for applying tensile strain in the corresponding channel region of semiconductor device 100, such as silicon, SiC, SiCP, SiP, combinations thereof, etc. The epitaxial source / drain region 122 in region 100N can have a facet.

[0034] The epitaxial source / drain region 122 in region 100P can be formed by masking the exposed portion of the active region 106 in region 100N and etching the exposed portion of the active region 106 in region 100P to form a groove. The epitaxial source / drain region 122 in region 100P is then epitaxially grown in the groove. The epitaxial source / drain region 122 can include any acceptable material suitable for a p-type transistor. For example, if the active region 106 is made of silicon, the epitaxial source / drain region 122 in region 100P can include a material for applying compressive strain in the corresponding channel region of the semiconductor device 100, such as SiGe, SiGeB, Ge, GeSn, combinations thereof, etc. The epitaxial source / drain region 122 in region 100P can have a facet.

[0035] The epitaxial source / drain region 122 can be formed by implanting dopant, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The n-type and / or p-type dopants used for the epitaxial source / drain region 122 can be any dopants discussed previously. In some embodiments, the epitaxial source / drain region 122 can be doped in situ during growth.

[0036] exist Figure 6 In Figure 5 An ILD 124 is deposited over the structure shown. The ILD 124 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), flowable CVD (FCVD), or combinations thereof. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or combinations thereof. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer (not shown) may be provided between the ILD 124 and the epitaxial source / drain region 122, mask 116, and gate spacer 120. The contact etch stop layer may include a dielectric material having a different etch rate than the material of the ILD 124 above, such as silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof.

[0037] exist Figure 7In this process, a planarization process, such as a CMP process, can be performed to make the top surface of the ILD 124 flush with the top surface of the mask 116. In some embodiments, the planarization process may also remove the mask 116 on the dummy gate 114, as well as portions of the gate sealing spacer 118 and gate spacer 120 along the sidewalls of the mask 116. In the illustrated embodiment, after the planarization process, the top surfaces of the mask 116, gate sealing spacer 118, gate spacer 120, and ILD 124 are substantially coplanar or flush with each other within the process variations of the planarization process. Thus, the top surface of the mask 116 is exposed through the ILD 124. In embodiments where the mask 116 is also removed, the planarization process makes the top surface of the ILD 124 flush with the top surface of the dummy gate 114.

[0038] exist Figure 8 In this process, a protective layer 126 is formed over the ILD 124. The protective layer 126 protects the ILD 124 from damage by subsequent process steps. The protective layer 126 may also be referred to as an etch stop layer. In some embodiments, the ILD 124 is recessed below the top surface of the mask 116, material of the protective layer 126 is deposited in the formed recess, and a planarization process such as CMP is performed to make the top surface of the protective layer 126 flush with the top surface of the mask 116. In some embodiments, the protective layer 126 may include SiN, SiC, SiCN, SiCO, combinations thereof, etc., and the protective layer 126 may be deposited using ALD, CVD, combinations thereof, etc.

[0039] exist Figure 9 In the process, the dummy gate 114 and mask 116 are removed in one (or more) etching steps (see...). Figure 8This forms an opening 128. In some embodiments, a portion of the dummy dielectric layer 108 in the opening 128 may also be removed. In other embodiments, only the dummy gate 114 is removed, while the dummy dielectric layer 108 is retained and exposed by the opening 128. In some embodiments, the dummy dielectric layer 108 is removed from the opening 128 in a first region of the die (e.g., a core logic region) and retained in the opening 128 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 114 and the mask 116 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process that selectively etches the dummy gate 114 and the mask 116 without etching the protective layer 126, the gate sealing spacer 118, and the gate spacer 120 using a reactive gas. Each opening 128 exposes a corresponding channel region of the active region 106. Each channel region is disposed between adjacent pairs of epitaxial source / drain regions 122. During removal, the dummy dielectric layer 108 can be used as an etch stop layer when etching the dummy gate 114 and mask 116. The dummy dielectric layer 108 can then be optionally removed after the removal of the dummy gate 114 and mask 116.

[0040] exist Figure 10 In the middle, at opening 128 (see Figure 9 A gate dielectric layer 130 and a gate electrode 132 are formed in the gate to form a gate stack 134. The gate stack 134 may also be referred to as a replacement gate stack. Figure 11 It shows Figure 10 A detailed view of region 136. In some embodiments, in opening 128 (see...) Figure 9 The material forming the gate dielectric layer 130. The material forming the gate dielectric layer 130 may also be a material formed on the top surface of the protective layer 126. In some embodiments, the gate dielectric layer 130 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 130 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 130 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 130 may include molecular beam deposition (MBD), ALD, PECVD, combinations thereof, etc.

[0041] Subsequently, material for the gate electrode 132 is deposited over the gate dielectric layer 130 and the opening 128 is filled (see [link]). Figure 9 The remainder of ). Although in Figure 10 The diagram shows a single-layer gate electrode 132, but the gate electrode 132 may include any number of pad layers 132A, any number of work function adjustment layers 132B, and conductive fill layers 132C, such as Figure 11As shown. The liner layer 132A may include TiN, TiO, TaN, TaC, combinations thereof, multilayers thereof, etc., and can be formed using PVD, CVD, ALD, combinations thereof, etc. In region 100N, the work function adjustment layer 132B may include Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, multilayers thereof, etc., and can be formed using PVD, CVD, ALD, combinations thereof, etc. In region 100P, the work function adjustment layer 132B may include TiN, WN, TaN, Ru, Co, combinations thereof, multilayers thereof, etc., and can be formed using PVD, CVD, ALD, combinations thereof, etc. In some embodiments, the conductive filler layer 132C may include Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, multilayers thereof, etc., and the conductive filler layer 132C may be formed by PVD, CVD, ALD, electroplating, plating, combinations thereof, etc.

[0042] In filling opening 128 (see Figure 9 Afterward, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 130 and the gate electrode 132 located above the top surface of the protective layer 126. The remaining portions of the gate electrode 132 and the gate dielectric layer 130 thus form the gate stack 134 of the semiconductor device 100.

[0043] The formation of the gate dielectric layer 130 in regions 100N and 100P can occur simultaneously, such that the gate dielectric layer 130 in each region is formed of the same material. In other embodiments, the gate dielectric layer 130 in each region can be formed using different processes, such that the gate dielectric layer 130 in different regions can be formed of different materials. The formation of the conductive fill layer 132C in regions 100N and 100P can occur simultaneously, such that the conductive fill layer 132C in each region is formed of the same material. In other embodiments, the conductive fill layer 132C in each region can be formed using different processes, such that the conductive fill layer 132C in different regions can be formed of different materials. When using different processes, individual masking steps can be used to mask and expose appropriate regions.

[0044] exist Figure 12In this process, the gate stack 134 is recessed downwards below the top surface of the protective layer 126 to form a groove 138. In some embodiments, the recessing process includes one or more etching processes. The one or more etching processes may include etching processes that are selective to the material of the gate stack 134 and substantially do not etch the materials of the protective layer 126, the gate sealing spacer 118, and the gate spacer 120. The groove 138 extends below the top surface of the protective layer 126 to a depth D1. In some embodiments, the depth D1 is between about 25 nm and about 150 nm.

[0045] Figure 13 and Figure 15 This is a cross-sectional view of an intermediate stage in the fabrication of a hard mask 140 over a gate stack 134, according to some embodiments. Figure 13 In the middle, along groove 138 (see Figure 12 A first layer 140A is formed on the sidewalls and bottom of the protective layer 126, a second layer 140B is formed on the first layer 140A, and a third layer 140C is formed on the second layer 140B. In some embodiments, the third layer 140C passes through the filling groove 138 (see...). Figure 12 In other embodiments, the third layer 140C is omitted. In such an embodiment, the second layer 140B is filled through the groove 138 (see...). Figure 12 The first layer 140A may also be referred to as a padding layer, the second layer 140B may also be referred to as a support layer, the third layer 140C may also be referred to as a cover layer, and the hard mask 140 may also be referred to as a self-aligned contact (SAC) hard mask. In some embodiments, the first layer 140A has a thickness between about 2 nm and about 10 nm. In some embodiments, the second layer 140B has a thickness between about 2 nm and about 10 nm. In some embodiments, the third layer 140C has a thickness between about 10 nm and about 30 nm.

[0046] Figure 14 This illustrates a first layer 140A, a second layer 140B, and a third layer 140C for a hard mask 140 according to some embodiments (see...). Figure 13 and Figure 15A table of possible materials is provided. In Example #1, the first layer 140A comprises SiN, the second layer 140B comprises Si, a metal nitride material (such as TaN, TiN, AlN, or ZrN), or a metal oxide material (such as TiO, HfO, AlO, or ZrO), and the third layer 140C comprises SiN. In Example #2, the first layer 140A comprises TiN, the second layer 140B comprises AlN, and the third layer 140C comprises SiN. In Example #3, the first layer 140A comprises AlN, the second layer 140B comprises TiN, and the third layer 140C comprises SiN. In Example #4, the first layer 140A comprises a metal nitride material (such as TiN, AlN, or ZrN) or a metal oxide material (such as TiO, HfO, AlO, or ZrO), the second layer 140B comprises SiN, and the third layer 140C is omitted. In embodiment #5, the first layer 140A comprises SiN, the second layer 140B comprises a metal nitride material (such as TaN, AlN, or TiN), and the third layer 140C is omitted. In some embodiments, a hard mask 140 comprising a metal oxide material has better insulating properties than a hard mask 140 comprising a metal nitride material.

[0047] Return to reference Figure 13 The first layer 140A, the second layer 140B, and the third layer 140C can be formed using plasma-enhanced ALD (PEALD) processes, thermal ALD processes, etc. In some embodiments, the PEALD process is performed using a plasma system, such as a 13.56 Hz capacitively coupled plasma (CCP) system with a power between about 100 W and 800 W, and a process temperature between about 200°C and about 500°C. In some embodiments, the ALD process is performed at a process temperature between about 100°C and about 400°C.

[0048] In some embodiments, when the first layer 140A, the second layer 140B, or the third layer 140C is made of SiN, a process gas mixture including a silicon precursor gas, a nitrogen precursor gas, and additional gases is used to perform the PEALD or ALD process. In some embodiments, the silicon precursor gas includes SiH2I2 (diiodosilane) gas, the nitrogen precursor gas includes N2 gas, and the additional gas includes H2 gas. In other embodiments, the silicon precursor gas includes SiH2Cl2 (dichlorosilane) gas, the nitrogen precursor gas includes N2 gas, NH3 gas, or a mixture thereof, and the additional gas includes Ar gas.

[0049] In some embodiments, when the first layer 140A or the second layer 140B is made of TaN, a process gas mixture comprising a tantalum precursor gas, a nitrogen precursor gas, and additional gases is used to perform the PEALD or ALD process. In some embodiments, the tantalum precursor gas includes TaCl5, Ta(NMe2)5, Ta(OEt)5, and Ta(N t Bu)(NEt2)3、Ta(N t Pn)(NMe2)3, Ta(NMe2)5, TaF5, Ta(N t Bu)(NEtMe)3, or Ta(N i Pr)(NEtMe)3, the nitrogen precursor gas includes N2 gas, NH4 gas or mixtures thereof, and additional gases include H2 gas.

[0050] In some embodiments, when the first layer 140A or the second layer 140B is made of TiN, a process gas mixture comprising a titanium precursor gas, a nitrogen precursor gas, and additional gases is used to perform the PEALD or ALD process. In some embodiments, the titanium precursor gas comprises TiCl4 or Ti(NMe2)4, the nitrogen precursor gas comprises N2 gas, NH3 gas, or a mixture thereof, and the additional gas comprises H2 gas.

[0051] In some embodiments, when the first layer 140A or the second layer 140B is made of HfO, a process gas mixture including hafnium precursor gas, oxygen precursor gas, and additional gases is used to perform the PEALD or ALD process. In some embodiments, the hafnium precursor gas includes Hf(NEt2)4, Hf(NEtMe)4, Hf(NMe2)4, Hf(OH)3NH2, Hf(mp)4, and Hf(O)4. t Bu)4, the oxygen precursor gas includes O2 gas, and the additional gas includes N2 gas.

[0052] In some embodiments, when the first layer 140A or the second layer 140B is made of TiO, a process gas mixture including titanium precursor gas and oxygen precursor gas is used to perform the PEALD or ALD process.

[0053] In some embodiments, the titanium precursor gas includes TiCl4 or Ti(NMe2)4, and the oxygen precursor gas includes O2 gas, H2O gas, or a mixture thereof.

[0054] In some embodiments, when the first layer 140A or the second layer 140B is made of AlO, a process gas mixture including aluminum precursor gas and oxygen precursor gas is used to perform the PEALD or ALD process.

[0055] In some embodiments, the aluminum precursor gas includes AlH3 (MeNC4H4) or AlMe3, and the oxygen precursor gas includes CO2 gas, O2 gas, H2O gas, or a mixture thereof.

[0056] In some embodiments, when the first layer 140A or the second layer 140B is made of AlN, a process gas mixture comprising an aluminum precursor gas, a nitrogen precursor gas, and an additional gas is used to perform the PEALD or ALD process. In some embodiments, the aluminum precursor gas comprises AlH3 (MeNC4H4) or AlMe3, the nitrogen precursor gas comprises N2 gas, NH3 gas, or a mixture thereof, and the additional gas comprises H2 gas.

[0057] In some embodiments, when the first layer 140A or the second layer 140B is made of ZrO, a process gas mixture comprising a zirconium precursor gas, an oxygen precursor gas, and an additional gas is used to perform the PEALD or ALD process. In some embodiments, the zirconium precursor gas comprises Zr(NEt2)4, Zr(NEtMe)4, or Zr(OtBu)4, the oxygen precursor gas comprises O2 gas, and the additional gas comprises N2 gas.

[0058] exist Figure 15 In the filling groove 138 (see Figure 12 Following this, a planarization process such as CMP can be performed to remove excess portions of the first layer 140A, the second layer 140B, and the third layer 140C, which lie above the top surface of the ILD 124. In some embodiments, the planarization process also removes the protective layer 126, thereby exposing the top surface of the ILD 124. The remaining portions of the first layer 140A, the second layer 140B, and the third layer 140C form a hard mask 140. After the planarization process, the top surface of the hard mask 140 is substantially coplanar or flush with the top surface of the ILD 124 within the process variations of the planarization process. In some embodiments, the hard mask 140 has a height H1 between about 50 nm and about 90 nm. In other embodiments, the hard mask 140 has a height H1 between about 10 nm and about 30 nm.

[0059] By using the above reference Figure 14 The material forms a first layer 140A and / or a second layer 140B, the sidewalls and corners of the hard mask 140 are reinforced and the sidewall and corner losses are reduced or avoided in the subsequent etching process that forms openings for the source / drain contacts.

[0060] exist Figure 16In this embodiment, ILD 142 is formed over hard mask 140 and ILD 124, and hard mask 144 is formed over ILD 142. In some embodiments, ILD 142 may be formed using materials and methods similar to those used for ILD 124, and this description will not be repeated here. In some embodiments, ILD 124 and ILD 142 comprise the same material. In other embodiments, ILD 124 and ILD 142 comprise different materials. In some embodiments, hard mask 144 may comprise TiN, WC, W, WCN, WN, Ti, SiN, SiC, SiCN, SiCO, combinations thereof, etc., and hard mask 144 may be formed using CVD, ALD, combinations thereof, etc.

[0061] exist Figure 17 In this embodiment, hard masks 144 and ILDs 124 and 142 are patterned to form openings 146. In the illustrated embodiment, opening 146 fully exposes epitaxial source / drain regions 122A and 122B, fully exposes a hard mask 140”' inserted between epitaxial source / drain regions 122A and 122B, partially exposes a hard mask 140’ adjacent to epitaxial source / drain region 122A, and partially exposes a hard mask 140” adjacent to epitaxial source / drain region 122B. Specifically, opening 146 includes a first opening 146A exposing epitaxial source / drain region 122A, a second opening 146B exposing epitaxial source / drain region 122B, and a third opening 146C exposing hard masks 140’, 140”, and 140”. In other embodiments, the opening 146 may expose any number of epitaxial source / drain regions 122 and any number of hard masks 140, depending on the design requirements of the semiconductor device 100.

[0062] In some embodiments, the patterning process for forming the opening 146 may include a first patterning process for patterning the hard mask 144 and a second patterning process for patterning the ILDs 124 and 142. In some embodiments, the first patterning process includes suitable photolithography and etching processes. The first etching process of the first patterning process may be a dry etching process, a wet etching process, etc. The first etching process may be anisotropic.

[0063] In some embodiments, the second patterning process includes using a patterned hard mask 144 as an etching mask and transferring the pattern of the patterned hard mask 144 to ILDs 124 and 142 in a second etching process. In some embodiments, the second etching process is an atomic layer etching (ALE) process and uses a fluorocarbon compound (having the chemical formula C) x F yThe second etching process is performed using etchants such as CF2, C4F6, C3F8, CH3F, etc., O2, CO2, Ar, or N2, or combinations thereof. In some embodiments, the second etching process may be anisotropic.

[0064] Further in Figure 17 In some embodiments, the second etching process further etches the exposed hard masks 140', 140”, and 140”', such that the corners of the exposed hard masks 140' and 140” are removed and the height of the exposed hard mask 140”' is reduced. After the second etching process is completed, the exposed hard mask 140”' has a height H2. In some embodiments, the height H2 of the exposed hard mask 140”' is less than the height H1 of the unetched hard mask 140 (see [link to documentation]). Figure 15 In some embodiments, height H2 is between about 5 nm and about 25 nm. In some embodiments, height H2 and height H1 (see...) Figure 15 The ratio is between approximately 0.055 and approximately 1. This is based on the above reference. Figure 14 The material forms the first layer 140A and / or the second layer 140B of the hard mask 140, and the sidewalls and corners of the hard masks 140', 140” and 140”' are reinforced and the loss of sidewalls, corners and height is reduced or avoided.

[0065] Furthermore, in some embodiments, the second etching process also etches gate sealing spacers 118 and 120 adjacent to the epitaxial source / drain regions 122A and 122B. In some embodiments, after the second etching process is completed, the width of the etched gate sealing spacer 118 decreases as the etched gate sealing spacer 118 extends away from the active region 106, and the width of the etched gate spacer 120 decreases as the etched gate spacer 120 extends away from the active region 106.

[0066] Figure 18 This is a flowchart illustrating an ALE process 200 according to some embodiments. Figure 19 and Figure 20 This is a cross-sectional view of an intermediate stage during the execution of ALE process 200 according to some embodiments. (Reference) Figure 18 and Figure 19 The ALE process 200 includes performing N ALE cycles 202. In some embodiments, N is between 1 and 50. In some embodiments, the ALE cycle 202 includes performing step 204, wherein, on the layer 212 to be etched (e.g., such as...), Figure 17A first gas 214 is introduced over the ILD layers 124 and 142 shown. In some embodiments, the first gas 214 may comprise a fluorocarbon gas and may be ionized. In some embodiments, the first gas 214 is adsorbed onto the exposed surface of layer 212. In some embodiments, the time for introducing the first gas 214 is between about 0.1 seconds and about 20 seconds. In some embodiments, the flow rate of the first gas 214 is between about 0.1 sccm and about 200 sccm.

[0067] In some embodiments, the adsorbed fluorocarbon gas forms a fluoropolymer layer 216 above layer 212. In some embodiments, the thickness of the fluoropolymer layer 216 depends on the material of layer 212, such as... Figure 20 As shown. In some embodiments, when layer 212 is made of silicon oxide, the fluoropolymer layer 216 has a thickness T1 between about 0 nm and about 5 nm. In some embodiments, when layer 212 is made of silicon nitride, the fluoropolymer layer 216 has a thickness T2 between about 0 nm and about 15 nm. In some embodiments, when layer 212 is made of silicon, the fluoropolymer layer 216 has a thickness T3 between about 0 nm and about 20 nm. In some embodiments, when layer 212 is made of metal oxide or metal nitride, the fluoropolymer layer 216 has a thickness T4 between about 0 nm and about 40 nm. In some embodiments, thickness T1 is less than thickness T2, thickness T2 is less than thickness T3, and thickness T3 is less than thickness T4. As described in more detail below, the thickness of the fluoropolymer layer 216 affects the etch rate of layer 212, such that layer 212 with a thicker fluoropolymer layer has a lower etch rate.

[0068] Further reference Figure 18 and Figure 19 In step 206, the unadsorbed portion of the first gas 214 is purged with a non-reactive gas such as N2, Ar, or combinations thereof. In some embodiments, the purging time is between 1 second and 10 seconds. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0069] In step 208, a second gas 220 is introduced over layer 212. In some embodiments, the second gas 220 comprises gases that have been ionized to obtain Ar. + Ar gas with ions. In some embodiments, Ar is made... + Ions are accelerated toward and bombard layer 212. Due to the bombardment, the bonds between the atoms in layer 212 are broken. In some embodiments, when layer 212 is made of silicon oxide, Ar is used... +The bombardment of ions breaks the bonds between silicon atoms 218 and oxygen atoms (not shown). Subsequently, molecules of the first gas 214 adsorbed on layer 212 (e.g., molecules such as fluorocarbon molecules) react with silicon atoms 218 to form volatile byproducts 222.

[0070] In some embodiments, the fluoropolymer layer 216 formed above layer 212 protects layer 212 from Ar. + Damage from ion bombardment. In some embodiments, the material on which a thicker fluoropolymer layer is formed has fewer broken bonds, which results in the generation of fewer volatile byproducts 222 and subsequently a lower etching rate.

[0071] In step 210, volatile byproducts 222 are purged using a non-reactive gas such as N2, Ar, or combinations thereof. In some embodiments, the purging time is between 1 second and 10 seconds. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm. In some embodiments, ALE cycle 202 etches atomic layers 212a of layer 212. The number of atomic layers removed from layer 212 can be adjusted by changing the amount of N in the ALE cycle.

[0072] Return to reference Figure 17 The material of hard mask 140 is selected so that ILD 124 and 142 are etched using ALE process 200 (see...). Figure 18 and Figure 19 When the hard mask 140 is not significantly etched, in some embodiments, as referenced above... Figure 14 The materials used in the selection of the first layer 140A and / or the second layer 140B are described, and the etch rate of the hard mask 140 is lower than the etch rates of ILDs 124 and 142. In some embodiments, as referenced above... Figure 14 The materials of the first layer 140A and / or the second layer 140B described have high ion bombardment resistance and low sputtering yield (due to high binding energy and high density), and allow the formation of a thick non-volatile fluorocarbon polymer layer for further protection against ion bombardment damage.

[0073] exist Figure 21 In this process, a cleaning process is performed on the exposed epitaxial source / drain regions 122A and 122B. In some embodiments, the cleaning process removes any residual oxides that may remain on the exposed epitaxial source / drain regions 122A and 122B after the formation of the opening 146. In some embodiments, the cleaning process also removes the hard mask 144 (see...). Figure 17 And expose ILD 142. As described in more detail below, in some embodiments, the cleaning process includes using an etching system 300 (see [link to etching system]). Figure 22The etching process is performed, and then a heating device 400 (see...) is used. Figure 23 Perform heat treatment.

[0074] exist Figure 22 In some embodiments, it will include Figure 17 A wafer 303 with a specific structure is introduced into a chamber 301 of an etching system 300. The etching system 300 includes a platform 305 within the chamber 301, and the wafer 303 is placed on the platform 305. In some embodiments, the platform 305 includes a cooling line 307, such as a water line, configured to maintain the temperature of the wafer 303 within a desired temperature range. In some embodiments, the temperature of the wafer 303 is between about 20°C and about 90°C. In some embodiments, the etching system 300 also includes inlets 309A and 309B, and outlets 311A ​​and 311B. Inlets 309A and 309B are configured to introduce process gases into the chamber 301. Outlets 311A ​​and 311B are configured to discharge reaction byproducts from the chamber 301. In some embodiments, inlet 309A introduces NH3 gas into the chamber 301, and inlet 309B introduces HF gas into the chamber 301. In some embodiments, the NH3 gas and HF gas are mixed before the gas mixture is introduced into the chamber 301.

[0075] In some embodiments, NH3 and HF molecules are adsorbed onto the surface of wafer 303 and react with residual oxides, such as silicon oxide. NH3 and HF molecules react with silicon oxide through reactions (1) and (2):

[0076] SiO2+4F+4NH3-->SiF4+2H2O+4NH3 (1)

[0077] SiF4+2HF+2NH3-->(NH4)2SiF6 (2)

[0078] As a result of reactions (1) and (2), compound layer 313 is formed on the surface of wafer 303 at the location of residual oxide. In some embodiments, compound layer 313 comprises (NH4)2SiF6.

[0079] exist Figure 23In this process, wafer 303 is transferred into heating device 400. Heating device 400 includes platform 403 located within chamber 401, and wafer 303 is placed on platform 403. In some embodiments, platform 403 includes heater 405 configured to raise the temperature of wafer 303 to a desired temperature. Heater 405 may include one or more heating elements, such as resistance heating elements. In some embodiments, wafer 303 is heated to a temperature between about 100°C and about 200°C for a duration between about 7 seconds and about 120 seconds. In some embodiments, heat treatment of wafer 303 is performed to decompose compound layer 313 into volatile components through chemical reaction (3).

[0080] (NH4)2SiF6-->SiF4+2HF+2NH3. (3)

[0081] Subsequently, the volatile components are discharged from chamber 401 through outlets 407A and 407B. In some embodiments, for example, the heat treatment process is performed in a non-reactive gas atmosphere, such as an N2 gas atmosphere.

[0082] exist Figure 24 and Figure 25 In this configuration, source / drain contacts 152A and 152B are formed above the epitaxial source / drain regions 122A and 122B, respectively. Figure 24 In the process of performing the cleaning process, an opening 146 (see [link to article]) is made above the epitaxial source / drain regions 122A and 122B. Figure 21 Silicide layers 148A and 148B are formed respectively. In some embodiments, a metal material is deposited in the opening 146. The metal material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, combinations thereof, etc., and may be formed using PVD, sputtering, combinations thereof, etc. Subsequently, an annealing process is performed to form silicide layers 148A and 148B. In some embodiments where the epitaxial source / drain region 122 includes silicon, the annealing process reacts the metal material with silicon to form a silicide of the metal material at the interface between the metal material and the epitaxial source / drain region 122. After the formation of silicide layers 148A and 148B, unreacted portions of the metal material are removed, for example, using a suitable removal process such as a suitable etching process.

[0083] After the formation of silicide layers 148A and 148B, at opening 146 (see...) Figure 21A conductive layer 150 is formed in and above the ILD 142. In some embodiments, the conductive layer 150 fills the opening 146. In some embodiments, the conductive layer 150 is formed by first forming a barrier layer (not shown separately) in and above the opening 146. The barrier layer may extend along the bottom and sidewalls of the opening 146. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, multilayers thereof, etc., and may be formed by ALD, CVD, PVD, sputtering, combinations thereof, etc. Subsequently, an adhesion layer (not shown separately) is formed in and above the barrier layer in and above the opening 146. The adhesion layer may include cobalt, ruthenium, alloys thereof, combinations thereof, multilayers thereof, etc., and may be formed by ALD, CVD, PVD, sputtering, combinations thereof, etc. After forming the adhesion layer, a seed layer (not shown separately) is formed in and above the adhesion layer in and above the opening 146. The seed layer may include copper, titanium, nickel, gold, manganese, combinations thereof, multilayers thereof, etc., and may be formed by ALD, CVD, PVD, sputtering, combinations thereof, etc. Subsequently, a conductive filler material (not shown separately) is formed within the opening 146 and above the seed layer above the ILD 142. In some embodiments, the conductive filler material fills the opening 146. The conductive filler material may include copper, aluminum, tungsten, ruthenium, cobalt, combinations thereof, alloys thereof, multilayers thereof, etc., and may be formed using, for example, plating, ALD, CVD, PVD, or other suitable methods.

[0084] exist Figure 25 In the process of forming conductive layer 150 (see...) Figure 24 After that, a planarization process is performed to remove the overfilled openings 146 of the conductive layer 150 (see...). Figure 21 In some embodiments, the planarization process also removes ILD 142 (see [reference]). Figure 24 The portion of ILD 124, the portion of hard mask 140, the portion of gate sealing spacer 118, and the portion of gate spacer 120. The remaining portion of conductive layer 150 is in opening 146A (see...). Figure 21 Source / drain contacts 152A are formed in the opening 146B, and source / drain contacts 152B are formed in the opening 146B. The planarization process may include CMP, etch-back, polishing, or combinations thereof. After the planarization process, the top surfaces of the source / drain contacts 152A, 152B, ILD 124, hard mask 140, gate sealing spacer 118, and gate spacer 120 are substantially flush or coplanar with each other within the process variations of the planarization process. This is achieved by using the above reference... Figures 13 to 15The material forms a hard mask 140, which is essentially unetched and provides good isolation between the source / drain contacts 152A and 152B.

[0085] In some embodiments, due to the above references Figure 17 In the described etching process, the width of hard mask 140' decreases as hard mask 140' extends away from the top surface of the corresponding gate stack 134, the width of hard mask 140" decreases as hard mask 140" extends away from the top surface of the corresponding gate stack 134, and the width of hard mask 140"' decreases as hard mask 140"' extends away from the top surface of the corresponding gate stack 134. In some embodiments, the width of source / drain contact 152A increases as source / drain contact 152A extends away from epitaxial source / drain region 122A, and the width of source / drain contact 152B increases as source / drain contact 152B extends away from epitaxial source / drain region 122B.

[0086] exist Figure 26 In this embodiment, ILD 154 is formed over ILD 124, hard mask 140, and source / drain contacts 152. In some embodiments, ILD 154 may be formed using materials and methods similar to those used for ILD 124, and this description will not be repeated here. In some embodiments, ILD 124 and 154 comprise the same material. In other embodiments, ILD 124 and 154 comprise different materials. In some embodiments, gate contacts 156 are formed to make electrical contact with a corresponding gate stack 134, and conductive vias 158 are formed to make electrical contact with a corresponding source / drain contact 152. In some embodiments, ILD 154 and hard mask 140 are patterned to form openings for gate contacts 156 and conductive vias 158. In some embodiments, the patterning process includes suitable photolithography and etching processes. Suitable etching processes may include one or more dry etching processes. The etching process may be anisotropic. An opening for the gate contact 156 extends through the ILD 154 and the corresponding hard mask 140, exposing the corresponding gate stack 134. An opening for the conductive via 158 extends through the ILD 154, exposing the corresponding source / drain contact 152. After forming the opening, the gate contact 156 and the conductive via 158 are formed in the corresponding opening. In some embodiments, the gate contact 156 and the conductive via 158 may be formed using materials and methods similar to those used for the source / drain contacts 152, and this description will not be repeated here.

[0087] Figure 27A cross-sectional view of a semiconductor device 500 according to some embodiments is shown. Semiconductor device 500 and semiconductor device 100 (see...) Figure 26 Similarly, similar components are labeled with similar reference numerals, and descriptions of similar components will not be repeated here. In some embodiments, reference numerals similar to those described above may be used. Figures 1 to 16 The process steps described are used to form the semiconductor device 500, and this description will not be repeated here. In the illustrated embodiment, a hard mask 140 is formed such that layer 140C (see...) Figure 26 () is omitted.

[0088] According to an embodiment, the device includes a substrate containing an active region, a gate stack above the active region, and a hard mask above the gate stack. The hard mask includes a capping layer, a support layer extending along the sidewalls and bottom of the capping layer, and a pad layer extending along the sidewalls and bottom of the support layer. The support layer includes a metal oxide material or a metal nitride material.

[0089] The embodiments may include one or more of the following components: In the device, the pad layer includes a first nitride material different from the metal nitride material. In the device, the capping layer includes a second nitride material different from the metal nitride material. In the device, the first nitride material and the second nitride material are the same. In the device, the first nitride material and the second nitride material are different. The device also includes an epitaxial source / drain region extending into an active region adjacent to the gate stack. The device also includes a source / drain contact located above the epitaxial source / drain region, the top surface of the source / drain contact being flush with the top surface of the hard mask.

[0090] According to another embodiment, the device includes a substrate containing an active region, a first spacer structure and a second spacer structure located above the active region, a gate stack located above the active region and between the first spacer structure and the second spacer structure, and a hard mask located above the gate stack and between the first spacer structure and the second spacer structure. A first sidewall of the first spacer structure faces a second sidewall of the second spacer structure. The top surface of the gate stack is lower than the top surface of the first spacer structure and the top surface of the second spacer structure. The hard mask includes a pad layer extending along the top surface of the gate stack, the first sidewall of the first spacer structure, and the second sidewall of the second spacer structure, a support layer located above the pad layer, and a capping layer located above the support. The pad layer includes a first nitride material. The support layer includes a second nitride material or a first oxide material. The capping layer includes a third nitride material. The device also includes an epitaxial source / drain region embedded in the active region adjacent to the first spacer structure and a source / drain contact located above the epitaxial source / drain region and adjacent to the first spacer structure. The top surface of the source / drain contact is flush with the top surface of the hard mask.

[0091] Embodiments may include one or more of the following components. In the device, the width of the first spacer structure decreases as the first spacer structure extends away from the active region. In the device, the width of the second spacer structure decreases as the second spacer structure extends away from the active region. In the device, the width of the source / drain contact increases as the source / drain contact extends away from the epitaxial source / drain region. In the device, the first nitride material includes SiN, the second nitride material includes TaN, TiN, AlN, or ZrN, and the third nitride material includes SiN. In the device, the first nitride material includes SiN, the first oxide material includes TiO, HfO, AlO, or ZrO, and the third nitride material includes SiN. In the device, the first nitride material includes TiN or AlN, the second nitride material includes TiN or AlN, and the third nitride material includes SiN.

[0092] According to another embodiment, a method includes forming a dummy gate structure over an active region of a substrate, the dummy gate structure having a first sidewall and a second sidewall opposite to the first sidewall; forming a first spacer structure on the first sidewall of the dummy gate structure; forming a second spacer structure on the second sidewall of the dummy gate structure; replacing the dummy gate structure with a replacement gate structure such that the replacement gate structure is recessed to form a groove embedded between the first spacer structure and the second spacer structure; and forming a hard mask in the groove. Forming the hard mask includes forming a pad layer along the sidewalls and bottom of the groove; forming a support layer over the pad layer in the groove; and forming a capping layer over the support layer in the groove. The support layer comprises a metal nitride material or a metal oxide material.

[0093] The embodiment may include one or more of the following components. The method further includes forming an epitaxial source / drain region in an active region adjacent to the first spacer structure. The method further includes forming a source / drain contact above the epitaxial source / drain region and adjacent to the first spacer structure, the top surface of the source / drain contact being flush with the top surface of the hard mask. In this method, the pad layer and the support layer comprise different materials. The capping layer and the support layer comprise different materials. In this method, the metal nitride material is TaN, TiN, AlN, or ZrN, and the metal oxide material is TiO, HfO, AlO, or ZrO.

[0094] The foregoing outlines the features of the embodiments described herein, enabling those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: Substrate, including the active region; A gate stack is located above the active region; as well as A hard mask, located above the gate stack, includes: a cover layer; a support layer extending along the sidewalls and bottom of the cover layer, wherein the support layer comprises a metal nitride material; and a pad layer extending along the sidewalls and bottom of the support layer. The liner layer includes a first nitride material that is different from the metal nitride material.

2. The semiconductor device according to claim 1, wherein, The substrate is a semiconductor substrate.

3. The semiconductor device according to claim 1, wherein, The capping layer includes a second nitride material that is different from the metal nitride material.

4. The semiconductor device according to claim 3, wherein, The first nitride material is the same as the second nitride material.

5. The semiconductor device according to claim 3, wherein, The first nitride material is different from the second nitride material.

6. The semiconductor device of claim 1, further comprising an epitaxial source / drain region extending into the active region adjacent to the gate stack.

7. The semiconductor device of claim 6 further includes a source / drain contact located above the epitaxial source / drain region, the top surface of the source / drain contact being flush with the top surface of the hard mask.

8. A semiconductor device, comprising: Substrate, including the active region; A first spacer structure and a second spacer structure are located above the active region, with the first sidewall of the first spacer structure facing the second sidewall of the second spacer structure. A gate stack is located above the active region and between the first spacer structure and the second spacer structure, wherein the top surface of the gate stack is lower than the top surface of the first spacer structure and the top surface of the second spacer structure. A hard mask, located above the gate stack and between the first spacer structure and the second spacer structure, the hard mask comprising: a pad layer extending along the top surface of the gate stack, the first sidewall of the first spacer structure, and the second sidewall of the second spacer structure, the pad layer comprising a first nitride material; a support layer located above the pad layer, the support layer comprising a second nitride material or a first oxide material; and a cover layer located above the support layer, the cover layer comprising a third nitride material; Epitaxial source / drain regions are embedded in the active region adjacent to the first spacer structure; and A source / drain contact is located above the epitaxial source / drain region and adjacent to the first spacer structure, and the top surface of the source / drain contact is flush with the top surface of the hard mask.

9. The semiconductor device according to claim 8, wherein, The width of the first spacer structure decreases as the first spacer structure extends away from the active region.

10. The semiconductor device according to claim 9, wherein, The width of the second spacer structure decreases as the second spacer structure extends away from the active region.

11. The semiconductor device according to claim 8, wherein, The width of the source / drain contact increases as the source / drain contact extends away from the epitaxial source / drain region.

12. The semiconductor device according to claim 8, wherein, The first nitride material includes SiN, the second nitride material includes TaN, TiN, AlN or ZrN, and the third nitride material includes SiN.

13. The semiconductor device according to claim 8, wherein, The first nitride material includes SiN, wherein the first oxide material includes TiO, HfO, AlO or ZrO, and wherein the third nitride material includes SiN.

14. The semiconductor device according to claim 8, wherein, The first nitride material includes TiN or AlN, the second nitride material includes TiN or AlN, and the third nitride material includes SiN.

15. A method of forming a semiconductor device, comprising: A dummy gate structure is formed above the active region of the substrate, the dummy gate structure having a first sidewall and a second sidewall opposite to the first sidewall; A first spacer structure is formed on the first sidewall of the dummy gate structure; A second spacer structure is formed on the second sidewall of the dummy gate structure; Replace the dummy gate structure with a replacement gate structure; The replacement gate structure is recessed to form a groove embedded between the first spacer structure and the second spacer structure; as well as A hard mask is formed in the groove, wherein forming the hard mask includes: forming a padding layer along the sidewalls and bottom of the groove; forming a support layer above the padding layer in the groove, the support layer comprising a metal nitride material; and forming a cover layer above the support layer in the groove, wherein the padding layer comprises a first nitride material different from the metal nitride material.

16. The method of claim 15, further comprising forming an epitaxial source / drain region in the active region adjacent to the first spacer structure.

17. The method of claim 16, further comprising forming a source / drain contact above the epitaxial source / drain region and adjacent to the first spacer structure, the top surface of the source / drain contact being flush with the top surface of the hard mask.

18. The method according to claim 15, wherein, The substrate is a semiconductor substrate.

19. The method according to claim 15, wherein, The cover layer and the support layer comprise different materials.

20. The method of claim 15, wherein, The metal nitride material is TaN, TiN, AlN, or ZrN.

Images