Glitch-free multi-clock switching circuit supporting design for testability

Abstract

A glitch-free multi-clock switching circuit supporting testability design relates to integrated circuit technology. The invention comprises a clock selection decoding circuit and N parallel clock signal branches, where N is an integer greater than 2; the clock signal branches comprise: a selector, a reset processor, a multi-input AND gate, a synchronizer, a branch D flip-flop, and a gated clock module; the bypass control terminal of each clock signal branch is connected to a bypass input terminal of the multi-input AND gate in all other branches, and each bypass input terminal is only connected to one bypass control terminal. The invention supports glitch-free clock switching, and the invention switches at the falling edge of the clock. Due to the existence of negative feedback, it is ensured that only one clock is turned on at the same time.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology. Background Art

[0002] The glitch-free clock switching circuit is widely used in the design of SOC or ASIC chips because it can ensure that no glitches are generated during the clock switching process. The glitch-free clock switching circuit in the prior art is difficult to meet the requirements of testability design. It is difficult to test the circuit directly. Using other testing methods requires more testing time and it is difficult to achieve a high test coverage. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a glitch-free multi-clock switching circuit structure which can be flexibly configured and can support testability design.

[0004] The technical solution adopted by the present invention to solve the technical problem is to provide a glitch-free multi-clock switching circuit supporting testability design, characterized in that it includes a clock selection decoding circuit and N parallel clock signal branches, where N is an integer greater than 2;

[0005] The clock signal branch comprises:

[0006] A selector, whose first input terminal is connected to the test clock point, whose second input terminal is used as the clock signal input terminal of the branch where it is located, and whose control terminal is connected to the mode signal input point;

[0007] A reset processor, wherein the control terminal is connected to the mode signal input point, the test reset terminal is connected to the test reset signal input point, the reset signal terminal is connected to the reset signal input point, and the clock signal input terminal is connected to the output end of the selector of the branch;

[0008] A multi-input AND gate having a clock input and N-1 bypass inputs,

[0009] A synchronizer, whose synchronization signal input terminal is connected to the output terminal of the multi-input AND gate of the branch, whose clock signal input terminal is connected to the output terminal of the selector of the branch, and whose reset signal terminal is connected to the output terminal of the reset processor of the branch.

[0010] A branch D flip-flop, whose D terminal is connected to the output terminal of the synchronizer of the branch, whose clock terminal is connected to the output terminal of the selector of the branch, and whose reset terminal is connected to the output terminal of the reset processor. The end serves as the bypass control end of this branch;

[0011] A gated clock module, whose enable clock input terminal is connected to the Q terminal of the branch D flip-flop, whose input clock terminal is connected to the output terminal of the selector of the branch, whose control terminal mode signal input point, and whose output terminal is used as the final output terminal of the branch;

[0012] The bypass control terminal of each clock signal branch is connected to a bypass input terminal of the multi-input AND gate in all other branches, and each bypass input terminal is connected to only one bypass control terminal;

[0013] The final output of each clock signal branch is connected one by one to each input of the multi-input OR gate, the output of the multi-input OR gate is connected to the first input of the output selector, and the second input of the output selector is connected to the test clock point.

[0014] The reset processor comprises:

[0015] The first D flip-flop has its D terminal connected to the high level VCC, the clock terminal as the clock signal input terminal, and the reset terminal as the reset signal terminal.

[0016] The second D flip-flop has a D terminal connected to the Q terminal of the first D flip-flop, a clock terminal connected to the clock terminal of the first D flip-flop, and a toggle terminal connected to the toggle terminal of the first D flip-flop.

[0017] The reset selector has a first input terminal connected to the Q terminal of the second D flip-flop, a second input terminal as a test reset terminal, an output terminal as an output terminal of the reset processor, and a control terminal as a control terminal of the reset processor.

[0018] The synchronizer comprises:

[0019] The front-stage D flip-flop has its D terminal as a synchronization signal input terminal, its clock terminal as a clock signal input terminal, and its reset terminal as a reset signal terminal;

[0020] The D terminal of the subsequent D flip-flop is connected to the Q terminal of the previous D flip-flop, the clock terminal is connected to the clock terminal of the previous D flip-flop, the reset terminal is connected to the reset terminal of the previous D flip-flop, and the Q terminal serves as the output terminal of the synchronizer.

[0021] The gated clock module comprises:

[0022] A first OR gate, one input terminal of which is used as an enable clock input terminal and the other input terminal of which is used as a control terminal;

[0023] A latch, whose input terminal is connected to the output terminal of the OR gate and whose enable terminal serves as the input clock terminal;

[0024] an inverter, whose input terminal is connected to the output terminal of the latch;

[0025] The second OR gate has one input terminal connected to the output terminal of the inverter, another input terminal connected to the enable terminal of the latch, and an output terminal thereof serving as the output terminal of the gated clock module.

[0026] The beneficial effects of the present invention are:

[0027] 1. Support rapid expansion of input clocks. You only need to modify the clock decoding circuit according to the number of input clocks, expand the corresponding input AND gates and OR gates, and keep other circuit structures unchanged to meet more clock switching requirements.

[0028] 2. Supporting glitch-free clock switching, the present invention switches at the falling edge of the clock. Due to the existence of negative feedback, it is ensured that only one clock is turned on at the same time.

[0029] 3. Supporting testability design. The present invention has a test mode function. In the test mode, all clock sources of the circuit switching circuit are synchronized to a unified test clock, thereby realizing controllable control of all registers inside the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a circuit schematic diagram of the present invention.

[0031] Figure 2 It is a structural diagram of the reset processing module.

[0032] Figure 3 This is the schematic diagram of the synchronizer.

[0033] Figure 4 This is the schematic diagram of the gated clock module. DETAILED DESCRIPTION

[0034] In the present invention, the connection end for internal connection is called "end", such as the control end of the resetter. The connection end for external connection is called "point", such as the test clock input point and the mode signal input point. In the present invention, the signal name of "point" is used as the mark of the point, such as Figure 1 In the example, the signal provided by the test clock input point TEST_Clock is TEST_Clock, and the signal provided by the mode signal input point testmode_en is testmode_en.

[0035] See also Figure 1 , the present invention includes a clock selection decoding circuit 101 and N parallel clock signal branches, N is an integer greater than 2;

[0036] Taking the branch where the selector 102 is located as an example, the clock signal branch includes:

[0037] A selector 102, whose first input terminal is connected to the test clock point TEST_Clock, and whose second input terminal is used as the clock signal input terminal of the branch, for example, the connection terminal marked as Clock_in1 in the selector 102; and whose control terminal is connected to the mode signal input point testmode_en;

[0038] A reset processor 105, whose control terminal is connected to the mode signal input point testmode_en, the test reset terminal is connected to the test reset signal input point TEST_Rst, the reset signal terminal is connected to the reset signal input point Rst, and the clock signal input terminal is connected to the output end of the selector of the branch;

[0039] a multi-input AND gate 108 having a clock input terminal and N-1 bypass input terminals, wherein the bypass input terminals are used to receive signals from other branches;

[0040] A synchronizer 111, whose synchronization signal input terminal is connected to the output terminal of the multi-input AND gate 108 of the branch, whose clock signal input terminal CK is connected to the output terminal of the selector of the branch, and whose reset signal terminal RST is connected to the output terminal of the reset processor 105 of the branch,

[0041] A branch D flip-flop 114, whose D terminal is connected to the output terminal of the synchronizer of the branch, whose clock terminal is connected to the output terminal of the selector of the branch, whose reset terminal CLR is connected to the output terminal of the reset processor, The end is used as the bypass control end of the branch; the bypass control end is used to output control signals to other branches other than the branch;

[0042] A gated clock module 117, whose enable clock input terminal Clk_en is connected to the Q terminal of the branch D flip-flop 114, whose input clock terminal Clk_in is connected to the output terminal of the selector of the branch, whose control terminal TE is connected to the mode signal input point testmode_en, and whose output terminal serves as the final output terminal of the branch;

[0043] The bypass control terminal of each clock signal branch is connected to a bypass input terminal of the multi-input AND gate in all other branches, and each bypass input terminal is connected to only one bypass control terminal. Figure 1 The multi-input AND gate 108 in the branch where the selector 102 is located (hereinafter referred to as branch 102, the same applies to other branches) has an input terminal that is only used to connect the bypass control terminal of branch 103 (i.e., the bypass control terminal of D flip-flop 115). In short, for each multi-input AND gate, each branch except the branch where it is located has a corresponding input terminal, which is called the bypass input terminal. At the same time, the bypass control terminal of each branch is also connected to the bypass input terminals of other branches. For example, the bypass control terminal of branch 102 is connected to a bypass input terminal of branch 103 and a bypass input terminal of branch 104. If there are more branches, the same applies.

[0044] The final output of each clock signal branch is connected to each input of the multi-input OR gate one by one, the output of the multi-input OR gate is connected to the first input of the output selector, and the second input of the output selector is connected to the test clock point. Referring to branch 102, the output of the gated clock module 117 is connected to an input of the multi-input OR gate 120 as the final output of branch 102, and the same is true for other branches. The final selector 121 is called an output selector, and its two inputs are connected to the multi-input OR gate 120 and the test clock point TEST_Clock respectively, and its control terminal is connected to the mode signal input point testmode_en.

[0045] See also Figure 2 , the reset processor includes:

[0046] The first D flip-flop has its D terminal connected to the high level VCC, the clock terminal as the clock signal input terminal, and the reset terminal CLR as the reset signal terminal.

[0047] The second D flip-flop has its D terminal connected to the Q terminal of the first D flip-flop, its clock terminal connected to the clock terminal of the first D flip-flop, and its reset terminal CLR connected to the reset terminal of the first D flip-flop.

[0048] The reset selector has a first input terminal connected to the Q terminal of the second D flip-flop, a second input terminal as a test reset terminal, an output terminal as an output terminal of the reset processor, and a control terminal as a control terminal of the reset processor.

[0049] See also Figure 3 , the synchronizer includes:

[0050] The front-stage D flip-flop has its D terminal as the synchronization signal input terminal Sync_in, its clock terminal as the clock signal input terminal, and its reset terminal as the reset signal terminal Rst;

[0051] The D terminal of the subsequent D flip-flop is connected to the Q terminal of the previous D flip-flop, the clock terminal is connected to the clock terminal of the previous D flip-flop, the reset terminal is connected to the reset terminal of the previous D flip-flop, and the Q terminal serves as the output terminal Sync_out of the synchronizer.

[0052] See also Figure 4 , the gated clock module comprises:

[0053] A first OR gate, one input terminal of which is used as an enable clock input terminal for inputting an enable clock Clk_en, and the other input terminal of which is used as a control terminal for inputting a control signal TE;

[0054] A latch, whose input terminal is connected to the output terminal of the OR gate and whose enable terminal serves as the input clock terminal;

[0055] an inverter, whose input terminal is connected to the output terminal of the latch;

[0056] The second OR gate has one input terminal connected to the output terminal of the inverter, and the other input terminal connected to the enable terminal of the latch. Its output terminal serves as the output terminal of the gated clock module and outputs the Clk_out signal.

[0057] The functions of each unit are described as follows:

[0058] The clock selection decoding circuit 101 completes the decoding of multiple clock selection signals and outputs a valid signal. 102, 103, and 104 are all two-to-one MUX circuits, which complete the switching of the clock path in the functional mode and the test mode.

[0059] 105, 106, and 107 are reset processors, whose main function is to complete asynchronous reset synchronous release in functional mode to ensure that their timing functions are correct and no timing violations occur. In test mode, the reset is directly controlled by the test reset to ensure the test controllability of the circuit.

[0060] 108, 109, and 110 are multi-input AND gates, whose inputs are the clock selection signal of the clock selection decoding circuit and the feedback signals of other clock selection channels, so as to ensure that only one clock is selected at the same time.

[0061] 111, 112, 113 are signal synchronization modules. Since the feedback signals of other clock selection channels and the clock selection signal of the clock selection decoding circuit and the following D flip-flop are asynchronous clocks, synchronization is required to avoid circuit timing violations.

[0062] 114, 115, and 116 are falling edge triggered D flip-flops, which are used to ensure that the switching signal is changed at the falling edge of the clock and that the clock is switched at a low level.

[0063] 117, 118, and 119 are clock gating units. A simple clock gating unit can be completed by an AND gate, but it cannot prevent the occurrence of glitches. In actual circuit design, a dedicated clock gating unit provided by a wafer foundry is often used.

[0064] 120 is a multi-input OR gate that allows the selected clock to pass through.

[0065] 121 is a two-to-one MUX, and its function is that in the test mode, the subsequent circuit is directly controlled by the test clock.

Claims

1. A glitch-free multi-clock switching circuit supporting design for testability, characterized in that: It includes a clock selection decoding circuit and N parallel clock signal branches, where N is an integer greater than 2; The clock signal branch comprises: A selector, whose first input terminal is connected to the test clock point, whose second input terminal is used as the clock signal input terminal of the branch where it is located, and whose control terminal is connected to the mode signal input point; A reset processor, wherein the control terminal is connected to the mode signal input point, the test reset terminal is connected to the test reset signal input point, the reset signal terminal is connected to the reset signal input point, and the clock signal input terminal is connected to the output end of the selector of the branch; A multi-input AND gate having a clock input and N-1 bypass inputs, A synchronizer, whose synchronization signal input terminal is connected to the output terminal of the multi-input AND gate of the branch, whose clock signal input terminal is connected to the output terminal of the selector of the branch, and whose reset signal terminal is connected to the output terminal of the reset processor of the branch. A branch D flip-flop, whose D terminal is connected to the output terminal of the synchronizer of the branch, whose clock terminal is connected to the output terminal of the selector of the branch, and whose reset terminal is connected to the output terminal of the reset processor. The end serves as the bypass control end of this branch; A gated clock module, whose enable clock input terminal is connected to the Q terminal of the branch D flip-flop, whose input clock terminal is connected to the output terminal of the selector of the branch, whose control terminal mode signal input point, and whose output terminal is used as the final output terminal of the branch; The bypass control terminal of each clock signal branch is connected to a bypass input terminal of the multi-input AND gate in all other branches, and each bypass input terminal is connected to only one bypass control terminal; The final output of each clock signal branch is connected one by one to each input of the multi-input OR gate, the output of the multi-input OR gate is connected to the first input of the output selector, and the second input of the output selector is connected to the test clock point.

2. The glitch-free multi-clock switching circuit supporting design for testability according to claim 1, characterized in that: The reset processor comprises: The first D flip-flop has its D terminal connected to the high level VCC, the clock terminal as the clock signal input terminal, and the reset terminal as the reset signal terminal. The second D flip-flop has a D terminal connected to the Q terminal of the first D flip-flop, a clock terminal connected to the clock terminal of the first D flip-flop, and a toggle terminal connected to the toggle terminal of the first D flip-flop. The reset selector has a first input terminal connected to the Q terminal of the second D flip-flop, a second input terminal as a test reset terminal, an output terminal as an output terminal of the reset processor, and a control terminal as a control terminal of the reset processor.

3. The glitch-free multi-clock switching circuit supporting design for testability according to claim 1, characterized in that: The synchronizer comprises: The front-stage D flip-flop has its D terminal as a synchronization signal input terminal, its clock terminal as a clock signal input terminal, and its reset terminal as a reset signal terminal; The D terminal of the subsequent D flip-flop is connected to the Q terminal of the previous D flip-flop, the clock terminal is connected to the clock terminal of the previous D flip-flop, the reset terminal is connected to the reset terminal of the previous D flip-flop, and the Q terminal serves as the output terminal of the synchronizer.

4. The glitch-free multi-clock switching circuit supporting design for testability according to claim 1, characterized in that: The gated clock module comprises: A first OR gate, one input terminal of which is used as an enable clock input terminal and the other input terminal of which is used as a control terminal; A latch, whose input terminal is connected to the output terminal of the OR gate and whose enable terminal serves as the input clock terminal; an inverter, whose input terminal is connected to the output terminal of the latch; The second OR gate has one input terminal connected to the output terminal of the inverter, another input terminal connected to the enable terminal of the latch, and an output terminal thereof serving as the output terminal of the gated clock module.

5. The glitch-free multi-clock switching circuit supporting DFT as claimed in claim 1, characterized in that: The branch D flip-flop is falling edge triggered.

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