Interlayer conductive structure of circuit board and manufacturing method thereof

Abstract

The present invention relates to an interlayer conductive structure for a circuit board and a method for manufacturing the same. The interlayer conductive structure is suitable for forming in a circuit board, wherein the circuit board includes two traces and an insulating portion located between the traces. The insulating portion has a through hole. The interlayer conductive structure is located in the through hole and connects the traces. The interlayer conductive structure includes a column and a pair of protrusions. The protrusions are located at both ends of the through hole and connect the column to the traces. The protrusions protrude from the outer surfaces of the traces. Each protrusion has a convex curved surface, wherein the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole. In this way, the structure of the portion connecting the interlayer conductive structure and the traces can be strengthened, reducing or preventing the formation of cracks.

Description

Technical Field

[0001] The present invention relates to a circuit board and a manufacturing process thereof, and in particular to an interlayer conductive structure of a circuit board and a manufacturing method thereof. Background Art

[0002] Conventional multilayer wiring boards (PCBs) typically feature through-holes, conductive through-hole structures, and multiple wiring layers. The conductive through-hole structure is formed within the through-hole, with each end of the conductive through-hole structure connecting two non-coplanar wiring layers to electrically connect them. The connection between the conductive through-hole structure and the wiring layer—that is, the portion of the conductive through-hole structure located near either end of the through-hole—is relatively fragile and can sometimes form cracks, reducing reliability and potentially causing defects such as disconnections between the conductive through-hole structure and the wiring layer. Summary of the Invention

[0003] At least one embodiment of the present invention provides an interlayer conductive structure of a circuit board to strengthen the structure of the portion connecting the conductive through-hole structure and the circuit layer.

[0004] At least one embodiment of the present invention further provides a method for manufacturing the interlayer conductive structure of the circuit board.

[0005] The interlayer conductive structure provided by at least one embodiment of the present invention is suitable for being formed in a circuit board, wherein the circuit board includes two traces and an insulating portion located between the traces. The insulating portion has a through hole, and the interlayer conductive structure is located in the through hole and connects the traces. The interlayer conductive structure includes a column and a pair of protrusions. The column is located in the through hole and has opposite end faces. The protrusions connect the end faces and the traces, respectively, and are located at both ends of the through hole, wherein each trace has an inner surface connected to the insulating portion and an outer surface away from the insulating portion, and the protrusions protrude from the outer surfaces of the traces. Each protrusion has a convex curved surface, wherein the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.

[0006] In at least one embodiment of the present invention, each trace further has a long axis, and the through hole has a hole wall. The wall thickness of each protrusion relative to the hole wall decreases gradually from the long axis along the hole wall toward a direction away from the long axis.

[0007] In at least one embodiment of the present invention, the convex surface has a curvature radius, wherein the curvature radius, the axis, and the long axis of the trace are coplanar, and the curvature radius is greater than or equal to 3 microns.

[0008] In at least one embodiment of the present invention, the column is cylindrical in shape, and the column also has a thinnest wall thickness.

[0009] In at least one embodiment of the present invention, the column includes a pair of end portions and a central section, wherein the end portions respectively have the end surfaces, and the central section is connected between the end portions, wherein the wall thickness of each end portion is greater than the wall thickness of the central section.

[0010] In at least one embodiment of the present invention, the wall thickness of each terminal portion decreases from the end surface toward the central section.

[0011] In at least one embodiment of the present invention, the column also has a thinnest wall thickness, and the thinnest wall thickness is located in the central section.

[0012] In at least one embodiment of the present invention, each protrusion further comprises a first curved surface and a second curved surface, wherein the first curved surface extends from the protruding curved surface to the outer surface, and the second curved surface extends from the protruding curved surface to the inner wall surface of the central section.

[0013] In at least one embodiment of the present invention, each protrusion further has a first curved surface, and the first curved surface extends from the protruding curved surface to the outer surface.

[0014] The manufacturing method of the interlayer conductive structure of the circuit board provided by at least one embodiment of the present invention includes the following steps. First, a circuit substrate is provided, wherein the circuit substrate includes two initial traces and an insulating portion located between these initial traces. Thereafter, a through hole is formed in the circuit substrate, wherein the through hole extends from one of the initial traces to the other initial trace. Two patterned cover layers are formed, wherein the circuit substrate is located between these patterned cover layers, and these patterned cover layers respectively cover the edges of the two ends of the through hole, but do not cover these initial traces. These patterned cover layers each have two openings, and these openings are connected to the through hole. Thereafter, the circuit substrate and the through hole are subjected to an electroplating process using these patterned cover layers as masks. After the electroplating process, these patterned cover layers are removed.

[0015] In at least one embodiment of the present invention, the manufacturing method further includes forming a seed layer on the circuit substrate and in the through hole before forming the patterned cover layers, wherein the seed layer fully covers the circuit substrate and the hole wall of the through hole.

[0016] In at least one embodiment of the present invention, the manufacturing method further includes removing a portion of the seed layer located on the circuit substrate after removing the patterned cover layers.

[0017] In at least one embodiment of the present invention, the method of removing a portion of the seed layer includes micro-etching.

[0018] In at least one embodiment of the present invention, these patterned mask layers are dry films after exposure and development.

[0019] In at least one embodiment of the present invention, a method of forming the through hole includes laser drilling or mechanical drilling.

[0020] Based on the above, since the protrusions located at both ends of the through hole will protrude from the outer surface of the trace, and the distance between the protruding curved surface of each protrusion and the axis of the through hole is less than the radius of the through hole, the interlayer conductive structure has a relatively thick thickness at the protrusion to strengthen the structure of the part connecting the interlayer conductive structure and the trace, thereby reducing or avoiding the formation of cracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 9 The figure is a schematic diagram of a method for manufacturing an interlayer conductive structure of a circuit board according to at least one embodiment of the present invention.

[0022] Figure 10A yes Figure 9 A cross-sectional perspective diagram of a circuit board in FIG.

[0023] Figure 10B yes Figure 9 Schematic diagram of a top view of the circuit board in FIG.

[0024] Figure 10C yes Figure 10A A cross-sectional perspective diagram of a circuit board in FIG.

[0025] Figure 10D yes Figure 10B Schematic diagram of the cross section of the circuit board in .

[0026]

Main component symbol description

[0027] 10: Circuit board 11: Initial routing

[0028] 12: Insulation portion 12a: Upper surface

[0029] 12b: lower surface 13: through hole

[0030] 13a: Axis 13e: Edges at both ends of through hole 13

[0031] 13s: hole wall 15: seed layer

[0032] 15t: thickness 18: metal layer

[0033] 60: Patterned cover layer 61: Opening

[0034] 100: Interlayer conductive structure 110: Pillar

[0035] 111: End surface 113: Through hole

[0036] 115: Central section 115s: Inner wall surface

[0037] 119: terminal portion 120: protruding portion

[0038] 121: First curved surface 122: Second curved surface

[0039] 129: convex surface 129r: curvature radius

[0040] 900: Circuit board 910: Routing

[0041] 910a: long axis 911: outer surface

[0042] 912: Inner surface D9: Distance between the convex curved surface 129 and the axis 13a of the through hole 13

[0043] R13: Aperture of through hole 13 R60: Aperture of opening 61

[0044] r13: radius of through hole 13 T15, T19, T20: wall thickness DETAILED DESCRIPTION

[0045] In the following text, in order to clearly present the technical features of the present invention, the dimensions (such as length, width, thickness and depth) of the elements (such as layers, films, substrates and regions, etc.) in the drawings will be magnified in a non-proportional manner. Therefore, the description and explanation of the embodiments below are not limited to the dimensions and shapes presented by the elements in the drawings, but should cover the dimensions, shapes and deviations thereof caused by the actual process and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, and the sharp angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the patent application of the present invention.

[0046] Secondly, the words "about," "approximately," or "substantially" that appear in the present case not only cover the numerical values ​​and numerical ranges that are clearly stated, but also cover the permissible deviation range that can be understood by a person of ordinary skill in the technical field to which the invention belongs, wherein this deviation range can be determined by the error generated during measurement, and this error is caused, for example, by the limitations of the measurement system or process conditions. In addition, "about" can mean within one or more standard deviations of the above-mentioned numerical value, such as ±30%, ±20%, ±10%, or ±5%. The words "about," "approximately," or "substantially" that appear in this text can select an acceptable deviation range or standard deviation based on the optical properties, etching properties, mechanical properties, or other properties, and do not apply a single standard deviation to all properties such as the above-mentioned optical properties, etching properties, mechanical properties, and other properties.

[0047] Figures 1 to 9 Schematic diagram of a method for manufacturing an interlayer conductive structure of a circuit board according to at least one embodiment of the present invention. Figure 1 and Figure 2 In the manufacturing method of this embodiment, first, a circuit substrate 10 is provided, wherein Figure 1 is a schematic top view of the circuit substrate 10, and Figure 2 yes Figure 1 The circuit substrate 10 is substantially a circuit board and has at least two circuit layers.

[0048] In this embodiment, the circuit substrate 10 can be a double-sided wiring board and has two wiring layers, wherein each wiring layer includes at least one trace. Figure 2 For example, the circuit substrate 10 includes two non-coplanar circuit layers, each of which includes an initial trace 11 , wherein the insulating portion 12 is located between the two circuit layers. That is, the insulating portion 12 is located between the two initial traces 11 .

[0049] In other embodiments, circuit substrate 10 may be a multilayer wiring board having more than two wiring layers, at least one of which may be located within insulating portion 12. Specifically, insulating portion 12 may include multiple stacked insulating layers (not shown), with at least one wiring layer sandwiched between two adjacent insulating layers. The insulating layer may be made of resin or ceramic. For example, the insulating layer may be formed from a resin sheet (prepreg).

[0050] It is worth noting that when the circuit substrate 10 has more than two circuit layers, the circuit substrate may further include at least one conductive blind via structure (not shown). The conductive blind via structure is disposed within the insulating portion 12 and connects two adjacent circuit layers, thereby electrically connecting the two adjacent circuit layers through the conductive blind via structure. Furthermore, each circuit layer may further include at least one pad (not shown). The pad can be used to mount electronic components, and at least one initial trace 11 can be connected to at least one pad.

[0051] Since circuit substrate 10 can have more than two circuit layers, the number of circuit layers included in circuit substrate 10 can be three or more, and is not limited to two. Furthermore, in other embodiments, each circuit layer can include multiple traces. Therefore, even if circuit substrate 10 is essentially a double-sided circuit board with two circuit layers, circuit substrate 10 can include two or more initial traces 11, wherein at least two initial traces 11 can be disposed on either upper surface 12a or lower surface 12b of insulating portion 12.

[0052] See also Figure 3 and Figure 4 ,in Figure 3 is a schematic top view of the circuit substrate 10, and Figure 4 yes Figure 3 Next, at least one through hole 13 is formed in the circuit substrate 10, wherein the through hole 13 can be formed by laser drilling or mechanical drilling. Figure 3 and Figure 4 Only one through hole 13 is shown in each embodiment, but in other embodiments, multiple through holes 13 may be formed. Figure 3 and Figure 4 The number of through holes 13 is not limited.

[0053] Through-hole 13 is formed through circuit substrate 10, extending from one initial trace 11 (e.g., initial trace 11 located on upper surface 12a) to another initial trace 11 (e.g., initial trace 11 located on lower surface 12b) and formed within insulating portion 12. Thus, insulating portion 12 has at least one through-hole 13 exposed on both upper surface 12a and lower surface 12b. Furthermore, during the formation of through-hole 13, not only is a portion of insulating portion 12 removed, but portions of initial trace 11 may also be removed.

[0054] See also Figure 5 , which is based on Figure 4 A cross-sectional schematic diagram is drawn. After the through hole 13 is formed, a seed layer 15 is formed on the circuit substrate 10 and in the through hole 13, wherein the seed layer 15 fully covers the circuit substrate 10 and the through hole 13. Specifically, the through hole 13 has a hole wall 13s, and the seed layer 15 fully covers these initial traces 11, the upper surface 12a and the lower surface 12b of the insulating portion 12, and the hole wall 13s. The seed layer 15 can be formed by electroless plating (electroless plating) or physical vapor deposition (PVD), wherein physical vapor deposition is, for example, sputtering or evaporation. In addition, the seed layer 15 has a relatively thin thickness 15t, which is, for example, between 0.2 microns and 1.2 microns.

[0055] See also Figure 6 and Figure 7 Then, two patterned cover layers 60 are formed. These patterned cover layers 60 cover the two opposite sides of the circuit substrate 10 respectively. Figure 6 A schematic top view of the circuit substrate 10 covered by the patterned cover layers 60 is shown. Figure 7 Draw Figure 6 The circuit substrate 10 is located between these patterned cover layers 60 , and these patterned cover layers 60 may not cover the initial traces 11 .

[0056] Each of these patterned cover layers 60 has two openings 61, that is, each patterned cover layer 60 has one opening 61, wherein these openings 61 are aligned with the through hole 13 so that these openings 61 can communicate with the through hole 13. In this embodiment, the aperture R60 of the opening 61 is smaller than the aperture R13 of the through hole 13, so that these patterned cover layers 60 can respectively cover the edges 13e at both ends of the through hole 13 (please refer to Figure 3 Since the patterned cover layer 60 may not cover the initial trace 11, the edge 13e of the initial trace 11 is not covered by the patterned cover layer 60. Figure 6 In addition, these patterned cover layers 60 can all be dry films after exposure and development.

[0057] It should be noted that, since multiple through-holes 13 can be formed in other embodiments, not only can the insulating portion 12 have multiple through-holes 13, but each patterned cover layer 60 can also have multiple openings 61 aligned with these through-holes 13. In other words, each patterned cover layer 60 has at least one opening 61. Therefore, the number of openings 61 in each patterned cover layer 60 is not limited to just one.

[0058] See also Figure 8 , then, using these patterned cover layers 60 as masks, the circuit substrate 10 and the through-holes 13 are subjected to an electroplating process. Specifically, before forming these patterned cover layers 60, the seed layer 15 has completely covered the circuit substrate 10 and the hole walls 13s. Therefore, a current can be applied to the seed layer 15 to perform an electroplating process to deposit metal in the areas not covered by the patterned cover layers 60, thereby forming an interlayer conductive structure 100 in the through-holes 13 and forming a metal layer 18 on each initial trace 11. Figure 8 From a perspective, the interlayer conductive structure 100 includes a portion of the seed layer 15 located within the through hole 13 , and the initial traces 11 are located between the metal layers 18 .

[0059] The above electroplating process includes a through hole plating (PTH) process, and the plating solution used in the electroplating process may include a low concentration of leveler, or may not contain a leveler. The leveler contains a plurality of positive ions and tends to adhere to areas with high negative charge density, thereby hindering metal deposition. Therefore, the above electroplating process using a low concentration of leveler or without a leveler can cause more metal to be deposited on the edges 13e at both ends of the through hole 13 (marked at Figure 7 ) place.

[0060] See also Figure 8 and Figure 9 After the electroplating process is performed, that is, after the interlayer conductive structure 100 is formed, the patterned cover layers 60 are removed. After removing the patterned cover layers 60, the portion of the seed layer 15 on the circuit substrate 10 is removed, and the remaining seed layer 15 covered by the metal layer 18 and the interlayer conductive structure 100 is retained, wherein the retained seed layer 15 is located on the hole wall 13s and the circuit layer (such as the initial trace 11). At this point, a method including an insulating portion 12, an interlayer conductive structure 100 and a plurality of traces 910 ( Figure 9 The circuit board 900 (shown as two lines) is basically completed, wherein each trace 910 includes an initial trace 11 , a metal layer 18 and a portion of a seed layer 15 , and the portion of the seed layer 15 is located between the initial trace 11 and the metal layer 18 .

[0061] The method of removing part of the seed layer 15 may include micro-etching. Micro-etching is usually wet etching, so in the process of micro-etching, not only part of the seed layer 15 is removed, but also part of the interlayer conductive structure 100 is removed. However, the thickness 15t of the seed layer 15 is quite thin (for example, between 0.2 microns and 1.2 microns), and the etching amount of the micro-etching is, for example, between about 0.2 microns and 0.6 microns. Therefore, after micro-etching, the thickness and appearance of both the interlayer conductive structure 100 and the metal layer 18 will not change significantly. In other words, the thickness and appearance of both the interlayer conductive structure 100 and the metal layer 18 are basically not affected by micro-etching.

[0062] Figure 10A yes Figure 9 A schematic cross-sectional view of a circuit board in FIG. Figure 10A The cross-section of the via 113 and the trace 910 is shown. Figure 10A The internal structure of the via 113 and the initial trace 11, the seed layer 15 and the metal layer 18 of the trace 910 can be presented. Figure 10A The trace 910 in FIG. 1 may be drawn along a cross section parallel to the extending direction of the trace 910 .

[0063] See also Figure 9and Figure 10A In the circuit board 900, the insulating portion 12 is located between the traces 910, and the interlayer conductive structure 100 formed in the circuit board 900 connects the traces 910 and includes a column 110 and a pair of protrusions 120. Figure 9 The column 110, the protrusion 120 and the trace 910 are clearly shown. Figure 9 The dashed lines represent the boundaries between the pillar 110, the protrusion 120 and the trace 910. Figure 9 The dashed lines shown are virtual auxiliary lines, and the boundaries among the pillar 110 , the protrusion 120 and the trace 910 are not clearly visible in actual situations.

[0064] The pillar 110 is located in the through hole 13 and has two opposite end surfaces 111. The protrusions 120 are respectively located at the two ends of the through hole 13 and respectively connect the end surfaces 111 and the traces 910. Therefore, the pillar 110 is located between the protrusions 120, and at either end of the through hole 13, the protrusion 120 protrudes from the end surface 111. In addition, since the interlayer conductive structure 100 includes a portion of the seed layer 15 located in the through hole 13, each of the pillar 110 and the protrusion 120 also includes a portion of the seed layer 15, as shown in FIG. Figure 9 shown.

[0065] In this embodiment, the interlayer conductive structure 100 can be hollow. Specifically, the pillar 110 can be cylindrical and have a conductive hole 113, wherein the conductive hole 113 and the through hole 13 can be substantially coaxial. The pillar 110 includes a pair of end portions 119 and a central section 115, wherein the central section 115 is connected between the end portions 119. The end portions 119 each have end surfaces 111, so that the end portions 119 are respectively connected to the protrusions 120.

[0066] It should be noted that while the interlayer conductive structure 100 may be hollow in this embodiment, in other embodiments, the interlayer conductive structure 100 may also be solid. Specifically, the pillars 110 in other embodiments may be solid metal pillars and lack the vias 113. Therefore, the interlayer conductive structure 100 is not limited to being hollow. Furthermore, in other embodiments, the interlayer conductive structure 100 may further include a filling material, such as ink, silver glue, or copper paste, to fill the vias 113.

[0067] The wall thickness T19 of each end portion 119 may be greater than the wall thickness T15 of the central section 115, wherein Figure 9 The wall thickness T15 shown may be the thinnest wall thickness of the column 110. In other words, the thinnest wall thickness (i.e. Figure 9The wall thickness T15 shown is located in the central section 115. In addition, the wall thickness T19 of each end portion 119 can decrease from the end surface 111 toward the central section 115, as shown in FIG. Figure 9 Therefore, the via hole 113 has a non-uniform aperture.

[0068] Each protrusion 120 has a protruding curved surface 129. During the electroplating process to form the interlayer conductive structure 100, a plating solution containing a low-concentration leveler or no leveler can be used to allow more metal to be deposited on both ends of the through hole 13. In this way, the protrusions 120 are formed, and the distance D9 between the protruding curved surface 129 and the axis 13a of the through hole 13 can be significantly smaller than the radius r13 of the through hole 13, where the radius r13 is equal to half the aperture R13 (see Figure 7 ).

[0069] Each trace 910 has an outer surface 911 and an inner surface 912. The inner surface 912 is connected to the insulating portion 12, while the outer surface 911 is away from the insulating portion 12. The protrusions 120 protrude from the outer surface 911 of the traces 910. Each protrusion 120 may further have a first curved surface 121 and a second curved surface 122. The first curved surface 121 extends from the protruding curved surface 129 to the outer surface 911, and the second curved surface 122 extends from the protruding curved surface 129 to the inner wall surface 115s of the central section 115, as shown in FIG. Figure 9 shown.

[0070] Figure 10B yes Figure 9 The top view of the circuit board in Figure 10C yes Figure 10A A schematic cross-sectional view of a circuit board in FIG. Figure 10C It is drawn along the cross section of the end surface 111 and the wall of the seed layer 15, and the part of the protrusion 120 located just above the end surface 111 is removed. Figure 10C In the embodiment, most of the protrusions 120 are omitted, and Figure 10C The remaining protrusions 120 are not shown.

[0071] See also Figure 10B and Figure 10C , each trace 910 further has a long axis 910a, wherein Figure 9 It can be along Figure 10B The cross-sectional view is drawn based on the long axis 910a in FIG. 1 , and the long axis 910a can actually pass through the axis 13a. Figure 10A The trace 910 shown may be drawn along a cross section parallel to the long axis 910 a to show the initial trace 11 , the seed layer 15 and the metal layer 18 of the trace 910 .

[0072] from Figure 10BIt can be seen that the wall thickness T20 of each protrusion 120 relative to the hole wall 13s can be gradually reduced from the long axis 910a along the hole wall 13s toward the direction away from the long axis 910a, as shown in FIG. Figure 10B shown.

[0073] Figure 10D yes Figure 10B A cross-sectional diagram of a circuit board in FIG. Figure 10D It is along Figure 10B Refer to Figure 10D In the interlayer conductive structure 100, the convex surface 129 has a curvature radius 129r, which can be greater than or equal to 3 microns. Therefore, the protrusion 120 of the interlayer conductive structure 100 has a sufficient thickness to ensure that the portion connected between the interlayer conductive structure 100 and the trace 910 has a certain structural strength, thereby effectively reducing or avoiding the formation of cracks. In addition, Figure 10D It is obvious from the cross-sectional view that the radius of curvature 129r, the axis 13a and the major axis 910a are coplanar.

[0074] It is worth mentioning that the interlayer conductive structure 100 disclosed in the above embodiment can be a conductive through-hole structure. However, in other embodiments, the interlayer conductive structure 100 can also be a conductive buried hole structure. Specifically, the circuit board 900 can be a semi-finished product of the circuit board, and in the subsequent process, multiple circuit layers can be additionally made on opposite sides of the circuit board 900, wherein these circuit layers can be formed by a build-up method. In the process of making these circuit layers, the two ends of the interlayer conductive structure 100 can be respectively covered with two insulating layers, wherein the insulating layer can be formed by a resin sheet. In this way, the interlayer conductive structure 100 can be buried in the circuit board, thereby forming a conductive buried hole structure.

[0075] In summary, at least one embodiment of the present invention provides an interlayer conductive structure comprising a pair of protrusions located at either end of a through-hole. Because the protrusions protrude beyond the outer surface of the trace, and the distance between the curved surface of each protrusion and the axis of the through-hole is less than the radius of the through-hole, the interlayer conductive structure is substantially thicker at the protrusions. This strengthens the structure of the portion connecting the interlayer conductive structure to the trace, reducing or preventing crack formation and thereby maintaining or improving reliability.

[0076] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. An interlayer conductive structure of a circuit board, characterized in that: Suitable for forming in a circuit board, wherein the circuit board includes two traces and an insulating portion located between the traces, the insulating portion has a through hole, and the interlayer conductive structure is located in the through hole and connects the traces, the interlayer conductive structure includes: a column located in the through hole and having opposite end surfaces; and A pair of protrusions are respectively connected to the end surface and the traces, and are respectively located at both ends of the through hole, wherein each trace has an inner surface connected to the insulating portion and an outer surface away from the insulating portion, and the protrusions respectively protrude from the outer surface of the traces, each of the protrusions has a convex curved surface, and the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole, and the convex curved surface has a curvature radius, and the curvature radius is greater than or equal to 3 microns.

2. The interlayer conductive structure of the circuit board according to claim 1, characterized in that: Each of the traces further has a long axis, and the through hole has a hole wall. The wall thickness of each of the protrusions relative to the hole wall decreases gradually from the long axis along the hole wall toward a direction away from the long axis.

3. The interlayer conductive structure of the circuit board according to claim 1, characterized in that: The radius of curvature, the axis center, and the long axis of the trace are coplanar.

4. The interlayer conductive structure of the circuit board according to claim 3, characterized in that: The column is cylindrical in shape and has a minimal wall thickness.

5. The interlayer conductive structure of the circuit board according to claim 1, characterized in that: The column includes: a pair of terminal portions, each having the end surface; and The central section is connected between the terminal portions, wherein the wall thickness of each of the terminal portions is greater than the wall thickness of the central section.

6. The interlayer conductive structure of the circuit board according to claim 5, characterized in that: The wall thickness of each of the terminal portions decreases gradually from the end surface toward the central section.

7. The interlayer conductive structure of the circuit board according to claim 5, characterized in that: The cylinder also has a thinnest wall thickness, and the thinnest wall thickness is located in the central section.

8. The interlayer conductive structure of the circuit board according to claim 5, characterized in that: Each of the protrusions further comprises: a first curved surface extending from the convex curved surface to the outer surface; and The second curved surface extends from the convex curved surface to the inner wall surface of the central section.

9. The interlayer conductive structure of the circuit board according to claim 1, characterized in that: Each of the protruding portions further has a first curved surface, and the first curved surface extends from the protruding curved surface to the outer surface.

10. A method for manufacturing an interlayer conductive structure of a circuit board, characterized in that: include: Providing a circuit substrate, wherein the circuit substrate includes two initial traces and an insulating portion located between the initial traces; forming a through hole in the circuit substrate, wherein the through hole extends from one of the initial traces to another of the initial traces; forming two patterned cover layers, wherein the circuit substrate is located between the patterned cover layers, and the patterned cover layers respectively cover edges at both ends of the through hole but do not cover the initial trace, and the patterned cover layers each have two openings, and the openings are connected to the through hole; Using the patterned cover layer as a mask, performing an electroplating process on the circuit substrate and the through hole; as well as After the electroplating process is performed, the patterned cover layer is removed.

11. The method for manufacturing an interlayer conductive structure of a circuit board according to claim 10, wherein: Also includes: Before forming the patterned cover layer, a seed layer is formed on the circuit substrate and in the through hole, wherein the seed layer fully covers the circuit substrate and the hole wall of the through hole.

12. The method for manufacturing an interlayer conductive structure of a circuit board according to claim 11, wherein: Also includes: After removing the patterned cover layer, a portion of the seed layer located on the circuit substrate is removed.

13. The method for manufacturing an interlayer conductive structure of a circuit board according to claim 12, wherein: Methods for removing a portion of the seed layer include micro-etching.

14. The method for manufacturing an interlayer conductive structure of a circuit board according to claim 10, wherein: The patterned cover layers are all dry films after exposure and development.

15. The method for manufacturing an interlayer conductive structure of a circuit board according to claim 10, wherein: Methods for forming the through hole include laser drilling or mechanical drilling.

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