Analog Signal Monitoring System and Method for Electromagnetic Compatibility Testing of Integrated Circuits

Abstract

The present invention relates to the field of monitoring of electromagnetic immunity test signals for integrated circuits, and particularly relates to an analog signal monitoring system and method for electromagnetic compatibility testing of integrated circuits. The present invention obtains a reference analog signal and a reference digital signal through a reference signal generation unit; samples the analog signal under test for electromagnetic compatibility testing of an integrated circuit chip through an analog signal acquisition unit and converts it into a digital signal under test; calibrates the reference digital signal through a calibration unit and calibrates the reference digital signal according to the sampled value when the analog signal under test is in a normal state; compares the signal under test and the reference signal through two-level comparison units, namely an analog signal comparison unit and a digital signal comparison unit, to judge abnormalities; and performs real-time monitoring and analysis on the digital signal under test through a digital signal analysis unit to automatically determine the immunity ability level of the integrated circuit chip.

Description

Technical Field

[0001] The present invention relates to the technical fields of electronic devices and electromagnetic compatibility cross technologies, and provides a monitoring device and method for analog signals during the immunity test of integrated circuit analog signals, specifically relating to an analog signal monitoring system and method for integrated circuit electromagnetic compatibility testing. Background Art

[0002] The invention "A Monitoring and Assisting Device and Method for Integrated Circuit Electromagnetic Compatibility Testing" with the application number 202210626148.0 provides a method of adaptive learning and monitoring, mainly including sampling the first feedback signal in the working state without electromagnetic interference of the IC under test and performing data analysis. The device compares the data analysis results with the preset IC types in the device to identify the type of the IC under test. The device adaptively learns the first feedback signal according to the preset method corresponding to the type of the IC under test and obtains the learning result data. The device determines the preset test items of the IC under test according to the learning result data, then samples the second feedback signal during the electromagnetic compatibility test of the IC under test, and performs real-time comparative analysis on the test feedback signal in the second stage with the preset test items and preset test standards to judge whether the working state of the IC under test is normal. If the judgment is no, an alarm prompt is issued.

[0003] With the continuous development of integrated circuit technology, the electromagnetic immunity tests of power chips and analog chips are increasing. However, there is currently no dedicated monitoring device, resulting in many blind spots in the monitoring during the electromagnetic sensitivity test.

[0004] It is mainly manifested in the following 4 points:

[0005] 1. In the existing invention, the system is complex, has many functions, and the device cost is high;

[0006] 2. In the existing invention, the monitoring of the signal under test is completed in the FPGA or single-chip microcomputer, and the intermediate AD conversion and other links prolong the abnormal discovery time, and the rapid capture of abnormalities cannot be achieved;

[0007] 3. In the monitoring of AC signals, the instantaneous value comparison method is directly used, which is prone to misjudgment, resulting in low reliability and stability of the device;

[0008] 4. Regarding the requirement of grading for the integrated circuit immunity test requirements, the existing invention does not involve the relevant methods for realizing this function. Summary of the Invention

[0009] The purpose of the present invention is to overcome the problems in the prior art that abnormalities cannot be quickly captured, the reliability and stability of the device are not high, and the grading requirements for the integrated circuit immunity test cannot be carried out, and a monitoring system and method for analog signals for integrated circuit electromagnetic compatibility testing are proposed.

[0010] To achieve the above object, the present invention is implemented through the following technical solutions.

[0011] The present invention provides an analog signal monitoring system for electromagnetic compatibility testing of integrated circuits, characterized in that the system includes: a reference signal generation unit, an analog signal sampling unit, a calibration unit, an analog signal comparison unit, a digital signal analysis unit, and a digital signal comparison unit;

[0012] The reference signal generation unit is used to generate a reference analog signal; it is also used to convert the reference analog signal into a reference digital signal;

[0013] The analog signal acquisition unit is used to sample the measured analog signal for electromagnetic compatibility testing of the integrated circuit chip and transmit it to the analog signal comparison unit. At the same time, the measured analog signal is converted into a measured digital signal and transmitted to the digital signal comparison unit;

[0014] The calibration unit is used to perform self-calibration on the generated reference digital signal and calibrate the reference digital signal according to the normal state value of the measured analog signal collected;

[0015] The analog signal comparison unit is used to compare the measured analog signal and the reference analog signal, and then judge the abnormality of the integrated circuit chip;

[0016] The digital signal comparison unit is used to compare the measured digital signal and the reference digital signal, and then analyze the abnormality;

[0017] The digital signal analysis unit is used to perform real-time monitoring and analysis on the measured digital signal, and then determine the immunity ability level of the integrated circuit chip.

[0018] As an improvement of the above technical solution, the system further includes: a signal parameter setting unit and a pulse width modulation unit; the signal parameter setting unit is used to set the relevant parameters of the reference signal according to the requirements of the integrated circuit chip;

[0019] The pulse width modulation unit is used to generate a PWM wave according to the set relevant parameters of the reference signal;

[0020] The reference signal generation unit includes a D / A conversion circuit and an A / D conversion circuit;

[0021] The D / A conversion circuit is used to convert the PWM wave generated by the pulse width modulation unit into a reference analog signal;

[0022] The A / D conversion circuit is used to convert the reference analog signal converted by the D / A conversion circuit into a reference digital signal.

[0023] As one of the improvements to the above technical solution, the analog signal sampling unit includes: an interface circuit, a protection circuit, a limit protection circuit, an isolation operational amplifier, a conditioning circuit, and an AD converter;

[0024] The protection circuit includes: an electrostatic, surge protection, and filtering circuit for protecting the circuit;

[0025] The limit protection circuit is used to prevent the circuit from being damaged due to excessive input of analog signals;

[0026] The isolation operational amplifier circuit is used to isolate the interface circuit and the internal circuit;

[0027] The conditioning circuit is used to condition the voltage of the analog signal within the range allowed by the AD converter;

[0028] The AD converter is used to convert the analog signal into a digital signal.

[0029] As one of the improvements to the above technical solution, the analog signal comparison unit includes a subtractor circuit and a DA converter;

[0030] The digital signal comparison unit includes a comparator circuit;

[0031] The non-inverting input terminal of the subtractor is connected to the reference analog signal, and the inverting input terminal is connected to the measured analog signal, which is used to compare the measured analog signal with the reference analog signal in real time and transmit it to the DA converter to obtain a tolerance signal;

[0032] The comparator is used to compare the tolerance signal with the set tolerance value in the reference digital signal and transmit the comparison result to the alarm circuit;

[0033] The non-inverting input terminal and the inverting input terminal of the subtractor are respectively connected with a first digital potentiometer and a second digital potentiometer; the first digital potentiometer and the second digital potentiometer are used to amplify and reduce the tolerance value.

[0034] As one of the improvements to the above technical solution, the calibration unit, the digital signal analysis unit, the digital signal comparison unit, and the pulse width modulation unit are all implemented based on the FPGA circuit;

[0035] The signal parameter setting unit is implemented based on the CAN bus circuit.

[0036] As one of the improvements to the above technical solution, the system further includes: a storage circuit, a fast alarm circuit, a hierarchical display circuit, and a power supply circuit;

[0037] The storage circuit is used to store the state and record events when the integrated circuit chip has an abnormality;

[0038] The quick alarm circuit is used to give an alarm when an abnormality occurs in the integrated circuit chip;

[0039] The grading display circuit is used to output the immunity ability level of the judged integrated circuit chip.

[0040] The power supply circuit is used to supply power to the whole system;

[0041] An electrostatic and surge protection circuit and a filtering circuit are arranged at the power interface of the power supply circuit; the power supply module of the power supply circuit adopts an isolated power supply module; the isolated power supply module is used for power voltage conversion and electrical isolation;

[0042] When the circuits of the system are arranged on the PCB board, the power supplies of the digital circuit part and the analog circuit part are isolated by magnetic beads; the power supply circuit supplies power to the analog circuit and the digital circuit in sequence.

[0043] The present invention also proposes an analog signal monitoring method for integrated circuit electromagnetic compatibility testing, which is realized based on the system described in any one of the above, and the method includes the following steps:

[0044] S1. Generate a PWM wave according to the set relevant parameters through the pulse width modulation unit and transmit it to the D / A conversion circuit;

[0045] S2. Convert the PWM wave output by the pulse width modulation unit into a reference analog signal through the D / A conversion circuit and transmit it to the analog signal comparison circuit and the calibrated AD converter;

[0046] S3. Convert the reference analog signal output by the D / A conversion circuit into a reference digital signal through the calibrated AD converter and feedback it to the calibration unit, and perform self-calibration on the reference digital signal through the calibration unit until the frequency, phase and amplitude of the reference digital signal are consistent with the expected set values;

[0047] S4. Sample the measured analog signal in the normal state of the integrated circuit chip through the analog signal acquisition unit and transmit it to the analog signal comparison unit; at the same time, process the measured analog signal in the normal state through the analog signal acquisition unit to obtain an analog digital signal and transmit it to the calibration unit;

[0048] S5. Compare the analog digital signal obtained by processing the sampled value of the measured analog signal in the normal state and the reference digital signal after the reference analog signal generated by the reference signal generation unit is converted by the AD converter in the calibration unit, and calibrate the reference digital signal until the phase is consistent with the signal in the normal state, and then start the test;

[0049] S6. Compare the measured analog signal and the reference analog signal through the analog signal comparison unit, and then judge for anomalies. If there are anomalies, alarm through the fast alarm circuit;

[0050] S7. Convert the measured analog signal into a measured digital signal and then transmit it to the digital signal analysis unit; monitor and analyze the measured digital signal in real time through the digital signal analysis unit, and then determine the immunity ability level of the integrated circuit chip;

[0051] S8. Compare the measured digital signal and the reference digital signal through the digital signal comparison unit, and then analyze the anomalies and output the anomaly analysis results.

[0052] As one of the improvements of the above technical solution, in S5, the calibration unit calibrates the reference signal, specifically including:

[0053] S5-1. Sample the reference analog signal and the test analog signal, and perform normalization processing respectively;

[0054] S5-2. Judge the phase difference between the normalized reference analog signal and the measured analog signal, and judge whether the phase difference is greater than 180°;

[0055] S5-3. If it is greater than 180°, adjust the phase of the reference analog signal by 180°, and return to S5-2; if it is not greater than 180°, continue to judge whether the phase difference is greater than 90°;

[0056] S5-4. If it is greater than 90°, adjust the phase of the reference analog signal by 90°, and return to S5-2; if it is not greater than 90°, enter S5-5;

[0057] S5-5. Perform PI adjustment on the reference analog signal and the measured analog signal;

[0058] S5-6. Judge whether the phase difference between the adjusted reference analog signal and the measured analog signal is less than the set value. If it is not less than the set value, return to S5-5; if it is less than the set value, adjust the amplitudes of the adjusted reference analog signal and the measured analog signal so that the amplitude difference between the reference analog signal and the measured analog signal is less than the set value.

[0059] As one of the improvements of the above technical solution, in S7, the digital signal analysis unit determines the immunity ability level of the integrated circuit chip, including the following steps:

[0060] S7-1. Judge whether a test stop signal is received; if not, continue to judge; if received, enter S7-2;

[0061] S7-2. Determine whether there is any abnormality in the signal under test during the test; if there is no abnormality, output the immunity ability level as Class A; if there is an abnormality, proceed to S7-3;

[0062] S7-3. Determine whether the current signal under test is normal. If it is normal, output the immunity ability level as Class C; if it is not normal, proceed to S7-4;

[0063] S7-4. Cut off the power supply of the integrated circuit chip. After a period of time according to the parameter settings, restart the integrated circuit chip; re-determine whether the current signal under test is normal. If it is normal, output the immunity ability level as Class D; if it is not normal, output the immunity ability level as Class E.

[0064] As an improvement of the above technical solution, before the monitoring, the method generates a query table of sine PWM waves through software and stores them in the Flash memory in the order of addresses successively, storing n numbers, where n is an odd number and n≥10N; during the monitoring, according to the test accuracy requirements, calculate the number of read points N of the FPGA from the memory within one cycle; if the calculated N is an odd number, take N as N; if N is an even number, take N as N+1; the frequency f2 of the wave read by the FPGA from the memory is f2 = N*f1, where f1 is the frequency of the test signal.

[0065] The advantages of the present invention compared with the prior art are as follows:

[0066] 1. During the immunity test, the device of the present invention monitors the instantaneous value of the monitored analog signal of the power supply chip and the analog chip in real time, including analog and digital two-stage comparison circuits. The analog comparison circuit is on the outer layer to realize the fast capture technology of faults and give a quick alarm; the digital comparison circuit is on the inner layer to analyze and store the characteristics of the monitored signal in detail.

[0067] 2. The device of the present invention should have strong electromagnetic anti-interference ability and is not affected by external electromagnetic interference during the immunity test process.

[0068] 3. The device of the present invention can quickly track the AC signal and has a phase self-calibration function, so as to quickly and accurately monitor the AC signal.

[0069] 4. The device of the present invention sets the preset value online through the CAN bus, which increases the flexibility of the device monitoring. At the same time, it can realize the function of the upper computer without developing the upper computer, reducing the cost.

[0070] 5. The device of the present invention analyzes the monitored signal during the test process and automatically outputs the immunity ability level according to the abnormal situation and standard regulations. Description of the Drawings

[0071] Figure 1(a) is the main framework diagram of the system of the present invention, and Figure 1(b) is the overall block diagram of the analog signal monitoring device circuit for the electromagnetic compatibility test of integrated circuits of the present invention;

[0072] Figure 2 It is the power supply circuit structure diagram of the monitoring device of the present invention;

[0073] Figure 3 It is the analog signal sampling and processing circuit diagram of the monitoring device of the present invention;

[0074] Figure 4 It is the circuit diagram of the tolerance online adjustable comparison method added to the present invention to realize the monitoring of AC signals;

[0075] Figure 5 It is the flowchart of the AC signal tracking method;

[0076] Figure 6 It is the flowchart of the analog signal monitoring method;

[0077] Figure 7 It is the flowchart of the immunity ability level judgment method. Specific implementation manner

[0078] Aiming at the problems and deficiencies existing in the current analog signal monitoring technical solution for the electromagnetic compatibility anti-interference test of integrated circuits, the present application proposes an integrated circuit analog signal electromagnetic compatibility anti-interference test monitoring device and method. When this device is used for the electromagnetic compatibility anti-interference test, it can monitor the instantaneous state of the monitored analog signals of various power supply chips and analog chips in real time, including analog and digital two-stage comparison circuits. The analog comparison circuit is on the outer layer, and it captures abnormalities in the sampling link, realizing the rapid capture of abnormalities; the digital comparison circuit is implemented in the inner-layer FPGA, and combined with storage technology, it operates and judges according to the level judgment process specified in the standard, realizing the classification of anti-interference ability levels. This device corrects the phase of the reference AC signal through technologies such as AC signal zero-crossing detection and phase compensation, realizes the monitoring of the instantaneous state of AC signals, and improves the speed and accuracy of capturing AC signal abnormalities. This device realizes the CAN bus online parameter setting function, enhances the flexibility of the system, improves the debugging and test efficiency, reduces the upper computer part at the same time, and reduces the device cost.

[0079] The following further illustrates the technical solution provided by the present invention in conjunction with embodiments.

[0080] Embodiment 1

[0081] As shown in Figure 1(a), it is the main framework diagram of the system of the present invention; as shown in Figure 1(b), it is the circuit block diagram of the embodiment of the system of the present invention.

[0082] 1.1 Overall block diagram

[0083] This device mainly consists of nine parts: FPGA circuit, analog signal sampling and processing circuit, CAN communication circuit, power supply circuit, storage circuit, D / A conversion circuit, comparison circuit, fast alarm circuit and hierarchical display circuit. The overall block diagram is shown in Figure 1(b). The power supply circuit mainly powers the entire device; the analog signal acquisition and processing circuit mainly conducts signal sampling, conditioning and AD conversion. The CAN bus circuit mainly conducts online setting of monitoring preset values and real-time transmission of monitoring status to the remote auxiliary device. The FPGA circuit is the core control chip of this device, mainly realizing three functions: (1) real-time monitoring and analysis of the data after AD conversion, and determination of the anti-interference ability of the test chip; (2) generation of corresponding PWM waves according to the parameters set by the CAN bus and the calibration coefficient; (3) detection of the zero-crossing point of the measured signal, adjustment of the phase of the reference signal, so that the phases of the reference signal and the monitored signal are consistent. The storage circuit mainly stores the status and records events when the working status of the monitored chip is abnormal. The analog signal comparison circuit mainly compares with the reference signal in the sampling link to achieve fast capture of abnormalities. In addition, according to the parameters set by the CAN bus, the tolerance value is adjusted through the online adjustable comparison method circuit for setting the tolerance value. The alarm circuit mainly gives an alarm when the working status of the monitored chip is abnormal. The D / A circuit mainly converts the PWM wave sent by the FPGA into the corresponding analog signal. The A / D conversion circuit in the calibration path mainly converts the analog signal after D / A conversion into a digital quantity, feeds it back to the FPGA, compares it with the monitored signal, and finely adjusts the phase of the reference signal. The analog signal of the chip under test should be connected to the monitoring device, and the power supply of the chip under test is controlled by the monitoring device.

[0084] 1.2 Power Supply Circuit

[0085] The power supply structure of this device is as Figure 2As shown in the figure, an electrostatic and surge protection circuit and a filtering circuit are designed at the power interface. Then, the CUWB1205YMD-6WR3 isolated power module from Mornsun, which converts 15V to 5V, is adopted. This module not only plays the role of power voltage conversion but also acts as electrical isolation, eliminating the differential-mode interference in the transmission path. The converted 5V power supply first powers the analog circuit part and then the digital circuit part. The power supplies of the digital circuit part and the analog part are isolated by magnetic beads to reduce the influence of the digital part on the analog part circuit; (All the analog circuits on the PCB board are powered by the power supply before the magnetic beads, and all the digital circuits on the PCB board are powered by the power supply before the magnetic beads) A 0-ohm resistor is placed between the ground of the analog circuit and the ground of the digital circuit in this device, and the single-point grounding method for the analog part and the digital part is adopted; When laying out the PCB, the digital circuit and the analog circuit are separated accordingly; The above three measures reduce the interference between each part, improve the EMC performance of the device, improve the signal quality, and improve the monitoring accuracy of the device.

[0086] 1.3 Analog signal sampling and processing circuit

[0087] The schematic diagram of the analog signal sampling and processing circuit of this device is as Figure 3 shown, mainly including five parts: a protection circuit, a limit protection circuit, an isolation operational amplifier, a conditioning circuit, and an FPGA circuit. The protection circuit includes electrostatic, surge protection, and filtering circuits; The limit protection circuit mainly prevents the subsequent circuit from being damaged due to excessive input of analog signals; To improve the electromagnetic protection ability of the system, the interface circuit and the internal circuit of the whole system are isolated by the ISO224 isolation chip. The isolation operational amplifier uses ISO224, which is powered by a single-ended power supply but can process positive and negative signals, simplifying the power supply and signal processing circuits; The conditioning circuit mainly conditions the analog signal to a value within the allowable range of the input pins of the AD chip; The AD conversion mainly converts the analog signal into a digital signal. This device uses the AD9226 with a 12-bit parallel interface; Finally, the sampling conversion result is output to the FPGA, and the FPGA judges the sampling value according to the set value.

[0088] Embodiment 2

[0089] A method for monitoring analog signals for integrated circuit electromagnetic compatibility testing according to Embodiment 2 of the present invention monitors analog signals for integrated circuit electromagnetic compatibility testing based on the analog signal monitoring system for integrated circuit electromagnetic compatibility testing in Embodiment 1. The method includes the following steps:

[0090] S1. Generate a PWM wave according to the set relevant parameters through the pulse width modulation unit and transmit it to the D / A conversion circuit;

[0091] S2. Convert the PWM wave output by the pulse width modulation unit into a reference analog signal through a D / A conversion circuit, and transmit it to the analog signal comparison circuit and the calibrated AD converter;

[0092] S3. Convert the reference analog signal output by the D / A conversion circuit into a reference digital signal through the calibrated AD converter, and feedback it to the calibration unit. The calibration unit performs self-calibration on the reference digital signal until the frequency, phase, and amplitude of the reference digital signal are consistent with the expected set values;

[0093] S4. Sample the measured analog signal in the normal state of the integrated circuit chip through the analog signal acquisition unit, and transmit it to the analog signal comparison unit; at the same time, process the measured analog signal in the normal state through the analog signal acquisition unit to obtain an analog-digital signal, and transmit it to the calibration unit;

[0094] S5. Compare the analog-digital signal obtained by processing the sampled value of the measured analog signal in the normal state with the reference digital signal obtained after the reference analog signal generated by the reference signal generation unit is converted by the AD converter in the calibration unit, and calibrate the reference digital signal until the phase is consistent with the signal in the normal state, and then start the test;

[0095] S6. Compare the measured analog signal with the reference analog signal through the analog signal comparison unit, and then judge the abnormality. If there is an abnormality, alarm through the fast alarm circuit;

[0096] S7. Convert the measured analog signal into a measured digital signal and transmit it to the digital signal analysis unit; the digital signal analysis unit performs real-time monitoring and analysis on the measured digital signal, and then determines the immunity ability level of the integrated circuit chip;

[0097] S8. Compare the measured digital signal with the reference digital signal through the digital signal comparison unit, and then analyze the abnormality and output the abnormality analysis result. 1.4 Tolerance Online Adjustable Comparison Method

[0098] As Figure 4 shown, the circuit diagram of the tolerance online adjustable comparison method added by the present invention to realize the monitoring of AC signals;

[0099] The tolerance online adjustable method mainly solves the problem of AC signal testing. For DC signals, the system default value can be used. The tolerance online adjustable comparison method is mainly implemented by a two-stage circuit of a subtractor and a comparator. Compared with the commonly used comparison method, this method adds a subtractor circuit, reduces the requirement for the phase consistency between the reference circuit and the measured signal, solves the problem of comparison errors caused by a small phase difference at the zero point, and avoids the output oscillation caused by this. The in-phase input of the subtractor is connected to the reference signal, and the reverse input is connected to the measured signal. The result of the real-time comparison between the measured signal and the reference signal is then compared with the set tolerance value. Among them, the reference signal and the tolerance value are adjusted according to the parameters set by the CAN bus. R1 and R2 are digital potentiometers, which can enlarge and reduce the difference between the measured signal and the reference value as needed to meet the test requirements of analog signals with different requirements.

[0100] 1.5 AC signal tracking method

[0101] To ensure the consistency between the reference signal and the measured signal, the phase and amplitude of the reference signal must be calibrated before testing. This paper proposes an AC signal phase tracking method that combines coarse adjustment and fine adjustment to speed up the tracking speed. When the phase difference is greater than 90°, a coarse adjustment method is used; when the phase difference is less than 90°, an incremental PI algorithm is used. After the phase is adjusted, the amplitude is adjusted. This method combines coarse adjustment and fine adjustment. Coarse adjustment speeds up the adjustment time, increases the convergence of the algorithm, and solves the problem of uncontrolled engineering caused by direct use of the PI algorithm; fine adjustment increases the adjustment time and adjustment accuracy. The specific process is as follows Figure 5 As shown, the following steps are included:

[0102] S1. Sampling the reference signal and the test signal, and performing normalization processing on them respectively;

[0103] S2. Determine whether the phase difference between the normalized reference signal and the test signal is greater than 180°;

[0104] S3. If it is greater than 180°, the phase of the reference signal is adjusted by 180° and returns to step S2; if it is not greater than 180°, continue to determine whether the phase difference is greater than 90°;

[0105] S4. If it is greater than 90°, adjust the phase of the reference signal by 90° and return to step S2; if it is not greater than 90°, proceed to step S5;

[0106] S5. The difference between the reference signal and the test signal is adjusted using an incremental PI algorithm;

[0107] S6. Determine whether the phase difference between the adjusted reference signal and the test signal is less than the set value. If it is not less than the set value, return to step S5; if it is less than the set value, adjust the amplitudes of the adjusted reference signal and the test signal so that the amplitude difference between the reference signal and the test signal is less than the set allowable value.

[0108] Before the test, according to the characteristics of data processing by the program, a lookup table of sine waves is generated by Matlab software and stored in the Flash memory in the order of addresses. Store n (odd number) numbers, and n≥10N. During the test, according to the test accuracy requirements, calculate the number of readings N that the FPGA reads from the memory within one cycle. For the convenience of AC signal tracking, if the calculated N is odd, then take N = N; if N is even, then take N = N + 1. For the test signal with frequency f1, the frequency f2 at which the FPGA reads numbers from the FLASH memory is f2 = N * f1, and f2 is obtained by frequency division and multiplication of the FPGA main frequency. If the phase of the reference signal is adjusted by 180°, the reading address value is incremented by (N - 1) forward; if the phase of the reference signal is adjusted by 90°, the reading address value is incremented by (N - 1) / 2 forward.

[0109] 1.6 Implementation method of analog signal monitoring

[0110] The monitoring method of this device is as Figure 6 shown. The monitoring adopts a two - level monitoring method. The first level uses an analog circuit for monitoring, which improves the response speed of system monitoring; the second - level monitoring uses a digital circuit for monitoring, which improves the accuracy and intelligence of system monitoring. Before starting the test, set the set value of the monitoring device according to the parameters of the tested chip. Then open the tested PCB board. After the chip output is stable, perform reference signal calibration, and then start the electromagnetic compatibility test. When the chip has an abnormality, an alarm is given. The first - level monitoring circuit (analog circuit) gives an alarm quickly, and the second - level monitoring circuit analyzes the abnormality specifically, locks and displays the chip fault status information. At the same time, the test data can be transmitted to the remote auxiliary device through the CAN bus as needed. The implementation method of analog signal monitoring includes the following steps:

[0111] S1. Set a preset value according to the status of the tested chip;

[0112] S2. After the tested chip is powered on and works stably, perform reference signal calibration;

[0113] S3. After calibration is completed, start monitoring; compare the reference signal and the measured signal to determine whether there is an abnormality in the measured signal. If there is an abnormality, enter step S4; if there is no abnormality, enter step S5;

[0114] S4. Use the first - level monitoring circuit to give an alarm, use the second - level monitoring circuit to perform abnormality analysis, output and lock the abnormality analysis result, and enter step S6;

[0115] S5. Determine whether the test is over. If not, return to step S3; if so, proceed to step S6;

[0116] S6. Shut down the chip under test.

[0117] 1.7 Method for Judging the Immunity Ability Level

[0118] Judging the immunity ability level is the most important part of the integrated circuit immunity test. According to the abnormal degree during the integrated circuit immunity test, the integrated circuit immunity standard classifies the immunity ability into five levels: A, B, C, D, and E. In actual tests, generally four levels, A, C, D, and E, are applied. Due to the continuous maturity of domestic integrated circuits in recent years, there are few devices supporting the integrated circuit electromagnetic compatibility test. Currently, there is no device with the function of judging the immunity ability level. There are potential electromagnetic radiation hazards for personnel during the test process. This application combines hardware design and proposes an automatic judgment method for the immunity ability level device. The flow chart is as Figure 7 shown. This method is completed through automatic monitoring and control by the device throughout the process, without the need for personnel to manually operate and monitor beside the test chip during the test process. It specifically includes the following steps:

[0119] S1. Determine whether a test stop signal is received; if not, continue to judge; if so, proceed to step S2;

[0120] S2. Determine whether there has been an abnormality in the monitoring signal status variable Symble bit during the test process; if there has been no abnormality (Symble = 0), output the immunity ability level as level A; if there has been an abnormality (Symble = 1), proceed to step S3;

[0121] S3. Turn off the interference signal applied to the chip under test, and at the same time inform the monitoring device through the CAN bus, automatically switch the signal status variable to Symble1. The operator does not need to open the darkroom door to operate the monitoring device, and the system automatically completes it;

[0122] S4. Determine whether the current monitoring signal is normal. If it is normal (Symble1 = 0 && Symble = 1), output the immunity ability level as level C; if it is not normal (Symble1 = 1 && Symble = 1), proceed to step S4;

[0123] S5. The device automatically cuts off the power supply of the PCB under test. After the countdown ends according to the parameter settings, the PCB under test is restarted; it is re-determined whether the current monitoring signal is normal. If it is normal (Symble12 = 0 && Symble1 = 1), the immunity ability level of D is output; if it is not normal (Symble12 = 1 && Symble1 = 1), the immunity ability level of E is output.

[0124] Key points of the proposal of this application:

[0125] Key point 1:

[0126] Structural block diagram of the integrated circuit electromagnetic compatibility test analog signal monitoring device. There is currently no such dedicated device. According to the characteristics of the electromagnetic compatibility tests of the power supply chip and the analog chip, this device is designed with a device including an FPGA circuit, an analog signal sampling and processing circuit, a CAN communication circuit, a power supply circuit, a storage circuit, and an alarm circuit.

[0127] Key point 2:

[0128] Abnormal monitoring and alarm method. To improve the response speed of the device to changes in the monitoring signal, this application proposes a two-stage monitoring circuit, one analog circuit and one digital circuit. To achieve the monitoring of AC signals, this article adds a subtractor in front of the common comparator circuit, and the latter stage is compared with the tolerance value, which can reduce the requirement for the reference signal to track the signal under test and avoid false alarms caused by phase differences. The analog alarm circuit is on the periphery. When an abnormality occurs, the analog monitoring circuit immediately responds with an alarm, and the digital circuit further analyzes the abnormal data and records the abnormal state.

[0129] Key point 3:

[0130] AC signal tracking method. To monitor the monitoring signal, it is necessary to ensure the consistency of the reference signal and the signal under test in the normal state. Before the test, the phase and amplitude of the reference signal need to be calibrated. This application proposes an AC signal phase tracking method that combines coarse adjustment and fine adjustment, which speeds up the tracking speed. When the phase difference is greater than 90°, the coarse adjustment method is used; when the phase difference is less than 90°, the fine adjustment method is used. After the phase adjustment, the amplitude is adjusted.

[0131] Key point 4:

[0132] Immunity ability level judgment method. According to the standards, this application proposes an automatic immunity ability level judgment method. According to the abnormal situation of the monitoring signal, the immunity ability level of the chip under test is automatically output, reducing the operation of the test personnel. The device completes it automatically, reducing the professional requirements for the test personnel and improving the test efficiency.

[0133] Protection points of the proposal of this application:

[0134] 1. Block diagram of the analog signal monitoring device for integrated circuit electromagnetic compatibility testing;

[0135] 2. Abnormality monitoring fast response and alarm method;

[0136] 3. Circuit and method for the device to achieve AC signal tracking;

[0137] 4. Engineering implementation method for the device to automatically determine the immunity ability level.

[0138] The present invention relates to the field of monitoring integrated circuit electromagnetic immunity test signals, and particularly relates to an analog signal monitoring system and method for integrated circuit electromagnetic compatibility testing. The present invention monitors the instantaneous value of the monitored analog signal of the integrated circuit in real time, including analog and digital two-stage comparison circuits: comparing the collected analog signal with the generated reference signal through the analog signal comparison circuit, and judging abnormalities, and alarming when abnormalities are judged; at the same time, processing the collected analog signal into a digital signal, and comparing it with the reference signal in the FPGA to analyze the abnormalities in detail. The present invention also determines the immunity ability level of the integrated circuit chip by analyzing the digital signal in the FPGA. The present invention also proposes a method for AC signal phase tracking combining coarse adjustment and fine adjustment, calibrating the phase and amplitude of the reference signal before testing, and accelerating the tracking speed of the AC signal.

[0139] It can be seen from the above specific description of the present invention that:

[0140] 1. The preset parameter values of the device in this application can be set by the CAN bus, without developing a dedicated upper computer, saving costs.

[0141] 2. The device in this application is designed with two-stage monitoring and alarm circuits, accelerating the reaction and capture ability of abnormal signals.

[0142] 3. The method for automatically judging the immunity ability of the chip is realized in this application, improving the intelligence of the device, reducing the requirements for testers, and saving labor at the same time.

[0143] 4. A fast AC signal tracking method is proposed in this application, improving the system calibration time and the efficiency of integrated circuit electromagnetic compatibility testing.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. An analog signal monitoring system for electromagnetic compatibility testing of integrated circuits, characterized in that, The system includes: a reference signal generation unit, an analog signal sampling unit, a calibration unit, an analog signal comparison unit, a digital signal analysis unit, and a digital signal comparison unit; The reference signal generation unit is used to generate a reference analog signal; it is also used to convert the reference analog signal into a reference digital signal; The analog signal sampling unit is used to sample the measured analog signal for electromagnetic compatibility testing of the integrated circuit chip and transmit it to the analog signal comparison unit. At the same time, it converts the measured analog signal into a measured digital signal and transmits it to the digital signal comparison unit; The calibration unit is used to perform self-calibration on the generated reference digital signal and calibrate the reference digital signal according to the normal state value of the measured analog signal collected; The analog signal comparison unit is used to compare the measured analog signal and the reference analog signal, and then judge the abnormality of the integrated circuit chip; The digital signal comparison unit is used to compare the measured digital signal and the reference digital signal, and then analyze the abnormality; The digital signal analysis unit is used to perform real-time monitoring and analysis on the measured digital signal, and then determine the immunity ability level of the integrated circuit chip.

2. The analog signal monitoring system for electromagnetic compatibility testing of integrated circuits according to claim 1, wherein The system further includes: a signal parameter setting unit and a pulse width modulation unit; the signal parameter setting unit is used to set the relevant parameters of the reference signal according to the requirements of the integrated circuit chip; The pulse width modulation unit is used to generate a PWM wave according to the set relevant parameters of the reference signal; The reference signal generation unit includes a D / A conversion circuit and an A / D conversion circuit; The D / A conversion circuit is used to convert the PWM wave generated by the pulse width modulation unit into a reference analog signal; The A / D conversion circuit is used to convert the reference analog signal converted by the D / A conversion circuit into a reference digital signal.

3. The analog signal monitoring system for electromagnetic compatibility testing of integrated circuits according to claim 1, characterized in that The analog signal sampling unit includes: an interface circuit, a protection circuit, a limit protection circuit, an isolation operational amplifier, a conditioning circuit, and an AD converter; The protection circuit includes: an electrostatic, surge protection, and filtering circuit, which is used to protect the circuit; The limit protection circuit is used to prevent damage to the circuit caused by excessive input of the analog signal; The isolation operational amplifier circuit is used to isolate the interface circuit and the internal circuit; The conditioning circuit is used to condition the voltage of the analog signal within the range allowed by the AD converter; The AD converter is used to convert the analog signal into a digital signal.

4. The analog signal monitoring system for electromagnetic compatibility testing of integrated circuits according to claim 1, wherein The analog signal comparison unit includes a subtractor circuit and a DA converter; The digital signal comparison unit includes a comparator circuit; The non-inverting input terminal of the subtractor is connected to the reference analog signal, and the inverting input terminal is connected to the measured analog signal, which is used to compare the measured analog signal and the reference analog signal in real time and transmit it to the DA converter to obtain a tolerance signal; The comparator is used to compare the tolerance signal with the set tolerance value in the reference digital signal and transmit the comparison result to the alarm circuit; The non-inverting input terminal and the inverting input terminal of the subtractor are respectively connected with a first digital potentiometer and a second digital potentiometer; the first digital potentiometer and the second digital potentiometer are used to amplify and reduce the tolerance value.

5. The analog signal monitoring system for electromagnetic compatibility testing of integrated circuits according to claim 2, wherein The calibration unit, digital signal analysis unit, digital signal comparison unit, and pulse width modulation unit are all implemented based on the FPGA circuit; The signal parameter setting unit is implemented based on the CAN bus circuit.

6. The analog signal monitoring system for electromagnetic compatibility testing of integrated circuits according to claim 1, wherein The system further includes: a storage circuit, a fast alarm circuit, a hierarchical display circuit, and a power supply circuit; The storage circuit is used to store the status and record events when an abnormality occurs in the integrated circuit chip; The fast alarm circuit is used to give an alarm when an abnormality occurs in the integrated circuit chip; The hierarchical display circuit is used to output the immunity ability level of the judged integrated circuit chip; The power supply circuit is used to supply power to the entire system; An electrostatic and surge protection circuit and a filtering circuit are provided at the power interface of the power supply circuit; the power module of the power supply circuit uses an isolated power module; the isolated power module is used for power voltage conversion and electrical isolation; When the circuits of the system are arranged on the PCB board, the power supplies of the digital circuit part and the analog circuit part are isolated by magnetic beads; the power supply circuit supplies power to the analog circuit and the digital circuit in sequence.

7. An analog signal monitoring method for integrated circuit electromagnetic compatibility testing, implemented based on the system according to any one of claims 1-6, the method comprising the following steps: S1. Generate a PWM wave by the pulse width modulation unit according to the set relevant parameters and transmit it to the D / A conversion circuit; S2. Convert the PWM wave output by the pulse width modulation unit into a reference analog signal by the D / A conversion circuit and transmit it to the analog signal comparison circuit and the calibrated AD converter; S3. Convert the reference analog signal output by the D / A conversion circuit into a reference digital signal by the calibrated AD converter and feedback it to the calibration unit, and perform self-calibration on the reference digital signal by the calibration unit until the frequency, phase, and amplitude of the reference digital signal are consistent with the expected set values; S4. Sample the measured analog signal in the normal state of the integrated circuit chip by the analog signal sampling unit and transmit it to the analog signal comparison unit; at the same time, process the measured analog signal in the normal state by the analog signal sampling unit to obtain an analog digital signal and transmit it to the calibration unit; S5. Compare the analog digital signal obtained by processing the sampled value of the measured analog signal in the normal state and the reference digital signal obtained by converting the reference analog signal generated by the reference signal generation unit through the AD converter in the calibration unit, and calibrate the reference digital signal until the phase is consistent with the signal in the normal state, and then start the test; S6. Compare the measured analog signal and the reference analog signal by the analog signal comparison unit, and then judge the abnormality. If there is an abnormality, give an alarm through the fast alarm circuit; S7. Convert the measured analog signal into a measured digital signal and transmit it to the digital signal analysis unit; perform real-time monitoring and analysis on the measured digital signal by the digital signal analysis unit, and then determine the immunity ability level of the integrated circuit chip; S8. Compare the measured digital signal and the reference digital signal by the digital signal comparison unit, and then analyze the abnormality and output the abnormality analysis result.

8. The analog signal monitoring method for electromagnetic compatibility testing of integrated circuits according to claim 7, characterized in that, In S5, the calibration unit calibrates the reference signal, specifically including: S5-1. Sampling the reference analog signal and the test analog signal, and performing normalization processing on each of them; S5-2. Judging the phase difference between the normalized reference analog signal and the measured analog signal, and judging whether the phase difference is greater than 180°; S5-3. If it is greater than 180°, adjust the phase of the reference analog signal by 180°, and return to S5-2; if it is not greater than 180°, continue to judge whether the phase difference is greater than 90°; S5-4. If it is greater than 90°, adjust the phase of the reference analog signal by 90°, and return to S5-2; if it is not greater than 90°, enter S5-5; S5-5. Performing PI adjustment on the reference analog signal and the measured analog signal; S5-6. Judging whether the phase difference between the adjusted reference analog signal and the measured analog signal is less than the set value. If it is not less than the set value, return to S5-5; if it is less than the set value, adjust the amplitudes of the adjusted reference analog signal and the measured analog signal so that the amplitude difference between the reference analog signal and the measured analog signal is less than the set value.

9. The analog signal monitoring method for electromagnetic compatibility testing of integrated circuits according to claim 7, wherein In S7, the digital signal analysis unit determines the immunity ability level of the integrated circuit chip, including the following steps: S7-1. Judging whether a test stop signal is received; if not, continue to judge; if so, enter S7-2; S7-2. Judging whether there has been an abnormality in the measured signal during the test; if there has been no abnormality, output the immunity ability level as grade A; if there has been an abnormality, enter S7-3; S7-3. Judging whether the current measured signal is normal. If it is normal, output the immunity ability level as grade C; if it is not normal, enter S7-4; S7-4. Cut off the power supply of the integrated circuit chip. After a period of time ends according to the parameter setting, restart the integrated circuit chip; re-judge whether the current measured signal is normal. If it is normal, output the immunity ability level as grade D; if it is not normal, output the immunity ability level as grade E.

10. The analog signal monitoring method for electromagnetic compatibility testing of integrated circuits according to claim 7, characterized in that Before the method performs monitoring, a query table of sine PWM waves is generated by software and stored in the Flash memory in the order of addresses. Store n numbers, where n is an odd number and n≥10N; during monitoring, according to the test accuracy requirement, calculate the number of read points N from the memory by the FPGA within one cycle; If the calculated N is an odd number, take N as N; if N is an even number, take N as N + 1; the frequency f2 of the wave read by the FPGA from the memory = N * f1, where f1 is the frequency of the test signal.

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