Test Circuit and Its Test Method

Abstract

The present invention provides a test circuit and a test method thereof. The test circuit includes: an instruction pad, a first integrated circuit, a second integrated circuit, a first latch, and a second latch. The instruction pad receives an operation instruction. The first integrated circuit performs corresponding test operations according to the operation instruction and an internal selection signal. The second integrated circuit performs corresponding test operations according to the operation instruction and the internal selection signal. The first latch provides the operation instruction to the first integrated circuit according to the internal selection signal. The second latch provides the operation instruction to the second integrated circuit according to the internal selection signal.

Description

Technical Field

[0001] The present invention relates to a test circuit and a test method thereof, and more particularly to a test circuit and a test method thereof that share test pads and place the test pads on a scribe line. Background Art

[0002] After semiconductor integrated circuit components are fabricated, it is verified whether these integrated circuit components have certain expected characteristics or values, such as specific gain, resistance value, capacitance value, etc. This quality control method is called wafer acceptance testing. Sometimes, it is also necessary to program and test certain integrated circuit components on the wafer before the wafer is cut into individual chips. Therefore, how to configure test pads and ensure that the test pads do not affect the characteristics of the integrated circuit components will become an important issue. Summary of the Invention

[0003] The present invention proposes a test circuit and a test method herein. All test pads required are placed on the scribe line to reduce the impact on normal operation. In addition, a latch is added between the command pad and the integrated circuit. By enabling the latch, the operation command is sent to the corresponding integrated circuit, so that multiple integrated circuits can share the same command pad, thereby reducing the test pads required. Multiple integrated circuits can also share power pads and data pads, further reducing the test pads required.

[0004] In view of this, the present invention provides a test circuit, including a command pad, a first integrated circuit, a second integrated circuit, a first latch, and a second latch. The command pad receives an operation command. The first integrated circuit performs a corresponding test operation according to the operation command and an internal selection signal. The second integrated circuit performs a corresponding test operation according to the operation command and the internal selection signal. The first latch provides the operation command to the first integrated circuit according to the internal selection signal. The second latch provides the operation command to the second integrated circuit according to the internal selection signal.

[0005] According to an embodiment of the present invention, the command pad, the first latch, and the second latch are located on a scribe line between the first integrated circuit and the second integrated circuit.

[0006] According to an embodiment of the present invention, the test circuit further includes a test pad, an external selection pad, and a controller. The test pad receives a test signal. The external selection pad receives an external selection signal. The controller decodes the external selection signal into an internal signal according to the test signal.

[0007] According to an embodiment of the present invention, when a test signal transitions from a first state to a second state, the controller resets an internal selection signal. When the test signal transitions from the second state to the first state, the controller decodes an external selection signal into an internal signal. The internal signal is used to select one of a first integrated circuit and a second integrated circuit for corresponding test operations.

[0008] According to another embodiment of the present invention, when the test signal transitions from the second state to the first state, the controller decodes the external selection signal into an internal signal, and a first latch provides a deep power-saving instruction received by an instruction pad to the first integrated circuit according to the internal signal generated by the controller, so that the first integrated circuit operates in a deep power-saving mode.

[0009] According to an embodiment of the present invention, when the first integrated circuit operates in the deep power-saving mode, the controller also provides a test instruction received by the instruction pad to the second integrated circuit according to the external selection signal, so that the second integrated circuit performs corresponding test operations according to the test instruction.

[0010] According to an embodiment of the present invention, the first state is a low voltage level and the second state is a high voltage level.

[0011] According to an embodiment of the present invention, the test pad and the controller are located on a scribe line between the first integrated circuit and the second integrated circuit.

[0012] According to an embodiment of the present invention, the test circuit further includes a plurality of power pads. The power pads receive a power supply and are coupled to the first integrated circuit and the second integrated circuit to supply power to the first integrated circuit and the second integrated circuit, wherein the power pads are located on a scribe line between the first integrated circuit and the second integrated circuit.

[0013] According to an embodiment of the present invention, the test circuit further includes a plurality of data pads. The data pads are coupled to the first integrated circuit and the second integrated circuit to transmit data to one of the first integrated circuit and the second integrated circuit and receive data sent by one of the first integrated circuit and the second integrated circuit, wherein the data pads are located on a scribe line between the first integrated circuit and the second integrated circuit.

[0014] The present invention also provides a test method for testing a first integrated circuit and a second integrated circuit. The test method includes selecting the first integrated circuit; operating the first integrated circuit in a deep power-saving mode; selecting the second integrated circuit; and performing corresponding test operations on the second integrated circuit according to a test instruction.

[0015] According to an embodiment of the present invention, the steps of selecting the second integrated circuit and the steps of selecting the first integrated circuit further include receiving a test signal through a test pad; receiving an external selection signal through an external selection pad; decoding the external selection signal into an internal selection signal according to the test signal; and selecting one of the first integrated circuit and the second integrated circuit according to the internal selection signal.

[0016] According to an embodiment of the present invention, the test pad is located on a scribe line between the first integrated circuit and the second integrated circuit.

[0017] According to an embodiment of the present invention, the step of decoding the external selection signal into an internal selection signal according to the test signal further includes resetting the internal selection signal by a controller when the test signal transitions from a first state to a second state; and decoding the external selection signal into an internal signal when the test signal transitions from the second state to the first state.

[0018] According to an embodiment of the present invention, the first state is a low voltage level and the second state is a high voltage level.

[0019] According to an embodiment of the present invention, the step of operating the first integrated circuit in a deep power saving mode further includes receiving a deep power saving instruction through an instruction pad; providing the deep power saving instruction to the first integrated circuit according to the internal selection signal by a first latch; and operating the first integrated circuit in the deep power saving mode according to the deep power saving instruction.

[0020] According to an embodiment of the present invention, the step of performing a corresponding test operation on the second integrated circuit according to a test instruction further includes receiving the test instruction through the instruction pad; providing the test instruction to the second integrated circuit according to the internal selection signal by a second latch; and performing the corresponding test operation on the second integrated circuit according to the test instruction.

[0021] According to an embodiment of the present invention, the instruction pad, the first latch, and the second latch are located on a scribe line between the first integrated circuit and the second integrated circuit.

[0022] According to an embodiment of the present invention, the test method further includes receiving a power supply through a plurality of power pads, wherein the power pads are coupled to the first integrated circuit and the second integrated circuit and are located on a scribe line between the first integrated circuit and the second integrated circuit; and supplying power to the first integrated circuit and the second integrated circuit by the power supply.

[0023] According to an embodiment of the present invention, the test method further includes transmitting data to one of the first integrated circuit and the second integrated circuit through a plurality of data pads; and receiving the data sent by one of the first integrated circuit and the second integrated circuit through the data pads, wherein the data pads are coupled to the first integrated circuit and the second integrated circuit and are located on a scribe line between the first integrated circuit and the second integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram of a test circuit provided by an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of a test circuit provided by an embodiment of the present invention;

[0026] Figure 3 is a schematic diagram of a latch provided by an embodiment of the present invention;

[0027] Figure 4 is a timing diagram of a latch provided by an embodiment of the present invention;

[0028] Figure 5 is a block diagram of a signal generation circuit provided by an embodiment of the present invention;

[0029] Figure 6 is a timing diagram of a signal generation circuit provided by an embodiment of the present invention;

[0030] Figure 7 is a flowchart of a test method provided by an embodiment of the present invention;

[0031] Figure 8 is a timing diagram of a test method provided by an embodiment of the present invention;

[0032] Figure 9 and Figure 10 are schematic diagrams of test circuits provided by two embodiments of the present invention.

[0033] SYMBOL DESCRIPTION

[0034] 100, 200, 900, 100: Test circuit;

[0035] 110, 500: Signal generation circuit;

[0036] 111, 510: Controller;

[0037] 210, 910, 1010: Scribe line;

[0038] 300: Latch;

[0039] 400: Timing diagram;

[0040] 700: Test method;

[0041] PADT: Test pad;

[0042] PADP: Power pad;

[0043] PADD: Data pad;

[0044] PE1: First external selection pad;

[0045] PE2: Second external selection pad;

[0046] PEM: Mth external selection pad;

[0047] A<1:M>: External selection signal;

[0048] TM: Test signal;

[0049] SEL1: First internal selection signal;

[0050] SEL2: Second internal selection signal;

[0051] SELN: Nth internal selection signal;

[0052] PADCMD: Instruction pad;

[0053] LTCH1: First latch;

[0054] LTCH2: Second latch;

[0055] LTCH3: Third latch;

[0056] LTCH4: Fourth latch;

[0057] LTCHN: Nth latch;

[0058] IC1: First integrated circuit;

[0059] IC2: Second integrated circuit;

[0060] IC3: Third integrated circuit;

[0061] IC4: Fourth integrated circuit;

[0062] ICN: Nth integrated circuit;

[0063] CMD: Operation instruction;

[0064] DI: Input terminal;

[0065] CLK: Clock terminal;

[0066] Q: Output terminal;

[0067] A: First command;

[0068] B: The second command;

[0069] C: The third command;

[0070] D: The fourth command;

[0071] A1: The first external selection signal;

[0072] A2: The second external selection signal;

[0073] A<2:1>: The external selection signal;

[0074] S710 to S790: The step flow;

[0075] VS: The supply voltage;

[0076] DPD: The deep power saving command;

[0077] NOP: The no-operation command;

[0078] TC: The test command;

[0079] R1: The first rising edge;

[0080] F1: The first falling edge;

[0081] R2: The second rising edge;

[0082] F2: The second falling edge;

[0083] R3: The third rising edge;

[0084] F3: The third falling edge;

[0085] R4: The fourth rising edge;

[0086] F4: The fourth falling edge. Detailed implementation mode

[0087] Figure 1 is a block diagram of the test circuit provided by an embodiment of the present invention. As Figure 1As shown, the test circuit 100 includes a signal generation circuit 110, where the signal generation circuit 110 includes a test pad PADT, a first external selection pad PE1, a second external selection pad PE2, …, an Mth external selection pad PEM, and a controller 111. The test pad PADT is used to receive a test signal TM, and the first external selection pad PE1, the second external selection pad PE2, …, and the Mth external selection pad PEM receive external selection signals A<1:M>. The controller 111 decodes the external selection signals A<1:M> into a first internal selection signal SEL1, a second internal selection signal SEL2, …, and an Nth internal selection signal SELN according to the test signal TM.

[0088] The test circuit 100 further includes an instruction pad PADCMD, a first latch LTCH1, a second latch LTCH2, …, an Nth latch LTCHN, a first integrated circuit IC1, a second integrated circuit IC2, …, and an Nth integrated circuit ICN. The instruction pad PADCMD receives an operation instruction CMD, and the first latch LTCH1, the second latch LTCH2, …, and the Nth latch LTCHN respectively provide the operation instruction CMD received by the instruction pad PADCMD to one of the first integrated circuit IC1, the second integrated circuit IC2, …, and the Nth integrated circuit ICN according to the first internal selection signal SEL1, the second internal selection signal SEL2, …, and the Nth internal selection signal SELN.

[0089] According to an embodiment of the present invention, in order to prevent the test circuit 100 from interfering with the normal operation of the first integrated circuit IC1, the second integrated circuit IC2, …, and the Nth integrated circuit ICN, the test pad PADT, the controller 111, the instruction pad PADCMD, the first latch LTCH1, the second latch LTCH2, …, and the Nth latch LTCHN are located in the scribe line between the first integrated circuit IC1, the second integrated circuit IC2, …, and the Nth integrated circuit ICN. In other words, when the first integrated circuit IC1, the second integrated circuit IC2, …, and the Nth integrated circuit ICN are cut from the wafer into multiple chips, the test pad PADT, the controller 111, the instruction pad PADCMD, the first latch LTCH1, the second latch LTCH2, …, and the Nth latch LTCHN are also cut off together.

[0090] In many embodiments of the present invention, the first integrated circuit IC1, the second integrated circuit IC2, ..., and the Nth integrated circuit ICN may be memory circuits or any integrated circuits that need to be tested. According to an embodiment of the present invention, the first external selection pad PE1, the second external selection pad PE2, ..., and the Mth external selection pad PEM are existing pads in the integrated circuit. According to another embodiment of the present invention, the first external selection pad PE1, the second external selection pad PE2, ..., and the Mth external selection pad PEM may also be located in the scribe line 210. The detailed operation of the test circuit 100 will be described and explained below.

[0091] Figure 2 is a schematic diagram of a test circuit provided by an embodiment of the present invention. As Figure 2 shown, the test circuit 200 includes an instruction pad PADCMD, a first latch LTCH1, a second latch LTCH2, a third latch LTCH3, a fourth latch LTCH4, a first integrated circuit IC1, a second integrated circuit IC2, a third integrated circuit IC3, and a fourth integrated circuit IC4. According to an embodiment of the present invention, the test circuit 200 takes 4 integrated circuits as an example, which is only for illustration and explanation purposes and is not limited thereto in any form.

[0092] As Figure 2 shown, there is a scribe line 210 between the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4. The instruction pad PADCMD, the first latch LTCH1, the second latch LTCH2, the third latch LTCH3, and the fourth latch LTCH4 are located on the scribe line 210.

[0093] The first latch LTCH1 provides the operation instruction CMD received by the instruction pad PADCMD to the first integrated circuit IC1 according to the first internal selection signal SEL1. The second latch LTCH2 provides the operation instruction CMD to the second integrated circuit IC2 according to the second internal selection signal SEL2. The third latch LTCH3 provides the operation instruction CMD to the third integrated circuit IC3 according to the third internal selection signal SEL3. The fourth latch LTCH4 provides the operation instruction CMD to the fourth integrated circuit IC4 according to the fourth internal selection signal SEL4.

[0094] Figure 3 is a schematic diagram of a latch provided by an embodiment of the present invention. As Figure 3 shown, the latch 300 is a D-type flip-flop, where the latch 300 includes an input terminal DI, a clock terminal CLK, and an output terminal Q, and the clock terminal CLK receives the internal selection signal SEL. According to an embodiment of the present invention, the latch 300 corresponds to Figure 2The first latch LTCH1, the second latch LTCH2, the third latch LTCH3, and the fourth latch LTCH4 shown, and corresponding to Figure 1 the first latch LTCH1, the second latch LTCH2,..., and the Nth latch LTCHN shown. In other words, Figure 2 the first latch LTCH1, the second latch LTCH2, the third latch LTCH3, and the fourth latch LTCH4 shown can be D-type flip-flops.

[0095] Figure 4 is the timing diagram of the latch provided by an embodiment of the present invention. As Figure 4 shown, the timing diagram 400 is the operation timing diagram of the latch 300. The following description of the timing diagram 400 will be paired with Figure 3 for detailed description.

[0096] When the clock terminal CLK of the latch 300 receives an internal selection signal SEL that transitions from a low voltage level to a high voltage level, the latch 300 enters the pass state. As Figure 4 shown, when the input terminal DI receives the first command A, the output terminal Q also outputs the first command A; when the input terminal DI receives the second command B, the output terminal Q also outputs the second command B.

[0097] When the internal selection signal SEL transitions from a high voltage level to a low voltage level, the latch 300 enters the lock state. As Figure 4 shown, when the internal selection signal SEL received by the clock terminal CLK of the latch 300 transitions from a high voltage level to a low voltage level, and the input terminal DI receives the second command B, the output terminal Q outputs the second command B. Even if the input terminal DI receives the third command C or the fourth command D at this time, the output terminal Q still continuously outputs the second command B.

[0098] In other words, when Figure 2 one of the first internal selection signal SEL1, the second internal selection signal SEL2, the third internal selection signal SEL3, and the fourth internal selection signal SEL4 transitions from a low voltage level to a high voltage level and then from a high voltage level to a low voltage level, only one of the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4 receives the operation instruction CMD received by the command pad PADCMD.

[0099] Figure 5 is the block diagram of the signal generation circuit provided by an embodiment of the present invention. As Figure 5As shown, the signal generation circuit 500 includes a test pad PADT, a first external selection pad PE1, a second external selection pad PE2, and a controller 510. The signal generation circuit 500 corresponds to Figure 1 the signal generation circuit 110, and the controller 510 corresponds to Figure 1 the controller 111. To explain the operation of the signal generation circuit 500 in detail, Figure 5 taking two external selection pads and four internal selection signals as an example, it is not limited in any form.

[0100] The first external selection pad PE1 receives a first external selection signal A1, the second external selection pad PE2 receives a second external selection signal A2, the test pad PADT receives a test signal TM, and the controller 510 decodes the first external selection signal A1 and the second external selection signal A2 into a first internal selection signal SEL1, a second internal selection signal SEL2, a third internal selection signal SEL3, and a fourth internal selection signal SEL4 according to the test signal TM. The corresponding relationship between the detailed external selection signal A<2:1> and the internal selection signal SEL<4:1> is shown in Table 1 below.

[0101] Table 1

[0102] TM = 1 SEL<4:1> A<2:1>＝00 0001 A<2:1>＝01 0010 A<2:1>＝10 0100 A<2:1>＝11 1000

[0103] Figure 6 is the timing diagram of the signal generation circuit provided by an embodiment of the present invention. As Figure 6 shown, when the test signal TM transitions from a low voltage level to a high voltage level, the controller 510 zeros the internal selection signal SEL<4:1>, that is, sets the first internal selection signal SEL1, the second internal selection signal SEL2, the third internal selection signal SEL3, and the fourth internal selection signal SEL4 all to zero.

[0104] When the test signal TM is at a high voltage level, the controller 510 decodes the external selection signal A<2:1> into the internal selection signal SEL<4:1>. After the test signal TM transitions from a high voltage level to a low voltage level, the controller 510 outputs the decoded internal selection signal SEL<4:1>. When the test signal TM is at a low voltage level, regardless of the external selection signal A<2:1>, the controller 510 maintains the internal selection signal SEL<4:1> in the previous state.

[0105] Figure 7 is the flowchart of the test method provided by an embodiment of the present invention. Figure 8 is the timing diagram of the test method provided by an embodiment of the present invention. The following description of the Figure 7 flowchart will be accompanied by Figure 2 、Figure 5 and Figure 8 , for detailed description.

[0106] First, power the test circuit 200 (step S710). As Figure 8 shown, when powering the test circuit 200, the supply voltage VS is converted from a low voltage level to a high voltage level to power the test circuit 200, and the test signal TM is maintained at a low voltage level. At this time, although the instruction pad PADCMD receives a no-operation command NOP, no command can be input to any of the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4.

[0107] Next, select the second integrated circuit IC2 (step S720). As Figure 8 shown, when the test signal TM generates a first rising edge R1, the external selection signal A<2:1> is 01, the controller 510 decodes the external selection signal A<2:1>, and at the same time resets the internal selection signal SEL<4:1>. When the test signal TM generates a first falling edge F1, the controller 510 outputs the decoded external selection signal A<2:1> to the internal selection signal SEL<4:1> to be 0010, so that Figure 2 the instruction pad PADCMD of is coupled to the second integrated circuit IC2.

[0108] According to an embodiment of the present invention, Figure 2 the first latch LTCH1, the second latch LTCH2, the third latch LTCH3, and the fourth latch LTCH4 shown latch the first internal selection signal SEL1, the second internal selection signal SEL2, the third internal selection signal SEL3, and the fourth internal selection signal SEL4 respectively according to the test signal TM.

[0109] Turn off the second integrated circuit IC2 (step S730). When the instruction pad PADCMD receives a deep power-saving command DPD and provides the deep power-saving command DPD to the second integrated circuit IC2, the second integrated circuit IC2 operates in a deep power-saving mode according to the deep power-saving command DPD. According to an embodiment of the present invention, when the second integrated circuit IC2 operates in a deep power-saving mode, the input / output bus of the second integrated circuit IC2 is in a high-impedance state, and the power supply pin of the second integrated circuit IC2 is also turned off at the same time.

[0110] Select the third integrated circuit IC3 (step S740). As Figure 8As shown, when the test signal TM generates a second rising edge R2, the external selection signal A<2:1> is 10. The controller 510 decodes the external selection signal A<2:1> and zeros the internal selection signal SEL<4:1>. When the test signal TM generates a second falling edge F2, the controller 510 outputs the decoded external selection signal A<2:1> to the internal selection signal SEL<4:1> to be 0100, such that Figure 2 the instruction pad PADCMD of Figure 2 is coupled to the third integrated circuit IC3.

[0111] Turn off the third integrated circuit IC3 (step S750). When the instruction pad PADCMD receives the deep power saving command DPD and provides the deep power saving command DPD to the third integrated circuit IC3, the third integrated circuit IC3 operates in the deep power saving mode according to the deep power saving command DPD. According to an embodiment of the present invention, when the third integrated circuit IC3 operates in the deep power saving mode, the input / output bus of the third integrated circuit IC3 is in a high impedance state, and the power supply pin of the third integrated circuit IC3 is also turned off simultaneously.

[0112] Select the fourth integrated circuit IC4 (step S760). As Figure 8 shown, when the test signal TM generates a third rising edge R3, the external selection signal A<2:1> is 11. The controller 510 decodes the external selection signal A<2:1> and zeros the internal selection signal SEL<4:1>. When the test signal TM generates a third falling edge F3, the controller 510 outputs the decoded external selection signal A<2:1> to the internal selection signal SEL<4:1> to be 1000, such that Figure 2 the instruction pad PADCMD of Figure 2 is coupled to the fourth integrated circuit IC4.

[0113] Turn off the fourth integrated circuit IC4 (step S770). When the instruction pad PADCMD receives the deep power saving command DPD and provides the deep power saving command DPD to the fourth integrated circuit IC4, the fourth integrated circuit IC4 operates in the deep power saving mode according to the deep power saving command DPD. According to an embodiment of the present invention, when the fourth integrated circuit IC4 operates in the deep power saving mode, the input / output bus of the fourth integrated circuit IC4 is in a high impedance state, and the power supply pin of the fourth integrated circuit IC4 is also turned off simultaneously.

[0114] Select the first integrated circuit IC1 (step S780). As Figure 8As shown, when the test signal TM generates the fourth rising edge R4, the external selection signal A<2:1> is 00. The controller 510 decodes the external selection signal A<2:1> and resets the internal selection signal SEL<4:1>. When the test signal TM generates the fourth falling edge F4, the controller 510 outputs the decoded external selection signal A<2:1> to the internal selection signal SEL<4:1> to be 0001, such that Figure 2 the instruction pad PADCMD of Figure 2 is coupled to the first integrated circuit IC1.

[0115] Test the first integrated circuit IC1 (step S790). When the instruction pad PADCMD is coupled to the first integrated circuit IC1 and the instruction pad PADCMD receives the test command TC, the first integrated circuit IC1 performs corresponding test operations according to the test command TC.

[0116] In summary, the test method 700 turns off (N - 1) integrated circuits coupled to the instruction pad PADCMD, leaving only one integrated circuit for test operations, and places the pads required for testing on the scribe line to minimize the impact on the operations of the integrated circuits.

[0117] Figure 9 FIG. is a schematic diagram of a test circuit provided by another embodiment of the present invention. As Figure 9 shown, the test circuit 900 includes a power pad PADP, a first integrated circuit IC1, a second integrated circuit IC2, a third integrated circuit IC3, and a fourth integrated circuit IC4. The power pad PADP is used to receive power and simultaneously supply it to the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4.

[0118] According to other embodiments of the present invention, the test circuit 900 may include multiple power pads PADP. Here, only one power pad PADP is used for illustration and explanation, and is not limited thereto in any form. As Figure 9 shown, there is a scribe line 910 between the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4, where the power pad PADP is located on the scribe line 910. When the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4 are respectively cut into individual wafers, the power pad PADP will also be cut off simultaneously to reduce the impact on the normal operations of each integrated circuit.

[0119] Figure 10 FIG. is a schematic diagram of a test circuit provided by another embodiment of the present invention. As Figure 10As shown, the test circuit 1000 includes a data pad PADD, a first integrated circuit IC1, a second integrated circuit IC2, a third integrated circuit IC3, and a fourth integrated circuit IC4. The data pad PADD is coupled to the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4 to transmit data to one of the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4 and receive data transmitted by one of the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4.

[0120] According to other embodiments of the present invention, the test circuit 1000 may include a plurality of data pads PADD. Here, only one data pad PADD is used for illustration and explanation, and is not limited thereto in any form. As Figure 10 shown, there is a scribe line 1010 between the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4, and the data pad PADD is located on the scribe line 1010. When the first integrated circuit IC1, the second integrated circuit IC2, the third integrated circuit IC3, and the fourth integrated circuit IC4 are respectively diced into individual wafers, the data pad PADD will also be cut off at the same time to reduce the impact on the normal operation of each integrated circuit.

[0121] The present invention hereby provides a test circuit and a test method, in which all the pads required for testing are placed on the scribe line to reduce the impact on the integrated circuits in normal operation. In addition, a latch is added between the command pad and the integrated circuit, and the operation command is sent to the corresponding integrated circuit by enabling the latch, so that multiple integrated circuits can share the same command pad, thereby reducing the pads required for testing. In addition, multiple integrated circuits can also share the power pads and data pads, so that the pads required for testing can be further reduced.

Claims

1. A test circuit, characterized in that, Comprising: An instruction pad for receiving an operation instruction; A first integrated circuit for performing a corresponding test operation according to the operation instruction and an internal selection signal; A second integrated circuit for performing a corresponding test operation according to the operation instruction and the internal selection signal; A first latch for providing the operation instruction to the first integrated circuit according to the internal selection signal; And A second latch for providing the operation instruction to the second integrated circuit according to the internal selection signal; Wherein the instruction pad, the first latch and the second latch are located on a scribe line between the first integrated circuit and the second integrated circuit.

2. The test circuit according to claim 1, wherein Further comprising: A test pad for receiving a test signal; An external selection pad for receiving an external selection signal; A controller for decoding the external selection signal into the internal selection signal according to the test signal. When the test signal transitions from a first state to a second state, the controller resets the internal selection signal. When the test signal transitions from the second state to the first state, the controller decodes the external selection signal into the internal selection signal. The internal selection signal is used to select one of the first integrated circuit and the second integrated circuit to perform a corresponding test operation. When the test signal transitions from the second state to the first state, the controller decodes the external selection signal into the internal selection signal. The first latch provides a deep power saving instruction received by the instruction pad to the first integrated circuit according to the internal selection signal generated by the controller, so that the first integrated circuit operates in a deep power saving mode. When the first integrated circuit operates in the deep power saving mode, the controller further provides an operation instruction received by the instruction pad to the second integrated circuit according to the external selection signal, so that the second integrated circuit performs a corresponding test operation according to the operation instruction.

3. The test circuit according to claim 2, characterized in that, The first state is a low voltage level and the second state is a high voltage level.

4. The test circuit according to claim 2, wherein, Wherein the test pad and the controller are located on a scribe line between the first integrated circuit and the second integrated circuit.

5. The test circuit according to claim 1, wherein Further comprising: A plurality of power pads for receiving a power supply and being coupled to the first integrated circuit and the second integrated circuit for supplying power to the first integrated circuit and the second integrated circuit, wherein the power pads are located on a scribe line between the first integrated circuit and the second integrated circuit; And A plurality of data pads coupled to the first integrated circuit and the second integrated circuit for transmitting data to one of the first integrated circuit and the second integrated circuit and receiving data sent by one of the first integrated circuit and the second integrated circuit, wherein the data pads are located on a scribe line between the first integrated circuit and the second integrated circuit.

6. A testing method, characterized in that, For testing a first integrated circuit and a second integrated circuit, comprising: Selecting the first integrated circuit; Operate the first integrated circuit in a deep power-saving mode; Select the second integrated circuit; and Perform a corresponding test operation on the second integrated circuit according to an operation instruction; wherein the steps of selecting the second integrated circuit and the first integrated circuit further include: Receiving a test signal through a test pad; Receiving an external selection signal through an external selection pad; Decoding the external selection signal into an internal selection signal according to the test signal; and Selecting one of the first integrated circuit and the second integrated circuit according to the internal selection signal; wherein the step of decoding the external selection signal into the internal selection signal according to the test signal further includes: When the test signal transitions from a first state to a second state, a controller resets the internal selection signal; and When the test signal transitions from the second state to the first state, decoding the external selection signal into the internal selection signal; wherein the step of operating the first integrated circuit in the deep power-saving mode further includes: Receiving a deep power-saving instruction through an instruction pad; Using a first latch to provide the deep power-saving instruction to the first integrated circuit according to the internal selection signal; and Operating the first integrated circuit in the deep power-saving mode according to the deep power-saving instruction; wherein the step of performing a corresponding test operation on the second integrated circuit according to the operation instruction further includes: Receiving the operation instruction through the instruction pad; Using a second latch to provide the operation instruction to the second integrated circuit according to the internal selection signal; and Performing a corresponding test operation on the second integrated circuit according to the operation instruction; wherein the test pad is located on a scribe line between the first integrated circuit and the second integrated circuit, and the instruction pad, the first latch, and the second latch are located on a scribe line between the first integrated circuit and the second integrated circuit.

7. The test method according to claim 6, characterized in that, The first state is a low voltage level, and the second state is a high voltage level.

8. The test method according to claim 6, characterized in that, Further includes: Receiving a power supply through a plurality of power pads, wherein the power pads are coupled to the first integrated circuit and the second integrated circuit and are located on a scribe line between the first integrated circuit and the second integrated circuit; Powering the first integrated circuit and the second integrated circuit with the power supply; Transmitting data to one of the first integrated circuit and the second integrated circuit through a plurality of data pads; and Receiving data sent by one of the first integrated circuit and the second integrated circuit through the data pads, wherein the data pads are coupled to the first integrated circuit and the second integrated circuit and are located on a scribe line between the first integrated circuit and the second integrated circuit.

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