A SIP chip internal interconnection test method based on ATE

Abstract

The present invention proposes a method for testing the internal interconnection of a SIP chip based on ATE, and the method comprises the following steps: step S1, SVF writing an interconnection test program; step S2, parsing the written SVF program into a pattern capture format file; step S3, processing the vectors in the pattern capture format file that conform to the JTAG bus timing; step S4, transplanting the obtained test timing into the ATE test system, and performing an interconnection test according to the specific form of the interconnection model in the SIP chip. The present invention can generate a JTAG bus test timing efficiently and quickly for different interconnection models between the SIP chip and the ATE system, thereby improving the test efficiency.

Description

Technical Field

[0001] The invention relates to the technical field of system in package (SIP) chip testing, in particular to an ATE-based SIP chip internal interconnection testing method. Background Art

[0002] In recent years, with the continuous breakthroughs in nanoscale integrated circuit manufacturing technology, Moore's Law has reached a certain bottleneck. SIP technology provides a new design idea to solve this problem. Multiple unpackaged bare chips and passive devices such as resistors and capacitors are three-dimensionally integrated in a small system through SIP technology to form a SIP chip with specific functions. However, the continuous development of advanced packaging technology based on SIP chips and the continuous reduction of SOC bare core manufacturing processes have led to an increase in the device density inside the SIP chip, an increase in the variety of devices, and an increase in the density of internal interconnect lines, which has put forward higher requirements for the testing of internal interconnections of SIP chips.

[0003] In the 1990s, the European and American Joint Test Action Group (JTAG) first introduced the concept of boundary scan test technology into chip testing, and eventually formed the IEEE 1149.1 standard, which was recognized by the industry. After decades of exploration and research, JTAG test technology has been continuously innovated, forming the IEEE1149.4 standard for mixed signal testing, the IEEE 1149.6 standard for advanced digital networks, the IEEE 1500 standard for SoC chips, and the IEEE1532 standard for online configuration of programmable devices. For the testing of SIP chips, the Institute of Electrical and Electronics Engineers launched the IEEE 1838 standard in 2019. This standard was developed on the basis of IEEE 1149.1 and IEEE 1500, and is mainly used for complex SIP chip DFT circuit design. IEEE1838 provides theoretical guidance on solving the interoperability and testability issues between vertically stacked (such as 2.5D, 3D) chips. At present, there are no mature products compatible with IEEE 1838 in the industry. The JTAG test technology based on the IEEE 1149 standard is currently more mature and widely used. It has been widely used in the testing of electronic products such as single chips, single-board systems, and multi-chip system modules, and has a solid technical foundation in solving interconnection testing.

[0004] Based on the development of DFT technology, interconnection test solutions for complex electronic systems have emerged. The DiaTem test system developed by Temento Systems based on the IEEE 1149.1 standard is specifically designed for comprehensive interconnection testing of complex board-level digital circuit systems. The DiaTem system reserves 4 JTAG interfaces and can perform interconnection testing on multiple scan chain systems at the same time. Compared with foreign countries, China has also conducted research on testing technology for multi-core heterogeneous SIP chips and formed a series of testing methods. For example, Wuxi Zhongwei Tengxin Electronics Co., Ltd. proposed a method for 3D-SIP chip test vector compression, established a 3D-SIP chip testing device and system, invented a multi-layer stacked 3D-SIP chip testing method, and formed related testing software; the 58th Institute of China Electronics Technology Group Corporation proposed a multi-core heterogeneous SIP chip testing and debugging technology based on the JTAG interface; Xidian University proposed a high-speed chip collaborative testing based on multi-core heterogeneous SIP chips; Tianjin University of Science and Technology proposed a special test platform for multi-core heterogeneous SIP chips based on embedded technology; the First Academy of China Aerospace Science and Technology Corporation proposed a multi-core heterogeneous SIP chip testing technology based on JTAG testing technology; and the Xi'an Institute of Aeronautical Computing Technology of Aviation Industry proposed a test method research and test board design for SIPHKY2101A.

[0005] From the above content, it can be seen that the research on JTAG bus test technology abroad is relatively mature, and China has also achieved certain results in JTAG bus controllers. However, these results are mainly applied to board-level systems, and JTAG bus controllers are generally used to complete the test control of the object to be tested. There are few tests on SIP chips in the mass production stage, and from the existing complex SIP microsystem chip test technology, functional testing is generally used for testing. The functional test method must complete the loading of complex functional code streams through the ATE system, and it is difficult to complete the functional verification in collaboration with the ATE system for some complex interfaces (such as EMIF, PCIE, SRIO, etc.); secondly, it is difficult to accurately locate the fault when a functional test fails. It is urgent to study a set of internal interconnection test methods dedicated to the mass production stage of SIP chips.

[0006] When the JTAG bus controller is not designed inside the SIP chip and outside the DIB board, the ATE test system needs to complete the transmission and reception of the JTAG bus test sequence. However, it is relatively complicated to manually write the JTAG bus test vector in the ATE system, and it is urgent to find a new method to generate the JTAG bus test vector. Summary of the invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method for testing the internal interconnection of a SIP chip based on ATE.

[0008] The objective of the present invention is achieved through the following technical solutions:

[0009] A method for testing internal interconnection of a SIP chip based on ATE, the method comprising the following steps:

[0010] Step S1, SVF writes an interconnection test program;

[0011] Step S2, parsing the written SVF program into a pattern capture format file;

[0012] Step S3, processing the vectors in the pattern capture format file that conform to the JTAG bus timing;

[0013] Step S4: transplant the obtained test sequence into the ATE test system, and perform interconnection test according to the specific form of the interconnection model in the SIP chip.

[0014] Furthermore, in step S4, the interconnection model in the SIP chip includes a logic cluster interconnection model, a memory interconnection model, an ATE collaborative interconnection model, a scan chain interconnection model and an ATE direct connection model.

[0015] Furthermore, when a logic cluster interconnect model or a memory interconnect model is adopted, all IO ports of the NBS device are surrounded by scan links, the boundary scan cells connected to the input end of the NBS device are set to input mode, and the boundary scan cells connected to the output port are set to sampling mode, and the EXTEST test instruction is used for testing.

[0016] Furthermore, the specific test steps are as follows:

[0017] Step S411: the instruction register sends an EXTEST test instruction;

[0018] Step S412: sending a cycle of test stimulus to the NBS input port through the boundary scan unit connected to the NBS input port;

[0019] Step S413: the boundary scan unit connected to the NBS output port receives the test response of the first test cycle and analyzes the expected value, while the boundary scan unit at the input port continues to send the test stimulus of the second cycle;

[0020] Repeat step S413 to complete the test.

[0021] Furthermore, in the case of adopting the ATE cooperative interconnection model, the NBS circuit is surrounded by the scan link, the input port is connected to the boundary scan link, and the output port is directly connected to the ATE system.

[0022] Furthermore, the specific test steps are as follows:

[0023] Step S421: the instruction register sends a pre-installed instruction;

[0024] Step S422: sending a first test vector to a boundary scan unit connected to the NBS device through the TDI pin, at which point the first test stimulus has not yet acted on the input port of the NBS device;

[0025] Step S423: the instruction register is loaded with an external test instruction, and the first test stimulus sent by the preloaded instruction acts on the input end of the NBS device;

[0026] Step S424: the ATE receives the first test response of the NBS device and compares it with the expected value, and the TDI port sends the second test stimulus at the same time;

[0027] Repeating step S424 can complete the test vector verification of all cycles of the NBS device.

[0028] Furthermore, in the case of adopting the scan chain interconnection model, half of the network ports are used as input ports and half of the network ports are used as output ports, and the setting of input port data and the reading of output port data are completed through the boundary scan unit.

[0029] Furthermore, the specific test steps are as follows:

[0030] Step S431: the instruction register sends a pre-installed instruction;

[0031] Step S432: Sending a first test vector to the boundary scan unit of the BS1 device through the TDI pin;

[0032] Step S433: the instruction register is loaded with an external test instruction;

[0033] Step S434: the boundary scan unit at the BS2 device end receives the first test response and compares it with the expected value, and at the same time the TDI port sends the second test stimulus;

[0034] Repeat step S434 to complete the test.

[0035] Furthermore, in the case of adopting the ATE direct connection model, the boundary scan unit pins of the BS device are directly connected to the digital channels of the ATE system.

[0036] Furthermore, the specific test steps are as follows:

[0037] Step S441: the instruction register sends a pre-installed instruction;

[0038] Step S442: sending a first test vector to a boundary scan unit connected to the BS device through the TDI pin;

[0039] Step S443: the instruction register is loaded with an external test instruction;

[0040] Step S444: the ATE terminal receives the first test response and compares it with the expected value, and the TDI port sends the second test stimulus at the same time;

[0041] Repeat step S444 to complete the test.

[0042] NBS device stands for Non-Boundary Scan (NBS) device;

[0043] BS device stands for Boundary Scan (BS) device.

[0044] The beneficial effects of the present invention are:

[0045] According to the different interconnection models between SIP chip and ATE system, JTAG bus test timing is generated efficiently and quickly to improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a flow chart of a method for testing internal interconnection of a SIP chip based on ATE according to an embodiment of the present invention;

[0047] Figure 2 is a schematic diagram of an SVF program according to an embodiment of the present invention;

[0048] Figure 3 is a schematic diagram of a PCF file obtained by conversion according to an embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of a test sequence of an embodiment of the present invention;

[0050] Figure 5 It is a schematic diagram of the structure of a logic cluster interconnection model and a memory interconnection model according to an embodiment of the present invention;

[0051] Figure 6 It is a schematic diagram of the structure of the ATE collaborative interconnection model according to an embodiment of the present invention;

[0052] Figure 7 is a schematic diagram of the structure of a scan chain interconnection model according to an embodiment of the present invention;

[0053] Figure 8 It is a structural diagram of an ATE direct connection model according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0055] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0056] Embodiment 1:

[0057] like Figure 1 As shown, the SIP chip internal interconnection testing method based on ATE proposed in the embodiment of the present invention specifically includes the following steps:

[0058] Step S1, SVF writes the interconnection test program. The SVF language is relatively mature in the industrial world and is a high-level description of the JTAG bus operation. Its main application scenarios include program loading of programmable devices and boundary scan test logic description, both of which are based on the JTAG interface to complete the corresponding operations. In the Quartus and ISE development environments, SVF files for describing program design can be generated, and the decoding of SVF files and online program loading are completed through the simulator and JTAG interface. In addition to its application in CPLD and FPGA programmable devices, SVF is also commonly used for board-level JTAG interconnection testing. In JTAG interconnection testing, SVF is mainly used to describe test processes and methods, with good readability and versatility. Table 1 shows the correspondence between the IEEE1149.1 state machine state and SVF instructions. As shown in Table 1, some mandatory test instructions in SVF correspond to the states in the JTAG state machine in IEEE 1149.1. In boundary scan testing, test instruction setting and test data transmission and reception are mainly performed by switching the state of the state machine. SVF statements can describe this process in detail. Therefore, you can write the corresponding SVF test program according to the specific test requirements, and then convert the SVF test file into a test sequence that complies with the JTAG bus, and then complete the test on the ATE test platform.

[0059] IEEE11.49.1 state name SVF Commands Test-Logic-Reset RESET Run-Test / Idle IDLE Select-DR-Scan DRSELECT Capture-DR DRCAPTURE Shift-DR DRSHIFT Exit1-DR DREXIT1 …… …… Exit1-IR IREXIT1 Pause-IR IRPAUSE Exit2-IR IREXIT2 Update-IR IRUPDATE

[0060] Table 1

[0061] Step S2: Parse the written SVF program into a pattern capture format (PCF) file. Figure 2 The SVF program shown in the figure is used as an example to illustrate. First, the first 14 lines of the SVF program are used to control the JTAG state machine to run to the Run-Test / Idle state, preparing for the subsequent instruction register operation and data register operation. According to the state machine switching principle of TAPC, no matter where the initial state of the state machine is, as long as the state control pin TMS sends a high-level signal for 5 or more clock cycles, the state machine will jump to the Run-Test / Idle state. The test vector generated in the PCF file after the first 14 lines of the SVF program are transcoded is Figure 3 The Test Logic Reset section in the figure describes the level status of TCK, TMS, TDI, and TDO in each clock cycle in turn. Then, the IDCODE instruction SIR 6TDI(04)MASK(3f) is sent to the instruction register, where SIR is the instruction register send command, the following 6 represents the instruction register length of the target device, TDI(04) indicates that the IDCODE instruction "000100" is written from the TDI port to the instruction register, and MASK(3f) indicates that the lower 6 bits of the data input from the previous TDI port are valid. The SIR 6TDI(04)MASK(3f) program corresponds to the test vector in the PCF file as follows: Figure 3 In the Loading Device With "IDCODE" Instruction section, after writing the IDCODE instruction to the instruction register, the device identification register is connected to the TDI / TDO link. The SDR32TDI (00000000) SMASK (00000000) TDO (000ae02f) MASK (ffffffff) program is used to complete the reading and verification of the device identification. Among them, SDR is the data register operation instruction. From the BSDL file, we can know that the device identification data is 000ae02f. The TMS port controls the state machine to run to the Shift-DR state and shifts the identification information out of the TDO port at the falling edge of the CLK clock. After completing the ID data reading, the TMS control state machine returns to the Run-Test / Idle state. The corresponding test vector in the PCF file is as follows: Figure 3 The ReadID portion of the

[0062] Step S3: Process the vectors in the Pattern Capture Format (PCF) file that conform to the JTAG bus timing. Figure 3Take the PCF file shown in the figure as an example, and convert the Test Logic Reset part, Loading Device With "IDCODE" Instruction part and ReadID part in the file into test timing. The specific form is as follows Figure 4 shown.

[0063] Step S4, transplant the obtained test sequence into the ATE test system, and perform interconnection test according to the specific form of the interconnection model in the SIP chip. The interconnection model in the SIP chip includes a logic cluster interconnection model, a memory interconnection model, an ATE collaborative interconnection model, a scan chain interconnection model, an ATE direct connection model, and other models.

[0064] like Figure 5 As shown in the figure, in the logic cluster interconnection model, all IO pins of non-boundary scan devices are connected to the boundary scan link. This model is more common inside the SIP chip. The logic cluster interconnection model is very similar to the memory interconnection model. All IO pins of NBS devices are connected to the boundary scan link. Therefore, the above model can also be called the memory interconnection model.

[0065] All IO ports of the NBS device are surrounded by scan links. The boundary scan cells connected to the input end of the NBS device are set to input mode, and the boundary scan cells connected to the output port are set to sampling mode. The EXTEST test instruction is used for testing. The specific test steps are as follows:

[0066] Step S411: the instruction register sends an EXTEST test instruction;

[0067] Step S412: sending a cycle of test stimulus to the NBS input port through the boundary scan unit connected to the NBS input port;

[0068] Step S413: The boundary scan unit connected to the NBS output port receives the test response of the first test cycle and analyzes the expected value, while the boundary scan unit at the input port continues to send the test stimulus of the second cycle.

[0069] Repeating step S413 can complete the test of the logical cluster model.

[0070] like Figure 6 As shown in the figure, in the ATE collaborative interconnection model, the NBS circuit is surrounded by the scan link, the input port is connected to the boundary scan link, and the output port is directly connected to the ATE system. The specific test steps are as follows:

[0071] Step S421: the instruction register sends a pre-installed instruction;

[0072] Step S422: sending a first test vector to a boundary scan unit connected to the NBS device through the TDI pin, at which point the first test stimulus has not yet acted on the input port of the NBS device;

[0073] Step S423: the instruction register is loaded with an external test instruction, and the first test stimulus sent by the preloaded instruction acts on the input end of the NBS device;

[0074] Step S424: the ATE receives the first test response of the NBS device and compares it with the expected value, while the TDI port sends the second test stimulus.

[0075] Repeating step S424 can complete the test vector verification of all cycles of the NBS device.

[0076] like Figure 7 As shown in the figure, the boundary scan units of the two BS devices in the scan chain interconnection model are connected to each other, and all interconnection ports are connected to the boundary scan link. This interconnection model is also very common in SIP chips. The test method for the scan chain interconnection model still continues the test method in the board-level interconnection test system, with half of the network ports as input ports and half of the network ports as output ports. The boundary scan unit is used to complete the setting of input port data and the reading of output port data. The specific test steps are as follows:

[0077] Step S431: the instruction register sends a pre-installed instruction;

[0078] Step S432: Sending a first test vector to the boundary scan unit of the BS1 device through the TDI pin;

[0079] Step S433: the instruction register is loaded with an external test instruction;

[0080] Step S434: The boundary scan unit at the BS2 device end receives the first test response and compares it with the expected value, while the TDI port sends the second test stimulus.

[0081] Repeating step S434 can complete the test of the scan chain interconnection model.

[0082] like Figure 8 As shown, the IO port of the boundary scan device in the ATE direct connection model directly establishes a physical connection with the ATE. For the test of the ATE direct connection model, the ATE system can send high and low levels as the input end, and the boundary scan unit detects the high and low timing sent by the ATE, thereby completing the test of the ATE direct connection network. Conversely, the boundary scan unit is used as the input end to send high and low levels, and the ATE end detects the high and low levels sent by the boundary scan unit. The boundary scan unit pins of the BS device are directly connected to the digital channel of the ATE system. The specific test steps are as follows:

[0083] Step S441: the instruction register sends a pre-installed instruction;

[0084] Step S442: sending a first test vector to a boundary scan unit connected to the BS device through the TDI pin;

[0085] Step S443: the instruction register is loaded with an external test instruction;

[0086] Step S444: The ATE end receives the first test response and compares it with the expected value, and at the same time the TDI port sends the second test stimulus.

[0087] Repeat step S444 to complete the test of the ATE direct connection model.

[0088] The above-mentioned embodiments only express the specific implementation of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A method for testing internal interconnection of a SIP chip based on ATE, characterized in that , the test method comprises the following steps: Step S1, SVF writes an interconnection test program; Step S2, parsing the written SVF program into a pattern capture format file; Step S3, processing the vectors in the pattern capture format file that conform to the JTAG bus timing; Step S4: transplant the obtained test sequence into the ATE test system, and perform interconnection test according to the specific form of the interconnection model in the SIP chip.

2. The ATE-based SIP chip internal interconnection testing method according to claim 1, characterized in that: In step S4, the interconnection model in the SIP chip includes a logic cluster interconnection model, a memory interconnection model, an ATE collaborative interconnection model, a scan chain interconnection model and an ATE direct connection model.

3. The ATE-based SIP chip internal interconnection testing method according to claim 2, characterized in that: When the logic cluster interconnect model or the memory interconnect model is adopted, all IO ports of the NBS device are surrounded by scan links, the boundary scan cells connected to the input end of the NBS device are set to input mode, and the boundary scan cells connected to the output port are set to sampling mode, and the EXTEST test instruction is used for testing.

4. The ATE-based SIP chip internal interconnection testing method according to claim 3, characterized in that: The specific test steps are as follows: Step S411: the instruction register sends an EXTEST test instruction; Step S412: sending a cycle of test stimulus to the NBS input port through the boundary scan unit connected to the NBS input port; Step S413: the boundary scan unit connected to the NBS output port receives the test response of the first test cycle and analyzes the expected value, while the boundary scan unit at the input port continues to send the test stimulus of the second cycle; Repeat step S413 to complete the test.

5. The ATE-based SIP chip internal interconnection testing method according to claim 2, characterized in that: In the case of adopting the ATE collaborative interconnect model, the NBS circuit is surrounded by the scan link, the input port is connected to the boundary scan link, and the output port is directly connected to the ATE system.

6. The ATE-based SIP chip internal interconnection testing method according to claim 5, characterized in that: The specific test steps are as follows: Step S421: the instruction register sends a pre-installed instruction; Step S422: sending a first test vector to a boundary scan unit connected to the NBS device through the TDI pin, at which point the first test stimulus has not yet acted on the input port of the NBS device; Step S423: the instruction register is loaded with an external test instruction, and the first test stimulus sent by the preloaded instruction acts on the input end of the NBS device; Step S424: the ATE receives the first test response of the NBS device and compares it with the expected value, and the TDI port sends the second test stimulus at the same time; Repeating step S424 can complete the test vector verification of all cycles of the NBS device.

7. The ATE-based SIP chip internal interconnection testing method according to claim 2, characterized in that: In the case of adopting the scan chain interconnection model, half of the network ports are used as input ports and half of the network ports are used as output ports, and the setting of input port data and the reading of output port data are completed through the boundary scan unit.

8. The ATE-based SIP chip internal interconnection testing method according to claim 7, characterized in that: The specific test steps are as follows: Step S431: the instruction register sends a pre-installed instruction; Step S432: Sending a first test vector to the boundary scan unit of the BS1 device through the TDI pin; Step S433: the instruction register is loaded with an external test instruction; Step S434: the boundary scan unit at the BS2 device end receives the first test response and compares it with the expected value, and at the same time the TDI port sends the second test stimulus; The test can be completed by repeating step S434.

9. The ATE-based SIP chip internal interconnection testing method according to claim 2, characterized in that: In the case of the ATE direct connection model, the boundary scan cell pins of the BS device are directly connected to the digital channels of the ATE system.

10. The ATE-based SIP chip internal interconnection testing method according to claim 9, characterized in that: The specific test steps are as follows: Step S441: the instruction register sends a pre-installed instruction; Step S442: sending a first test vector to a boundary scan unit connected to the BS device through the TDI pin; Step S443: the instruction register is loaded with an external test instruction; Step S444: the ATE terminal receives the first test response and compares it with the expected value, and the TDI port sends the second test stimulus at the same time; Repeat step S444 to complete the test.

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