A quad-issue risc-v processor microdevice and method of operation thereof

Abstract

The present application relates to a kind of four launch RISC-V processor micro device and its working method, adopt multiple launch structure, be divided into 12~14 level shaping pipeline, can be used as a kind of high-performance pipeline architecture.To solve branch hazard, two-level branch prediction architecture is used in micro device;RISC-V instruction set is expanding and many long instructions appear, therefore, in the decoding stage, it is divided into 3 simple decoders and 1 complex decoder, the latter is responsible for the decoding of long instruction;Micro-operation queue is set subsequently in the decoding stage for the micro operation of instruction from the decoding stage decomposition, micro-operation queue provides 5 micro operations to the subsequent pipeline every cycle, the subsequent pipeline is all to micro-operation queue, but each micro operation has the mark of corresponding instruction for identifying which micro operation belongs to the instruction, prevent the block generated in the decoding stage.Four instructions are also implemented, while ensuring the high frequency of processor, try to improve the IPC of instruction.

Description

Technical Field

[0001] This invention relates to a four-issue processor microdevice operating under the RISC-V instruction set architecture and its operating method, belonging to the field of integrated circuit processor hierarchical design technology. Background Technology

[0002] As the fifth-generation reduced instruction set architecture, the RISC-V instruction set has significant advantages in both modularity and simplification. Modularity is reflected in the grouping of RISC-V instructions, which divides instructions with distinct characteristics into modules. For example, 'I' represents integer instructions, and 'B' represents bit-level manipulation instructions. RISC-V's modular instruction set is rapidly evolving. Simplification is reflected in the regularity of the RISC-V instruction set; the fields of the instruction set have a fixed format, which facilitates subsequent decoding.

[0003] Using a streamlined RISC-V instruction set allows for deeper pipelines to achieve higher clock frequencies, but deeper pipelines also mean higher costs for branch prediction failures. On the other hand, the RISC-V instruction set is evolving towards higher performance. For example, the V extension is used for support vector operations. These instructions are long instructions, with multiple operations within a single instruction. Therefore, deeper decoding is required to identify these specific operations.

[0004] The aforementioned characteristics of RISC-V allow for deeper pipelines and higher clock speeds, but this also presents challenges in designing high-performance RISC-V processors by navigating the risks of deep pipelines and handling long instructions. Summary of the Invention

[0005] This invention proposes a four-issue RISC-V processor microdevice, comprising a 12-14 stage pipeline. The invention describes the processor architecture's operation, pipeline partitioning, organization of key functional components, and implementation methods. It mainly includes the functions of each pipeline stage and their constituent functional components, as well as the four-issue decoding, μOP queue, register renaming, issue queue organization, execution unit organization, and ROB-related content. This invention presents the microdevice's pipeline, functional components, and the organization of key structures and components, providing an implementation method for the four-issue microdevice and the operation of the RISC-V instruction microoperation queue, focusing on microdevice planning without elaborating on the details.

[0006] Terminology Explanation:

[0007] 1. μOP, or Micro Operation, refers to the specific operations decomposed from the RISC-V instructions;

[0008] 2. ROB, or Reorder Buffer, is a buffer that enables instructions to be retired in order.

[0009] 3. Retire, signifying the completion of the instruction's lifecycle;

[0010] 4. Commit means that the command has been executed and the result of the command can be obtained;

[0011] 5. Cache, or buffer, is a high-speed data exchange storage device;

[0012] 6. Cacheline, a cache line, assumed to be 64 bytes here;

[0013] 7. ROB ID, which is the identifier of the instructions recorded in the ROB record;

[0014] 8. IQ, which stands for Instruction Queue;

[0015] 9. Logic registers: namely, the 32 registers x0~x31 defined by RISC-V;

[0016] 10. Physical registers: These are the actual registers that are implemented.

[0017] The technical solution of this invention is as follows:

[0018] A four-issue RISC-V processor microdevice includes a front end and a back end, the front end and the back end including a 12-stage shaping pipeline;

[0019] The front end is used for: instruction fetching, branch prediction, decoding, register renaming, instruction dispatch, and register file access;

[0020] The backend is used for instruction execution and reordering caching to achieve sequential retirement of instructions; instruction execution includes integer, floating-point, and branch instruction execution as well as memory access.

[0021] According to a preferred embodiment of the present invention, the front end includes a fetch stage, a fetch stage, a decode stage, a micro-operation queue allocation stage, a register renaming stage, a transmit stage, and a register access stage, for a total of 7 stages of integer pipeline;

[0022] The backend includes execution level 1 to 4 and retirement level, for a total of 5 levels of integral pipeline.

[0023] According to a preferred embodiment of the present invention, the instruction fetching stage includes a first-level BTB and an ICache. The first-level BTB is used for branch prediction at the first level, and the ICache is used to complete instruction fetching. The instruction fetching bandwidth is 128 bits, enabling the fetching of four instructions.

[0024] The instruction fetching stage includes a pre-decoding unit, a second-level BTB, a BHT, and an instruction packing unit. The pre-decoding unit decodes the instruction type using pre-decoding information to determine whether the instruction accesses the second-level BTB. The second-level BTB uses pre-decoding information and partial PC information to index and obtain the jump address of the branch instruction. The BHT is used to record the history of jump instructions and shifts once per cycle. The instruction packing unit is used to divide the data content from the instruction fetching stage into four instructions.

[0025] The decoding stage is used to decode four instructions from the instruction fetch stage. During instruction decoding, a suitable decoder is selected based on the pre-decoding information. The decoding stage includes four decoders: three simple decoders and one complex decoder. The simple decoders decode no more than two micro-operations, while the complex decoder is used to decode long instructions and decodes more than two micro-operations at a time.

[0026] The micro-operation queue allocation level is used to cache micro-operations decoded from the decoding level, and at the same time allocates five micro-operations to the subsequent pipeline each cycle.

[0027] The register renaming level is used to rename the five micro-operations from the micro-operation queue allocation level, resolving the name association between WAR and WAW in processor instructions. In this level, the instructions are still ordered. After allocating a new physical register number to the instruction, the physical register number and instruction ID are recorded and provided to the ROB. The ROB uses this information to record the instruction order and the instruction write-back register. In addition, after renaming the micro-operations, the register renaming level dispatches them according to the instruction source register and destination register information.

[0028] The launch stage is used to cache micro-operations from the register renaming stage into different launch queues by type;

[0029] The register access level is used to handle access requests from each transmit queue port.

[0030] According to a preferred embodiment of the present invention, the execution level includes an integer execution unit, a branch instruction execution unit, a multiplication unit, a division unit, and a memory access unit;

[0031] The integer execution unit is used to perform addition, logical operations, and shift operations in two's complement form.

[0032] The branch instruction execution unit is used to calculate the jump conditions and the target address of the branch instruction;

[0033] The multiplication unit and division unit are used to perform pipelined multiplication and division operations, respectively;

[0034] The memory access unit is used to process load and store instructions, which are used to access data in storage or write data to storage;

[0035] The integer execution unit returns the execution result in one cycle, the multiplication unit returns the result in three cycles, the division unit returns the result in three to four cycles, and the memory access unit also has its own pipeline stage, including the data cache stage, the data access stage, the address generation stage, and the write-back stage.

[0036] The retirement level includes the Retirement Block (ROB) and a register renaming table maintained jointly with the register renaming level. Each entry in the register renaming table contains the instruction ID, the instruction's destination register number, and a flag indicating whether the instruction has been written back. Writes to the ROB are ordered, following the sequence of instructions from the register renaming level. After the execution level completes all micro-operations of an instruction, the write-back flag is set, indicating that the instruction has been committed. Among the committed instructions, the oldest instruction is retired, and the lifetime of a retired instruction ends. For memory access instructions, a write buffer is also set; data is only actually modified in memory after it is written from the write buffer to the memory.

[0037] The operating method of the aforementioned four-issue RISC-V processor microdevice includes:

[0038] 1) Fetch instruction: Retrieve the instruction from the instruction cache and determine whether the instruction is a branch instruction;

[0039] 2) Branch prediction: If the instruction is a branch instruction, then branch prediction is performed, that is, the jump direction and jump address of the branch instruction are predicted, and the predicted address is fed back, and the value is retrieved again from the predicted address;

[0040] 3) Decoding: After retrieving the correct instruction, the instruction is decoded.

[0041] 4) Micro-operation queue: buffers micro-operations from the decoding stage and passes 5 micro-operations to the subsequent pipeline every cycle;

[0042] 5) Register renaming: Rename the registers of micro-operations from the micro-operation queue, that is, allocate a physical register for each micro-operation;

[0043] 6) Instruction dependency detection: Detects RAW dependency between instructions and micro-operations. If RAW dependency exists, a bypass operation is performed, bypassing the physical registers written by the previous instruction for subsequent instructions to read.

[0044] 7) Instruction issuance queue: After renaming and correlation detection of instructions, the oldest instruction is selected to be issued to the subsequent execution unit;

[0045] 8) Out-of-order processing: The execution port performs out-of-order processing on the emitted commands;

[0046] 9) ROB retired in order: After the instruction is executed, it is written back to the ROB table. The ROB sorts the instructions according to their age and retires the oldest instruction that has been completed.

[0047] 10) Instruction Buffer: The Write Buffer buffers retired LSU instructions.

[0048] According to a preferred embodiment of the present invention, fetching refers to generating the fetch address and maintaining the address of the ICache return instruction block; when the ICache does not generate a pause signal, fetching continues to read instructions in address order; when a refresh occurs, fetching is performed again from the fetch address according to different situations; fetching generates the fetch address according to the priority of various fetch conditions.

[0049] According to a preferred embodiment of the present invention, branch prediction comprises two stages:

[0050] The first stage is: prediction during the first level of instruction fetch, accessing the ICache, with prediction performed in 16-byte instruction blocks; the second stage is: prediction during the second level of instruction fetch, accessing the ICache, with prediction performed based on the specific instruction address.

[0051] According to a preferred embodiment of the present invention, the cache is configured as a set-associative structure and employs the PLRU replacement algorithm.

[0052] According to a preferred embodiment of the present invention, the decoding includes a pre-decoding stage and a decoding stage;

[0053] During the pre-decoding stage, a complete binary tree decomposition method is used to obtain four 16-bit or 32-bit instructions per cycle; the four-issue RISC-V processor microdevice identifies the opcode and func fields corresponding to special instruction types; and branch alias error checking is performed based on the instruction type obtained from the pre-decoding information.

[0054] During the decoding stage, up to four instructions are decoded in parallel at the decoding level, with each instruction being translated into one or more micro-operations.

[0055] According to a preferred embodiment of the present invention, after the instruction is decomposed into micro-operations during the decoding stage, the number of micro-operations is four or more, and a micro-operation queue is set up to buffer the micro-operations from the decoding.

[0056] The micro-operation queue has 4 write ports and 5 read ports. The write ports correspond to 4 decoders, and the read ports read out 5 micro-operations to rename the register level.

[0057] The micro-operation queue has an empty / full flag. If the micro-operation queue is full, a control signal is given to pause the decoder-level decoding.

[0058] The micro-operation queue receives pause signals from the subsequent pipeline;

[0059] According to a preferred embodiment of the present invention, in register renaming, five micro-operations are received from the micro-operation queue and the registers are renamed accordingly.

[0060] According to a preferred embodiment of the present invention, the specific implementation process of instruction dependency detection includes: comparing the destination register of the current instruction with the two source operands of all preceding instructions one by one; if the destination register number of the current instruction is the same as the source register number of a certain instruction, it is determined that there is an instruction dependency between the current instruction and the preceding instruction, and the source register number of the preceding instruction is passed to the destination register number of the current instruction; otherwise, there is no instruction dependency, and the physical register number allocated to the current instruction is passed down.

[0061] According to a preferred embodiment of the present invention, the instruction issuance process in the instruction issuance queue includes: after the instruction is renamed, the instruction is allocated to the corresponding instruction queue; if the source operands of the instruction are already prepared in the register or obtained through bypass, then the instruction is ready to be issued; the oldest instruction is selected from the prepared instructions according to the instruction's ROB ID and issued.

[0062] According to a preferred embodiment of the present invention, the execution port includes an integer execution port, a branch instruction execution port, a memory access instruction execution port, and a floating-point instruction execution port, and each type of execution port includes a corresponding instruction unit.

[0063] According to a preferred embodiment of the present invention, the ROB is retired in sequence, including: waiting for retirement after instruction submission, retiring 4 instructions per cycle, and retiring 4 instructions only after the 4 oldest instructions in the ROB have been submitted.

[0064] According to a preferred embodiment of the present invention, for the LSU write buffer, if the retired instruction is a store instruction, the retired instruction is retired to the write buffer, where the operation of writing the store instruction to memory is performed.

[0065] The beneficial effects of this invention are as follows:

[0066] 1. This invention implements a four-RISC-V instruction issue architecture, which can improve the processor's IPC.

[0067] 2. This invention employs a micro-operation queue mechanism in the RISC-V architecture, effectively preventing decoding-level blocking.

[0068] 3. This invention uses the RISC-V instruction set to implement deep pipelining, while also enabling the issuance of four instructions, thereby maximizing instruction IPC while ensuring a high processor clock frequency. Attached Figure Description

[0069] Figure 1 This is a schematic diagram of the finger taking process of the present invention;

[0070] Figure 2 This is a schematic diagram of branch prediction in this invention;

[0071] Figure 3 This is a schematic diagram of the RAW correlation detection circuit for the fourth micro-operation of the present invention;

[0072] Figure 4 This is a schematic diagram illustrating a specific implementation method of the working method of the four-issue RISC-V processor microdevice of the present invention. Detailed Implementation

[0073] The present invention will be further defined below with reference to the accompanying drawings and embodiments, but is not limited thereto.

[0074] Example 1

[0075] A four-issue RISC-V processor microdevice includes a front end and a back end, the front end and the back end including a 12-stage shaping pipeline;

[0076] The front end is used for: instruction fetching, branch prediction, decoding, register renaming, instruction dispatch, and register file access;

[0077] The backend is used for instruction execution and reordering caching to achieve sequential retirement of instructions; instruction execution includes integer, floating-point, and branch instruction execution as well as memory access.

[0078] Example 2

[0079] The difference between the four-issue RISC-V processor microdevice described in Embodiment 1 and the one described in Embodiment 1 is that:

[0080] The front end includes a 7-stage integer pipeline: instruction fetch stage 1, instruction fetch stage 2, decode stage, micro-operation queue allocation stage, register renaming stage, issue stage, and register access stage.

[0081] The backend includes execution level 1 to 4 and retirement level, for a total of 5 levels of integral pipeline.

[0082] The instruction fetch level includes a first-level BTB (Branch Target Buffer) and an ICache. The first-level BTB is used for branch prediction at the first level, and the ICache is used to complete instruction fetching. The instruction fetch bandwidth is 128 bits, which can fetch four instructions.

[0083] The instruction fetch level 2 includes a pre-decoding unit, a level 2 BTB, a BHT (Branch History Table), and an instruction packing unit. The pre-decoding unit decodes the instruction type using pre-decoding information to determine whether the instruction accesses the level 2 BTB. The level 2 BTB uses pre-decoding information and part of the PC information to index and obtain the jump address of the branch instruction. The BHT is used to record the history of jump instructions and shifts once per cycle. The instruction packing unit is used to divide the data content from the instruction fetch level 1 into four instructions.

[0084] The decoding stage is used to decode the four instructions from the fetch stage. During instruction decoding, an appropriate decoder is selected based on the pre-decoding information. The decoding stage includes four decoders: three simple decoders and one complex decoder. The simple decoders decode no more than two micro-operations, while the complex decoder is used to decode long instructions and decodes more than two micro-operations at a time.

[0085] The micro-operation queue allocation level is used to buffer the micro-operations decoded from the decoder. Although the decoder decodes four instructions, it usually needs to fully decode all four instructions, resulting in more than four micro-operations. Therefore, a micro-operation queue level is needed to temporarily store the micro-operations from the decoder to ensure that the decoder will not be blocked in the current cycle. At the same time, five micro-operations are allocated to the subsequent pipeline each cycle.

[0086] The register renaming level is used to rename the five micro-operations from the micro-operation queue allocation level, resolving the WAR and WAW name dependencies in processor instructions. Instructions are still ordered at this level. After allocating a new physical register number to an instruction, the physical register number and instruction ID are recorded and provided to the ROB. The ROB uses this information to record the instruction order and the instruction write-back register. In addition, after renaming the micro-operations, the register renaming level dispatches them based on the instruction source register and destination register information.

[0087] The issue stage is used to cache micro-operations from the register renaming stage into different issue queues, such as integer instruction queues, branch instruction queues, and floating-point instruction queues. Each queue corresponds to a specific execution port in the back-end pipeline. The issue stage needs to select the oldest instruction from the issue queue and issue it. An age matrix circuit is designed to issue the oldest instruction. After the instruction is issued, it enters the out-of-order execution stage.

[0088] The register access level is used to handle access requests from each transmit queue port. After each transmit queue transmits an instruction, it enters the register access level to retrieve the source operand in the absence of data feedforward. After retrieving the source operand, it is sent to the execution level for execution.

[0089] The backend refers to the out-of-order execution kernel, which includes the integer execution unit, branch instruction execution unit, floating-point execution unit, memory access unit, and ROB retirement unit. The floating-point unit has its own register file and pipeline, which is no different from the usual floating-point arithmetic pipeline.

[0090] The execution level includes an integer execution unit, a branch instruction execution unit, a multiplication unit, a division unit, and a memory access unit. The integer execution unit performs addition, logical operations, and shift operations using two's complement. The branch instruction execution unit calculates the jump conditions and target addresses for branch instructions. The multiplication and division units perform pipelined multiplication and division operations, respectively. The memory access unit processes load and store instructions to access or write data to memory.

[0091] The integer execution unit returns the execution result in one cycle, the multiplication unit returns the result in three cycles, the division unit returns the result in three to four cycles, and the memory access unit also has its own pipeline stage, including the data cache stage, the data access stage, the address generation stage, and the write-back stage.

[0092] The retirement level includes the Retirement Block (ROB) and a register renaming table maintained jointly with the register renaming level. Each entry in the register renaming table contains the instruction ID, the instruction's destination register number, and a flag indicating whether the instruction has been written back. Writes to the ROB are ordered, following the sequence of instructions from the register renaming level. After the execution level completes the execution of all micro-operations of an instruction, the write-back flag is set, indicating that the instruction has been committed. The oldest instruction among the committed instructions is retired, and the lifecycle of a retired instruction ends. For memory access instructions, a write buffer is also set up; data is only actually modified in memory after it is written from the write buffer to memory.

[0093] The microdevice of this invention can achieve a CoreMark score of 6.0 or higher.

[0094] Example 3

[0095] The operating method of a four-issue RISC-V processor microdevice according to Embodiment 2 is as follows: Figure 4 As shown, it includes:

[0096] 1) Instruction fetch: The instruction fetch unit retrieves a value from the instruction cache and determines whether the instruction is a branch instruction;

[0097] Instruction fetching refers to generating the fetch address and maintaining the address of the instruction block returned by the ICache. When the ICache does not generate a pause signal, instruction fetching continues to read instructions in address order. When a flush occurs, instruction fetching is restarted from the fetch address depending on the different situations. Instruction fetching generates the fetch address based on the priority of various conditions for fetching instructions.

[0098] Examples of the seven conditions for generating an instruction fetch address are as follows:

[0099] 1) No jump occurs, increments by 16 each time;

[0100] 2) This includes two scenarios: 1. Incorrect branch alias. 2. The first-level prediction did not predict the branch instruction, but after decoding, it was found to be an unconditional jump instruction;

[0101] 3) Second-level BTB prediction jump;

[0102] 4) When load is executed earlier, the physical address of store is the same as that of store executed later. Load retrieved the old data, which should be the data of the store instruction, i.e. there is RAW relatedness.

[0103] 5) The execution unit determines that the instruction prediction result of the front-end pipeline is incorrect;

[0104] 6) First-level prediction BTB predicts the jump address;

[0105] 7) This includes three scenarios: First, when the ALU executes a CSR instruction that changes the CPU state, it needs to re-fetch the instructions following the CSR. Second, interrupt exception handling. Third, a change in RISC-V mode.

[0106] These conditions have priorities. In RTL implementations, an if…else if…else… structure can be considered. Conditions 2) through 7) all require fetching instructions from new addresses and will trigger flush pipeline operations. If none of these conditions are met, the address is incremented by 16 bytes each time, i.e., condition 1. Each instruction fetch address is bounded by 16-byte boundaries because cache lines are multiples of 16 bytes, and page sizes are 4KB. This avoids issues related to crossing cache lines, as crossing cache lines or pages would require fetching instructions twice.

[0107] The read / write process of the address cache is as follows: Figure 1 As shown, if any of the above refreshes occur during the instruction fetch process, the address cache is cleared. When conditions 4) and 5) are both valid, the ROB IDs of the two conditions are compared, and the condition with the older ROB ID is selected.

[0108] 2) Branch prediction: If the instruction is a branch instruction, then branch prediction is performed, that is, the jump direction and jump address of the branch instruction are predicted, and the predicted address is fed back to the value fetching unit, and the value is fetched again from the predicted address;

[0109] like Figure 2As shown, branch prediction includes two stages:

[0110] The first stage is: prediction during the first level of instruction fetch, accessing the ICache, with prediction performed in 16-byte instruction blocks; the second stage is: prediction during the second level of instruction fetch, accessing the ICache, with prediction performed based on the specific instruction address.

[0111] The results of the second stage have higher priority than those of the first stage. Jump prediction is divided into jump direction prediction and jump address prediction. Jump direction prediction uses the BHT, and jump address prediction uses the BTB. The first-stage branch prediction uses a portion of the PC address to index the first-level BTB. The second-stage branch prediction architecture is shown in Figure 2. The instruction address and the Global History Register (GHR) are XORed to index the BHT, and the instruction address is used to index the second-level BTB to obtain the jump address. The jump address and jump direction information are encoded and output to subsequent pipeline stages.

[0112] The cache unit comprises ICache and ITLB. The cache unit mitigates the speed difference between the core and external memory. Based on the principle of locality of reference, ICache and ITLB store recently used instruction blocks, enabling the core to fetch instructions quickly. The cache is set-associative and uses the PLRU (pseudo-LRU) replacement algorithm. The cache size is set according to actual usage.

[0113] 3) Decoding: After retrieving the correct instruction through the first two steps, the instruction is decoded; a maximum of four instructions can be decoded; decoding includes a pre-decoding stage and a decoding stage;

[0114] The pre-decoding section needs to handle the following issues: 1) Since RISC-V has 16-bit and 32-bit instructions, the length of each instruction and the case of crossing 16-byte instruction block boundaries need to be considered. Four instructions are fetched each clock cycle, and the length and address of each instruction are calculated. 2) The pre-decoding obtains the instruction type and special instruction types, such as CSR instructions, fence instructions, and long instructions in the RISC-V extended instruction set. 3) Since the first-level BTB index uses part of the PC, instruction conflicts may occur. After the pre-decoding knows the instruction type, branch alias error checking is required.

[0115] In the pre-decoding stage, for problem 1), a complete binary tree decomposition method can be used to obtain four 16-bit or 32-bit instructions per cycle; for problem 2), only the four-issue RISC-V processor microdevice needs to identify the opcode and func fields corresponding to the special instruction type; for problem 3), branch alias error checking can be performed based on the instruction type of the obtained pre-decoding information.

[0116] During the decoding stage, up to four instructions are decoded in parallel at the decoder level, with each instruction translated into one or more micro-operations. A simple decoder can decode one or two micro-operations, while a long instruction decoder can decompose one or two or more micro-operations. Therefore, based on the pre-decoding information, the four instructions can be scheduled to different decoders.

[0117] 4) Micro-operation queue: buffers micro-operations from the decoding stage and passes 5 micro-operations to the subsequent pipeline every cycle;

[0118] Micro-operations define the attributes and operations of instruction execution. RISC-V instructions can be decomposed into one or more micro-operations, depending mainly on the complexity of the instructions and the architecture design. In the architecture design, the definition of each micro-operation should be given so that the decoder can decompose it. Each micro-operation is the smallest operation that can be executed in the subsequent execution level.

[0119] After the decoding stage breaks down instructions into micro-operations, if there are four or more micro-operations, a micro-operation queue is set up to buffer the micro-operations from the decoding stage. For example, here the micro-operation queue is set to a depth of 64 items to buffer 64 micro-operations from the decoding stage. The micro-operation queue has the following characteristics:

[0120] The micro-operation queue has 4 write ports and 5 read ports. The write ports correspond to 4 decoders, and the read ports read out 5 micro-operations to rename the register level.

[0121] The micro-operation queue has an empty / full flag. If the micro-operation queue is full, a control signal is given to pause the decoder-level decoding.

[0122] The micro-operation queue receives pause signals from the subsequent pipeline; for example, when the subsequent pipeline is under resource pressure, a pause signal should be given to the micro-operation queue; when an anomaly or a guess error occurs in the subsequent pipeline, the micro-operations corresponding to the instruction whose position was updated compared to the instruction that caused the error should be cleared.

[0123] The micro-operation queue is essentially a multi-port synchronous FIFO structure, except that read and write control needs to consider more feedback signals. The micro-operation queue buffers micro-operations from the decoding level, and releases 5 micro-operations per cycle for subsequent register renaming and transmit phases.

[0124] 5) Register renaming: Rename the registers of micro-operations from the micro-operation queue, that is, allocate a physical register for each micro-operation;

[0125] In register renaming, five micro-operations are received from the micro-operation queue, and these micro-operations are then used to rename the registers. Register renaming is the first step in implementing out-of-order execution in the processor and is a common technique, which will not be described in detail here.

[0126] Register renaming resolves name dependencies between instructions, including both WAR and RAW cases, both of which can be solved by renaming registers. Name dependencies are caused by insufficient register resources. Therefore, it's necessary to allocate physical registers for the destination register of the instructions. By allocating new physical registers, the results of instructions to be executed earlier can be stored, eliminating the need to wait for related instructions to complete before starting subsequent instructions.

[0127] There is also a true dependency between instructions called RAW dependency. In this case, the second instruction must wait until the first instruction completes and obtains its result before it can fetch the result of the first instruction. For example, in the instruction fetch phase, whether a conditional branch instruction needs to jump would severely impact performance if the execution unit only knew whether a jump was necessary. Therefore, by predicting branch instructions to determine whether a jump is needed, subsequent instructions can "predict" the result in advance. This is a probabilistic way to resolve RAW hazards.

[0128] If there are RAW hazards between instructions, a data feedforward approach is needed to ensure that the second instruction receives the result of the first instruction immediately. This requires circuitry to detect these RAW data dependencies between instructions. This dependency can be handled at the register renaming level. Taking the fourth micro-operation as an example: it needs to determine if there is a RAW dependency with the preceding three instructions. RISC-V instructions have two source registers and one destination register. Therefore, the two source registers of the fourth instruction need to be compared with the physical register numbers allocated to the logical registers of the preceding three instructions. This allows the source register of the fourth instruction to be pointed to the physical register allocated to the logical register of the instruction with which it is related. This dependency detection circuitry is as follows: Figure 3 As shown.

[0129] 6) Instruction dependency detection: Detects RAW (Read After Write) dependency between instructions and micro-operations. If RAW dependency exists, a bypass operation is performed, bypassing the physical register written by the previous instruction for subsequent instructions to read.

[0130] The specific implementation process of instruction dependency detection includes: comparing the destination register of the current instruction with the two source operands of all preceding instructions one by one; if the destination register number of the current instruction is the same as the source register number of a certain instruction, it is determined that there is an instruction dependency between the current instruction and the preceding instruction, and the source register number of the preceding instruction is passed to the destination register number of the current instruction; otherwise, there is no instruction dependency, and the physical register number allocated to the current instruction is passed down.

[0131] 7) Instruction issue queue: After renaming and correlation detection of instructions, the oldest instruction is selected to be issued to the subsequent execution unit; there are a total of 8 instruction issue queues: AIQ0 and AIQ1 are cache queues for integer instructions, BIQ is the branch instruction queue, LSIQ (2) and SDIQ are memory access instruction queues, and VIQ0 and VIQ1 are floating-point instruction queues.

[0132] In the instruction issue queue, the instruction issue process includes: after the instruction is renamed, the instruction is assigned to the corresponding instruction queue; if the source operands of the instruction are already prepared in the register or obtained through bypass, then the instruction is ready to be issued; from the prepared instructions, the oldest instruction is selected according to the instruction's ROB ID for issuance.

[0133] After register renaming is completed, instructions need to be dispatched to the corresponding instruction queue. During instruction dispatch, the allocation is based on the resources of the instruction queue, reorder cache, and other queues. Dispatched instructions need to be assigned corresponding ROBID flags, which are released upon instruction commit. After micro-operations are decoded, each micro-operation has a corresponding instruction tag. The allocated ROB resources are distributed according to the instruction; that is, micro-operations of the same instruction are recorded in the same ROB entry.

[0134] After out-of-order instruction execution is complete, the instruction needs to be submitted as needed based on the ROB ID. If the branch instruction execution unit detects a prediction error, the pipeline needs to be refreshed based on the ROB ID. The ROB ID allocation principle is to allocate sequentially. After each instruction is assigned an ID, the ID is incremented by 1 to become the ID of the next instruction to be assigned.

[0135] Depending on the type of execution unit corresponding to the instruction, the instruction queue is configured with ALU-type instruction reservation queues, LSU-type instruction queues, and floating-point instruction queues, etc. Each instruction queue has its own inherent depth and a corresponding age matrix, and each instruction queue corresponds to the port of the corresponding execution unit. As long as the execution unit has idle time or there are older instructions in the current instruction queue that have not yet been issued, the oldest instruction in the current instruction queue will be issued to the corresponding port according to the age matrix.

[0136] For example, if an instruction queue has a depth of 8 items, then the age matrix is ​​an 8×8 matrix. Each row of the year-zero matrix represents the position in the instruction queue, and the columns represent the age relationship with its items. That is, each row corresponds to the age relationship with the other 7 rows. When the processor starts up, the age matrix is ​​reset to 0. Thereafter, whenever a new instruction is allocated to the instruction queue, the new row of the year-zero matrix is ​​updated with the valid instruction vectors already in the instruction queue.

[0137] The instruction validity vector indicates whether the instructions in this line are ready, and satisfies the following conditions:

[0138] 1) An instruction is written to the current item in the instruction queue;

[0139] 2) The source operand of this instruction is ready (either via feedforward or it is already ready to access the register);

[0140] After an instruction is issued, the physical register is accessed based on the source register number in the instruction to obtain the operation data. This data is then sent to the corresponding execution port for execution. If the source operand in the instruction comes from a data feedforward, then register access is not required.

[0141] 8) Out-of-order processing: The execution port performs out-of-order processing on the emitted commands;

[0142] The execution ports include integer execution ports (Port0 and Port1), branch instruction execution ports (Port2), memory access instruction execution ports (Port3-Port5), and floating-point instruction execution ports (Port6 and Port7). Each type of execution port includes the corresponding instruction unit.

[0143] After an instruction is issued and its operands are obtained from the register file or data bypass, they are sent to the execution unit, which is a general-purpose unit. After the execution unit returns the result after 1-4 cycles, it is written to the ROB entry of the instruction corresponding to the micro-operation, which is called the micro-operation commit. When all micro-operations of an instruction are committed, it is called the instruction commit.

[0144] 9) ROB retired in order: After the instruction is executed, it is written back to the ROB table. The ROB sorts the instructions according to their age and retires the oldest instruction that has been completed.

[0145] ROBs are retired sequentially, including: instructions waiting to be retired after being committed, and 4 instructions being retired each cycle. Only when the 4 oldest instructions in the ROB have been committed and no exceptions occur (no execution exceptions or interruptions occur), are the 4 instructions retired.

[0146] 10) Instruction Buffer: The Write Buffer buffers retired LSU instructions (i.e., load and store instructions).

[0147] The instruction cache, specifically the write buffer for LSU, is used to retire retired instructions that are store instructions. Since store instructions take many clock cycles to write data to memory, typically hundreds of times the number of register access cycles, retired instructions are moved to the write buffer where the store instruction write operation to memory is implemented.

Claims

1. A quad-issue RISC-V processor microdevice, comprising: The processor comprises a front end and a back end, and the front end and the back end comprise a 12-stage integer pipeline; The front end is used for instruction fetching, branch prediction, decoding, register renaming, instruction dispatching and register bank access; The back end is used for instruction execution and reorder buffer, and realizes in-order retirement of instructions; the instruction execution comprises integer, floating point and branch instruction execution and memory access; The front end comprises a first-stage instruction fetching stage, a second-stage instruction fetching stage, a decoding stage, a micro-operation queue allocation stage, a register renaming stage, an emission stage and a register access stage, and the front end comprises a 7-stage integer pipeline; the back end comprises 1-4 execution stages and a retirement stage, and the back end comprises a 5-stage integer pipeline; The first-stage instruction fetching stage comprises a first-stage BTB and an ICache, the first-stage BTB is used for first-stage branch prediction, and the ICache is used for completing instruction fetching; the instruction fetching bandwidth is 128 bits, and four instructions are fetched; The second-stage instruction fetching stage comprises a pre-decoding unit, a second-stage BTB, a BHT and an instruction packing unit; the pre-decoding unit decodes the type of an instruction through pre-decoding information, and is used for judging whether the instruction accesses the second-stage BTB; the second-stage BTB is indexed by the pre-decoding information and part of PC information, and obtains the jump address of a branch instruction; the BHT is used for recording the history of a jump instruction, and is shifted once per cycle; and the instruction packing unit is used for dividing the data content from the first-stage instruction fetching stage into four instructions; The decoding stage is used for decoding four instructions from the second-stage instruction fetching stage; when decoding the instructions, a suitable decoder is selected according to the pre-decoding information; the decoding stage comprises four decoders, wherein three are simple decoders, and one is a complex decoder; the simple decoders decode no more than two micro-operations; and the complex decoder is used for decoding a long instruction, and decodes more than two micro-operations at a time; The micro-operation queue allocation stage is used for buffering the micro-operations decoded from the decoding stage, and allocates five micro-operations for the subsequent pipeline per cycle; The register renaming stage is used for performing register renaming on the five micro-operations from the micro-operation queue allocation stage, and solves WAR and WAW name dependencies in processor instructions; in this stage, the instructions are still in order; after a new physical register number is allocated to the instructions, the physical register number and the instruction ID are recorded and provided to the ROB, and the ROB records the order of the instructions and the write-back registers of the instructions by using the information; in addition, the register renaming stage dispatches the micro-operations according to the source register and destination register information of the instructions after the micro-operations are renamed; The emission stage is used for classifying the micro-operations from the register renaming stage into different emission queues; The register access stage is used for processing access requests from the ports of the emission queues.

2. The quad-issue RISC-V processor microdevice of claim 1, wherein, The execution stage comprises an integer execution unit, a branch instruction execution unit, a multiplication unit, a division unit and a memory access unit; The integer execution unit is used for executing integer complement addition, logical operation and shift operation; The branch instruction execution unit is used for calculating the jump condition and the target address of a branch instruction; The multiplication unit and the division unit are respectively used for completing pipeline multiplication and division operation. The memory access unit is used for processing load and store instructions, and is used for accessing data in the storage or writing data into the storage; The integer execution unit returns the execution result in one cycle, the multiplication unit returns the result in three cycles, the division unit returns the result in three to four cycles, and the memory access unit also has its own pipeline, including a data cache stage, a data access stage, an address generation stage, and a write-back stage; The retirement stage includes a ROB and a register renaming table maintained jointly with the register renaming stage, each table entry of the register renaming table including an instruction ID, an instruction destination register number, and a flag indicating whether the instruction is write-back; the writing of the ROB is in order, and the writing is in order according to the order of the instructions from the register renaming stage; when the execution stage completes the execution of all micro-operations of an instruction, the write-back flag is set, indicating that the instruction has been submitted; the oldest instruction is selected from the submitted instructions for retirement, and the life cycle of the retired instruction ends; for memory type instructions, a write buffer is also provided, and the data is written to the memory from the write buffer before the data in the memory is actually changed.

3. The method of operating a quad-issue RISC-V processor microdevice of claim 1 or 2, wherein, It includes: 1) instruction fetch: fetching from the instruction cache and determining whether the instruction is a branch instruction; 2) branch prediction: if the instruction is a branch instruction, branch prediction is performed, that is, the jump direction and jump address of the branch instruction are predicted, and the predicted address is fed back to fetch from the predicted address; 3) decoding: after the correct instruction is fetched, the instruction is decoded; 4) micro-operation queue: buffering micro-operations from the decoding stage and transmitting 5 micro-operations to the subsequent pipeline every cycle; 5) register renaming: performing register renaming on the micro-operations from the micro-operation queue, that is, assigning physical registers to each micro-operation; 6) instruction dependency detection: detecting RAW dependencies between instructions and micro-operations, and if RAW dependencies exist, performing bypass operations to bypass the physical registers written by the previous instructions to the subsequent instructions; 7) instruction issue queue: selecting the oldest instruction from the instructions that have completed renaming and dependency detection and issuing the instruction to the subsequent execution unit; 8) out-of-order processing: the execution port performs out-of-order processing on the issued instructions; 9) ROB in-order retirement: after the instruction is executed, the table entry is written back to the ROB, and the ROB is retired according to the new and old order of the instructions and the oldest instruction that has been completed; 10) instruction cache: the write buffer buffers the retired LSU instructions.

4. The method of Claim 3, wherein, Instruction fetch is to generate a fetch address and maintain the address of the ICache returning an instruction block; when the ICache does not generate a pause signal, the instruction fetch reads instructions in address order; when flushing occurs, the instruction fetch takes instructions from the fetch address according to different conditions; the instruction fetch generates a fetch address according to the priority of various conditions of the fetched instruction.

5. The method of Claim 3, wherein, Branch prediction includes two stages: The first stage is a prediction in a first-stage instruction fetch accessing the ICache, and the first stage predicts in a 16-byte instruction block; the second stage is a prediction in a second-stage instruction fetch accessing the ICache, and the second stage predicts according to a specific instruction address.

6. The method of Claim 3, wherein: The decoding includes a pre-decoding stage and a decoding stage; In the pre-decoding stage, a complete binary tree decomposition method is adopted, and 4 instructions of 16 bits or 32 bits are obtained per cycle; the four-emission RISC-V processor micro device identifies the opcode and func field corresponding to the special instruction type; and branch aliasing error checking is performed according to the instruction type of the obtained pre-decoding information; In the decoding stage, at most 4 instructions are decoded in parallel in the decoding stage, and each instruction is translated into one or more micro-operations.

7. The method of Claim 3, wherein: After the instructions are decomposed into micro-operations in the decoding stage, the number of micro-operations is four or more, a micro-operation queue is set to buffer the micro-operations from the decoding; The micro-operation queue has 4 write ports and 5 read ports, the write ports correspond to 4 decoders, and the read ports read out 5 micro-operations to the register renaming stage; The micro-operation queue has an empty-full flag, and if the micro-operation queue is full, a control signal is given to suspend the decoding of the decoding stage; The micro-operation queue receives a pause signal from the subsequent pipeline.

8. The method of any of claims 3-7, wherein the four-transmit RISC-V processor microdevice is a RISC-V processor microdevice. The specific implementation process of the instruction dependency detection includes: comparing the destination register of the current instruction with the two source operands of all previous instructions one by one; if the destination register number of the current instruction is the same as the source register number of a certain instruction, it is determined that there is an instruction dependency between the current instruction and the previous instruction, and the source register number of the previous instruction is passed to the destination register number of the current instruction; otherwise, there is no instruction dependency, and the physical register number allocated to the current instruction is passed down; In the instruction emission queue, the instruction emission process includes: after the instruction renaming is completed, the instruction is allocated to the corresponding instruction queue; if the source operands of the instruction are all ready in the register or obtained through bypassing, the instruction is ready to be emitted; the oldest instruction is selected from the instructions that are ready to be emitted according to the ROB ID of the instruction for emission; The execution port includes a shaping execution port, a branch instruction execution port, a memory instruction execution port and a floating point instruction execution port, and each type of execution port includes a corresponding instruction unit.

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