Flash memory device and method of manufacturing the same

Abstract

The application provides a flash memory device and a preparation method thereof, and is applied to the technical field of semiconductors. In the preparation method of the flash memory device, a heat treatment process is added after the process step of forming a gate sidewall on the sidewall of a word line, so that the conductive material with a partial thickness of the top surface of the word line close to the gate sidewall is converted into insulating material, thereby avoiding the short circuit between the metal silicide layer formed on other parts of the top surface of the word line and the metal plug of the split-gate flash memory, and causing the failure of the split-gate flash memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a flash memory device and a preparation method thereof. BACKGROUND

[0002] As a kind of non-volatile storage, flash memory device has the characteristics of convenience, high storage density and strong reliability, and is widely used. The structure of the existing flash memory device is usually divided into split-gate structure, stacked-gate structure or combination thereof, wherein the split-gate flash memory device has the characteristics of high programming efficiency.

[0003] However, in the prior art, due to the height difference between the active region ACT of the split-gate flash memory and the shallow trench isolation structure STI, as shown in Figure 1 , after the etching step of forming the gate spacer, there is a thin layer of word line polysilicon height above the part near the gate spacer of the split-gate flash memory, as shown in Figure 1 . The existence of this phenomenon will cause the metal silicide above the final word line to be relatively thick and easy to shrink between the contact, and cause short circuit between them, thereby causing the failure of the split-gate flash memory, as shown in Figure 2 . SUMMARY

[0004] The purpose of the present application is to provide a flash memory device and a preparation method thereof, to solve the problem of short circuit between the metal silicide above the word line and the metal plug of the split-gate flash memory caused by the height difference between the active region and the shallow trench isolation structure and the over-etching process in the process of forming the gate spacer in the existing split-gate flash memory, thereby causing the failure of the split-gate flash memory.

[0005] In the first aspect, to solve the above technical problem, the present application provides a preparation method of a flash memory device, which can specifically include the following steps:

[0006] A semiconductor substrate is provided, and a trench isolation structure for defining the active region of the flash memory device is formed in the semiconductor substrate. A storage structure, a word line located on both sides of the storage structure and a gate spacer located on both sides of the word line are formed on the surface of the semiconductor substrate corresponding to the active region. The top surface of the trench isolation structure is higher than the top surface of the semiconductor substrate, and the material of the word line is conductive material.

[0007] A heat treatment process is performed on the semiconductor substrate containing the gate spacer to convert the conductive material with a part of the thickness of the top surface of the word line near the gate spacer into insulating material.

[0008] Further, the storage structure mentioned in the present application can be a double storage bit structure of shared source line.

[0009] Further, the conductive material of the word line can be polysilicon or doped polysilicon.

[0010] Further, the heat treatment process performed on the semiconductor substrate containing the gate side wall can include a rapid thermal oxidation process (RTO).

[0011] Further, the process parameters of the rapid thermal oxidation process can include: the temperature range can be 905-1105℃, and the heating time range can be 15-25s.

[0012] Further, the etching step of forming the gate side wall on the surface of the semiconductor substrate can further include an over-etching process step.

[0013] Further, after converting the conductive material of the part of the thickness of the top surface of the word line close to the gate side wall into insulating material, the preparation method can further include: performing a silicidation process on the semiconductor substrate to form a metal silicide layer on the top surface of the word line.

[0014] Further, after converting the conductive material of the part of the thickness of the top surface of the word line into insulating material, the preparation method can further include:

[0015] forming an interlayer dielectric layer, which buries the storage structure and the word line with the top surface converted into insulating material;

[0016] etching the interlayer dielectric layer to form a contact hole exposing the surface of the semiconductor substrate on both sides of the gate side wall, and filling the contact hole with conductive metal to form a conductive plug.

[0017] Further, the thickness of the metal material deposited during the silicidation process of forming the metal silicide layer can be:

[0018] In a second aspect, based on the same inventive concept as the preparation method of the flash memory device mentioned above, the present application also provides a flash memory device, which can be prepared by the preparation method of the flash memory device mentioned above, wherein the storage structure of the flash memory device is a double storage bit structure of shared source line with insulating material covering the top surface of the word line.

[0019] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0020] In the method for manufacturing the flash memory device, a heat treatment process is added after the process step of forming the gate spacer on the sidewall of the word line, so that the conductive material near the partial thickness of the top surface of the word line is converted into insulating material, thereby avoiding the short circuit between the metal silicide layer formed on the other part of the top surface of the word line and the metal plug of the split-gate flash memory, and causing the failure of the split-gate flash memory. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a structure diagram of a split-gate flash memory formed by using the semiconductor process method of the prior art;

[0022] Figure 2 is a structure diagram of the split-gate flash memory formed by using the semiconductor process method of the prior art, which has the problem of short circuit between the metal silicide above the word line and the metal plug of the split-gate flash memory;

[0023] Figure 3 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] As described in the background, in the prior art, due to the height difference between the active region ACT and the shallow trench isolation structure STI of the split-gate flash memory, as shown in Figure 1 , after the etching step of forming the gate spacer (there is also OE in this process), there is a thin layer of word line polysilicon on the part of the word line near the gate spacer, as shown in Figure 2 . Among them, Figure 1 is a structure diagram of a split-gate flash memory formed by using the semiconductor process method of the prior art; Figure 2 is a structure diagram of the split-gate flash memory formed by using the semiconductor process method of the prior art, which has the problem of short circuit between the metal silicide above the word line and the metal plug of the split-gate flash memory. The existence of this phenomenon will cause the metal silicide above the final word line to be relatively thick at this position and easy to shrink into the distance between the CONTACT, and cause short circuit between them, thereby causing the failure of the split-gate flash memory.

[0025] Therefore, the present application provides a flash memory device and a method for manufacturing the same, to solve the problem of short circuit between the metal silicide above the word line and the metal plug of the split-gate flash memory, which is caused by the height difference between the active region and the shallow trench isolation structure of the split-gate flash memory and the over-etching process in the formation process of the gate spacer, and further causes the failure of the split-gate flash memory.

[0026] The flash memory device and the method for manufacturing the same according to the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the drawings are very simplified and are not drawn to scale, and are only used to facilitate and clarify the description of the embodiments of the present application. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in other ways not specifically described herein, and therefore the present application is not limited to the specific embodiments disclosed below.

[0027] As shown in the present application and claims, unless the context clearly indicates otherwise, the words "one", "an", "a", and / or "the" do not mean "only one", but can include a plurality or "one or more" unless the context clearly indicates otherwise. Generally, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements. In the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is partially enlarged without the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions including length, width and depth should be included in actual manufacturing.

[0028] With reference to the drawings, the present application provides a flash memory device and a method for manufacturing the same. Figure 3 , Figure 3 The flowchart of the method for manufacturing the flash memory device according to an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the method for manufacturing the flash memory device according to the present application can specifically include the following steps: Figure 3

[0029] ​Step S100: A semiconductor substrate is provided, in which a trench isolation structure STI is formed to define the active region ACT of a flash memory device. A memory structure, word lines located on both sides of the memory structure, and gate sidewalls located on both sides of the word lines are formed on the surface of the semiconductor substrate corresponding to the active region. The top surface of the trench isolation structure is higher than the top surface of the semiconductor substrate, and the word lines are made of a conductive material. The semiconductor substrate serves as a platform for subsequent processes to generate the flash memory device. The semiconductor substrate can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate. For example, in this embodiment, the semiconductor substrate is a silicon wafer. The word line material can be polycrystalline silicon or doped polycrystalline silicon. The gate sidewall is also the word line sidewall, and the material of the sidewall is a single-layer film structure of silicon dioxide, which can also be a multi-layer film structure of ONO stacking structure. This invention does not specifically limit it in this regard.

[0030] In this embodiment, a semiconductor substrate made of silicon can be provided first. Then, using etching and filling processes, rows of STI structures arranged sequentially and spaced apart along the Y direction are formed within the semiconductor substrate. The top surface of the formed STI structure 101 is higher than the top surface of the semiconductor substrate. Figure 1 As shown, a dual-memory bit structure 251 with a shared source line is then formed sequentially on the surface of the semiconductor substrate, along with word lines 110 located on both sides of the memory structure 251. Subsequently, gate sidewalls 120 are formed on the sidewalls of the word lines 110 using deposition and etching processes.

[0031] Depend on Figure 1As shown, the top surface of the formed gate side wall 120 is lower than the top surface of the portion of the word line 110 close to the gate side wall 120. This is because of the height difference between the active region ACT of the split-gate flash memory and the shallow trench isolation structure STI, and the over-etching OE in the process of forming the gate side wall 120, whether wet etching or dry etching, which results in the height of the top surface of the formed gate side wall 120 being lower than the expected design height, thereby causing the above-described problems.

[0032] To solve the problem, the inventors of the present application propose to convert the conductive material of a portion of the thickness of the top surface of the word line 110 close to the gate side wall 120 into insulating material, thereby isolating the metal silicide layer formed on the other top surface of the word line from the metal plug formed on the surface of the semiconductor substrate on both sides of the storage structure 251 for external connection of the drain D of the memory device (widening the distance between the two in the lateral direction), thereby avoiding the short circuit between the metal silicide layer formed on the other part of the top surface of the word line and the metal plug of the split-gate flash memory, causing the split-gate flash memory to fail, i.e., achieving the purpose of the present application.

[0033] Further, to avoid the metal silicide layer (not shown) formed on the remaining top surface of the word line 110 in the subsequent process from being higher than the portion of the top surface of the word line close to the gate side wall converted into insulating material in the direction perpendicular to the surface of the semiconductor substrate. For example, in an embodiment of the present application, the metal material deposited during the silicidation process for forming the metal silicide layer can be Co, and its thickness range can be: That is, the thickness cannot be too thick. And after forming the metal silicide layer, the semiconductor substrate needs to be cleaned several times, for example, the present application is cleaned twice to remove the excess metal material attached to the top surface of the word line after the formation of the metal silicide layer, which also causes the problems described in the background art.

[0034] Step S200, performing a heat treatment process on the semiconductor substrate containing the gate side wall 120 to convert the conductive material of a portion of the thickness of the top surface of the word line close to the gate side wall into insulating material.

[0035] In the present embodiment, after the semiconductor structure with the gate side wall 120, the word line 110 and the storage structure 251 is formed by the step S100, the semiconductor substrate containing the semiconductor structure as mentioned above can be subjected to a heat treatment process, so as to convert the part of the thickness of the word line 110 which is close to the gate side wall 120 and is made of conductive material, such as polysilicon, into insulating material, such as silicon dioxide, by the temperature change of the heat treatment process. Then, the metal silicide layer and the metal plug CT are formed by corresponding process steps, so as to avoid the technical problems mentioned in the background of the present application, and achieve the technical effects of the present application. Figure 1

[0036] As an example, the heat treatment process for the semiconductor substrate containing the gate side wall 120 in the step S200 can be a rapid thermal oxidation process RTO. Of course, it can also be other heat treatment processes which can achieve the above-mentioned purposes, such as annealing process, etc. Further, when the heat treatment process is the rapid thermal oxidation process RTO, the process parameters thereof can include: the temperature range is 905-1105℃, and specifically can be 905℃, 910℃, 920℃, 930℃, 940℃, 950℃, 960℃, 970℃, 980℃, 990℃, 995℃, 1000℃ and 1005℃. The heating time range can be 15-25s, and specifically can be 15s, 16s, 17s, 18s, 19s, 20s, 21s, 22s, 23s, 24s and 25s. Preferably, the optimal reaction temperature of the rapid thermal oxidation process RTO is 1005℃, and the reaction time is 20s / piece.

[0037] As an example, the present application provides a preparation method, after the part of the thickness of the top surface of the word line is converted into insulating material, the preparation method can further include: subjecting the semiconductor substrate to silicidation treatment, so as to form a metal silicide layer on the top surface of the word line.

[0038] Further, after the part of the thickness of the top surface of the word line close to the gate side wall is converted into insulating material, the preparation method can further include:

[0039] forming an interlayer dielectric layer, which buries the storage structure and the word line whose top surface is converted into insulating material;

[0040] etching the interlayer dielectric layer, so as to form a contact hole which exposes the surface of the semiconductor substrate on both sides of the gate side wall, and filling the contact hole with conductive metal, so as to form a conductive plug.

[0041] ​Since the above-mentioned processes for forming the metal silicide layer and the metal plug CT are all existing processes, they will not be described in detail in this invention.

[0042] Furthermore, based on the same inventive concept as the above-described flash memory device fabrication method, the present invention also provides a flash memory device, which can be fabricated using the flash memory device fabrication method described above, wherein the storage structure of the flash memory device is a shared source line dual-bit structure with insulating material covering the top surface of the word line.

[0043] In summary, in the method for fabricating a flash memory device provided by the present invention, after the process step of forming the gate sidewall located on the word line sidewall, a heat treatment process is added to convert a portion of the conductive material near the top surface of the word line close to the gate sidewall into an insulating material. This avoids the problem of short circuits between the metal silicide layer subsequently formed at other locations on the top surface of the word line and the metal plug of the gate flash memory, which would otherwise cause the gate flash memory to fail.

[0044] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0045] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0046] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating a flash memory device, characterized in that, Includes the following steps: A semiconductor substrate is provided, in which a trench isolation structure for defining an active region of a flash memory device is formed. On the surface of the semiconductor substrate corresponding to the active region, a memory structure, word lines located on both sides of the memory structure, and gate sidewalls located on both sides of the word lines are formed. The top surface of the trench isolation structure is higher than the top surface of the semiconductor substrate, and the word lines are made of a conductive material. A thermal processing is performed on the semiconductor substrate containing the gate sidewall to convert a portion of the conductive material near the top surface of the word line close to the gate sidewall into an insulating material.

2. The method for fabricating a flash memory device as described in claim 1, characterized in that, The storage structure is a dual-bit structure with a shared source line.

3. The method for fabricating a flash memory device as described in claim 1, characterized in that, The conductive material of the word lines is polycrystalline silicon.

4. The method for fabricating a flash memory device as described in claim 3, characterized in that, The thermal processing of the semiconductor substrate containing the gate sidewalls includes a rapid heating oxidation process.

5. The method for fabricating a flash memory device as described in claim 4, characterized in that, The process parameters of the rapid heating oxidation process include: a temperature range of 905℃ to 1105℃ and a heating time range of 15s to 25s.

6. The method for fabricating a flash memory device as described in claim 1, characterized in that, The etching process for forming the gate sidewall on the surface of the semiconductor substrate includes an over-etching process step.

7. The method for fabricating a flash memory device as described in claim 3, characterized in that, After converting a portion of the conductive material on the top surface of the word line into an insulating material, the preparation method further includes: silicide treatment of the semiconductor substrate to form a metal silicide layer on the top surface of the word line.

8. The method for fabricating a flash memory device as described in claim 7, characterized in that, After converting a portion of the conductive material near the top surface of the word line close to the gate sidewall into an insulating material, the fabrication method further includes: An interlayer dielectric layer is formed, which buries the memory structure and the word lines on the top surface, which are converted into insulating material. The interlayer dielectric layer is etched to form contact holes that expose the semiconductor substrate surfaces on both sides of the gate sidewall, and the contact holes are filled with conductive metal to form conductive plugs.

9. The method for fabricating a flash memory device as described in claim 7, characterized in that, The thickness range of the metal material deposited during the silicide treatment to form the metal silicide layer is:

10. A flash memory device, characterized in that, The flash memory device is manufactured using the method described in any one of claims 1 to 9, wherein the storage structure of the flash memory device is a shared source line dual-bit structure with insulating material covering the top surface of the word line.

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