Method for eliminating pseudo gate height difference
By forming a metal silicide protective layer on the pseudo-gate structure and using a filler layer and photolithography to planarize the pseudo-gate structure, the problem of SiGe epitaxial layer damage caused by uneven photoresist consumption is solved, and the electrical stability of the device is improved.
Patent Information
- Application Number
- CN202511695354.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-02-17
AI Technical Summary
In existing processes, the photoresist etch-back process can easily lead to uneven photoresist consumption when eliminating dummy gate height differences, resulting in damage to the SiGe epitaxial layer and affecting the device's electrical properties.
Metal silicide is used as a protective layer. The pseudo gate structure is made highly flat through filling layer and photolithography process, avoiding direct etching of the semiconductor substrate surface material. The metal layer is used to protect the SiGe epitaxial layer.
It effectively reduces surface material damage to the semiconductor substrate on both sides of the dummy gate, especially damage to the SiGe epitaxial layer in the PMOS region, and improves the electrical stability of the device.
Smart Images
Figure CN121548095A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for eliminating dummy gate height differences. Background Technology
[0002] In some existing processes, embedded epitaxial layers are used to improve carrier mobility in the channel region of the device, thereby improving device performance. In this case, the source and drain regions of a PMOS device typically form an embedded SiGe epitaxial layer. During SiGe growth, the pFET (PMOS region) is exposed. The hard oxide mask (OX HM) layer above the polysilicon gate in the dummy gate structure of the PMOS region is consumed, resulting in a height difference in the dummy gate structure between the nFET (NMOS) and the pFET. This height difference persists in subsequent process steps after the SiGe epitaxial layer is formed. In existing processes, photoresist etch back (PREB) is used to eliminate this difference. Furthermore, this process can reduce the height difference between dummy gates introduced in other steps. In the current process flow, the formation of metal silicides such as NiSi, known as the NiSi process loop, is performed first. The NiSi loop then removes TiN and NiPt using a wet process, before entering the PREB loop. The PREB loop first deposits SiN and then coats it with photoresist (PR) to protect the NiSi layer above SiGe. The PREB etching process consists of two steps: a first etch (EB1) and a second etch (EB2). EB1 etches the PR down to the PREB SiN, exposing the deposited SiN. EB2 etches downwards, stopping at the silicon nitride hard mask layer (SiN HM) above the poly layer. Finally, a contact etch stop layer (CESL) thinning process is used to remove the remaining PREB SiN and the SiN from the sidewalls of the dummy gate structure.
[0003] Because PR has fluidity and varying pattern densities lead to different PR coating thicknesses, this non-uniformity makes it more difficult to balance exposing SiN and protecting SiGe in the PR thickness after EB1 etching. Furthermore, to eliminate n / pFET loading, EB2 needs to be pushed downwards and the sidewalls etched to reduce the risk of defects in subsequent processes. During this process, PR continues to be consumed; if the PR thickness is insufficient to shield the SiGe, it will cause SiGe damage, ultimately affecting the device's electrical performance.
[0004] like Figures 1A to 1CThe diagram shown is a schematic representation of the device structure in each step of the existing PREB process. Before performing the PREB process, the following steps are performed:
[0005] like Figure 1A As shown, a semiconductor substrate 101 with a dummy gate structure 105 formed on its surface is provided. The semiconductor substrate 101 includes an NMOS formation region 101a and a PMOS formation region 101b. The heights of the dummy gate structure 105 in the NMOS formation region 101a and the heights of the dummy gate structure 105 in the PMOS formation region 101b are not the same.
[0006] The dummy gate structure 105 comprises a gate dielectric layer (not shown), a polysilicon gate 102, a silicon nitride hard mask layer 103, and an oxide hard mask layer 104, stacked sequentially. Embedded SiGe epitaxial layers 106 are formed in the semiconductor substrate 101 on both sides of the dummy gate structure 105 in the PMOS formation region 101b. During the formation of the embedded SiGe epitaxial layers 106, the PMOS formation region 101b is opened, thus consuming the exposed oxide hard mask layer 104, thereby reducing the height of the dummy gate structure 105 in the PMOS formation region 101b.
[0007] Sidewalls are also formed on the side of the pseudo-gate structure 105.
[0008] The process includes forming a metal silicide 107 after forming the embedded SiGe epitaxial layer 106. The metal silicide 107 is formed by a metal silicide reaction, and the metal layer outside the region where the metal silicide 107 is formed is removed. Figure 1A In this process, a metal silicide 107 is formed on the top surface of the embedded SiGe epitaxial layer 106.
[0009] Next, the PREB process is performed, including:
[0010] like Figure 1A As shown, a silicon nitride layer 108 is formed, followed by a photoresist layer 109.
[0011] like Figure 1B As shown, EB1 is then performed, which involves etching the photoresist layer 109 until the silicon nitride layer 108 is exposed.
[0012] like Figure 1C As shown, EB2 is then performed, which mainly targets the oxide hard mask layer 104 until it stops on the silicon nitride hard mask layer 103; EB2 also pushes the sidewalls downwards. However, due to Figure 1CAs shown, although the photoresist layer 109 is not etched in EB2, the photoresist layer 109 will still be consumed. If the consumption of the photoresist layer 109 is too large in EB2, the surface of the embedded SiGe epitaxial layer 106 may be exposed. In this case, the etching of EB2 will cause damage to the embedded SiGe epitaxial layer 106, which will affect the electrical properties of the device. Summary of the Invention
[0013] The technical problem to be solved by the present invention is to provide a method for eliminating the height difference of the pseudo gate, which can reduce the damage to the surface material of the semiconductor substrate on both sides of the pseudo gate during the planarization of the pseudo gate in different regions, such as reducing the damage to the embedded epitaxial layer such as SiGe on both sides of the pseudo gate structure of PMOS.
[0014] To solve the above-mentioned technical problems, the method for eliminating pseudo-gate height differences provided by the present invention includes the following steps:
[0015] Step 1: Provide a semiconductor substrate with a dummy gate structure formed on its surface. The semiconductor substrate includes an NMOS formation region and a PMOS formation region. The heights of the dummy gate structure in the NMOS formation region and the heights of the dummy gate structure in the PMOS formation region are not the same.
[0016] Step 2: Formation of metal silicides, including:
[0017] A first metal layer is formed, which covers the top and side surfaces of the dummy gate structure and the surface of the semiconductor substrate outside the dummy gate structure.
[0018] A metal silicide reaction is performed to form the metal silicide on the surface of the semiconductor substrate outside the dummy gate structure and in direct contact with the first metal layer, wherein the surface of the metal silicide and the outer surface of the first metal layer are retained.
[0019] Step 3: Form a first fill layer with a flat top surface, completely filling the gaps between the dummy gate structures and extending them over the top surface of the dummy gate structures.
[0020] Step 4: A first photoresist pattern is formed using a photolithography process, which opens up the top region of each of the pseudo-gate structures.
[0021] Step 5: Etch the first filling layer, the first metal layer, and the dummy gate structure sequentially to make the heights of each dummy gate structure equal.
[0022] Step 6: Remove the first photoresist pattern and the first filler layer in sequence.
[0023] Step 7: Remove the first metal layer. In steps 3 to 6, the first metal layer serves as a protective layer for the surface material of the semiconductor substrate on both sides of the pseudo-gate structure.
[0024] A further improvement is that the pseudo-gate structure includes a gate dielectric layer, a polysilicon gate, a first hard mask layer, and a second hard mask layer stacked sequentially.
[0025] A further improvement is that a first embedded epitaxial layer is formed in the semiconductor substrate on both sides of the dummy gate structure in the PMOS formation region.
[0026] A further improvement is that the material of the first embedded epitaxial layer includes SiGe.
[0027] A further improvement is that the material of the first hard mask layer includes silicon nitride; the material of the second hard mask layer includes silicon oxide; and the different thicknesses of the second hard mask layer result in different heights of the dummy gate structure.
[0028] A further improvement is that, in step five, the etching of the dummy gate structure stops on the first hard mask layer.
[0029] A further improvement is that sidewalls are formed on the sides of the dummy gate structure.
[0030] A further improvement is that the sidewall material includes silicon nitride.
[0031] A further improvement is that, after step seven, it also includes:
[0032] Step 8: Remove the silicon nitride from the first hard mask layer and the sidewalls using a wet process.
[0033] A further improvement is that the metal silicide includes NiSi.
[0034] A further improvement is that the first metal layer comprises a NiPt layer and a TiN layer stacked sequentially.
[0035] A further improvement is that, in step seven, a wet process is used to remove the first metal layer.
[0036] A further improvement is that the first filling layer includes a BARC layer.
[0037] After the metal silicide reaction is completed, this invention does not directly remove the first metal layer. Instead, it uses the first metal layer as a protective layer to protect the material on the semiconductor substrate surface corresponding to the bottom of the metal silicide. Furthermore, instead of using the PREB process as in existing methods to planarize the height of the dummy gate structures in different regions, it employs a first filler layer filling and photolithography process to open the top region of each dummy gate structure. Etching is then performed to make the heights of each dummy gate structure level. Since the etching only occurs on the top region of the dummy gate structure, and the regions between the dummy gate structures are protected by the first filler layer and photoresist, the etching does not damage the semiconductor substrate surface material outside the dummy gate structure. After the planarization etching of the dummy gate structure is completed, during the removal of the photoresist and the first filler layer, the first metal layer still protects the semiconductor substrate surface material outside the dummy gate structure. Therefore, this invention can reduce damage to the semiconductor substrate surface material on both sides of the dummy gate during the planarization of dummy gates in different regions, for example, reducing damage to the embedded epitaxial layers such as SiGe on both sides of the dummy gate structure of a PMOS. Attached Figure Description
[0038] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0039] Figures 1A-1C This is a schematic diagram of the device structure in each step of the existing PREB process;
[0040] Figure 2 This is a flowchart of a method for eliminating pseudo-gate height differences according to an embodiment of the present invention;
[0041] Figures 3A-3G This is a schematic diagram of the device structure in each step of the method for eliminating pseudo-gate height difference in an embodiment of the present invention. Detailed Implementation
[0042] like Figure 2 The diagram shown is a flowchart of a method for eliminating pseudo-gate height differences according to an embodiment of the present invention; as shown... Figures 3A to 3G The diagram shown is a schematic representation of the device structure in each step of the method for eliminating spurious gate height differences according to an embodiment of the present invention. The method for eliminating spurious gate height differences according to an embodiment of the present invention includes the following steps:
[0043] Step 1, such as Figure 3A As shown, a semiconductor substrate 201 with a dummy gate structure 205 formed on its surface is provided. The semiconductor substrate 201 includes an NMOS formation region 201a and a PMOS formation region 201b. The heights of the dummy gate structure 205 in the NMOS formation region 201a and the heights of the dummy gate structure 205 in the PMOS formation region 201b are not the same.
[0044] In this embodiment of the invention, the dummy gate structure 205 includes a gate dielectric layer (not shown), a polysilicon gate 202, a first hard mask layer 203, and a second hard mask layer 204 stacked sequentially. A first embedded epitaxial layer 206 is formed in the semiconductor substrate 201 on both sides of the dummy gate structure 205 in the PMOS formation region 201b. In some embodiments, the material of the first embedded epitaxial layer 206 includes SiGe.
[0045] In some embodiments, the material of the first hard mask layer 203 includes silicon nitride; the material of the second hard mask layer 204 includes silicon oxide. The formation of the first embedded epitaxial layer 206 affects the height of the dummy gate structure 205, and the varying thickness of the second hard mask layer 204 results in varying heights of the dummy gate structure 205. Figure 3A As shown, when the first embedded epitaxial layer 206 is formed, the PMOS formation region 201b is opened. Etching processes are used in the formation of the first embedded epitaxial layer 206. These etching processes will cause damage to the second hard mask layer 204, which will reduce the height of the dummy gate structure 205 in the PMOS formation region 201b.
[0046] In this embodiment of the invention, a sidewall 208 is further formed on the side of the dummy gate structure 205. The material of the sidewall 208 includes silicon nitride. Figure 3A In this context, the sidewall 208 is formed by stacking silicon oxide sidewall 2081 and silicon nitride sidewall 2082.
[0047] Step 2: Forming metal silicide 207a, including:
[0048] A first metal layer 207 is formed, which covers the top and side surfaces of the dummy gate structure 205 and the surface of the semiconductor substrate 201 outside the dummy gate structure 205.
[0049] A metal silicide reaction is performed to form the metal silicide 207a on the surface of the semiconductor substrate 201, which is in direct contact with the first metal layer 207 outside the dummy gate structure 205, with the first metal layer 207 remaining on the surface of the metal silicide 207a and the exterior.
[0050] In this embodiment of the invention, the metal silicide 207a comprises NiSi.
[0051] The first metal layer 207 includes a NiPt layer 2071 and a TiN layer 2072 stacked sequentially.
[0052] Step 3, as follows Figure 3BAs shown, a first filler layer 209 forming a flat top surface completely fills the spaced area between the dummy gate structures 205 and extends over the top surface of the dummy gate structures 205.
[0053] In this embodiment of the invention, the first filling layer 209 includes a BARC layer.
[0054] Step 4, as follows Figure 3C As shown, a first photoresist pattern 210 is formed using a photolithography process. The first photoresist pattern 210 opens up the top region of each of the dummy gate structures 205.
[0055] Step 5, as follows Figure 3D As shown, the first filling layer 209, the first metal layer 207 and the pseudo gate structure 205 are etched sequentially to make the heights of each pseudo gate structure 205 equal.
[0056] In this embodiment of the invention, the etching of the pseudo-gate structure 205 stops on the first hard mask layer 203.
[0057] During the etching of the second hard mask layer 204, the sidewall 208 is also pushed downwards. The material pushed downwards includes both silicon nitride and oxide. At this time, the etching gas needs to be set. An etching gas with a selectivity ratio of 1:1 is used to push SiN and Oxide downwards, and finally stop on SiN HM, i.e., the first hard mask layer 203.
[0058] Step Six, as Figure 3E As shown, the first photoresist pattern 210 and the first filler layer 209 are removed sequentially.
[0059] Step 7, as follows Figure 3F As shown, the first metal layer 207 is removed. In steps three to six, the first metal layer 207 serves as a protective layer for the surface material of the semiconductor substrate 201 on both sides of the dummy gate structure 205. Figure 3E As shown, after the height difference of the pseudo-gate structure 205 is eliminated, the first metal layer 207 can effectively protect the first embedded epitaxial layer 206 at the bottom.
[0060] In some embodiments, a wet process is used to remove the first metal layer 207.
[0061] Also includes:
[0062] Step 8: Remove the silicon nitride (SiN sidewalls 2082) from the first hard mask layer 203 and the sidewalls 208 using a wet process. In this embodiment of the invention, the CESL Slim process is used to remove the silicon nitride from the first hard mask layer 203 and the sidewalls 208.
[0063] In this embodiment of the invention, after the metal silicide reaction is completed, the first metal layer 207 is not directly removed. Instead, the first metal layer 207 is used as a protective layer to protect the material on the surface of the semiconductor substrate 201 corresponding to the bottom of the metal silicide 207a. Furthermore, instead of using the PREB process as in existing methods to planarize the height of the dummy gate structures 205 in different regions, a filling and photolithography process using the first filling layer 209 is used to open the top region of each dummy gate structure 205. Then, etching is performed to make the heights of each dummy gate structure 205 level. Since the etching is only performed on the top region of the dummy gate structures 205, the heights of the dummy gate structures 205 are not directly affected. The area is protected by the first filling layer 209 and photoresist, so the etching will not damage the surface material of the semiconductor substrate 201 outside the pseudo gate structure 205. After the planarization etching of the pseudo gate structure 205 is completed, the first metal layer 207 will still protect the surface material of the semiconductor substrate 201 outside the pseudo gate structure 205 during the removal of photoresist and the first filling layer 209. Therefore, the embodiment of the present invention can reduce the damage to the surface material of the semiconductor substrate 201 on both sides of the pseudo gate during the planarization of the pseudo gate in different regions, such as reducing the damage to the embedded epitaxial layer such as SiGe on both sides of the pseudo gate structure 205 of PMOS.
[0064] In this embodiment of the invention, to reduce the risk of SiGe damage, n / pFET loading is eliminated after rapid self-aligned silicide thermal processing. At this point, NiPt and TiN remain on top of SiGe, providing some protection. Eliminating n / pFET loading is achieved by defining the area to be etched using Litho etching, and then etching BARC, TiN and NiPt, and SiN and Oxide respectively. After eliminating nFET and pFET loading through etching, NiPt and TiN are removed, and then residual SiN and sidewall SiN are removed using CESL Slim.
[0065] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A method of eliminating false gate height differences, characterized by, The method comprises the following steps: Step 1: providing a semiconductor substrate with a dummy gate structure formed on a surface, the semiconductor substrate comprising an NMOS forming region and a PMOS forming region, the height of the dummy gate structure in the NMOS forming region being different from the height of the dummy gate structure in the PMOS forming region; Step 2: forming a metal silicide, comprising: forming a first metal layer covering the top surface and side surface of the dummy gate structure and the surface of the semiconductor substrate outside the dummy gate structure; carrying out a metal silicidation reaction to form the metal silicide on the surface of the semiconductor substrate outside the dummy gate structure and directly contacted with the first metal layer, the surface of the metal silicide and the external first metal layer being reserved; Step 3: forming a first filling layer with a flat top surface to completely fill the interval region between the dummy gate structures and extend above the top surface of the dummy gate structure; Step 4: forming a first photoresist pattern by a photoetching process, the first photoresist pattern opening the top region of each dummy gate structure; Step 5: etching the first filling layer, the first metal layer and the dummy gate structure in sequence to make the height of each dummy gate structure flat; Step 6: removing the first photoresist pattern and the first filling layer in sequence; Step 7: removing the first metal layer, the first metal layer serving as a protective layer of the surface material of the semiconductor substrate on both sides of the dummy gate structure in steps 3 to 6.
2. The method of claim 1, wherein: The dummy gate structure comprises a gate dielectric layer, a polysilicon gate, a first hard mask layer and a second hard mask layer stacked in sequence.
3. The method of claim 2, wherein: A first embedded epitaxial layer is formed in the semiconductor substrate on both sides of the dummy gate structure in the PMOS forming region.
4. The method of claim 3, wherein: The material of the first embedded epitaxial layer comprises SiGe.
5. The method of claim 2, wherein: The material of the first hard mask layer comprises silicon nitride, the material of the second hard mask layer comprises silicon oxide, and the thickness of the second hard mask layer is different to make the height of the dummy gate structure different.
6. The method of claim 5, wherein: In step 5, the etching of the dummy gate structure is stopped on the first hard mask layer.
7. The method of eliminating false gate height differences as claimed in claim 6 wherein: A side wall is further formed on the side surface of the dummy gate structure.
8. The method of eliminating false gate height differences as claimed in claim 7, wherein: The material of the side wall comprises silicon nitride.
9. The method of claim 8, wherein: After step 7, further comprising: Step 8: removing the silicon nitride of the first hard mask layer and the side wall by a wet process.
10. The method of removing false gate height differences of claim 1, wherein: The metal silicide comprises NiSi.
11. The method of removing false gate height differences of claim 10, wherein: The first metal layer comprises a NiPt layer and a TiN layer stacked in sequence.
12. The method of eliminating false gate height differences as claimed in claim 11, wherein: In step 7, the first metal layer is removed by a wet process.
13. The method of eliminating false gate height differences of claim 1, wherein: The first filling layer comprises a BARC layer.