Array substrate, display panel and electronic device

Abstract

The embodiment of the present application provides an array substrate, a display panel and an electronic device, the array substrate comprises a first display area and a second display area located on both sides of the first display area, and the array substrate comprises: a substrate; at least one metal wiring layer located on one side of the substrate, the wiring density of the metal wiring layer corresponding to the position of the second display area is greater than the wiring density of the metal wiring layer corresponding to the position of the first display area; a reflection weakening layer located in the second display area and covering the side of the metal wiring layer away from the substrate, the reflection weakening layer is used for weakening or eliminating the external light reflected by the metal wiring layer. By arranging the reflection weakening layer in the second display area on both sides of the first display area, the periodic distribution of the metal wiring layer reflected in the second display area can be destroyed, so that the phenomenon of uneven reflection on both sides of the display panel in the screen-off state is weakened.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and more specifically, to an array substrate, a display panel, and an electronic device. Background Technology

[0002] With the development of display panel manufacturing technology, users have increasingly higher requirements for display panel display effects. In order to further reduce the bezel of the display panel and increase the screen-to-body ratio, some solutions place the Gate In Panel (GIP) circuit or fanout circuit, which was originally located in the non-display area on the bezel, on both sides of the effective display area. This causes the spacing distribution period of the traces on both sides of the effective display area to be different from that in the middle area, resulting in uneven reflection (mura) on both sides of the display panel when the screen is off. Summary of the Invention

[0003] To overcome the technical problems mentioned in the background, this application provides an array substrate, the array substrate including a first display area and second display areas located on both sides of the first display area, the array substrate comprising:

[0004] Substrate;

[0005] At least one metal wiring layer located on one side of the substrate, wherein the wiring density in the second display area of ​​the metal wiring layer is greater than the wiring density in the first display area;

[0006] A reflection-reducing layer is located in the second display area and covers the metal trace layer on the side away from the substrate. The reflection-reducing layer is used to reduce or eliminate external light reflected by the metal trace layer.

[0007] In one possible implementation, the array substrate further includes at least one planarization layer; the reflection reduction layer is located on the side of the planarization layer furthest from the substrate, facing the substrate.

[0008] In one possible implementation, the at least one metal wiring layer includes a first metal layer, a second metal layer, and a third metal layer; the array substrate further includes:

[0009] A semiconductor structure located on one side of the substrate;

[0010] A gate insulating layer located on the side of the semiconductor structure away from the substrate; the first metal layer located on the side of the gate insulating layer away from the substrate;

[0011] A capacitor dielectric layer located on the side of the first metal layer away from the substrate; a second metal layer located on the side of the capacitor dielectric layer away from the substrate;

[0012] An interlayer insulating layer is located on the side of the second metal layer away from the substrate; the reflection weakening layer is located on the side of the interlayer insulating layer away from the substrate; the third metal layer is located on the side of the reflection weakening layer away from the substrate; at least a portion of the metal traces in the third metal layer are electrically contacted with the semiconductor structure through vias penetrating the reflection weakening layer, the interlayer insulating layer, and the capacitor dielectric layer.

[0013] The planarization layer is located on the side of the third metal layer away from the substrate.

[0014] In one possible implementation, the reflection-reducing layer includes a first polarizing film.

[0015] In one possible implementation, the reflection-reducing layer is doped with dispersive particles;

[0016] Preferably, the particle size of the dispersive particles is from 1 nm to 100 nm.

[0017] In one possible implementation, the dispersive particles include metal oxide particles;

[0018] Preferably, the metal oxide particles include zirconium oxide particles or titanium oxide particles.

[0019] In one possible implementation, the reflection-reducing layer includes a refractive layer, the refractive index of which is greater than the refractive index of at least one planarization layer located on the side of the refractive layer away from the substrate;

[0020] Preferably, the thickness of the refractive layer is greater than 120 nm.

[0021] In one possible implementation, the refractive index of the refractive layer is greater than 2.5;

[0022] Preferably, the material of the refractive layer includes amorphous silicon.

[0023] This application also provides a display panel, which includes the array substrate provided in this application and a light-emitting device layer located on the side of the reflection reduction layer away from the substrate.

[0024] Preferably, the reflection attenuation layer includes a first polarizing film; a second polarizing film is also disposed on the side of the light-emitting device layer away from the array substrate, wherein the polarization direction of the first polarizing film is the same as the phase delay direction of the second polarizing film.

[0025] This application also provides an electronic device that includes the display panel provided in this application.

[0026] Compared with the prior art, this application has the following beneficial effects:

[0027] This application provides an array substrate, a display panel, and an electronic device. By providing a reflection weakening layer in the second display area on both sides of the first display area, the periodic distribution of reflection in the metal trace layer in the second display area can be disrupted, thereby reducing the uneven reflection on both sides of the display panel in the screen-off state. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the wiring in the display panel;

[0030] Figure 2 One of the schematic diagrams of the display panel provided in this embodiment;

[0031] Figure 3 This is a second schematic diagram of the display panel provided in this embodiment;

[0032] Figure 4 This is the third schematic diagram of the display panel provided in this embodiment;

[0033] Figure 5 This is the fourth schematic diagram of the display panel provided in this embodiment;

[0034] Figure 6 This is the fifth schematic diagram of the display panel provided in this embodiment. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0037] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0038] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0039] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0040] The active area (AA) of a display panel typically has multiple metal trace layers 140, and each metal trace layer 140 contains multiple parallel AA area trace circuits 103 extending in the same direction. Please refer to... Figure 1 In some implementations, in order to reduce the screen bezel, the side routing circuits 104 (such as GIP circuits or fan-out circuits) in the non-display areas on both sides of the AA area are set in the AA area, such as between adjacent AA area routing circuits 103.

[0041] However, the inventors discovered that the AA area routing circuit 103 is usually distributed at equal intervals according to a certain pattern, while the distribution spacing of the side routing circuit 104 is different from that of the AA area routing circuit 103. After the side routing circuit 104 is placed on both sides of the AA area, the AA area routing circuit 103 and the side routing circuit 104 will produce moiré patterns due to the superposition of reflected light with different distribution periods when reflecting external light, which will cause the screen-off mura phenomenon to appear on both sides of the AA area, affecting the user experience.

[0042] Based on the discovery and research of the above problems, this embodiment provides a solution to reduce the phenomenon of screen muting on both sides of the display panel. The solution provided in this embodiment will be described in detail below.

[0043] Please see again Figure 1 This embodiment provides an array substrate, which includes a first display area 101 and a second display area 102 located on both sides of the first display area 101.

[0044] It should be noted that, in this embodiment, both the first display area 101 and the second display area 102 are part of the AA area, and the display panel may further include a non-display area (not shown) located on at least one side outside the AA area. For example, the non-display area may surround the AA area.

[0045] Please refer to Figure 2 The array substrate may include a substrate 110, at least one metal trace layer 140, and a reflection reduction layer 190.

[0046] The at least one metal wiring layer 140 is located on one side of the substrate 110. In this embodiment, the wiring density in the metal wiring layer 140 located in the second display area 102 is greater than the wiring density located in the first display area 101.

[0047] Specifically, in one possible implementation, the first display area 101 may include an AA area routing circuit 103, and the second display area 102 may include an AA area routing circuit 103 and a side routing circuit 104 (e.g., a GIP circuit or a fan-out circuit), wherein at least a portion of the AA area routing circuit 103 and the side routing circuit 104 extend in the same direction and parallel to each other.

[0048] In one possible implementation, there may be multiple metal trace layers 140, which can be used to form electrodes, capacitors, or signal transmission traces for the thin-film transistor (TFT) driving units in the array substrate. The AA region trace circuit 103 may be located on the same metal trace layer 140 as the side trace circuit 104; in another possible implementation, the AA region trace circuit 103 may be located on a different metal trace layer 140 from the side trace circuit 104.

[0049] In this embodiment, the reflection-reducing layer 190 is located in the second display area 102 and covers the side of the metal wiring layer 140 away from the substrate 110. In one possible implementation, other film layers may be disposed between the metal wiring layer 140 and the reflection-reducing layer 190; in another possible implementation, the reflection-reducing layer 190 may be directly disposed on the side of the metal wiring layer 140 away from the substrate 110 and cover the metal wiring layer 140.

[0050] The reflection weakening layer 190 is used to weaken or eliminate external light reflected by the metal trace layer 140. Thus, the reflection weakening layer 190 can reduce the reflected light from the side trace circuit 104 in the second display area 102, or disrupt the distribution period of the reflected light from the side trace circuit 104, thereby reducing the risk of moiré patterns caused by the mixing of light reflected from the side trace circuit 104 and the light reflected from the AA area trace circuit 103, and mitigating the uneven reflection on both sides of the display panel in the screen-off state.

[0051] For some possible implementations, please refer to Figure 3 The array substrate further includes at least one planarization layer 170, and the reflection reduction layer 190 is located on the side of the planarization layer 170 furthest from the substrate 110, facing the substrate 110. The side of the planarization layer 170 furthest from the substrate 110 may also contain an anode layer 210 of the light-emitting device layer, a pixel defining layer 220, a support structure 230, etc. Thus, the reflection reduction layer 190 is located between the anode layer 210 and the substrate 110, ensuring that the reflection reduction layer 190 does not affect the flatness of the anode layer 210 or the light-emitting effect of the light-emitting device layer located above the anode layer 210.

[0052] In one possible implementation, please refer to Figure 4 The array substrate may include a plurality of the metal trace layers 140, for example, it may include a first metal layer 141, a second metal layer 142 and a third metal layer 143 stacked sequentially from the direction close to the substrate 110 to the direction away from the substrate 110.

[0053] Specifically, please refer to Figure 4The array substrate may include a semiconductor structure 120 located on one side of the substrate 110, a gate insulating layer 130 located on the side of the semiconductor structure 120 away from the substrate 110, a first metal layer 141 located on the side of the gate insulating layer 130 away from the substrate 110, a capacitor dielectric layer 150 located on the side of the first metal layer 141 away from the substrate 110, a second metal layer 142 located on the side of the capacitor dielectric layer 150 away from the substrate 110, an interlayer insulating layer 160 located on the side of the second metal layer 142 away from the substrate 110, a reflection weakening layer 190 located on the side of the interlayer insulating layer 160 away from the substrate 110, a third metal layer 143 located on the side of the reflection weakening layer 190 away from the substrate 110, and a planarization layer 170 located on the side of the third metal layer 143 away from the substrate 110. In this process, at least a portion of the metal traces in the third metal layer 143 are electrically contacted with the semiconductor structure 120 through vias penetrating the capacitor dielectric layer 150, the interlayer insulating layer 160, and the reflection weakening layer 190, for example, electrically contacting the source electrode or drain electrode in the semiconductor structure 120.

[0054] In addition, the planarization layer 170 may also be provided with an anode layer 210, a pixel defining layer 220, and a support structure 230 on the side away from the substrate 110. The anode layer 210 is electrically contacted with a portion of the metal traces in the third metal layer 143 through a through hole penetrating the planarization layer 170.

[0055] The side trace circuit 104 can be located in the first metal layer 141 or the second metal layer 142, so that the reflection weakening layer 190 can weaken or eliminate the reflected light from the first metal layer 141 and the second metal layer 142.

[0056] In one possible implementation, please refer to Figure 5 The array substrate may include a plurality of the metal trace layers 140, for example, it may include a first metal layer 141, a second metal layer 142 and a third metal layer 143 stacked sequentially from the direction close to the substrate 110 to the direction away from the substrate 110.

[0057] Specifically, please refer to Figure 5The array substrate may include a semiconductor structure 120 located on one side of the substrate 110, a gate insulating layer 130 located on the side of the semiconductor structure 120 away from the substrate 110, a first metal layer 141 located on the side of the gate insulating layer 130 away from the substrate 110, a capacitor dielectric layer 150 located on the side of the first metal layer 141 away from the substrate 110, a second metal layer 142 located on the side of the capacitor dielectric layer 150 away from the substrate 110, an interlayer insulating layer 160 located on the side of the second metal layer 142 away from the substrate 110, a third metal layer 143 located on the side of the interlayer insulating layer 160 away from the substrate 110, a reflection weakening layer 190 located on the side of the third metal layer 143 away from the substrate 110, and a planarization layer 170 located on the side of the reflection weakening layer 190 away from the substrate 110, wherein the reflection weakening layer 190 covers the third metal layer 143. In this process, at least a portion of the metal traces in the third metal layer 143 are electrically contacted with the semiconductor structure 120 through vias penetrating the interlayer insulating layer 160 and the capacitor dielectric layer 150, for example, electrically contacting the source electrode or drain electrode in the semiconductor structure 120.

[0058] In addition, the planarization layer 170 may also be provided with an anode layer 210, a pixel defining layer 220, and a support structure 230 on the side away from the substrate 110. The anode layer 210 is electrically in contact with a portion of the metal traces in the third metal layer 143 through a through-hole penetrating the planarization layer 170 and the reflection weakening layer.

[0059] The side trace circuit 104 can be located in the first metal layer 141, the second metal layer 142, or the third metal layer 143. In this way, the reflection weakening layer 190 can weaken or eliminate the reflected light from the first metal layer 141, the second metal layer 142, and the third metal layer 143.

[0060] In one possible implementation, please refer to Figure 6 The array substrate may include a plurality of the metal trace layers 140, for example, it may include a first metal layer 141, a second metal layer 142, a third metal layer 143 and a fourth metal layer 144 sequentially stacked from the direction close to the substrate 110 to the direction away from the substrate 110.

[0061] Specifically, please refer to Figure 6The array substrate may include a semiconductor structure 120 located on one side of the substrate 110, a gate insulating layer 130 located on the side of the semiconductor structure 120 away from the substrate 110, a first metal layer 141 located on the side of the gate insulating layer 130 away from the substrate 110, a capacitor dielectric layer 150 located on the side of the first metal layer 141 away from the substrate 110, a second metal layer 142 located on the side of the capacitor dielectric layer 150 away from the substrate 110, and a layer located on the side of the second metal layer 142 away from the substrate 110. The semiconductor structure 120 comprises an interlayer insulating layer 160 on one side of the substrate 110, a third metal layer 143 on the side of the interlayer insulating layer 160 away from the substrate 110, a first planarization layer 171 on the side of the third metal layer 143 away from the substrate 110, a fourth metal layer 144 on the side of the first planarization layer 171 away from the substrate 110, a reflection-reducing layer 190 on the side of the fourth metal layer away from the substrate 110, and a second planarization layer 172 on the side of the reflection-reducing layer away from the substrate 110. At least a portion of the metal traces in the third metal layer 143 are electrically contacted with the semiconductor structure 120 through vias penetrating the interlayer insulating layer 160 and the capacitor dielectric layer 150, for example, electrically contacting the source or drain electrode in the semiconductor structure 120. At least a portion of the metal traces in the fourth metal layer 144 are electrically contacted with at least a portion of the metal traces in the third metal layer 143 through vias penetrating the first planarization layer 171.

[0062] In addition, the second planarization layer 172 may also be provided with an anode layer 210, a pixel defining layer 220, and a support structure 230 on the side away from the substrate 110. The anode layer 210 is electrically in contact with a portion of the metal traces in the fourth metal layer 144 through a through hole penetrating the first planarization layer 171 and the reflection elimination layer 190.

[0063] The side trace circuit 104 can be located in the first metal layer 141, the second metal layer 142, the third metal layer 143, or the fourth metal layer 144. In this way, the reflection weakening layer 190 can weaken or eliminate the reflected light from the first metal layer 141, the second metal layer 142, the third metal layer 143, and the fourth metal layer 144.

[0064] In one possible implementation, the reflection reduction layer 190 includes a first polarizing film. The first polarizing film may include structures such as a linear polarizer and a phase retardation film. Thus, external light can pass through the first polarizing film and strike components such as a light sensor or optical fingerprint sensor beneath the array substrate. Light reflected by the metal trace layer 140 in the array substrate is blocked by the first polarizing film and cannot be reflected back out. This eliminates the light reflected from the side traces, thereby preventing the moiré pattern caused by the superposition of reflected light from the AA area trace circuit 103 and the side trace circuit 104.

[0065] In another possible implementation, the reflection-reducing layer 190 is doped with dispersive particles. When light incident from the outside or reflected from the metal trace layer 140 passes through the reflection-reducing layer 190, the dispersive particles cause reflection dispersion, thus altering the propagation path of the light. This disrupts the periodic distribution of the reflected light from the side trace circuit 104, thereby preventing the superposition of reflected light from the AA area trace circuit 103 and the side trace circuit 104, which would otherwise produce moiré patterns. In this embodiment, the particle size of the dispersive particles is from 1 nm to 100 nm.

[0066] Furthermore, in this embodiment, the dispersive particles include metal oxide particles. For example, the dispersive particles may include zirconium oxide particles or titanium oxide particles.

[0067] In another possible implementation, the reflection-reducing layer 190 includes a refractive layer with a refractive index greater than that of at least one planarization layer 170 located on the side of the refractive layer away from the substrate 110. Thus, external light can pass through the planarization layer 170 and the refractive layer and be incident on components such as light sensors or optical fingerprint sensors beneath the array substrate. However, because the transmittance of the refractive layer is greater than that of at least one planarization layer 170 located on the side of the refractive layer away from the substrate 110, the light reflected by the metal trace layer 140 will undergo total internal reflection at the interface between the refractive layer and the planarization layer 170, thus preventing the reflected light from passing through the planarization layer 170. This eliminates the light reflected by the side trace circuit 104, thereby preventing the superposition of reflected light from the AA area trace circuit 103 and the side trace circuit 104, which would otherwise produce moiré patterns. In this embodiment, the thickness of the refractive layer can be greater than 120 nm.

[0068] Furthermore, the refractive index of the refractive layer is greater than 2.5. For example, the material of the refractive layer may include amorphous silicon.

[0069] This application also provides a display panel, which includes the array substrate provided in this application and a light-emitting device layer located on the side of the reflection weakening layer 190 away from the substrate 110.

[0070] Furthermore, a second polarizing film is disposed on the light-emitting device layer. The reflection-reducing layer 190 can be a first polarizing film. The polarization direction of the first polarizing film is the same as the phase retardation direction of the second polarizing film disposed on the light-emitting device layer on the array substrate. Thus, light that has passed through the second polarizing film and whose phase has been delayed can continue to pass through the first polarizing film, but the reflected light from the metal trace layer 140 covered by the first polarizing film cannot pass through the first polarizing film.

[0071] This application also provides an electronic device that includes the display panel provided in this application.

[0072] This application provides an array substrate, a display panel, and an electronic device. By providing a reflection weakening layer in the second display area on both sides of the first display area, the periodic distribution of reflection in the metal trace layer in the second display area can be disrupted, thereby reducing the uneven reflection on both sides of the display panel in the screen-off state.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes a first display area and a second display area located on both sides of the first display area. Both the first display area and the second display area are part of an effective display area. The array substrate also includes a non-display area located outside at least one side of the effective display area. The array substrate includes: Substrate; At least one metal trace layer is located on one side of the substrate, wherein the trace density in the second display area of ​​the metal trace layer is greater than the trace density in the first display area; the first display area includes an effective display area trace circuit, and the second display area includes an effective display area trace circuit and a side trace circuit; A reflection reduction layer is located in the second display area and covers the metal trace layer on the side away from the substrate. The reflection reduction layer is used to reduce or eliminate external light reflected by the metal trace layer. The array substrate further includes at least one planarization layer; the reflection reduction layer is located on the side of the planarization layer furthest from the substrate, facing the substrate.

2. The array substrate according to claim 1, characterized in that, The at least one metal wiring layer includes a first metal layer, a second metal layer, and a third metal layer; the array substrate further includes: A semiconductor structure located on one side of the substrate; A gate insulating layer located on the side of the semiconductor structure away from the substrate; the first metal layer located on the side of the gate insulating layer away from the substrate; A capacitor dielectric layer located on the side of the first metal layer away from the substrate; a second metal layer located on the side of the capacitor dielectric layer away from the substrate; An interlayer insulating layer is located on the side of the second metal layer away from the substrate; the reflection weakening layer is located on the side of the interlayer insulating layer away from the substrate; the third metal layer is located on the side of the reflection weakening layer away from the substrate; at least a portion of the metal traces in the third metal layer are electrically contacted with the semiconductor structure through vias penetrating the reflection weakening layer, the interlayer insulating layer, and the capacitor dielectric layer. The planarization layer is located on the side of the third metal layer away from the substrate.

3. The array substrate according to claim 1, characterized in that, The reflection reduction layer includes a first polarizing film.

4. The array substrate according to claim 1, characterized in that, The reflection weakening layer is doped with dispersive particles.

5. The array substrate according to claim 4, characterized in that, The particle size of the dispersive particles is from 1 nm to 100 nm.

6. The array substrate according to claim 4, characterized in that, The dispersive particles include metal oxide particles.

7. The array substrate according to claim 6, characterized in that, The metal oxide particles include zirconium oxide particles or titanium oxide particles.

8. The array substrate according to claim 1, characterized in that, The reflection-reducing layer includes a refractive layer, the refractive index of which is greater than the refractive index of at least one planarization layer located on the side of the refractive layer away from the substrate.

9. The array substrate according to claim 8, characterized in that, The thickness of the refractive layer is greater than 120 nm.

10. The array substrate according to claim 8, characterized in that, The refractive index of the refractive layer is greater than 2.

5.

11. The array substrate according to claim 10, characterized in that, The material of the refractive layer includes amorphous silicon.

12. A display panel, characterized in that, The display panel includes the array substrate as described in claim 1 and a light-emitting device layer located on the side of the reflection-reducing layer away from the substrate.

13. The display panel according to claim 12, characterized in that, The reflection attenuation layer includes a first polarizing film; a second polarizing film is also disposed on the side of the light-emitting device layer away from the array substrate, wherein the polarization direction of the first polarizing film is the same as the phase delay direction of the second polarizing film.

14. An electronic device, characterized in that, The electronic device includes the display panel as described in claim 13.

Images