Power device with improved trench termination region and shield gate trench contact region

Abstract

The present invention discloses a shielded-gate trench MOSFETs with gate trenches separated from terminal trenches, wherein at least one terminal trench surrounds the outer edge of the gate trench and does not surround the gate metal pad area. The shielded gate in each gate trench is connected to the source metal through at least one shielded-gate trench contact area, and the distance between the at least one shielded-gate trench contact area and at least one gate metal wire is greater than 100 μm. In addition, the present invention also discloses a breakdown voltage enhancement region and an avalanche capability enhancement region in the device structure.

Description

Technical Field

[0001] The present invention mainly relates to a shielded-gate trench (SGT) MOSFETs (metal oxide semiconductor field effect transistors) having at least one terminal trench that surrounds an outer edge of a gate trench located in an active region and does not surround a gate metal pad region. A shielded gate in each gate trench is connected to a source metal through at least one shielded-gate trench contact region, and an optimal distance suitable for high-frequency applications is provided between the at least one shielded-gate trench contact region and at least one gate metal wire. Background Art

[0002] In high-frequency applications, the shielded-gate resistance Rs plays an important role in the reverse recovery time Trr of the parasitic body diode and the switching voltage Vsw between the drain and source. The larger the shielded-gate resistance Rs, the lower the Trr and Vsw. However, if Rs is too large, the breakdown voltage will become unstable, so an optimal Rs value needs to be found.

[0003] FIG. 1A shows a prior art SGT MOSFET100 disclosed in U.S. Patent No. 7,768,064, which includes a resistance element 101 located between a shielded gate 102 and a source to reduce the reverse recovery charge Qrr of the parasitic body diode in the shielded-gate trench MOSFET100. In addition, the shielded-gate trench MOSFET 100 further includes: a planar source-body contact region for connecting the n+ source region 103 and the P body region 104 to the source metal 105; and a p+ ohmic body contact doping region 106 for reducing the contact resistance between the source metal 105 and the P body region 104.

[0004] FIG. 1B is a top view of the shielded-gate trench MOSFET 100 shown in FIG. 1A. As can be seen from the figure, the resistance element 101 (shown by a dashed line) is located between the end contact regions 106 and 107, where the end contact region 106 is connected to the shielded gate 102 (as shown in FIG. 1A), and the end contact region 107 is connected to the source metal 105. However, fabricating the resistance element 101 requires additional costs, such as an additional mask for fabricating a polysilicon resistor.

[0005] Therefore, there is still a need to provide a new device structure to solve the above-mentioned problems and limitations. Summary of the Invention

[0006] The present invention discloses a novel SGT MOSFET, which includes an improved trench terminal and gate trenches separated from the terminal trenches. Among them, at least one terminal trench surrounds the outer edge of the gate trench and does not surround the gate metal pad area; the shield gate in each gate trench is connected to the source metal through at least one shield gate trench contact area, and an optimal distance suitable for high-frequency applications is provided between the at least one shield gate trench contact area and at least one gate metal wire.

[0007] Combining a multi-step epitaxial (MSE) layer structure with a multi-step sidewall oxide (MSO) structure can further reduce the specific on-resistance of the device. The MSO structure is a field plate oxide layer that surrounds the shield gate in the gate trench and has a multi-step sidewall oxide layer with a stepwise decreasing thickness from the bottom of the gate trench to the body region, where each step sidewall oxide layer has a uniform thickness.

[0008] One aspect of the present invention is to disclose an SGT device, including: an active region, a terminal region, a gate metal pad area, a central gate metal wire, and at least one shield gate trench contact row area; the active region includes: a plurality of gate trenches along a first axis, formed in an epitaxial layer of a first conductivity type, the epitaxial layer being located on a substrate of a first conductivity type, the gate trenches including a first type of active trench having a first active trench length and a second type of active trench close to the gate metal pad area and having a second active trench length, where the length of the first type of active trench is greater than that of the second type of active trench; the terminal region includes at least one first type of terminal trench that surrounds the outer periphery of the plurality of gate trenches along the first axis and a second axis, where the first axis is perpendicular to the second axis, at least one first type of terminal trench is separated from the plurality of gate trenches and does not surround the gate metal pad area; the SGT device further includes: a plurality of gate trenches formed in the active region, surrounded by a source region of a first conductivity type, the source region being located in a body region of a second conductivity type and close to the upper surface of the epitaxial layer of a first conductivity type, where each gate trench includes a gate and a shield gate; the shield gate is insulated from the epitaxial layer through a first insulating layer, the gate is insulated from the epitaxial layer through a gate oxide layer, the shield gate is insulated from the gate through a polysilicon interlayer oxide (IPO), the gate oxide layer surrounds the gate, and the thickness of the gate oxide layer is less than that of the first insulating layer; the gate in each gate trench is connected to the gate metal pad through a central gate metal wire having a plurality of gate trench contact areas below; the shield gate in each gate trench is connected to the source metal through at least one shield gate trench contact area located on the gate trench, at least one shield gate trench contact area is located in at least one shield gate contact row area along the second axis, the distance between at least one shield gate trench contact area and the gate metal wire is greater than 100 μm, and the central gate metal is located near the middle of the source metal.

[0009] According to another aspect of the present invention, in some preferred embodiments, a shielded gate extended resistor is used to replace the resistor element in the prior art disclosed in U.S. Patent No. 7,768,064, which can be achieved by depositing a shielded gate trench contact region in an area with an optimal distance from the gate metal wire. Therefore, this operation does not increase additional costs nor introduce any defects.

[0010] According to another aspect of the present invention, in some preferred embodiments, the epitaxial layer is a single epitaxial layer with a uniform doping concentration. In some other preferred embodiments, the epitaxial layer is an MSE layer with different doping concentrations, and its doping concentration decreases stepwise along the sidewall of the gate trench, from the bottom of multiple gate trenches to the first-type body region.

[0011] According to another aspect of the present invention, in some preferred embodiments, the SGT device further includes a channel termination region located in the terminal region, which has a second-type source region with a first conductivity type and connected to the epitaxial layer below the channel termination metal, and there is no first-type body region between two adjacent terminal trenches.

[0012] According to another aspect of the present invention, in some preferred embodiments, within each gate trench, the gate is located above the shielded gate. In some other preferred embodiments, the shielded gate is located in the middle of the gate trench, and the gate is formed around the upper two sides of the shielded gate.

[0013] According to another aspect of the present invention, in some preferred embodiments, the first insulating layer is a single oxide layer with a uniform thickness. In some other preferred embodiments, the first insulating layer has an MSO structure, and its thickness decreases stepwise along the sidewall of the gate trench, from the bottom of the gate trench to the body region.

[0014] According to another aspect of the present invention, in some preferred embodiments, the SGT device further includes two long shielded gate trench contact row regions and one short shielded gate trench contact row region. The two long shielded gate trench contact row regions are respectively located at the top and bottom of the source metal, and the one short shielded gate trench contact row region is located above the gate metal pad region, and each gate trench has two shielded gate trench contact regions.

[0015] According to another aspect of the present invention, in some preferred embodiments, the SGT device further includes a long shielded gate trench contact row region located at the top of the source metal, wherein each gate trench has a shielded gate trench contact region.

[0016] According to another aspect of the present invention, in some preferred embodiments, the SGT device further includes a long shield gate trench contact row region located at the bottom of the source metal and a short shield gate trench contact row region located above the gate metal pad region, wherein each gate trench has a shield gate trench contact region.

[0017] According to another aspect of the present invention, an SGT device is also disclosed, including: an active region, a terminal region, a gate metal pad region, a plurality of gate metal wires, and a central shield gate trench contact row region; the active region includes: a plurality of gate trenches along a first axis, formed in an epitaxial layer of a first conductivity type, the epitaxial layer being located above a substrate of a first conductivity type, the gate trenches including a first type of active trench having a first trench length and a second type of active trench near the gate metal pad region and having a second trench length, wherein the length of the first type of active trench is greater than that of the second type of active trench; the terminal region includes at least one first type of terminal trench, which surrounds the outside of the gate trenches along the first axis and a second axis, wherein the first axis is perpendicular to the second axis, at least one first type of terminal trench is separated from the plurality of gate trenches and does not surround the gate metal pad region; the gate in each gate trench is connected to the gate metal pad through a plurality of gate metal wires having a plurality of gate trench contact regions thereunder; the shield gate in each gate trench is connected to the source metal through at least one shield gate trench contact region; the plurality of gate metal wires are all along the second axis and include a top long gate metal wire, a bottom long gate metal wire, and a short gate metal wire located above the gate metal pad region; the central shield gate contact row region is along the second axis and near the middle of the source metal; the shield gate in each gate trench is connected to the source metal through a plurality of shield gate trench contact regions located in the central shield gate contact row region and on each gate trench, and the distance between the shield gate trench contact region and each gate metal wire is greater than 100 μm.

[0018] According to another aspect of the present invention, an SGT device is also disclosed, including: an active region, a terminal region, a gate metal pad region, and a plurality of gate metal wires; the active region includes a plurality of gate trenches formed in an epitaxial layer of a first conductivity type, the epitaxial layer being located above a substrate of a first conductivity type; the gate in each gate trench is connected to the gate metal pad through a plurality of gate metal wires having a plurality of gate trench contact regions thereunder; the shield gate in each gate trench is connected to the source metal through at least one shield gate trench contact region, wherein the distance between the at least one shield gate trench contact region and any one of the gate metal wires is greater than 100 μm.

[0019] According to another aspect of the present invention, in some preferred embodiments, the plurality of gate metal wires include a long gate metal wire and two short gate metal wires. Among them, the one long gate metal wire is located in the middle region of the active region, and the two short gate metal wires are respectively located above and below the gate metal pad region. In some other preferred embodiments, the plurality of gate metal wires include three long gate metal wires and two short gate metal wires. The three long gate metal wires are respectively located in the top, middle, and bottom regions of the active region, and the two short gate metal wires are respectively located above and below the gate metal pad region.

[0020] According to another aspect of the present invention, in some preferred embodiments, the SGT device further includes two shield gate trench contact row regions respectively located at the top and bottom of the source metal, and each gate trench has at least one shield gate trench contact region. In some other preferred embodiments, the SGT device further includes two shield gate trench contact row regions between the plurality of gate metal wires, and each gate trench has at least one shield gate trench contact region.

[0021] According to another aspect of the present invention, in some preferred embodiments, the shield gate resistance of the shield gate is in the range of 0.2 Ω to 2.0 Ω.

[0022] According to another aspect of the present invention, in some preferred embodiments, the SGT device further includes a source breakdown voltage holding region adjacent to the lower surface of the body region and separated from a plurality of adjacent gate trenches to avoid avalanche breakdown near the channel region. The parasitic bipolar transistor ((n+ / p / N) existing in the channel region is easily turned on, resulting in device failure at a relatively low avalanche energy level. Since the breakdown voltage of the source breakdown voltage holding region is lower than that of the parasitic bipolar transistor, the avalanche current will directly flow through the source breakdown voltage holding region to the source metal without turning on the parasitic bipolar transistor. Therefore, the avalanche capability of the device with the source breakdown voltage holding region is enhanced.

[0023] According to another aspect of the present invention, in some preferred embodiments, the SGT device further includes an electric field reduction region surrounding the bottom of each gate trench, and its doping concentration is lower than that of the first epitaxial layer of the multi-step epitaxial layer to enhance the breakdown voltage of the device. The purpose of setting the electric field reduction region in the SGT device is to solve the problem of reduced breakdown voltage caused by the fact that the field oxide layer thickness at the bottom of each gate trench is smaller than that of the sidewall field oxide layer.

[0024] By referring to the following respective drawings and reading the detailed description of the preferred embodiments below, the above and other objects and advantages of the present invention will undoubtedly be obvious to those of ordinary skill in the art. Description of the Drawings

[0025] The advantages of these and other embodiments of the present invention will be apparent from the following detailed description in conjunction with the accompanying drawings, in which:

[0026] FIG. 1A is a cross-sectional view of an SGT MOSFET disclosed in the prior art.

[0027] FIG. 1B is a top view of the SGT MOSFET shown in FIG. 1A.

[0028] Figure 2A is a simplified top view of a preferred SGT MOSFET according to the present invention.

[0029] Figure 2B is according to the present invention Figure 2A A detailed top view of a preferred embodiment of the SGT MOSFET shown.

[0030] Figure 3A is a simplified top view of another preferred SGT MOSFET according to the present invention.

[0031] Figure 3B is according to the present invention Figure 3A A detailed top view of a preferred embodiment of the SGT MOSFET shown.

[0032] Figure 4A is a simplified top view of another preferred SGT MOSFET according to the present invention.

[0033] Figure 4B is according to the present invention Figure 4A A detailed top view of a preferred embodiment of the SGT MOSFET shown.

[0034] Figure 5 is according to the present invention Figure 2B A cross-sectional view of a preferred A-B section of the embodiment shown.

[0035] Figure 6 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B section of the embodiment shown.

[0036] Figure 7 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B section of the embodiment shown.

[0037] Figure 8 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B section of the embodiment shown.

[0038] Figure 9 is according to the present invention Figure 2BAnother cross-sectional view of a preferred A-B cross-section of the illustrated embodiment.

[0039] Figure 10A is a simplified top view of another preferred SGT MOSFET according to the present invention.

[0040] Figure 10B is according to the present invention Figure 10A A detailed top view of a preferred embodiment of the illustrated SGT MOSFET.

[0041] Figure 11 is a top view of another preferred SGT MOSFET according to the present invention.

[0042] Figure 12 is a top view of another preferred SGT MOSFET according to the present invention.

[0043] Figure 13 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the illustrated embodiment.

[0044] Figure 14 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the illustrated embodiment.

[0045] Figure 15 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the illustrated embodiment.

[0046] Figure 16 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the illustrated embodiment.

[0047] Figure 17 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the illustrated embodiment. Detailed implementation

[0048] The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. The present invention may, but need not, be embodied in different forms and should not be limited to the embodiments described herein. For example, the description herein refers more to N-channel semiconductor integrated circuits, but it is obvious that other devices are also possible. The following is a detailed description of preferred embodiments for practicing the present invention with reference to the respective drawings. Some directional terms, such as "top", "bottom", "front", "rear", "above", "below", etc., are described with reference to the directions of the respective drawings. Since the elements in the embodiments can be placed in many different directions, the directional terms in the present invention are for description only and should not be regarded as a limitation of the present invention. It should be understood that various structural or logical alternatives and modifications in the embodiments should be covered within the true spirit and scope of the present invention. Therefore, the following detailed description should not be regarded as a limitation of the present invention, and the scope of the present invention is defined by the appended claims. It should be understood that the inventive features of the various preferred embodiments described in the present invention can be combined with each other, unless otherwise specifically stated.

[0049] Figure 2A is a simplified top view of a preferred SGT semiconductor power device according to the present invention. The SGT semiconductor power device includes an active region, a terminal region, a gate metal pad region 237, a central gate metal wire 227 near the middle of the source metal 212, a top long shielded gate trench contact row region 235, a bottom long shielded gate trench contact row region 236, and a short shielded gate trench contact row region 238 located above the gate metal pad region.

[0050] Figure 2B is according to the present invention Figure 2ADetailed top view of a preferred embodiment of the SGT MOSFET shown, wherein the SGT semiconductor power device includes an active region, a terminal region, a gate metal pad region 237', a central gate metal wire 227' located near the middle of the source metal 212' and having a plurality of gate trench contact regions 207' below it, a top long shielded gate trench contact row region 235', a bottom long shielded gate trench contact row region 236' and a short shielded gate trench contact row region 238' located above the gate metal pad region. In the active region, a plurality of first type active trenches 214' and second type active trenches 204' are formed in the N-type epitaxial layer above the N+ substrate along a first axis (y-axis direction), wherein the trench length of the first type active trench 214' is greater than that of the second type active trench 204'. In each first type active trench 214', a top shielded gate trench contact region 205' located in the top long shielded gate trench contact row region 235' and a bottom shielded gate trench contact region 206' located in the bottom long shielded gate trench contact row region 236' are formed. In each second type active trench 204', a top shielded gate trench contact region 205' located in the top long shielded gate trench contact row region 235' and a bottom shielded gate trench contact region 208' located in the short shielded gate trench contact row region 238' are formed. The gate in each gate trench is connected to the gate metal pad region 237' through the central gate metal wire 227' located near the middle of the source metal 212' and having a plurality of gate trench contact regions 207' below it. The shielded gate in each gate trench is connected to the source metal through the shielded gate trench contact regions 205' and 206', and the shielded gate trench contact regions 205' and 206' are arranged in the top and bottom shielded gate contact row regions 235' and 236' along a second axis (x-axis direction) respectively. The distance (D SG , as shown in the figure) between the top shielded gate trench contact region 205' and the central gate metal wire 227' is greater than 100 μm. In the terminal region, a plurality of terminal trenches including a first terminal trench 220' and a second terminal trench 222' are formed, and the terminal trenches surround the outside of the first type active trenches 214' and the second type active trenches 204' along the first axis (y-axis direction) and the second axis (x-axis direction), wherein the first axis is perpendicular to the second axis, the first terminal trench 220' is separated from the gate trenches 214' and 204', and does not surround the gate metal pad region 237'. Both the inner edge and the outer edge of the first terminal trench 220' and the second terminal trench 222' have a straight shape. A channel termination metal 218' is formed in the terminal region. In addition, the shielded gate in each second type active trench 204' is connected to a built-in shielded gate extension resistor (R SG, a source metal 212' as shown in the figure. The built-in shield gate extended resistor is located between the top shield gate trench contact region 205' and the central gate metal wire 227', with a resistance value of 0.2 Ω to 2.0 Ω, so as to reduce the reverse recovery charge Qrr and the switching voltage Vsw of the parasitic body diode in the SGT device.

[0051] Figure 3A is a simplified top view of another preferred SGT semiconductor power device according to the present invention. The SGT semiconductor power device includes an active region, a terminal region, a gate metal pad region 337, a central gate metal wire 327, and a top long shield gate trench contact row region 335.

[0052] Figure 3B is according to the present invention Figure 3A a detailed top view of a preferred embodiment of the SGT MOSFET shown in the figure. Among them, the SGT semiconductor power device includes an active region, a terminal region, a gate metal pad region 337', a central gate metal wire 327', and a top long shield gate trench contact row region 335'. The semiconductor power device is similar in structure to Figure 2B the invention described above, except that in the present invention, only one top shield gate trench contact region 305' and one gate trench contact region 307' are formed in each first-type active gate trench 314' and second-type active gate trench 304'. In addition, the distance (D SG , as shown in the figure) between the shield gate trench contact region 305' and the gate metal wire 327' near the middle of the source metal 312' is greater than 100 μm.

[0053] Figure 4A is a simplified top view of another preferred SGT semiconductor power device according to the present invention. The SGT semiconductor power device includes an active region, a terminal region, a gate metal pad region 437, a central gate metal wire 427, a bottom long shield gate trench contact row region 436, and a short shield gate trench contact row region 438 located above the gate metal pad region.

[0054] Figure 4B is according to the present invention Figure 4A a detailed top view of a preferred embodiment of the SGT MOSFET shown in the figure. Among them, the SGT semiconductor power device includes an active region, a terminal region, a gate metal pad region 437', a central gate metal wire 427', a bottom long shield gate trench contact row region 436', and a short shield gate trench contact row region 438' located above the gate metal pad region. The semiconductor power device is similar to Figure 2BThe described inventions have a similar structure, except that in the present invention, only one bottom shield gate trench contact region 406' or 408' and one gate trench contact region 407' near the middle of the source metal 412' are formed in each first type active gate trench 414' or second type active gate trench 404'. The distance (D SG , as shown in the figure) between the shield gate trench contact region 406' and the gate metal wire 427' is greater than 100 μm.

[0055] Figure 5 is according to the present invention Figure 2BCross-sectional view of a preferred A-B cross-section of the illustrated embodiment, which includes an active region and a termination region and has a single N-type epitaxial layer 502 with a uniform doping concentration. The device includes an N-channel SGT MOSFET formed on the N-type epitaxial layer, which is located above an N+ substrate 500, and the back surface of the N+ substrate 500 is coated with a Ti / Ni / Ag post-metal layer 501 as the drain metal. In the N-type epitaxial layer 502, a plurality of gate trenches 504 located in the active region and edge trenches 514 located in the termination region extend vertically downward from the upper surface of the N-type epitaxial layer 502 into the N-type epitaxial layer 502 without contacting the common interface of the N-type epitaxial layer 502 and the N+ substrate 500. Each gate trench 504 located in the active region includes a shield gate (SG, as shown) 505 in the lower part of the trench and a single gate (G, as shown) 507 above the shield gate 505 in the upper part of the trench. The shield gate 505 is insulated from the adjacent epitaxial layer by a first insulating layer 506, and the gate 507 is insulated from the adjacent epitaxial layer by a gate oxide layer 509, where the thickness of the gate oxide layer 509 is less than that of the first insulating layer 506, and the first insulating layer 506 has a uniform thickness along the sidewall of the trench. At the same time, the shield gate 505 and the gate 507 are insulated from each other by a polysilicon inter-oxide layer (IPO) 508. Between every two adjacent trench gates 504, a P-body region 510 having an n+ source region 511 is formed, which extends from near the upper surface of the N-type epitaxial layer 502. The p-body region 510, the n+ source region 511, and the shield gate 505 are connected to the source metal 512 through a plurality of trench contact regions 513. The plurality of trench contact regions 513 are all filled with metal plugs and barrier layers, which extend through the insulating layer 517 into the P-body region 510, and the bottom of each trench contact region 513 is surrounded by a p+ body contact region 520 located below the n+ source region 511. In the termination region outside the edge of the active region in the N-type epitaxial layer 502, a p+ body contact doping region 520 is formed, which at least surrounds the bottom of the trench source-body contact region 513, and there is no n+ source region above this p+ body contact region 520. There is no presence of the source region 511 and the body region 510 in the active region between two adjacent edge trenches 514 in the termination region. Each edge trench 514 in the termination region includes a trench field plate 515, which is insulated from the adjacent epitaxial layer by a second insulating layer 516, where the trench width Tw2 and the trench depth Td2 of the edge trench 514 are both greater than or equal to the trench width Tw1 and the trench depth Td1 of the gate trench 504 in the active region (Tw2≥Tw2 and Td2≥Td1). The mesa width Mw1 between two adjacent gate trenches 504 is greater than or equal to the mesa width Mw2 between two adjacent edge trenches 514 (Mw1≥Mw2).In addition, the terminal region further includes a trench termination metal 518, which is connected to the n+ source region 511, the N-type epitaxial layer 502, and the p+ body contact doping region 520 through a trench-type channel termination contact region 519.

[0056] Figure 6 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the embodiment shown, which embodiment includes an active region and a terminal region, and has a two-step epitaxial layer structure. The SGT semiconductor power device is similar to Figure 5 the invention described above, except that in the present invention, the N-type epitaxial layer includes two step epitaxial layers with different doping concentrations: a bottom epitaxial layer (N1, as shown) 602 with a doping concentration of D1 and a top epitaxial layer (N2, as shown) 603 located above the bottom epitaxial layer 602 with a doping concentration of D2, where the relationship between D1 and D2 is D2 < D1 to further reduce the specific on-resistance.

[0057] Figure 7 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the embodiment shown, which embodiment includes an active region and a terminal region, and has a three-step epitaxial layer structure. The SGT semiconductor power device is similar to Figure 5 the invention described above, except that in the present invention, the N-type epitaxial layer includes three step epitaxial layers with different doping concentrations, and its doping concentration decreases stepwise along the sidewall of the gate trench from the bottom of the gate trench to the first body region direction. The N-type multi-step epitaxial layer includes: a bottom first epitaxial layer (N1, as shown) 702 with a doping concentration of D1, a middle second epitaxial layer (N2, as shown) 703 with a doping concentration of D2, and a top third epitaxial layer (N3, as shown) 723 with a doping concentration of D3, where the relationship between D1, D2, and D3 is D3 < D2 < D1 to further reduce the specific on-resistance. Among them, D2 can be the average value of D1 and D3.

[0058] Figure 8 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the embodiment shown, which embodiment includes an active region and a terminal region, and has a three-step epitaxial layer structure. The SGT semiconductor power device is similar to Figure 7 the invention described above, except that in the present invention, the gate trench 804 located in the active region has a Figure 7 different shielding gate structure. In each gate trench 804, the shielding gate (SG, as shown) 805 is located in the middle of the trench, and the gate (G, as shown) 807 is formed around the upper two sides of the shielding gate 805.

[0059] Figure 9 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the illustrated embodiment, which embodiment includes an active region and a termination region and has a three-step epitaxial layer structure. The SGT semiconductor power device is the same as Figure 7 the invention described above, except for different first and second insulating layers. In the present invention, the first insulating layer 906 in the gate trench 904 has a three-step sidewall oxide layer structure: a lower oxide layer along the lower sidewall and bottom of the gate trench 904 with a uniform first thickness Tox,b, a middle oxide layer with a uniform second thickness Tox,m, and an upper oxide layer with a uniform third thickness Tox,u, where the relationship among Tox,b, Tox,m, and Tox,u is Tox,b > Tox,m > Tox,u, so as to further reduce the specific on-resistance while maintaining the same breakdown voltage. Among them, Tox,m can be the average value of Tox,b and Tox,u. The second insulating layer 916 in the edge trench 914 has a three-step sidewall oxide layer structure similar to the first insulating layer 906 in the gate trench 904.

[0060] Figure 10A A simplified top view of another preferred SGT semiconductor power device according to the present invention. The SGT semiconductor power device includes an active region, a termination region, a gate metal pad region 1037, a central shielded gate trench contact row region 1035, a top long gate metal wire 1027, a bottom long gate metal wire 1028, and a short gate metal wire 1029 located above the gate metal pad region.

[0061] Figure 10B is according to the present invention Figure 10A A detailed top view of a preferred embodiment of the SGT MOSFET shown, wherein the SGT semiconductor power device includes an active region, a termination region, a gate metal pad region 1037', a central shielded gate trench contact row region 1035', a top long gate metal wire 1027', a bottom long gate metal wire 1028', and a short gate metal wire 1029' located above the gate metal pad region. The semiconductor power device is the same as Figure 2BThe described inventions have similar structures. Except in the present invention, a plurality of different gate metal wires 1027’, 1028’ and 1029’ are all along the second axis (x-axis direction), and the central shield gate contact row region 1035’ is located near the middle of the source metal 1012’ along the second axis (x-axis direction). Inside each first-type active gate trench 1014’, a top gate trench contact region 1007’, a bottom gate trench contact region 1009’ and a shield gate trench contact region 1006’ located in the middle of the source metal 1012’ are formed. Inside each second-type active gate trench 1004’, a top gate trench contact region 1007’, a bottom gate trench contact region 1039’ and a shield gate trench contact region 1006’ located near the bottom gate trench contact region 1039’ are formed. The shield gate in each gate trench is connected to the source metal through the shield gate trench contact regions 1006’ arranged along the second axis (x-axis direction) in each of the gate trenches 1014’ and 1004’ and located in the central shield gate trench contact row region 1035’, and the distance between the shield gate trench contact region 1006’ and each gate metal wire is greater than 100μm.

[0062] Figure 11 FIG. 4 is a top view of another preferred SGT MOSFET according to the present invention, wherein the SGT semiconductor power device includes an active region, a terminal region, a gate metal pad region 1137, a central long gate metal wire 1127 located in the middle region of the active region, two short gate metal wires 1119 respectively located above and below the gate metal pad region, a top shield gate trench contact row region 1135 and a bottom shield gate trench contact row region 1136. In the active region, a plurality of first-type active trenches 1114 and second-type active trenches 1104 are formed along the first axis (y-axis direction) in an N-type epitaxial layer on an N+ substrate, wherein the trench length of the first-type active trench 1114 is greater than that of the second-type active trench 1104. The gate in each gate trench 1114 or 1104 is respectively connected to the gate metal pad region 1137 through a plurality of gate metal wires 1127 or 1119 having a plurality of gate trench contact regions 1107 or 1109 below. The shield gate in each of the gate trenches 1114 and 1104 is connected to the source metal 1112 through the shield gate trench contact regions 1105 and 1106 arranged along the second axis (x-axis direction) in the top and bottom shield gate trench contact row regions 1135 and 1136, and the minimum distance between the shield gate trench contact regions 1105 and 1106 and the plurality of gate metal wires 1107 and 1109 is greater than 100μm.

[0063] Figure 12is a top view of another preferred SGT MOSFET according to the present invention, wherein the SGT semiconductor power device includes an active region, a terminal region, a gate metal pad region 1237, a top long gate metal wire 1239, an intermediate long gate metal wire 1227, a bottom long gate metal wire 1259, two short gate metal wires 1219 respectively above and below the gate metal pad region, a top shield gate trench contact row region 1235 and a bottom shield gate trench contact row region 1236. In the active region, a plurality of first-type active trenches 1214 and second-type active trenches 1204 are formed in an N-type epitaxial layer above an N+ substrate along a first axis (y-axis direction), wherein the trench length of the first-type active trench 1214 is greater than that of the second-type active trench 1204. The gate in each gate trench 1214 or 1204 is respectively connected to the gate metal pad region 1237 through a plurality of gate metal wires 1239, 1227, 1259 or 1219 having a plurality of gate trench contact regions 1229, 1207, 1249 or 1209 thereunder. The shield gate in each of the gate trenches 1214 and 1204 is connected to the source metal 1212 through shield gate trench contact regions 1205 and 1206 arranged in the top and bottom shield gate trench contact row regions 1235 and 1236 along a second axis (x-axis direction).

[0064] Figure 13 Another preferred Figure 2B cross-sectional view of an A-B section of the embodiment shown according to the present invention, which embodiment includes an active region and a terminal region and has a two-step epitaxial layer structure. The SGT semiconductor power device is similar to Figure 6 the invention described above, except that in the present invention, a P-type source breakdown voltage holding region 1330 is formed on the lower surface adjacent to the body region 1310 between two adjacent gate trenches 1304, which is separated from the adjacent gate trenches 1304. The P-type source breakdown voltage holding region 1330 shields the PN junction between the P body region 1310 and the top epitaxial layer 1303 (N2, as shown) near the channel region 1340, preventing avalanche breakdown therefrom, thereby improving the avalanche ability of the device. The P-type source breakdown voltage holding region 1330 can be formed by performing boron ion implantation on the trench-type source-body contact region 1313.

[0065] Figure 14 Another preferred Figure 2B cross-sectional view of an A-B section of the embodiment shown according to the present invention, which embodiment includes an active region and a terminal region and has a two-step epitaxial layer structure. The SGT semiconductor power device is similar to Figure 13The described invention has a similar structure. Except in the structure of the present invention, it further includes an N-type electric field reducing region N* with a doping concentration of D*, which surrounds the bottom of each gate trench 1404 located in the active region and each edge trench 1414 located in the terminal region. The doping concentration D* of the N-type electric field reducing region N* is lower than the doping concentration D1 of the bottom first epitaxial layer (N1, as shown in the figure) 1402 to increase the breakdown voltage. The N-type electric field reducing region N* can be formed by implanting ions of P-type dopants such as boron or BF2 into the bottom of the gate trench 1404 and the edge trench 1414.

[0066] Figure 15 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B section of the illustrated embodiment, which includes an active region and a terminal region and has a three-step epitaxial layer structure. The SGT semiconductor power device is the same as Figure 14 The described invention has a similar structure. Except in the present invention, the N-type epitaxial layer includes three step epitaxial layers with different doping concentrations, and their doping concentrations decrease step by step along the sidewall of the gate trench from the bottom of the gate trench to the direction of the first body region. The N-type multi-step epitaxial layer includes: a bottom first epitaxial layer (N1, as shown in the figure) 1502 with a doping concentration of D1, a middle second epitaxial layer (N2, as shown in the figure) 1503 with a doping concentration of D2, and a top third epitaxial layer (N3, as shown in the figure) 1523 with a doping concentration of D3. Among them, the relationship between D1, D2, and D3 is D3 < D2 < D1 to further reduce the specific on-resistance. Among them, D2 can be the average value of D1 and D3.

[0067] Figure 16 is according to the present invention Figure 2B Another cross-sectional view of a preferred A-B section of the illustrated embodiment, which includes an active region and a terminal region and has a three-step epitaxial layer structure. The SGT semiconductor power device is the same as Figure 8 The described invention has a similar structure. Except in the present invention, a P-type source breakdown voltage holding region 1630 is formed on the lower surface adjacent to the body region 1610 between two adjacent gate trenches 1604, and it is separated from the adjacent gate trench 1604. In addition, it further includes an N-type electric field reducing region N* with a doping concentration of D*, which surrounds the bottom of each gate trench 1604 located in the active region and each edge trench 1614 located in the terminal region. The doping concentration D* of the N-type electric field reducing region N* is lower than the doping concentration D1 of the bottom first epitaxial layer (N1, as shown in the figure) 1602 to increase the breakdown voltage. The N-type electric field reducing region N* can be formed by implanting ions of P-type dopants such as boron or BF2 into the bottom of the gate trench 1604 and the edge trench 1614.

[0068] Figure 17 according to the present invention Figure 2B Another cross-sectional view of a preferred A-B cross-section of the embodiment shown, the embodiment includes an active region and a terminal region, and has a single N-type epitaxial layer 1702 with a uniform doping concentration. The SGT semiconductor power device is similar to Figure 9 the invention described above, except that in the present invention, a P-type source breakdown voltage holding region 1730 is formed between two adjacent gate trenches 1704 and adjacent to the lower surface of the body region 1710, which is separated from the adjacent gate trenches 1704 to enhance the avalanche capability of the device.

[0069] Although the present invention has been described in accordance with the preferred embodiments, it should be understood that the above disclosure should not be considered as a limitation of the present invention. The embodiments described above are generally N-channel devices, and by reversing the polarity of the conduction type, the embodiments can also be applied to P-channel devices. After reading the above disclosure, various alternatives and modifications will undoubtedly be obvious to those skilled in the art. Therefore, the appended claims should be construed to cover all alternatives and modifications that fall within the true spirit and scope of the present invention.

Claims

1. A shielded gate trench device, comprising: An active region, a terminal region, a gate metal pad region, a central gate metal wire, and at least one shielded gate trench contact row region; The active region includes: a plurality of gate trenches along a first axis, formed in an epitaxial layer having a first conductivity type, the epitaxial layer being located on a substrate having the first conductivity type, the gate trenches including a first type of active trench having a first active trench length and a second type of active trench near the gate metal pad region having a second active trench length, wherein the length of the first type of active trench is greater than that of the second type of active trench; The terminal region includes at least one first type of terminal trench that surrounds the outside of the plurality of gate trenches along the first axis and a second axis, wherein the first axis is perpendicular to the second axis, the at least one first type of terminal trench is separated from the plurality of gate trenches and does not surround the gate metal pad region; The plurality of gate trenches in the active region are surrounded by a first type of source region having the first conductivity type, the first type of source region being located in a first type of body region having a second conductivity type and close to the upper surface of the epitaxial layer having the first conductivity type, wherein each of the plurality of gate trenches includes a gate and a shielded gate; the shielded gate is insulated from the epitaxial layer by a first insulating layer, the gate is insulated from the epitaxial layer by a gate oxide layer, the shielded gate is insulated from the gate by an inter-polyoxide (IPO), the gate oxide layer surrounds the gate, and the thickness of the gate oxide layer is less than that of the first insulating layer; The gate in each of the gate trenches is connected to the gate metal pad through the central gate metal wire having a plurality of gate trench contact regions below; The shielded gate in each of the gate trenches is connected to the source metal through at least one shielded gate trench contact region located on each gate trench, the at least one shielded gate trench contact region is located in the at least one shielded gate contact row region along the second axis, the distance between the at least one shielded gate trench contact region and the gate metal wire is greater than 100 μm, and the central gate metal is located near the middle of the source metal.

2. The shield gate trench device according to claim 1, wherein The epitaxial layer is a multi-step epitaxial layer, and its doping concentration decreases step by step along the sidewall of the gate trench from the bottom of the plurality of gate trenches to the direction of the first type of body region.

3. The shield gate trench device according to claim 1, characterized in that, It further includes a channel termination region located in the terminal region, the channel termination region has a second type of source region having the first conductivity type, which is connected to the epitaxial layer below the channel termination metal, and there is no first type of body region between two adjacent terminal trenches.

4. The shield gate trench device according to claim 1, wherein In each of the plurality of gate trenches, the gate is located above the shielded gate.

5. The shield gate trench device according to claim 1, characterized in that, The shielded gate is located in the middle of each of the plurality of gate trenches, and the gate is formed around the upper two sides of the shielded gate.

6. The shield gate trench device according to claim 1, wherein The first insulating layer is a single oxide layer having a uniform thickness along the sidewalls of the plurality of gate trenches.

7. The shield gate trench device according to claim 1, wherein The first insulating layer has a multi-step sidewall oxide layer structure, and its thickness decreases step by step along the sidewalls of the gate trenches from the bottoms of the plurality of gate trenches to the body region direction.

8. The shield gate trench device according to claim 1, wherein It further includes: two long shield gate trench contact rows and one short shield gate trench contact row. The two long shield gate trench contact rows are respectively located at the top and bottom of the source metal, and the one short shield gate trench contact row is located above the gate metal pad region, wherein each gate trench has two shield gate trench contact regions.

9. The shield gate trench device according to claim 1, wherein, It further includes: one long shield gate trench contact row located at the top of the source metal, wherein each of the plurality of gate trenches has one shield gate trench contact region.

10. The shield gate trench device according to claim 1, wherein, It further includes: one long shield gate trench contact row located at the bottom of the source metal and one short shield gate trench contact row located above the gate metal pad region, wherein each of the plurality of gate trenches has one shield gate trench contact region.

11. A shield gate trench (SGT) device, which includes: One active region, one gate metal pad region and a plurality of gate metal wires; The active region includes a plurality of gate trenches formed in a first-conductivity-type epitaxial layer, and the epitaxial layer is located on a substrate having the first conductivity type; The plurality of gate trenches located in the active region are surrounded by a first-type source region having the first conductivity type. The first-type source region is located in a first-type body region having a second conductivity type and is close to the upper surface of the epitaxial layer having the first conductivity type. Wherein, each of the gate trenches includes a gate and a shield gate; insulation between the shield gate and the epitaxial layer is achieved through a first insulating layer, insulation between the gate and the epitaxial layer is achieved through a gate oxide layer, insulation between the shield gate and the gate is achieved through an inter-poly oxide layer (IPO), the gate oxide layer surrounds the gate, and the thickness of the gate oxide layer is less than that of the first insulating layer; The gate in each of the gate trenches is connected to the gate metal pad through the plurality of gate metal wires having a plurality of gate trench contact regions below; The shield gate in each of the gate trenches is connected to the source metal through at least one shield gate trench contact region, wherein the distance between the at least one shield gate trench contact region and any one of the plurality of gate metal wires is greater than 100 μm.

12. The shield gate trench device according to claim 11, wherein The plurality of gate metal wires includes one long gate metal wire located in the middle region of the active region and two short gate metal wires respectively located above and below the gate metal pad region.

13. The shield gate trench device according to claim 12, wherein, It further includes two shield gate trench contact rows located at the top and bottom of the source metal, wherein each of the plurality of gate trenches has the at least one shield gate trench contact region.

14. The shield gate trench device according to claim 11, characterized in that, The plurality of gate metal wires includes three long gate metal wires and two short gate metal wires. The three long gate metal wires are respectively located at the top, middle and bottom regions of the active region, and the two short gate metal wires are respectively located above and below the gate metal pad region.

15. The shielded gate trench device according to claim 11, characterized in that, It further includes two shield gate trench contact row regions between the multiple gate metal wires, wherein each of the multiple gate trenches has at least one shield gate trench contact region.

16. A shield gate trench (SGT) device, comprising: An active region, a gate metal pad region and at least one gate metal wire; The active region includes multiple gate trenches formed in an epitaxial layer of a first conduction type, and the epitaxial layer is located on a substrate of the first conduction type; The epitaxial layer is a multi-step epitaxial layer with different doping concentrations; The multiple gate trenches located in the active region are surrounded by source regions of the first conduction type, and the source regions of the first conduction type are located in a body region of a second conduction type and are close to the upper surface of the epitaxial layer of the first conduction type. Each of the gate trenches includes a gate and a shield gate; the shield gate is insulated from the epitaxial layer through a first insulating layer, the gate is insulated from the epitaxial layer through a gate oxide layer, the shield gate is insulated from the gate through a polysilicon inter-oxide layer (IPO), the gate oxide layer surrounds the gate, and the thickness of the gate oxide layer is less than that of the first insulating layer; The gate in each of the multiple gate trenches is connected to the gate metal pad through at least one gate metal wire having multiple gate trench contact regions below; The shield gate in each of the gate trenches is connected to source metal through at least one shield gate trench contact region, wherein the distance between the at least one shield gate trench contact region and the at least one gate metal wire is greater than 100 μm; A source breakdown voltage holding region of the second conduction type, which is adjacent to the lower surface of each body region and is separated from the adjacent multiple gate trenches.

17. The shielded gate trench device according to claim 16, wherein It further includes an electric field reducing region of the first conduction type, which surrounds the bottom of each of the multiple gate trenches, and the doping concentration of the electric field reducing region is lower than that of the first epitaxial layer of the multi-step epitaxial layer.

18. The shield gate trench device according to claim 16, wherein The doping concentration of each multi-step epitaxial layer decreases step by step along the sidewall of the gate trench from the bottom of the multiple gate trenches to the body region direction.

19. The shield gate trench device according to claim 16, characterized in that, In each of the multiple gate trenches, the gate is located above the shield gate.

20. The shield gate trench device as described in claim 16, characterized in that, The shield gate is located in the middle of each of the multiple gate trenches, and the gate is formed around the upper two sides of the shield gate.

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