An IGBT device with a deep buffer layer and high-density trenches and a preparation method thereof

Abstract

The present invention discloses an IGBT device with a deep buffer layer and high-density trenches and a preparation method thereof, which relates to the field of semiconductor device manufacturing and includes the following steps: A. Preparation of an epitaxial layer; B. Preparation of a front-end terminal structure; C. Preparation of a front-side high-density trench MOSFET structure; the high-density trenches include a plurality of cell active trenches, cell dummy trenches, and dicing channel trenches; D. Preparation of a circuit connection layer and a passivation layer; E. Preparation of the back side of the wafer. The present invention is beneficial to alleviating the warping problem in the production of IGBT devices on large-size wafers, and the depth and concentration of the buffer layer are easy to adjust, which can fully meet the application requirements and improve the yield of IGBT chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and particularly to an IGBT device with a deep buffer layer and high-density trenches and a preparation method thereof. Background Art

[0002] For the back electric field cutoff layer of the existing traditional IGBT, high-energy ion implantation is often used and realized through thermal annealing or laser annealing. For example, when phosphorus or arsenic is used, the implantation depth is 2 - 3 um, and through laser annealing, a depth range of 3 - 6 um and a concentration range of 1e16 - 1e17 / cm-3 can be achieved; when light ions such as protons and helium are used, the implantation depth can be 2 - 40 um, and through thermal annealing, a depth range of 3 - 40 um and a concentration range of 1e16 - 1e17 / cm-3 can be achieved. Such high-energy implantation machine tools have high costs, and also have high requirements for annealing. It is necessary to improve the activation rate as much as possible under the condition of a lower activation temperature.

[0003] Due to the trench depth of 4 - 7 um in the existing traditional IGBT devices, and the continuous increase in trench density, the wafer is prone to very large warpage during the production process. And after thinning, during back high-energy implantation and annealing, stress distribution is prone to be uneven, resulting in wafer breakage, making it difficult to promote the production of IGBTs on larger wafer sizes. Summary of the Invention

[0004] To solve the defects in the prior art, the purpose of the present invention is to provide a preparation method for an IGBT device with a deep buffer layer and high-density trenches.

[0005] The purpose of the present invention is achieved through the following technical solutions: A preparation method for an IGBT device with a deep buffer layer and high-density trenches, comprising the following steps:

[0006] A. Preparation of an epitaxial layer;

[0007] B. Preparation of a front-end terminal structure;

[0008] C. Preparation of a front high-density trench MOSFET structure; the high-density trenches include a plurality of cell active trenches, cell dummy trenches, and dicing channel trenches;

[0009] D. Preparation of a circuit connection layer and a passivation layer;

[0010] E. Preparation of the back of the wafer.

[0011] Further, the step A specifically includes the following steps:

[0012] S1. Grow a first epitaxial layer on the upper surface of a semiconductor substrate by means of vapor deposition. The first epitaxial layer is doped with a trivalent element or a pentavalent element.

[0013] S2. Grow a second epitaxial layer on the first epitaxial layer by means of vapor deposition. The second epitaxial layer is doped with a trivalent element or a pentavalent element.

[0014] Further, the first epitaxial layer is a buffer layer, and the second epitaxial layer is a breakdown voltage layer. The polarity of the element doped in the second epitaxial layer is the same as the polarity of the element doped in the first epitaxial layer. The trivalent element includes boron, and the pentavalent elements include arsenic and phosphorus.

[0015] Further, the preparation of the front terminal structure in step B specifically includes the following steps:

[0016] S3. Deposit silicon dioxide on the second epitaxial layer to obtain a thick oxide layer.

[0017] S4. Spin-coat a first photoresist layer on the thick oxide layer, and define the circuit pattern on the mask plate on the first photoresist layer by exposure using a lithography machine.

[0018] S5. Transfer the circuit pattern to the thick oxide layer by dry or wet etching, and remove the first photoresist layer.

[0019] S6. Perform ion implantation on the second epitaxial layer to obtain a terminal region. The impurities implanted include a trivalent element or a pentavalent element, and thermal activation is performed on the implanted impurities to obtain a terminal implanted region. The number of ion implantation times is one or more.

[0020] Further, step C specifically includes the following steps:

[0021] S7. Fabricate a hard mask on the upper surface of the second epitaxial layer. The material of the hard mask is silicon dioxide, and it is obtained by low-temperature chemical vapor deposition or high-temperature furnace tube process.

[0022] S8. Spin-coat a second photoresist layer on the hard mask, and define the pattern of high-density trenches on the mask template on the second photoresist layer by exposure using a lithography machine.

[0023] S9. After forming a circuit pattern on the second photoresist layer, transfer the circuit pattern to the silicon dioxide hard mask by dry etching, and remove the second photoresist layer.

[0024] S10. After forming a circuit pattern on the hard mask, use dry etching to form a plurality of high-density trenches on the second epitaxial layer, and remove the hard mask. The high-density trenches include a plurality of cell active trenches, cell dummy trenches, and dicing channel trenches.

[0025] S11. Through a furnace tube thermal oxidation process, grow a sacrificial oxide layer on the sidewalls of the trenches.

[0026] S12. Remove the sacrificial oxide layer by wet etching, and then grow the gate oxide layer through a high-temperature furnace tube thermal oxidation process.

[0027] S13. Deposit a layer of polysilicon on top of the high-density trenches and the second epitaxial layer by low-pressure chemical vapor deposition.

[0028] S14. Spin-coat a third photoresist layer on the polysilicon. Define the trench pattern on the mask plate on the third photoresist layer by exposure using a lithography machine, and transfer the trench pattern to the polysilicon by dry etching. Then remove the third photoresist layer.

[0029] S15. Fabricate the body region by performing body region ion implantation on the second epitaxial layer. The impurities implanted include trivalent elements or pentavalent elements, and thermally activate the implanted impurities.

[0030] S14. Spin-coat a fourth photoresist layer on the upper surface of the epitaxial wafer. Define the active region pattern on the mask plate on the fourth photoresist layer by exposure using a lithography machine, thereby realizing the active region pattern.

[0031] S17. Fabricate the active region by performing active region implantation on the second epitaxial layer. The impurities implanted include trivalent elements or pentavalent elements, and thermally activate the implanted impurities.

[0032] S18. Grow a silicon dioxide insulating layer on the surface of the epitaxial wafer.

[0033] Further, the cell active trenches and cell dummy trenches are located in the middle, and the dicing street trenches are located on both sides of the cell active trenches and cell dummy trenches; the cell dummy trenches include cell floating dummy trenches, cell source dummy trenches, and cell gate dummy trenches.

[0034] Further, the step D specifically includes the following steps:

[0035] S19. Spin-coat a fifth photoresist layer on the surface of the silicon dioxide insulating layer. Define the contact hole pattern on the mask plate on the fifth photoresist layer by exposure using a lithography machine; the contact holes include gate contact holes, emitter contact holes, and terminal contact holes.

[0036] S20. After realizing the gate contact hole, emitter contact hole, and terminal contact hole patterns on the fifth photoresist layer, transfer the patterns to the silicon dioxide by dry etching.

[0037] S21. Dope high-concentration impurities into the bottoms of the gate contact holes, emitter contact holes, and terminal contact holes by ion implantation, and anneal to activate the impurities to fabricate the ohmic contact layer.

[0038] S22. Deposit metallic titanium as a bonding layer by means of vapor deposition, form a silicide by using rapid thermal annealing, then deposit metallic tungsten isotropically, and remove the metallic tungsten outside the contact holes by dry etching to form a tungsten plug.

[0039] S23. Deposit metallic aluminum by means of sputtering, spin-coat a sixth photoresist layer, form a circuit connection layer by dry or dry-wet mixing after exposure, and remove the sixth photoresist layer.

[0040] S24. Deposit a passivation layer, and open the pad area through photolithography and etching processes.

[0041] Further, the step E specifically includes the following steps:

[0042] S25. Thin the back silicon substrate of the IGBT device until it is thinned to the first epitaxial layer.

[0043] S26. Inject a trivalent or pentavalent element with low energy and low dose into the back of the IGBT device by ion implantation, with the energy range of 10 - 40 k and the dose range of 1e12 - 1e13 / cm2, and form a collector after activation.

[0044] S27. Alloy the back of the IGBT device by evaporation or sputtering, and achieve ohmic contact after annealing to form back metal.

[0045] An IGBT device with deep buffer layer and high-density trenches, and the IGBT device with deep buffer layer and high-density trenches is prepared according to the preparation method of the IGBT device with deep buffer layer and high-density trenches.

[0046] Further, the device includes a terminal region, a dicing street region, and an active region, and a plurality of trench structures are provided in the dicing street region and the active region.

[0047] In summary, compared with the prior art, the present invention has the following beneficial effects:

[0048] (1) In the IGBT device of the present invention, the same trench structure as the active region is added in the dicing street, reducing the degree of wafer warping and enabling the production of high-density trench IGBTs on large wafer sizes.

[0049] (2) The front structure of the device of the present invention can achieve a very high trench density. Different front technologies, including injection enhancement, carrier storage, etc., can be adopted without increasing the process cost, and the capacitance composition ratio of the device of the present invention can be easily adjusted to meet the requirements of different application scenarios.

[0050] (3) The formation of the back buffer layer of the IGBT device described in the present invention does not require high-energy implantation and annealing, reducing the risk of fragmentation caused by this process step during the back process;

[0051] (4) The depth and concentration of the back buffer layer of the IGBT device described in the present invention can be easily adjusted. Therefore, the back injection efficiency and transport coefficient of the IGBT can be adjusted, enabling different turn-off characteristics to meet the requirements of different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects, and advantages of the present invention will become more apparent:

[0053] Figure 1 It is a top view of an IGBT device with a deep buffer layer and high-density trenches;

[0054] Figure 2 It is a processing schematic diagram of specific step S1 in step A of a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches;

[0055] Figure 3 It is a processing schematic diagram of specific step S2 in step A of a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches;

[0056] Figure 4 It is a processing schematic diagram of specific step S3 in step B of a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches;

[0057] Figure 5 It is a processing schematic diagram of specific step S4 in step B of a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches;

[0058] Figure 6 It is a processing schematic diagram of specific step S5 in step B of a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches;

[0059] Figure 7 It is a processing schematic diagram of specific step S6 in step B of a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches;

[0060] Figure 8 It is a processing schematic diagram of specific step S7 in step C of a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches;

[0061] Figure 9 It is a processing schematic diagram of specific step S8 in step C of a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches;

[0062] Figure 10 Schematic diagram of the processing of specific step S9 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0063] Figure 11 Schematic diagram of the processing of specific step S10 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0064] Figure 12 Schematic diagram of the processing of specific step S11 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0065] Figure 13 Schematic diagram of the processing of specific step S12 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0066] Figure 14 Schematic diagram of the processing of specific step S13 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0067] Figure 15 Schematic diagram of the processing of specific step S14 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0068] Figure 16 Schematic diagram of the processing of specific step S15 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0069] Figure 17 Schematic diagram of the processing of specific step S16 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0070] Figure 18 Schematic diagram of the processing of specific step S17 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0071] Figure 19 Schematic diagram of the processing of specific step S18 in step C of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0072] Figure 20 Schematic diagram of the processing of specific step S19 in step D of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0073] Figure 21 Schematic diagram of the processing of specific step S20 in step D of a preparation method for an IGBT device with a deep buffer layer and high-density trenches;

[0074] Figure 22 Schematic diagram of the processing of specific step S21 in step D of a preparation method for an IGBT device with a deep buffer layer and high-density trenches

[0075] Figure 23 Schematic diagram of the processing of specific step S22 in step D of a preparation method for an IGBT device with a deep buffer layer and high-density trenches

[0076] Figure 24 Schematic diagram of the processing of specific step S23 in step D of a preparation method for an IGBT device with a deep buffer layer and high-density trenches

[0077] Figure 25 Schematic diagram of the processing of specific step S24 in step E of a preparation method for an IGBT device with a deep buffer layer and high-density trenches

[0078] Figure 26 Schematic diagram of the processing of specific step S25 in step E of a preparation method for an IGBT device with a deep buffer layer and high-density trenches

[0079] Figure 27 Schematic diagram of the processing of specific step S26 in step E of a preparation method for an IGBT device with a deep buffer layer and high-density trenches

[0080] Figure 28 Schematic diagram of the processing of specific step S27 in step E of a preparation method for an IGBT device with a deep buffer layer and high-density trenches

[0081] Figure 29 For Figure 1 Schematic cross-sectional view along A-A

[0082] Reference numerals:

[0083] 1. Silicon substrate; 2. First epitaxial layer; 3. Second epitaxial layer; 4. Thick oxide layer; 5. First photoresist layer; 6. Terminal region; 7. Hard mask; 8. Second photoresist layer; 9. Cell active trench; 10. Cell floating dummy trench; 101. Cell source dummy trench; 102. Cell gate dummy trench; 11. Dicing channel trench; 12. Sacrificial oxide layer; 13. Gate oxide layer; 14. Polysilicon; 15. Third photoresist layer; 16. Body region; 161. Terminal implantation region; 162. Dicing channel implantation region; 17. Fourth photoresist layer; 18. Active region; 19. Insulating layer; 20. Fifth photoresist layer; 21. Gate contact hole; 211. Ohmic contact layer; 22. Emitter contact hole; 23. Terminal contact hole; 24. Metal; 241. Terminal metal mask; 25. Sixth photoresist layer; 26. Gate; 27. Emitter; 28. Passivation layer; 29. Collector; 30. Backside metal; 31. Dicing channel region; 32. Active region Detailed implementation manners

[0084] The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. For those of ordinary skill in the art, without departing from the concept of the present invention, several changes and improvements can still be made, and these all fall within the protection scope of the present invention. In the ranges disclosed herein, the endpoints and any values are not limited to the exact ranges or values, and these ranges or values should be understood to include values close to these ranges or values. For numerical ranges, between the endpoint values of each range, between the endpoint values of each range and individual point values, and between individual point values, they can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed herein. The present invention will be described in detail below in conjunction with specific embodiments:

[0085] An embodiment of the present invention provides a method for manufacturing an IGBT device with a deep buffer layer and high-density trenches as shown in Figure 1 、 Figure 29 . In a specific embodiment, this method is used to achieve a very high trench density in the front structure of the device. Without increasing the process cost, different front technologies can be adopted, including injection enhancement, carrier storage and other technologies, and the capacitance composition ratio of the device described in the present invention can be very easily adjusted to meet the requirements of different application scenarios and reduce the degree of wafer warping, realizing the production of high-density trench IGBTs on large wafer sizes. The specific steps are as follows:

[0086] Step A: Preparation of the epitaxial layer.

[0087] Step B: Preparation of the front terminal structure.

[0088] Step C: Preparation of the front high-density trench MOSFET structure. The high-density trenches include several cell active trenches, cell pseudo-trenches, and dicing channel trenches;.

[0089] Step D: Preparation of the circuit connection layer and the passivation layer 28.

[0090] Step E: Preparation of the back side of the wafer.

[0091] As a specific implementation manner, step A may specifically include:

[0092] Step S1: As shown in Figure 2As shown, a first epitaxial layer 2 is grown on the upper surface of the semiconductor substrate by vapor deposition as the buffer layer of the device described in the present invention. In this embodiment, the semiconductor substrate is specifically a silicon substrate 1. According to the different polarities of the device, a trivalent element (boron) can be selected for doping to prepare a P-type device or a pentavalent element (arsenic, phosphorus) for doping to prepare an N-type device. The thickness and concentration of the first epitaxial layer 2 will vary according to the depth and concentration of the buffer layer required by the application scenario.

[0093] Step S2, as Figure 3 shown, a second epitaxial layer 3 is grown on the first epitaxial layer 2 by vapor deposition as the voltage-resistant layer of the device described in the present invention. According to the different polarities of the device, a trivalent element (boron) can be selected for doping to prepare a P-type device or a pentavalent element (arsenic, phosphorus) for doping to prepare an N-type device. The polarity of the doping element is the same as that of the first epitaxial layer 2. The depth and concentration of the second epitaxial layer 3 can vary according to the requirements of the application scenario.

[0094] As a specific implementation manner, step B may specifically include:

[0095] Step S3, as Figure 4 shown, silicon dioxide is deposited on the second epitaxial layer 3 as the thick oxide layer 4 required for the terminal structure.

[0096] Step S4, as Figure 5 shown, a first photoresist layer 5 is spin-coated on the thick oxide layer 4, and the circuit pattern on the mask plate is defined on the first photoresist layer 5 through exposure by a lithography machine.

[0097] Step S5, as Figure 6 shown, the circuit pattern is transferred to the thick oxide layer 4 by dry or wet etching, and the photoresist is removed. On both sides of the second epitaxial layer 3, a group of strip-shaped thick oxide layers 4 with 2 in each group are obtained.

[0098] Step S6, as Figure 7 shown, the terminal region 6 is fabricated by ion implantation in the region of the second epitaxial layer 3 between the two groups of strip-shaped thick oxide layers 4 with 2 in each group (as Figure 29 shown). The impurities for ion implantation include trivalent elements (N-type MOSFET) or pentavalent elements (P-type MOSFET), and the implanted impurities are thermally activated to obtain two terminal implantation regions 161. Particularly, the ion implantation of the terminal implantation region 161 can be repeated once or multiple times to achieve different breakdown voltages.

[0099] As a specific implementation manner, step C may specifically include:

[0100] Step S7, as Figure 8As shown, a silicon dioxide thin film is deposited on the second epitaxial layer 3 as the hard mask 7 required for trench etching. The hard mask 7 can be prepared by low-temperature chemical vapor deposition or high-temperature furnace tube process.

[0101] Step S8: As Figure 9 shown, a second photoresist layer 8 is spin-coated on the hard mask 7. Through exposure by a lithography machine, the pattern of the high-density trenches corresponding to those in step S10 on the mask is defined on the second photoresist layer 8.

[0102] Step S9: As Figure 10 shown, after forming a circuit pattern on the second photoresist layer 8, the circuit pattern is transferred to the silicon dioxide hard mask 7 by dry etching, and the second photoresist layer 8 is removed.

[0103] Step S10: As Figure 11 shown, after forming a circuit pattern on the hard mask 7, high-density trenches are formed on the second epitaxial layer 3 by dry etching, and the hard mask 7 is removed.

[0104] Specifically, as a specific implementation manner, this method needs to define three types of trenches simultaneously. The high-density trenches include cell active trenches 9, cell dummy trenches, and dicing channel trenches 11. The cell active trenches 9 and cell dummy trenches are located in the middle, and the dicing channel trenches 11 are located on both sides.

[0105] Two cell active trenches 9 are located in the center of the second epitaxial layer 3 for the conduction effect of actual transistors. The cell dummy trenches include two cell floating dummy trenches 10 respectively located on both sides of the cell active trench 9, one cell source dummy trench 101 located on the side of the cell floating dummy trench 10 far from the cell active trench 9, and one cell gate dummy trench 102 located on the side of the cell floating dummy trench 10 far from the cell source dummy trench 101. By means of selective floating and connecting to the gate 26 and emitter 27, the cell dummy trenches can achieve the effects of improving breakdown voltage, adjusting capacitance, and adjusting the carrier distribution during conduction. Two groups of dicing channel trenches 11 are respectively located on both sides of the second epitaxial layer 3, and the number of each group of dicing channel trenches 11 is 2, which is beneficial to reducing the warping degree of large-size wafers.

[0106] As Figure 1 shown, in the dicing channel region 31, there are trenches with the same density parallel or perpendicular to the main chip, so as to achieve high-density trenches. The above numbers are not limitations of the present invention, but an example of an implementable form, and different numbers can be selected according to specific requirements.

[0107] Step S11: As Figure 12 shown, by using a furnace tube thermal oxidation process, a sacrificial oxide layer 12 is grown on the sidewalls of the high-density trenches.

[0108] Step S12: As Figure 13As shown, the sacrificial oxide layer 12 is removed by wet etching, and then the gate oxide layer 13 is grown by high-temperature furnace tube thermal oxidation process.

[0109] Step S13: As Figure 14 shown, a layer of polysilicon 14 is deposited on the high-density trenches and the second epitaxial layer 3 by low-pressure chemical vapor deposition.

[0110] Step S14: As Figure 15 shown, a third photoresist layer 15 is spin-coated on the polysilicon 14, and the trench pattern on the mask is defined on the third photoresist layer 15 by exposure of the lithography machine as Figure 16 shown. After the trench pattern is transferred to the polysilicon 14 by dry etching, the third photoresist layer 15 is removed. In particular, the polysilicon 14 retained by this method can connect the gate 26 trenches together and can also be used as the field plate structure of the terminal region 6.

[0111] Step S15: As Figure 16 shown, the middle body region 16 and the scribe lane implantation regions 162 on both sides are formed by ion implantation into the second epitaxial layer 3. The impurities implanted include trivalent elements (N-type MOSFET) or pentavalent elements (P-type MOSFET), and the implanted impurities are thermally activated.

[0112] Step S16: As Figure 17 shown, a fourth photoresist layer 17 is spin-coated on the upper surface of the epitaxial wafer, and the active region 18 pattern on the mask is defined on the fourth photoresist layer 17 by exposure of the lithography machine, thereby realizing the active region 18 pattern.

[0113] Step S17: As Figure 18 shown, the active region 18 between the two cell active trenches 9 is formed by implanting the second epitaxial layer 3 with the active region 18. The impurities implanted include trivalent elements (P-type MOSFET) or pentavalent elements (N-type MOSFET), and the implanted impurities are thermally activated.

[0114] Step S18: As Figure 19 shown, a silicon dioxide insulating layer 19 is grown on the upper surface of the epitaxial wafer.

[0115] As a specific implementation manner, step D may specifically include:

[0116] Step S19: As Figure 20 shown, a fifth photoresist layer 20 is spin-coated on the surface of the silicon dioxide insulating layer 19, and the contact hole pattern on the mask is defined on the fifth photoresist layer 20 by exposure of the lithography machine. The contact holes include the gate contact hole 21, the emitter contact hole 22, and the terminal contact hole 23 corresponding to Figure 23 .

[0117] Step S20, as Figure 21 shown, after the contact hole pattern is formed on the fifth photoresist layer 20, the pattern is transferred to the silicon dioxide insulating layer 19 by dry etching.

[0118] Step S21, as Figure 22 shown, high-concentration impurities are doped into the bottoms of the gate contact hole 21, emitter contact hole 22, and terminal contact hole 23 corresponding to Figure 23 by ion implantation, and the impurities are annealed and activated to fabricate the ohmic contact layer 211 of the contact hole.

[0119] Step S22, as Figure 23 shown, titanium metal is deposited as a bonding layer by vapor deposition, and silicide is formed by rapid thermal annealing. Subsequently, tungsten metal is deposited isotropically, and the tungsten metal outside the contact hole is removed by dry etching to form tungsten plugs in the gate contact hole 21, emitter contact hole 22, and terminal contact hole 23.

[0120] Step S23, as Figure 24 shown, metal 24 is deposited by sputtering, and then the sixth photoresist layer 25 is spin-coated. After exposure, a circuit connection layer is formed by dry or dry-wet mixing methods, and the sixth photoresist layer 25 is removed. Specifically, this method defines the terminal metal mask 241, two electrodes, one is the gate 26, and the other is the emitter 27.

[0121] Step S24, as Figure 25 shown, a passivation layer 28 is deposited, and the pad areas of the gate 26 and emitter 27 are opened by photolithography and etching processes.

[0122] As a specific implementation manner, step E may specifically include:

[0123] Step S25, as Figure 26 shown, the back silicon substrate 1 of the IGBT device is thinned until it is thinned to within the range of the first epitaxial layer 2.

[0124] Step S26, as Figure 27 shown, low-energy and low-dose particles, including trivalent elements (N-type IGBT) or pentavalent elements (P-type IGBT), are implanted into the back of the IGBT device by ion implantation, with an energy range of 10 - 40k and a dose range of 1e12 - 1e13 / cm2, and the implanted impurities are activated to form the collector 29.

[0125] Step S27, as Figure 28 shown, the back of the IGBT device is alloyed by evaporation or sputtering, and ohmic contact is achieved after annealing to form the back metal 30.

[0126] The embodiment of the present invention also provides an IGBT device with a deep buffer layer and high-density trenches, as Figure 1 、 Figure 29 shown, which includes a terminal region 6, a dicing channel region 31, and an active region 32. A high-density trench structure is provided in the dicing channel region 31 and the active region 32 of the IGBT device. The high-density trenches include a number of cell active trenches, cell pseudo-trenches, and dicing channel trenches. Among them, the terminal region 6 can have different repetition times according to different voltage levels; the dicing channel region 31 can have different repetition times according to different widths; the active region 32 can have different repetition times according to different current specifications.

[0127] The area of a 12-inch wafer is 2.25 times that of an 8-inch wafer and 4 times that of a 6-inch wafer. Therefore, at the same production efficiency, for a larger wafer, the chip yield increases exponentially. The present invention can alleviate the warping problem when manufacturing IGBT devices on large-size wafers, and the depth and concentration of the buffer layer are easy to adjust. The present invention can fully meet the requirements for trench density, trench type, and buffer layer in different application scenarios and improve the chip yield of IGBTs.

[0128] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0129] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for preparing an IGBT device with a deep buffer layer and high-density trenches, characterized in that: The steps include: A. Preparation of epitaxial layer; B. Preparation of front terminal structure; C. Fabrication of front-side high-density trench MOSFET structure; D. Preparation of circuit link layer and passivation layer (28); E. Preparation of the back side of the wafer; The preparation of the front terminal structure in step B specifically includes the following steps: S3, depositing silicon dioxide on the second epitaxial layer (3) to obtain a thick oxide layer (4); S4, performing spin coating on the thick oxide layer (4) and defining the circuit pattern on the mask on the first photoresist layer (5) by means of a photolithography machine exposure; S5, transferring the circuit pattern onto the thick oxide layer (4) by dry or wet etching, and removing the first photoresist layer (5); S6, performing ion implantation on the second epitaxial layer (3) to obtain a terminal region (6), wherein the ion implanted impurities include trivalent elements or pentavalent elements, and thermally activating the implanted impurities to obtain a terminal implantation region (161); the ion implantation is performed once or multiple times; The step C specifically includes the following steps: S7, forming a hard film (7) on the upper surface of the second epitaxial layer (3), wherein the hard film (7) is made of silicon dioxide and is prepared by low-temperature chemical vapor deposition or high-temperature furnace tube process; S8, spin coating a second photoresist layer (8) on the hard film (7), and defining the pattern of the high-density grooves on the mask on the second photoresist layer (8) through exposure by a photolithography machine; S9, after forming a circuit pattern on the second photoresist layer (8), transferring the circuit pattern to the silicon dioxide hard film (7) by dry etching, and removing the second photoresist layer (8); S10, after forming a circuit pattern on the hard film (7), forming a plurality of high-density grooves on the second epitaxial layer (3) by dry etching, and removing the hard film (7); the high-density grooves include a plurality of cell active grooves (9), cell pseudo grooves, and dicing grooves (11); S11, growing a sacrificial oxide layer (12) on the sidewall of the trench through a furnace thermal oxidation process; S12, removing the sacrificial oxide layer (12) by wet etching, and then growing a gate oxide layer (13) by a high-temperature furnace thermal oxidation process; S13, depositing a layer of polysilicon (14) on the high-density trench and the second epitaxial layer (3) by low-pressure chemical vapor deposition; S14, performing spin coating on the polysilicon (14) by a third photoresist layer (15), defining the groove pattern on the mask on the third photoresist layer (15) by exposure using a photolithography machine, and transferring the groove pattern to the polysilicon (14) by dry etching, and then removing the third photoresist layer (15); S15, performing ion implantation on the body region (16) of the second epitaxial layer (3) to obtain a body region (16), wherein the ion implanted impurities include trivalent elements or pentavalent elements, and thermally activating the implanted impurities; S16, performing spin coating on the upper surface of the epitaxial wafer by a fourth photoresist layer (17), and defining the pattern of the active area (18) on the mask on the fourth photoresist layer (17) by exposure using a photolithography machine, thereby realizing the pattern of the active area (18); S17, implanting an active region (18) into the second epitaxial layer (3) to obtain an active region (18), wherein the ion-implanted impurities include trivalent elements or pentavalent elements, and thermally activating the implanted impurities; S18, growing a silicon dioxide insulating layer (19) on the surface of the epitaxial wafer.

2. The method for preparing an IGBT device with a deep buffer layer and high-density trench according to claim 1, characterized in that: The step A specifically includes the following steps: S1. Growing a first epitaxial layer (2) on the upper surface of a semiconductor substrate by vapor deposition, wherein the first epitaxial layer (2) is doped with a trivalent element or a pentavalent element; S2. Growing a second epitaxial layer (3) on the first epitaxial layer (2) by vapor deposition, wherein the second epitaxial layer (3) is doped with a trivalent element or a pentavalent element.

3. The method for preparing an IGBT device with a deep buffer layer and high-density trenches according to claim 2, characterized in that: The first epitaxial layer (2) is a buffer layer, the second epitaxial layer (3) is a voltage-resistant layer, the polarity of the element doped in the second epitaxial layer (3) is the same as the polarity of the element doped in the first epitaxial layer (2), the trivalent element includes boron, and the pentavalent element includes arsenic and phosphorus.

4. The method for preparing an IGBT device with a deep buffer layer and high-density trenches according to claim 1, wherein: The cell active groove (9) and the cell pseudo groove are located in the middle, and the dicing groove (11) is located on both sides of the cell active groove (9) and the cell pseudo groove; the cell pseudo groove includes a cell floating pseudo groove (10), a cell source pseudo groove (101), and a cell gate pseudo groove (102).

5. The method for preparing an IGBT device with a deep buffer layer and high-density trenches according to claim 1, characterized in that: The step D specifically includes the following steps: S19, performing spin coating on the surface of the silicon dioxide insulating layer (19) by a fifth photoresist layer (20), and defining contact hole patterns on the mask plate on the fifth photoresist layer (20) by exposure using a photolithography machine; the contact holes include a gate contact hole (21), an emitter contact hole (22), and a terminal contact hole (23); S20, after realizing the patterns of the gate contact hole (21), the emitter contact hole (22), and the terminal contact hole (23) on the fifth photoresist layer (20), the patterns are transferred to silicon dioxide by dry etching; S21, doping high-concentration impurities into the bottoms of the gate contact hole (21), the emitter contact hole (22), and the terminal contact hole (23) by ion implantation, and annealing to activate the impurities to form an ohmic contact layer (211); S22. Depositing titanium as a bonding layer by vapor deposition and forming silicide by rapid thermal annealing, then isotropically depositing tungsten and removing the tungsten outside the contact hole by dry etching to form a tungsten plug. S23, depositing metallic aluminum by sputtering, spin-coating a sixth photoresist layer (25), forming a circuit link layer by a dry method or a dry-wet mixed method after exposure, and removing the sixth photoresist layer (25); S24, depositing a passivation layer (28), and opening the pad area through photolithography and etching processes.

6. The method for preparing an IGBT device with a deep buffer layer and high-density trenches according to claim 1, characterized in that: The step E specifically includes the following steps: S25, thinning the back silicon substrate (1) of the IGBT device until it is thinned to the first epitaxial layer (2); S26. Ion implantation is used to implant low-energy, low-dose trivalent or pentavalent elements into the back of the IGBT device. The energy range is 10-40k and the dose range is 1e12-1e13 / cm 2 After activation, a collector (29) is formed; S27, alloying the back of the IGBT device by evaporation or sputtering, and achieving ohmic contact after annealing to form a back metal (30).

7. An IGBT device with a deep buffer layer and high-density trenches, characterized in that: The deep buffer layer high-density trench IGBT device is manufactured according to the method for manufacturing a deep buffer layer high-density trench IGBT device according to any one of claims 1-6.

8. The deep buffer layer high-density trench IGBT device according to claim 7, characterized in that: The device comprises a terminal region (6), a scribe line region (31), and an active region (32); the scribe line region (31) and the active region (32) are provided with a plurality of high-density groove structures; the high-density grooves comprise a plurality of cellular active grooves (9), cellular pseudo grooves, and scribe line grooves (11).

Images