Preparation method of micro chip with p-face light emission and chip

Abstract

The application relates to the chip preparation field and discloses a P-face light-emitting micro chip preparation method and a chip. In the P-face light-emitting micro chip preparation method disclosed by the application, a chip is divided through the design of a first groove, so that stress is relieved when a large-area chip is peeled off, and when a chemical wet stripping technology is used, the chemical liquid access path is shortened, the problem that an epitaxial layer is easily damaged in the process of peeling off a sapphire substrate is solved, and the yield of the micro chip is improved.

Description

Technical Field

[0001] This invention relates to the field of chip fabrication, and provides a method for fabricating a microchip with P-side light emission and the chip itself. Background Technology

[0002] Current microarray chips or AR display chips generally use laser lift-off technology to modularize GaN materials, and then use semiconductor patterning etching process to isolate and divide pixel size in order to achieve pixel miniaturization of micro display products. However, because the laser damages GaN, the chip yield and reliability are highly unstable.

[0003] However, a new sapphire stripping technology has emerged in the industry – chemical wet stripping technology. Because this technology does not damage GaN materials, it can achieve high yield and high reliability of chips.

[0004] However, wet peeling has the following drawbacks when the chip size becomes large enough: 1. Large chips generate significant stress when detached from the sapphire crystal, making it difficult to implement subsequent processes for large modules. 2. Due to the large size, the chemical peeling process results in uneven peeling rates at the chip edges and interior, leading to uneven stress release in different areas of the chip during peeling. This can cause large chips to crack, ultimately resulting in a low yield. Summary of the Invention

[0005] This invention provides a solution to the problem of uneven stress release in different areas of a chip during chemical stripping, which leads to the cracking of large-size chips and improves the chip yield.

[0006] According to a first aspect of the present invention, a method for fabricating a microchip with P-side light emission is provided, comprising:

[0007] S1: A DPSS substrate is provided, the DPSS substrate includes a growth substrate and a patterned mask layer located on the growth substrate, and an epitaxial layer is formed on the patterned mask layer of the DPSS substrate; the epitaxial layer includes a transition layer, an N-type epitaxial layer, a light-emitting layer and a P-type epitaxial layer formed sequentially from bottom to top on the DPSS substrate.

[0008] S2: The epitaxial layer is bonded to a transfer substrate;

[0009] S3: Etch the transfer substrate to form a first trench penetrating the transfer substrate and the epitaxial layer on the transfer substrate and the epitaxial layer;

[0010] S4: Peel off the growth substrate;

[0011] S5: Thin the epitaxial layer;

[0012] S6: Fabricate an N-electrode on the thinned epitaxial layer;

[0013] S7: The N electrode is bonded to a CMOS substrate;

[0014] S8: Peel off the transfer substrate;

[0015] S9: Prepare pixels on the P-type epitaxial layer;

[0016] S10: Fill the spacing between the pixels with insulating reflective material;

[0017] S11: A first conductive layer is prepared on the P-type epitaxial layer and the insulating reflective material;

[0018] S12: A P electrode is fabricated in a non-pixel region on the first conductive layer to form a microchip with light emanating from the P surface.

[0019] Optionally, in step S2: an organic adhesive is applied to the transfer substrate to bond the epitaxial layer to the transfer substrate.

[0020] Optionally, the transfer substrate is made of silicon wafer or transparent glass.

[0021] Optionally, the first trench can be etched using photolithography.

[0022] Optionally, the first trench is composed of several columns of trenches, and each of the columns includes several rows of trenches, and the rows of trenches in adjacent columns are not connected.

[0023] Optionally, in step S5, the mask layer and the transition layer on the mask layer are removed by polishing or ICP thinning.

[0024] Optionally, in step S7, the bonding method includes at least one of the following: high-temperature bonding, high-pressure bonding, and vacuum bonding.

[0025] Optionally, the reflectivity of the insulating reflective material is greater than 50%.

[0026] Optionally, the first conductive layer is a transparent conductive layer.

[0027] Optionally, the material of the transparent conductive layer is: a metal film material, an oxide film material, or a polymer film material.

[0028] According to a second aspect of the present invention, a microchip with P-side light emission is also provided, which is prepared by the microchip fabrication method with P-side light emission described in the first aspect of the present invention.

[0029] The microchip fabrication method with P-side light emission provided by this invention divides the chip by designing a first trench, effectively solving the problem that large-sized chips generate great stress when they are released from sapphire crystal, making it difficult to carry out subsequent processes for large-sized modules. It also solves the problem that due to the large size, the chemical peeling rate is uneven at the chip edges and inside, resulting in uneven stress release in different areas of the chip during the peeling process, which leads to the cracking of large-sized chips, thus improving the yield of microchips. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic flowchart of a method for fabricating a P-side light-emitting microchip according to an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 1 ;

[0033] Figure 3 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 2 ;

[0034] Figure 4 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 3 ;

[0035] Figure 5 This is a top view of devices fabricated at different process stages according to a microchip fabrication method with P-side light emission provided in this embodiment of the invention. Figure 1 ;

[0036] Figure 6 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 4 ;

[0037] Figure 7 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 5 ;

[0038] Figure 8 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 6 ;

[0039] Figure 9 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 7 ;

[0040] Figure 10 This is a top view of devices fabricated at different process stages according to a microchip fabrication method with P-side light emission provided in this embodiment of the invention. Figure 2 ;

[0041] Figure 11 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 8 ;

[0042] Figure 12 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 9 ;

[0043] Figure 13 This is a schematic diagram of the structure of devices fabricated at different process stages according to a microchip fabrication method with P-surface light emission provided in the embodiments of the present invention. Figure 10 ;

[0044] Attached image annotations:

[0045] 100-DPSS substrate;

[0046] 101 - Production Base;

[0047] 102 - Graphical mask layer;

[0048] 200 - Epitaxial layer;

[0049] 201 - Transition Layer;

[0050] 202-N type epitaxial layer;

[0051] 2021-N electrode;

[0052] 203 - Emissive layer;

[0053] 204-P type epitaxial layer;

[0054] 300 - Transfer substrate;

[0055] 301 - First trench;

[0056] 400-COMS substrate;

[0057] 500 - First conductive layer;

[0058] 501-P electrode. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0061] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0062] In the manufacture of semiconductor devices, etching is a technique that selectively removes material (with or without a prior structure) from a thin film on a substrate, and patterns of that material are formed on the substrate through this removal.

[0063] Please refer to Figure 1 In one embodiment of the present invention, a method for fabricating a microchip with P-side light emission is provided, comprising:

[0064] S1: A DPSS substrate 100 is provided. The DPSS substrate 100 includes a growth substrate 101 and a patterned mask layer 102 located on the growth substrate 101. Epitaxial growth is performed on the patterned mask layer 102 of the DPSS substrate 100 to form an epitaxial layer 200. The epitaxial layer 200 includes a transition layer 201, an N-type epitaxial layer 202, a light-emitting layer 203, and a P-type epitaxial layer 204 formed sequentially from bottom to top on the DPSS substrate. For details regarding the epitaxial layer 200 grown on the DPSS substrate, please refer to [reference needed]. Figure 2 .

[0065] In one embodiment, the growth substrate 101 may be, for example, sapphire. Of course, the present invention is not limited thereto, and other growth substrates are also within the scope of protection of the present invention.

[0066] S2: The epitaxial layer 200 is bonded to a transfer substrate 300. Please refer to the diagram for the transferred device. Figure 3 .

[0067] In this embodiment of the invention, the transfer substrate may be made of silicon wafer or transparent glass. The epitaxial layer is bonded to the transfer substrate by applying organic adhesive.

[0068] The organic adhesive mentioned in the embodiments of the present invention can be plexiglass adhesive or silicone adhesive; that is, the present invention is not limited to the type of organic adhesive.

[0069] S3: The transfer substrate 300 is etched to form a first trench 301 penetrating the transfer substrate 300 and the epitaxial layer 200; the etched device is shown in the reference diagram. Figure 4 as well as Figure 5 .

[0070] In one specific embodiment, the first trench is etched on the transfer substrate using photolithography. The first trench consists of several columns of trenches, and each column includes several rows of trenches, with the row trenches of adjacent columns not communicating with each other. Of course, this invention is not limited to etching the first trench; other methods, such as ICP etching, to etch the first via on the epitaxial layer are also within the scope of this invention.

[0071] In a specific example, the row grooves and column grooves form a 3mm × 2mm module.

[0072] S4: Peel off the growth substrate.

[0073] In this embodiment of the invention, the design of the first trench effectively solves the problem of excessively large chip size. That is, by dividing the chip, the stress of large-area chips is relieved when peeling off the DPSS substrate by hand or blade. Furthermore, the first trench shortens the entry path of the chemical solution when using chemical wet stripping technology, so as to achieve synchronous and uniform stripping of the chip, ultimately providing high yield and high reliability of the chip.

[0074] S5: The epitaxial layer is thinned. Please refer to [reference needed] for the thinned device. Figure 6 .

[0075] In this embodiment of the invention, the thinning process can be achieved by polishing or ICP technology. Specifically, polishing or ICP technology is used to remove the patterned mask layer and the transition layer on the DPSS substrate to achieve the thinning process of the N-type epitaxial layer.

[0076] S6: Fabricate N-electrode 2021 on the thinned epitaxial layer; the device after fabricating N-electrode 2021 is as follows. Figure 7 As shown.

[0077] S7: The N electrode is bonded to a CMOS substrate 400. For example... Figure 8 As shown.

[0078] Specifically, an conductive bonding layer is fabricated on the CMOS substrate 400, and the N-electrode is bonded to the bonding layer.

[0079] In one specific implementation, the bonding method includes at least one of the following: high-temperature bonding, high-pressure bonding, and vacuum bonding. Of course, it is understood that the methods of electrode bonding are not limited to those listed above, and other electrode bonding methods are also within the scope of protection of this invention.

[0080] S8: Peel off the transfer substrate 300.

[0081] Since the transfer substrate is bonded to the epitaxial layer with organic adhesive, in a specific embodiment, the transfer substrate is removed by heating, laser, or dissolution.

[0082] S9: Pixels are fabricated on the P-type epitaxial layer 204. For the device after pixel fabrication, please refer to [the documentation / reference needed]. Figure 9 .

[0083] The epitaxial layer 200 is divided into multiple modules through the first trench 301. Pixels are fabricated on each module using photolithography, and excess epitaxial layer material is removed from each module. A schematic diagram of the pixel array structure is shown below. Figure 10 As shown.

[0084] S10: Fill the spacing between the pixels with insulating reflective material; the device after filling is as follows: Figure 11 As shown.

[0085] In one specific implementation, the reflectivity of the insulating reflective material is greater than 50%.

[0086] S11: A first conductive layer 500 is formed on the P-type epitaxial layer and the insulating reflective material; the first conductive layer 500 is a transparent conductive layer. In this embodiment of the invention, the material of the transparent conductive layer is a metal film material, an oxide film material, or a polymer film material. This invention is not limited to forming a transparent conductive layer; transparent conductive layers formed from other materials are also within the scope of protection of this invention. For example... Figure 12 As shown.

[0087] In this embodiment of the invention, the N-type epitaxial layers on each pixel are interconnected through the first conductive layer 500 and led to the N-electrode outside the pixel region to form a common N-electrode structure. Each pixel is driven individually by the peripheral driving circuit, thereby realizing independent control of each pixel.

[0088] S12: A P-electrode is fabricated in a non-pixel region on the first conductive layer 500 to form the light-emitting microchip from the P-surface. For example... Figure 13 As shown.

[0089] In the p-side light-emitting microchip fabrication method provided in this embodiment of the invention, the design of the first trench effectively solves the problem that large-sized chips generate great stress when they are released from sapphire crystal, making it difficult to carry out subsequent processes for large-sized modules. It also solves the problem that due to the large size, the chemical peeling rate is uneven at the chip edge and inside, resulting in uneven stress release in different areas of the chip during the peeling process, which leads to the cracking of large-sized chips. This improves the yield of array microchips.

[0090] This invention also provides a microchip with P-side light emission, which is fabricated according to the above-described method for fabricating a microchip with P-side light emission.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a microchip with P-face light emission, characterized in that, The method comprises the following steps: S1: providing a DPSS substrate, the DPSS substrate comprising a growth substrate and a patterned mask layer on the growth substrate, and epitaxially growing on the patterned mask layer of the DPSS substrate to form an epitaxial layer; the epitaxial layer comprising a transition layer, an N-type epitaxial layer, a light-emitting layer and a P-type epitaxial layer formed on the DPSS substrate in sequence from bottom to top; S2: bonding the epitaxial layer to a transfer substrate; S3: etching the transfer substrate to form a first trench penetrating through the transfer substrate and the epitaxial layer; The first trench is composed of a plurality of column trenches, and each of the plurality of column trenches comprises a plurality of row trenches, and the row trenches of adjacent column trenches are not communicated; S4: stripping the growth substrate by chemical wet method, or stripping the growth substrate by hand or blade; S5: thinning the epitaxial layer; S6: preparing an N electrode on the thinned epitaxial layer; S7: bonding the N electrode to a COMS substrate by bonding; S8: stripping the transfer substrate; S9: preparing a pixel point on the P-type epitaxial layer; S10: filling an insulating reflective material in the interval of the pixel point; S11: preparing a first conductive layer on the P-type epitaxial layer and the insulating reflective material; S12: preparing a P electrode on the non-pixel point area of the first conductive layer to form a micro chip for P-face light emission.

2. The method of claim 1, wherein the microchip is prepared in a P-face light emission. In step S2: the epitaxial layer is bonded to the transfer substrate by applying organic glue on the transfer substrate.

3. The method for preparing a micro chip for P-face light emission according to claim 2, wherein: The material of the transfer substrate is a silicon wafer or transparent glass.

4. The method of claim 1, wherein the microchip is prepared by a method comprising: forming a plurality of microchips on a substrate; and separating the plurality of microchips from the substrate. The first trench is etched by photolithography.

5. The method of claim 1, wherein the microchip is prepared by a method comprising: forming a plurality of microchips on a substrate; and separating the plurality of microchips from the substrate. In step S5, the mask layer and the transition layer thereon are removed by polishing or ICP thinning.

6. The method of claim 1, wherein the microchip is prepared by a method comprising: forming a plurality of microchips on a substrate; and separating the plurality of microchips from the substrate. In step S7, the bonding method at least includes one of the following: high-temperature bonding, high-pressure bonding, and vacuum bonding.

7. The method for preparing a micro chip for P-face light emission according to claim 1, wherein: The reflectivity of the insulating reflective material is greater than 50%.

8. The P-face light extraction microchip fabrication method of claim 1, wherein, The first conductive layer is a transparent conductive layer.

9. The method for preparing a micro chip for P-face light emission according to claim 8, wherein: The material of the transparent conductive layer is a metal film system material, an oxide film system material, or a polymer film system material.

10. A microchip with P-face light extraction, characterized in that The micro chip for P-face light emission is prepared by the method according to any one of claims 1-9.

Images