Common-mode voltage suppression method and system for quasi-Z-source simplified three-level inverter

Abstract

The present invention provides a common-mode voltage suppression method and system for a quasi-Z-source simplified three-level inverter. The method includes selecting two large vectors and two small vectors with low common-mode voltage amplitudes to form a basic voltage vector according to the sector where the reference voltage vector is located; writing a volt-second balance equation according to the selected basic voltage vector, combining the introduced small vector duty cycle distribution factor, thereby calculating the initial value of each basic voltage vector duty cycle and the small vector duty cycle distribution factor; designing a midpoint voltage balance controller to obtain a small vector duty cycle distribution factor correction value; using the small vector duty cycle distribution factor correction value and the initial value, combined with the set midpoint voltage balance control threshold, updating the small vector duty cycle distribution factor, thereby updating the duty cycle of each basic voltage vector; injecting a direct-through state into the small vector, designing a corresponding switch sequence, converting the switch sequence into a drive signal of a power switch tube, and controlling the operation of the quasi-Z-source simplified three-level inverter.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic power conversion, and in particular relates to a common-mode voltage suppression method and system for a quasi-Z-source simplified three-level inverter. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Quasi-Z-source three-level inverter has the advantages of single-stage power conversion, continuous input current, small passive device capacity, and no need to set dead time. It has been widely used in solar photovoltaic power generation, energy storage systems, motor drives and other fields. Quasi-Z-source neutral point clamped (NPC) and T-type three-level inverters are the two most commonly used quasi-Z-source three-level inverter topologies, but both require a large number of power switches, which inevitably increases system cost and volume.

[0004] In order to further reduce the number of power switch tubes, reduce system volume and cost, the quasi-Z source network can be combined with a simplified three-level inverter to form a quasi-Z source simplified three-level inverter, which contains ten power switch tubes, which is further reduced than the traditional quasi-Z source three-level inverter topology, and does not require the use of clamping diodes while maintaining advantages such as multi-level output, and has broad application prospects.

[0005] The inventors found that the existing modulation method for the quasi-Z-source simplified three-level inverter uses all basic voltage vectors to synthesize the reference voltage vector, which makes the system output common-mode voltage (CMV) amplitude very high, thereby causing many disadvantages such as common-mode current and electromagnetic interference, seriously affecting the normal operation of the system. Therefore, a common-mode voltage suppression method suitable for the quasi-Z-source simplified three-level inverter needs to be studied urgently. Summary of the invention

[0006] In order to solve the technical problems existing in the above-mentioned background technology, the present invention proposes a common-mode voltage suppression method and system for a quasi-Z-source simplified three-level inverter. The present invention can effectively suppress the common-mode voltage of the quasi-Z-source simplified three-level inverter system, while realizing the boost function of the system and ensuring the midpoint voltage balance.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] A first aspect of the present invention provides a common-mode voltage suppression method for a quasi-Z-source simplified three-level inverter.

[0009] A common mode voltage suppression method for a quasi-Z-source simplified three-level inverter includes:

[0010] According to the amplitude and phase angle of the reference voltage vector, determine the sector where the reference voltage vector is located;

[0011] According to the sector where the reference voltage vector is located, two large vectors and two small vectors with low common mode voltage amplitude are selected to form a basic voltage vector;

[0012] According to the selected basic voltage vector, write the volt-second balance equation, and combine it with the introduced small vector duty cycle allocation factor to calculate the initial value of each basic voltage vector duty cycle and small vector duty cycle allocation factor;

[0013] Design a midpoint voltage balance controller and obtain the correction value of the small vector duty cycle allocation factor;

[0014] Using the small vector duty cycle allocation factor correction value and the initial value, combined with the set midpoint voltage balance control threshold, the small vector duty cycle allocation factor is updated to update the duty cycle of each basic voltage vector;

[0015] The through state is injected into the small vector, the corresponding switching sequence is designed, and the switching sequence is converted into a driving signal of the power switch tube to control the operation of the quasi-Z-source simplified three-level inverter.

[0016] A second aspect of the present invention provides a common-mode voltage suppression system for a quasi-Z-source simplified three-level inverter.

[0017] The common mode voltage suppression system of a simplified quasi-Z source three-level inverter includes:

[0018] A sector determination module, configured to: determine the sector where the reference voltage vector is located according to the amplitude and phase angle of the reference voltage vector;

[0019] Basic voltage vector selection module: According to the sector where the reference voltage vector is located, two large vectors and two small vectors with low common mode voltage amplitude are selected to form a basic voltage vector;

[0020] A basic voltage vector duty cycle and small vector duty cycle allocation factor calculation module is configured to: write a volt-second balance equation according to the selected basic voltage vector, and combine the introduced small vector duty cycle allocation factor to calculate the initial value of each basic voltage vector duty cycle and small vector duty cycle allocation factor;

[0021] A midpoint voltage balancing controller module is configured to: design a midpoint voltage balancing controller to obtain a small vector duty cycle allocation factor correction value;

[0022] A small vector duty cycle allocation factor update module is configured to: update the small vector duty cycle allocation factor by using the small vector duty cycle allocation factor correction value and the initial value in combination with a set midpoint voltage balance control threshold, thereby updating the duty cycle of each basic voltage vector;

[0023] The through-state injection and switch sequence design module is configured to: inject the through-state into the small vector, design the corresponding switch sequence, convert the switch sequence into a drive signal of the power switch tube, and control the operation of the quasi-Z-source simplified three-level inverter.

[0024] A third aspect of the present invention provides a computer-readable storage medium.

[0025] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps in the common-mode voltage suppression method of a quasi-Z-source simplified three-level inverter as described in the first aspect above.

[0026] A fourth aspect of the present invention provides a computer device.

[0027] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps in the common-mode voltage suppression method of a quasi-Z-source simplified three-level inverter as described in the first aspect above are implemented.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The present invention can limit the common mode voltage of the quasi-Z source simplified three-level inverter system to ±V dc / 6, which is reduced by 1 / 2 compared with the traditional space vector modulation method.

[0030] 2. The present invention injects a lower direct-through state into a P-type small vector and an upper direct-through state into an N-type small vector to realize a system boost function without affecting the normal output AC voltage of the system.

[0031] 3. The present invention updates the small vector allocation factor according to the sector where the reference voltage vector is located and the DC side capacitor voltage deviation value, effectively controls the midpoint voltage balance, and the capacitor voltage fluctuation amplitude is very small.

[0032] 4. When abnormal factors cause the midpoint voltage to shift, the present invention has the ability to restore the midpoint voltage balance, thereby improving the operational reliability of the system.

[0033] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0035] Figure 1 The circuit topology diagram of the simplified quasi-Z-source three-level inverter;

[0036] Figure 2 A spatial vector diagram of a common-mode voltage suppression method for a quasi-Z-source simplified three-level inverter according to the present invention;

[0037] Figure 3 A control block diagram of a common-mode voltage suppression method for a quasi-Z-source simplified three-level inverter according to the present invention;

[0038] FIG. 4(a) and FIG. 4(b) are working waveforms of the system using the method of the present invention in the non-boost operation mode, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ).

[0039] Figure 5(a) and Figure 5(b) show the operating waveforms of the system using the traditional space vector modulation method in the non-boost operation mode, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ).

[0040] FIG6(a) and FIG6(b) are working waveforms of the system using the method of the present invention in the boost operation mode, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (ia 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ).

[0041] Figure 7(a) and Figure 7(b) show the operating waveforms of the system using the traditional space vector modulation method in the boost operation mode, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ).

[0042] FIG8(a) and FIG8(b) are working waveform diagrams of the system using the method of the present invention in the non-boost operation mode when the midpoint voltage balance control is enabled and then cancelled, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ).

[0043] FIG9(a) and FIG9(b) are working waveform diagrams of the system using the method of the present invention in the boost operation mode when the midpoint voltage balance control is changed from enabled to cancelled, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ). DETAILED DESCRIPTION

[0044] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0045] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0046] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0047] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the methods and systems according to various embodiments of the present disclosure. It should be noted that each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code may include one or more executable instructions for implementing the logical functions specified in each embodiment. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the flowchart and / or block diagram, and the combination of boxes in the flowchart and / or block diagram can be implemented using a dedicated hardware-based system that performs a specified function or operation, or can be implemented using a combination of dedicated hardware and computer instructions.

[0048] Embodiment 1

[0049] This embodiment provides a common-mode voltage suppression method for a quasi-Z-source simplified three-level inverter.

[0050] A common mode voltage suppression method for a quasi-Z-source simplified three-level inverter includes:

[0051] According to the amplitude and phase angle of the reference voltage vector, determine the sector where the reference voltage vector is located;

[0052] According to the sector where the reference voltage vector is located, two large vectors and two small vectors with low common mode voltage amplitude are selected to form a basic voltage vector;

[0053] According to the selected basic voltage vector, write the volt-second balance equation, and combine it with the introduced small vector duty cycle allocation factor to calculate the initial value of each basic voltage vector duty cycle and small vector duty cycle allocation factor;

[0054] Design a midpoint voltage balance controller and obtain the correction value of the small vector duty cycle allocation factor;

[0055] Using the small vector duty cycle allocation factor correction value and the initial value, combined with the set midpoint voltage balance control threshold, the small vector duty cycle allocation factor is updated to update the duty cycle of each basic voltage vector;

[0056] The through state is injected into the small vector, the corresponding switching sequence is designed, and the switching sequence is converted into a driving signal of the power switch tube to control the operation of the quasi-Z-source simplified three-level inverter.

[0057] Figure 1 The circuit topology diagram of the quasi-Z source simplified three-level inverter includes the following components: DC power supply, quasi-Z source network, simplified three-level inverter and load. Among them, the quasi-Z source network is connected between the DC power supply and the simplified three-level inverter to achieve the boost function; its input voltage is V in , the output voltage is V dc The simplified three-level inverter consists of 10 power switches (S1, S2, ..., S 10 ). Pulse Width Modulation (PWM) is used to control the on and off of each power switch tube. It can be understood that the power switch tube is an insulated gate bipolar transistor (IGBT); the power switch tube can also be implemented by other forms of transistors.

[0058] In the quasi-Z-source simplified three-level inverter system, the inherent high-frequency switching characteristics of the power devices generate common-mode voltage (CMV), which in turn causes many disadvantages such as common-mode current and electromagnetic interference, seriously affecting the normal operation of the system. Therefore, common-mode voltage suppression has become a key issue that needs to be solved urgently.

[0059] The common mode voltage is defined as the arithmetic mean of the three-phase output voltage of the system, that is,

[0060]

[0061] Among them, v ao 、v bo and v co is the three-phase output phase voltage of the simplified quasi-Z-source three-level inverter.

[0062] The switching states of the quasi-Z source simplified three-level inverter can be divided into two types: non-shoot-through state and shoot-through state. Like the ordinary simplified three-level inverter, the non-shoot-through state of the quasi-Z source simplified three-level inverter includes three types: [P], [O] and [N]. Select the neutral point of the quasi-Z source network (i.e. Figure 1 Point O1 in the figure is used as the reference point. When the switch state is [P], the output voltage of the bridge arm is +V dc / 2; when the switch state is [O], the bridge arm output voltage is 0; when the switch state is [N], the bridge arm output voltage is -V dc / 2. The quasi-Z-source simplified three-level inverter has three shoot-through states: Up-Shoot-Through (UST) state (abbreviated as [U]), Down-Shoot-Through (DST) state (abbreviated as [D]), and Full-Shoot-Through (FST) state (abbreviated as [F]).

[0063] Table 1 Basic voltage vectors and corresponding switch states selected by the method of the present invention

[0064]

[0065] Figure 2 The spatial vector diagram of the common-mode voltage suppression method of the quasi-Z-source simplified three-level inverter of the present invention. The basic voltage vectors, corresponding switch states and switched-on switches selected by the method of the present invention are shown in Table 1. It can be seen that the method of the present invention selects basic voltage vectors with low common-mode voltage amplitudes (including six large vectors, six small vectors with low common-mode voltage amplitudes, a zero vector with low common-mode voltage amplitude, and six through vectors). Among them, the selected six small vectors contain at most one P state or one N state to suppress the common-mode voltage of the system.

[0066] Figure 3 This is a control block diagram of the common-mode voltage suppression method of the quasi-Z-source simplified three-level inverter of the present invention. In order to achieve the goals of common-mode voltage suppression, midpoint voltage balance control and boost, a control strategy is designed, which specifically includes the following steps:

[0067] 1. Determine the sector where the reference voltage vector is located

[0068] The sector in which the reference voltage vector is located is determined based on its amplitude and phase angle.

[0069] 2. Basic voltage vector selection and small vector duty cycle allocation factor calculation

[0070] Without loss of generality, take sector 1 as an example to illustrate the basic voltage vector selection and duty cycle calculation method. When the reference voltage vector is located in sector 1, select the large vector V L1 [PNN], large vector V L2 [PPN], small vector V S1 [POO] and small vector V S2 [OON] Synthesize reference voltage vector. According to the volt-second balance principle, we can get:

[0071]

[0072] Among them, d L1 ,d L2 ,d S1 and d S2 Respectively represent the duty cycle of large vector [PNN], large vector [PPN], small vector [POO] and small vector [OON], V ref is the reference voltage vector.

[0073] Since four basic voltage vectors are used to synthesize the reference voltage vector, an indirect calculation method is designed to solve the duty cycle of the basic voltage vector. L1 [PNN], large vector V L2 [PPN], small vector V S1 [POO] and small vector V S2 The expressions of [OON] are

[0074]

[0075] Substituting the expressions of each basic voltage vector into the volt-second balance equation and simplifying it, we can get that the sum of the duty cycles of the two small vectors satisfies:

[0076]

[0077] Where m and θ are the modulation index and the phase angle of the reference voltage vector, respectively.

[0078] Introducing small vector duty cycle allocation factor D S1 and d S2 Respectively expressed as:

[0079]

[0080] In order to ensure the normal boost function of the system, it is necessary to allocate a factor for the small vector duty cycle For limiting processing, that is:

[0081]

[0082] Among them, d ST is the pass-through duty cycle.

[0083] Solving the above inequality group, we can get the small vector duty cycle allocation factor Need to meet

[0084]

[0085] Using the above small vector duty cycle allocation factor, the duty cycle of the two large vectors can be expressed as

[0086]

[0087] Since the duty cycle of each basic voltage vector must be greater than 0 and less than 1, the small vector duty cycle allocation factor can be obtained: The value range of is as follows:

[0088]

[0089] Comprehensive consideration of small vector duty cycle allocation factors The limiting situation is as follows:

[0090]

[0091]

[0092] According to the inequality scaling principle, it is not difficult to obtain

[0093]

[0094] Get the small vector duty cycle allocation factor Initial value of is the maximum value and minimum value The arithmetic mean of

[0095]

[0096] When the reference voltage vector is located in sectors other than sector 1, it is not difficult to obtain the duty cycle of the corresponding basic voltage vector and the value of the small vector duty cycle allocation factor by utilizing the phase angle mapping relationship between different sectors and the symmetry of the space vector diagram, which will not be repeated here.

[0097] 3. Design of midpoint voltage balance controller

[0098] The voltage across capacitors C2 and C3 in the quasi-Z source network is sampled, the deviation of the two capacitor voltages is calculated, and sent to the PI regulator. The output is calculated by taking the absolute value to obtain the small vector duty cycle allocation factor correction value y np ,Right now

[0099]

[0100] Among them, V C2 and V C3 are the voltages across capacitors C2 and C3, respectively, and k p,np and k i,np are the parameters of the PI regulator.

[0101] 4. Update of small vector duty cycle allocation factor

[0102] According to the system mid-point voltage balance control requirements, set the mid-point voltage balance control threshold ΔV np_th According to the sector where the reference voltage vector is located and the voltage deviation of capacitors C2 and C3, the small vector duty cycle allocation factor correction value is used to update the small vector duty cycle allocation factor. The specific rules are as follows:

[0103] (1) When -ΔV np_th <V C2 -V C3 <ΔV np_th When , the small vector duty cycle allocation factor remains unchanged at its initial value, that is,

[0104]

[0105] (2) When the reference voltage vector is located in sector 1, sector 3 or sector 5, and V C2 -V C3 >ΔV np_th When the small vector duty cycle allocation factor is updated to

[0106]

[0107] (3) When the reference voltage vector is located in sector 1, sector 3 or sector 5, and V C2 -V C3 <-ΔV np_th When the small vector duty cycle allocation factor is updated to

[0108]

[0109] (4) When the reference voltage vector is located in sector 2, sector 4 or sector 6, and V C2 -V C3 >ΔV np_th When the small vector duty cycle allocation factor is updated to

[0110]

[0111] (5) When the reference voltage vector is located in sector 2, sector 4 or sector 6, and V C2 -V C3 <-ΔV np_th When the small vector duty cycle allocation factor is updated to

[0112]

[0113] According to the constraints given by equations (10) and (11), the updated small vector duty cycle allocation factor is further limited, and the duty cycle of each basic voltage vector can be obtained.

[0114] 5. Through state injection and switch sequence design

[0115] Considering factors such as low output harmonic content and low switching loss, the switching sequence is designed. The lower pass state is injected into the P-type small vector, and the upper pass state is injected into the N-type small vector to achieve the boost function without affecting the normal output AC voltage of the system.

[0116] When the reference voltage vector is in sector 1, the switching sequence is designed as:

[0117] PNN-UUN-OON-PPN-PDD-POO-PDD-PPN-OON-UUN-PNN;

[0118] When the reference voltage vector is in sector 2, the switching sequence is designed as:

[0119] PPN-DPD-OPO-NPN-UUN-OON-UUN-NPN-OPO-DPD-PPN;

[0120] When the reference voltage vector is in sector 3, the switching sequence is designed as:

[0121] NPN-NUU-NOO-NPP-DPD-OPO-DPD-NPP-NOO-NUU-NPN;

[0122] When the reference voltage vector is in sector 4, the switching sequence is designed as:

[0123] NPP-DDP-OOP-NNP-NUU-NOO-NUU-NNP-OOP-DDP-NPP;

[0124] When the reference voltage vector is in sector 5, the switching sequence is designed as:

[0125] NNP-UNU-ONO-PNP-DDP-OOP-DDP-PNP-ONO-UNU-NNP;

[0126] When the reference voltage vector is in sector 6, the switching sequence is designed as:

[0127] PNP-PDD-POO-PNN-UNU-ONO-UNU-PNN-POO-PDD-PNP.

[0128] The switching sequence is converted into a driving signal of the power switch tube, thereby controlling the operation of the quasi-Z-source simplified three-level inverter system.

[0129] FIG. 4(a) and FIG. 4(b) are working waveforms of the system using the method of the present invention in the non-boost operation mode, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ). At this time, the DC input voltage is set to 400V, and the modulation index and the through duty cycle are set to 0.8 and 0 respectively. It can be seen that: the output voltage of the quasi-Z source network is basically equal to the DC input voltage, the line voltage is a five-level waveform, and the output current is a three-phase symmetrical sine waveform; the common-mode voltage amplitude is only 1 / 6 of the output voltage amplitude of the quasi-Z source network, that is, 67V; the voltages across capacitors C2 and C3 are equal, that is, the method of the present invention can effectively control the midpoint voltage balance.

[0130] Figure 5(a) and Figure 5(b) show the operating waveforms of the system using the traditional space vector modulation method in the non-boost operation mode, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ). At this time, the DC input voltage is set to 400V, the modulation index and the through duty cycle are set to 0.8 and 0 respectively. The system common-mode voltage amplitude is equal to 1 / 3 of the output voltage amplitude of the quasi-Z source network, that is, 133V. By comparing FIG4(a) and FIG5(a), it can be seen that: compared with the traditional space vector modulation method, the method of the present invention can reduce the common-mode voltage amplitude of the quasi-Z source simplified three-level inverter system by 1 / 2, which has obvious advantages.

[0131] FIG6(a) and FIG6(b) are working waveforms of the system using the method of the present invention in the boost operation mode, including the DC input voltage (V in ), quasi-Z source network output voltage (Vdc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ). At this time, the DC input voltage is set to 320V, and the modulation index and the through duty cycle are set to 0.8 and 0.1 respectively. Obviously, the output voltage amplitude of the quasi-Z source network is 400V, which is higher than the DC input voltage, verifying that the method of the present invention can realize the normal boost function of the system; the common mode voltage amplitude is only 1 / 6 of the output voltage amplitude of the quasi-Z source network, that is, 67V; the voltages across capacitors C2 and C3 are equal, and the fluctuation is very small, that is, the method of the present invention can effectively control the midpoint voltage balance.

[0132] Figure 7(a) and Figure 7(b) show the operating waveforms of the system using the traditional space vector modulation method in the boost operation mode, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ). At this time, the DC input voltage is set to 320V, the modulation index and the through duty cycle are set to 0.8 and 0.1 respectively. Obviously, when the traditional space vector modulation method is adopted, the system common mode voltage amplitude is as high as 1 / 3 of the quasi-Z source network output voltage amplitude, that is, 133V, which is twice the common mode voltage amplitude when the method of the present invention is adopted.

[0133] FIG8(a) and FIG8(b) are working waveform diagrams of the system using the method of the present invention in the non-boost operation mode when the midpoint voltage balance control is enabled and then cancelled, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3、V C4 ). At this time, the DC input voltage is set to 400V, and the modulation index and the through duty cycle are set to 0.8 and 0 respectively. In order to verify the midpoint voltage balance control function of the method of the present invention, resistors with resistances of 10kΩ and 1kΩ are connected in parallel at both ends of capacitors C2 and C3 respectively. Before the simulation time of 0.6s, the midpoint balance control function is enabled. It can be seen that: although resistors with different resistances are connected in parallel at both ends of capacitors C2 and C3, the voltages across the two capacitors can still remain equal. After the simulation time of 0.6s, the midpoint balance control function is canceled, and the voltages across the two capacitors are offset, and the midpoint voltage balance state cannot be maintained, which indicates that the method of the present invention has the ability to actively control the midpoint voltage balance. At the same time, the midpoint voltage balance control function does not affect the common-mode voltage suppression function.

[0134] FIG9(a) and FIG9(b) are working waveform diagrams of the system using the method of the present invention in the boost operation mode when the midpoint voltage balance control is changed from enabled to cancelled, including the DC input voltage (V in ), quasi-Z source network output voltage (V dc )、Line voltage(v ab ), common mode voltage (v cm )、Three-phase output current (i a 、i b 、i c ), DC side capacitor voltage (V C1 、V C2 、V C3 、V C4 ). At this time, the DC input voltage is set to 320V, and the modulation index and the through duty cycle are set to 0.8 and 0.1 respectively. In order to verify the midpoint voltage balance control function of the method of the present invention, resistors with resistance values ​​of 10kΩ and 1kΩ are connected in parallel at both ends of capacitors C2 and C3 respectively. Obviously, when the midpoint balance control function is cancelled, the voltages at both ends of capacitors C2 and C3 are no longer equal, thereby verifying the effectiveness of the midpoint voltage balance control function of the method of the present invention.

[0135] Embodiment 2

[0136] This embodiment provides a common-mode voltage suppression system for a quasi-Z-source simplified three-level inverter.

[0137] The common mode voltage suppression system of a simplified quasi-Z source three-level inverter includes:

[0138] A sector determination module, configured to: determine the sector where the reference voltage vector is located according to the amplitude and phase angle of the reference voltage vector;

[0139] Basic voltage vector selection module: According to the sector where the reference voltage vector is located, two large vectors and two small vectors with low common mode voltage amplitude are selected to form a basic voltage vector;

[0140] A basic voltage vector duty cycle and small vector duty cycle allocation factor calculation module is configured to: write a volt-second balance equation according to the selected basic voltage vector, and combine the introduced small vector duty cycle allocation factor to calculate the initial value of each basic voltage vector duty cycle and small vector duty cycle allocation factor;

[0141] A midpoint voltage balancing controller module is configured to: design a midpoint voltage balancing controller to obtain a small vector duty cycle allocation factor correction value;

[0142] A small vector duty cycle allocation factor update module is configured to: update the small vector duty cycle allocation factor by using the small vector duty cycle allocation factor correction value and the initial value in combination with a set midpoint voltage balance control threshold, thereby updating the duty cycle of each basic voltage vector;

[0143] The through-state injection and switch sequence design module is configured to: inject the through-state into the small vector, design the corresponding switch sequence, convert the switch sequence into a drive signal of the power switch tube, and control the operation of the quasi-Z-source simplified three-level inverter.

[0144] It should be noted here that the above-mentioned sector judgment module, basic voltage vector selection module, basic voltage vector duty cycle and small vector duty cycle allocation factor calculation module, midpoint voltage balance controller module, small vector duty cycle allocation factor update module and through state injection and switch sequence design module are the same as the examples and application scenarios implemented by the steps in Embodiment 1, but are not limited to the contents disclosed in the above-mentioned Embodiment 1. It should be noted that the above-mentioned modules as part of the system can be executed in a computer system such as a set of computer executable instructions.

[0145] Embodiment 3

[0146] This embodiment provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the steps in the common-mode voltage suppression method for a quasi-Z-source simplified three-level inverter as described in the first embodiment above are implemented.

[0147] Embodiment 4

[0148] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps in the common-mode voltage suppression method of the quasi-Z-source simplified three-level inverter as described in the first embodiment are implemented.

[0149] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0150] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0151] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0152] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0153] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0154] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A common mode voltage suppression method for a quasi-Z-source simplified three-level inverter, characterized in that: include: According to the amplitude and phase angle of the reference voltage vector, determine the sector where the reference voltage vector is located; According to the sector where the reference voltage vector is located, two large vectors and two small vectors with low common mode voltage amplitude are selected to form a basic voltage vector; According to the selected basic voltage vector, write the volt-second balance equation, and combine it with the introduced small vector duty cycle allocation factor to calculate the initial value of each basic voltage vector duty cycle and small vector duty cycle allocation factor; Design a midpoint voltage balance controller and obtain the correction value of the small vector duty cycle allocation factor; Using the small vector duty cycle allocation factor correction value and the initial value, combined with the set midpoint voltage balance control threshold, the small vector duty cycle allocation factor is updated to update the duty cycle of each basic voltage vector; The through state is injected into the small vector, the corresponding switching sequence is designed, the switching sequence is converted into the driving signal of the power switch tube, and the operation of the quasi-Z-source simplified three-level inverter is controlled; The process of updating the small vector duty cycle allocation factor includes: setting the midpoint voltage balance control threshold ΔV according to the system midpoint voltage balance control requirement. np_th ; According to the sector where the reference voltage vector is located and the voltage deviation of capacitors C2 and C3, the small vector duty cycle allocation factor correction value is used to update the small vector duty cycle allocation factor; When -ΔV np_th <V C2 -V C3 <ΔV np_th When , the small vector duty cycle allocation factor remains unchanged at its initial value, that is, When the reference voltage vector is located in sector 1, sector 3 or sector 5, and V C2 -V C3 >ΔV np_th When the small vector duty cycle allocation factor is updated to When the reference voltage vector is located in sector 1, sector 3 or sector 5, and V C2 -V C3 <-ΔV np_th When the small vector duty cycle allocation factor is updated to When the reference voltage vector is located in sector 2, sector 4 or sector 6, and V C2 -V C3 >ΔV np_th When the small vector duty cycle allocation factor is updated to Small vector duty cycle allocation factor correction value y np , expressed by the following formula: Among them, V C2 and V C3 are the voltages across capacitors C2 and C3, respectively, and k p,np and k i,np are the parameters of the PI regulator; When the reference voltage vector is located in sector 2, sector 4 or sector 6, and V C2 -V C3 <-ΔV np_th When the small vector duty cycle allocation factor is updated to 2. The common mode voltage suppression method of the quasi-Z-source simplified three-level inverter according to claim 1, characterized in that: Basic voltage vectors with low common mode voltage amplitudes are selected, including: six large vectors, six small vectors with low common mode voltage amplitudes, a zero vector with low common mode voltage amplitude, and six through vectors.

3. The common mode voltage suppression method of the quasi-Z-source simplified three-level inverter according to claim 1, characterized in that: The calculation of each basic voltage vector duty cycle specifically includes: Substitute the expressions of the two large vectors, the expressions of the two small vectors and the phase angle of the reference voltage vector into the volt-second balance equation to obtain the sum of the duty cycles of the two small vectors. Introduce the small vector duty cycle allocation factor to obtain the duty cycles of the two small vectors. According to the small vector duty cycle allocation factor, the duty cycles of the two large vectors are obtained; This results in the duty cycle of each basic voltage vector.

4. The common mode voltage suppression method of the quasi-Z-source simplified three-level inverter according to claim 1, characterized in that: The process of calculating the initial value of the small vector duty cycle allocation factor includes: According to the modulation index, the phase angle of the reference voltage vector and the direct duty cycle, the minimum and maximum values ​​of the small vector duty cycle allocation factor are calculated; when the reference voltage vector is located in sector 1, the minimum and maximum values ​​of the small vector duty cycle allocation factor are respectively Among them, m, θ and d ST are the modulation index, the phase angle of the reference voltage vector and the shoot-through duty cycle respectively; The initial value of the small vector duty cycle allocation factor is obtained according to the arithmetic mean of the maximum value and the minimum value of the small vector duty cycle allocation factor.

5. The common mode voltage suppression method of the quasi-Z-source simplified three-level inverter according to claim 1, characterized in that: The injecting of the through state into the small vector and designing the corresponding switch sequence specifically include: injecting the lower through state into the P-type small vector and injecting the upper through state into the N-type small vector; When the reference voltage vector is in sector 1, the switching sequence is designed as: PNN-UUN-OON-PPN-PDD-POO-PDD-PPN-OON-UUN-PNN; When the reference voltage vector is in sector 2, the switching sequence is designed as: PPN-DPD-OPO-NPN-UUN-OON-UUN-NPN-OPO-DPD-PPN; When the reference voltage vector is in sector 3, the switching sequence is designed as: NPN-NUU-NOO-NPP-DPD-OPO-DPD-NPP-NOO-NUU-NPN; When the reference voltage vector is in sector 4, the switching sequence is designed as: NPP-DDP-OOP-NNP-NUU-NOO-NUU-NNP-OOP-DDP-NPP; When the reference voltage vector is in sector 5, the switching sequence is designed as: NNP-UNU-ONO-PNP-DDP-OOP-DDP-PNP-ONO-UNU-NNP; When the reference voltage vector is in sector 6, the switching sequence is designed as: PNP-PDD-POO-PNN-UNU-ONO-UNU-PNN-POO-PDD-PNP.

6. A common-mode voltage suppression system for a simplified quasi-Z-source three-level inverter, characterized in that: include: A sector determination module, configured to: determine the sector where the reference voltage vector is located according to the amplitude and phase angle of the reference voltage vector; Basic voltage vector selection module: According to the sector where the reference voltage vector is located, two large vectors and two small vectors with low common mode voltage amplitude are selected to form a basic voltage vector; A basic voltage vector duty cycle and small vector duty cycle allocation factor calculation module is configured to: write a volt-second balance equation according to the selected basic voltage vector, and combine the introduced small vector duty cycle allocation factor to calculate the initial value of each basic voltage vector duty cycle and small vector duty cycle allocation factor; A midpoint voltage balancing controller module is configured to: design a midpoint voltage balancing controller to obtain a small vector duty cycle allocation factor correction value; A small vector duty cycle allocation factor update module is configured to: update the small vector duty cycle allocation factor by using the small vector duty cycle allocation factor correction value and the initial value in combination with a set midpoint voltage balance control threshold, thereby updating the duty cycle of each basic voltage vector; A through-state injection and switch sequence design module, which is configured to: inject a through-state into a small vector, design a corresponding switch sequence, convert the switch sequence into a drive signal for a power switch tube, and control the operation of a quasi-Z-source simplified three-level inverter; The process of updating the small vector duty cycle allocation factor includes: setting the midpoint voltage balance control threshold ΔV according to the system midpoint voltage balance control requirement. np_th ; According to the sector where the reference voltage vector is located and the voltage deviation of capacitors C2 and C3, the small vector duty cycle allocation factor correction value is used to update the small vector duty cycle allocation factor; When -ΔV np_th <V C2 -V C3 <ΔV np_th When , the small vector duty cycle allocation factor remains unchanged at its initial value, that is, When the reference voltage vector is located in sector 1, sector 3 or sector 5, and V C2 -V C3 >ΔV np_th When the small vector duty cycle allocation factor is updated to When the reference voltage vector is located in sector 1, sector 3 or sector 5, and V C2 -V C3 <-ΔV np_th When the small vector duty cycle allocation factor is updated to Small vector duty cycle allocation factor correction value y np , expressed by the following formula: Among them, V C2 and V C3 are the voltages across capacitors C2 and C3, respectively, and k p,np and k i,np are the parameters of the PI regulator; When the reference voltage vector is located in sector 2, sector 4 or sector 6, and V C2 -V C3 >ΔV np_th When the small vector duty cycle allocation factor is updated to When the reference voltage vector is located in sector 2, sector 4 or sector 6, and V C2 -V C3 <-ΔV np_th When the small vector duty cycle allocation factor is updated to 7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the common-mode voltage suppression method of a quasi-Z-source simplified three-level inverter as described in any one of claims 1 to 5 are implemented.

8. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the common-mode voltage suppression method of the quasi-Z-source simplified three-level inverter according to any one of claims 1 to 5 are implemented.

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